WO2021056908A1 - Pg引脚上电时序合理性的检测方法、系统及相关组件 - Google Patents

Pg引脚上电时序合理性的检测方法、系统及相关组件 Download PDF

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WO2021056908A1
WO2021056908A1 PCT/CN2019/129971 CN2019129971W WO2021056908A1 WO 2021056908 A1 WO2021056908 A1 WO 2021056908A1 CN 2019129971 W CN2019129971 W CN 2019129971W WO 2021056908 A1 WO2021056908 A1 WO 2021056908A1
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Prior art keywords
resistance value
pull
value
pin
resistance
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PCT/CN2019/129971
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English (en)
French (fr)
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王健
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苏州浪潮智能科技有限公司
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Priority to US17/764,334 priority Critical patent/US11863178B2/en
Publication of WO2021056908A1 publication Critical patent/WO2021056908A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/1774—Structural details of routing resources for global signals, e.g. clock, reset
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/12—Modifications for increasing the maximum permissible switched current
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
    • H03K19/01742—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals by means of a pull-up or down element

Definitions

  • the present invention relates to the technical field of circuits, and in particular to a method, a system and related components for detecting the rationality of a PG pin power-on sequence.
  • the correct power-on sequence is the prerequisite for the safe and reliable power supply of the power supply.
  • the Power Good signal is a key signal in the VR (Voltage Regulator, power module) chip.
  • the signal has two main functions. One is to feed back the working status of the power supply to the relevant control chip, and the other is to enable other power chips. Signal, so that the power supply is powered on according to the designed sequence. Therefore, if the PG signal is abnormal during power-on, it will affect the normal operation of the system.
  • the PG signal pin of the existing VR chip is usually of open-drain output type, and an external pull-up level is needed to realize the output of the high-level signal. That is, in the design, the PG signal needs to be connected to the pull-up resistor through a pull-up resistor. Pull the level to connect.
  • Figure 1 is a schematic diagram of using the TPS563210 chip to convert a 12V voltage to a 3.3V voltage.
  • the PG signal uses the output P3V3 as the pull-up level.
  • the pull-up resistor PR3 can usually refer to the withstand current of the chip pins and is selected as 1k resistance. Value of resistance.
  • Figure 2 is the power-on sequence shown in the chip data sheet of Figure 1. It can be seen from Figure 2 that when the output voltage Vo rises to 90% of the normal operating voltage, PG outputs a high level signal after a delay of about 1 ms.
  • Figure 3 shows the timing waveform detected in the actual application.
  • the PG signal should always be in a low level state before point b. After detecting that the output voltage reaches the critical value of 90%, it will go from point c after about 1ms. Becomes a high level signal.
  • the PG signal starts to rise from point a, and there is a voltage rise of about 1.2V when it reaches point b. Since the PG signal needs to be used as the Enable signal of the subsequent circuit, 1.2V may be high
  • the critical value of Enable in the subsequent chip may cause the malfunction of the subsequent circuit, and then affect the normal operation of the system.
  • the purpose of the present invention is to provide a method, system and related components for detecting the rationality of the power-on sequence of the PG pin, so as to effectively determine whether the power-on sequence of the PG pin in the VR chip is reasonable, and to avoid misoperation of subsequent circuits.
  • the present invention provides the following technical solutions:
  • a method for detecting the plausibility of the power-on sequence of the PG pin includes:
  • the value of the pull-up resistance of the PG pin is used as the first resistance value
  • the output is used to indicate that the resistance value of the pull-up resistor is unreasonable and the PG pin
  • it also includes:
  • it also includes:
  • it also includes:
  • the value is greater than or equal to the first resistance value, and greater than or equal to the second resistance value, and greater than or equal to the third resistance value, and greater than or equal to the
  • the fifth resistance value is less than or equal to the fourth resistance value.
  • a detection system for the plausibility of PG pin power-on sequence includes:
  • Pull-up level acquisition module for acquiring the pull-up level of the PG pin of the VR chip
  • the first resistance value determination module is used to determine the value of the pull-up resistance of the PG pin when the current value injected into the VR chip by the pull-up level is equal to the maximum withstand current of the VR chip. Take the value as the first resistance value;
  • the second resistance value determination module is used to obtain the equivalent resistance to ground when the PG pin is low, and calculate based on the equivalent resistance to ground when the output voltage of the PG pin is equal to the preset interference When the voltage is limited, the value of the pull-up resistance of the PG pin is used as the second resistance value;
  • the first prompt information output module is configured to output a signal used to indicate the pull-up resistor when it is determined that the actual resistance value of the pull-up resistor is lower than the first resistance value or lower than the second resistance value.
  • the first prompt message that the value is unreasonable and the PG pin power-on sequence has hidden dangers.
  • it also includes:
  • the third resistance value determining module is configured to obtain the value of the pull-up resistance when the VR chip reaches the preset maximum edge rate as the third resistance value;
  • a fourth resistance value determining module configured to obtain the value of the pull-up resistance when the VR chip reaches a preset minimum edge rate, as the fourth resistance value
  • the second prompt information output module is configured to output second prompt information when it is determined that the actual resistance value of the pull-up resistor is lower than the third resistance value or higher than the fourth resistance value.
  • it also includes:
  • a fifth resistance value determining module configured to obtain the value of the pull-up resistor when the power loss of the pull-up resistor reaches a preset loss threshold, as the fifth resistance value
  • the third prompt information output module is configured to output third prompt information when it is determined that the actual resistance value of the pull-up resistor is lower than the fifth resistance value.
  • it also includes:
  • the resistance value selection range display module is used to determine the resistance value selection range by using the first resistance value, the second resistance value, the third resistance value, the fourth resistance value and the fifth resistance value And display the selection range of the resistance value;
  • the value is greater than or equal to the first resistance value, and greater than or equal to the second resistance value, and greater than or equal to the third resistance value, and greater than or equal to the
  • the fifth resistance value is less than or equal to the fourth resistance value.
  • a device for detecting the plausibility of the power-on sequence of the PG pin includes:
  • Memory used to store computer programs
  • the processor is configured to execute the computer program to implement the steps of the method for detecting the rationality of the power-on sequence of the PG pin described in any one of the above.
  • a computer-readable storage medium having a computer program stored on the computer-readable storage medium, and when the computer program is executed by a processor, it implements the method for detecting the reasonableness of the PG pin power-on sequence of any one of the above step.
  • the applicant analyzes the rising trend of the waveform of the PG signal, considering that the rising trend of the waveform is basically the same as the trend of the pull-up level P3V3, so it is considered that the PG pin has a partial voltage when the PG pin is low, that is, the PG signal is low There is an equivalent resistance to ground at the level.
  • the equivalent resistance to ground is large, or the resistance of the pull-up resistor is low, due to the voltage division of the equivalent resistance to ground to the pull-up level, when the PG pin is low, the PG pin The output VOUT may also be higher, which may disturb the correct power-on sequence and cause malfunction of subsequent circuits. Therefore, when setting and selecting the resistance value of the pull-up resistor, it is necessary to consider whether the resistance value of the pull-up resistor is too low, which may cause an unreasonable power-on sequence of the PG pin.
  • this application determines that when the current value injected into the VR chip by the pull-up level is equal to the maximum withstand current of the VR chip, the value of the pull-up resistance of the PG pin is used as the first resistance value.
  • the first resistance represents the minimum value of the pull-up resistance when it is ensured that the current value injected into the VR chip by the pull-up level is less than or equal to the maximum withstand current of the VR chip.
  • this application obtains the equivalent resistance to ground when the PG pin is low, and calculates based on the equivalent resistance to ground when the output voltage of the PG pin is equal to the preset interference voltage limit, the upper limit of the PG pin is The value of the pull-up resistor is used as the second resistance value.
  • the second resistance represents the minimum value of the pull-up resistance when avoiding the malfunction of the subsequent circuit. Therefore, when it is determined that the actual resistance value of the pull-up resistor is lower than the first resistance value or lower than the second resistance value, the first prompt message is output. Therefore, the solution of the present application can effectively determine whether the power-on sequence of the PG pin in the VR chip is reasonable, and avoid misoperation of subsequent circuits.
  • Figure 1 is a schematic diagram of using the TPS563210 chip to convert a 12V voltage to a 3.3V voltage
  • FIG. 2 is a schematic diagram of a power-on sequence shown in the chip data sheet of FIG. 1;
  • Fig. 3 is a schematic diagram of timing waveforms detected in the actual application of the chip of Fig. 1;
  • FIG. 4 is an implementation flowchart of a method for detecting the rationality of the power-on sequence of the PG pin in the present invention
  • FIG. 5 is a schematic diagram of a timing waveform after adjusting the resistance of a pull-up resistor in a specific embodiment of the present invention
  • FIG. 6 is a schematic diagram of the structure of a detection system for the rationality of the power-on sequence of the PG pin in the present invention
  • FIG. 7 is a schematic structural diagram of a device for detecting the rationality of the power-on sequence of the PG pin in the present invention.
  • the core of the present invention is to provide a method for detecting the rationality of the power-on sequence of the PG pin, which can effectively determine whether the power-on sequence of the PG pin in the VR chip is reasonable, and to avoid the misoperation of the subsequent circuit.
  • the applicant first verified whether the abnormality was caused by external interference. Specifically, the circuit board slicing process was adopted, that is, the connection between the PG signal and the subsequent circuit was disconnected . However, after the test, the above abnormal situation still exists, and the influence of external interference can be eliminated, and then it can be determined that the problem lies in the voltage conversion circuit itself.
  • the applicant further analyzed the rising trend of the waveform of the PG signal, considering that the rising trend of the waveform is basically consistent with the trend of the pull-up level P3V3. It should be noted that although the waveform rising trend of the pull-up level P3V3 is not shown in FIG. 3, the waveform rising trend of the pull-up level P3V3 is basically the same as the waveform rising trend of VOUT. Therefore, the applicant considered that the PG pin has a partial voltage when it is at a low level. That is, there is an equivalent resistance to ground when the PG signal is low.
  • the PG pin When the equivalent resistance to ground is large, or the resistance of the pull-up resistor is low, due to the voltage division of the equivalent resistance to ground to the pull-up level, when the PG pin is low, the PG pin The output VOUT may also be higher. For example, it reaches 1.2V in Figure 3, which may disturb the correct power-on sequence and cause the subsequent circuit to malfunction.
  • FIG. 4 is an implementation flowchart of a method for detecting the rationality of the power-on sequence of the PG pin in the present invention, which may include the following steps:
  • Step S101 Obtain the pull-up level of the PG pin of the VR chip.
  • the pull-up level of the PG pin can be obtained by reading the parameter list of the VR chip. Of course, it can also be pulled up by the relevant staff through the input device.
  • the flat input enables the detection system for the plausibility of the power-on sequence of the PG pin to obtain the pull-up level of the PG pin.
  • Step S102 Determine the value of the pull-up resistance of the PG pin as the first resistance value when the current value injected into the VR chip by the pull-up level is equal to the maximum withstand current of the VR chip.
  • the value of the pull-up resistor will affect the current injected into the VR chip, and the larger the value of the pull-up resistor, the lower the injected current.
  • the lower the value of the pull-up resistor, the injected current The higher the current.
  • the VR chip has its set maximum withstand current. Therefore, the pull-up resistor cannot be set too low, that is, the value of the pull-up resistor needs to ensure that the pull-up level is injected into
  • the current value in the VR chip is less than or equal to the maximum withstand current of the VR chip, and the value of the smallest pull-up resistance that meets this index is the first resistance value described in this application.
  • the resistance of the pull-up resistor is 400 ⁇
  • the current value injected into the VR chip is equal to the maximum withstand current of the VR chip
  • 400 ⁇ is the first described in this application.
  • the resistance needs to be set to at least 400 ohms.
  • step S102 can refer to the related prior art to calculate that the tolerance is satisfied.
  • the critical value of the pull-up resistance of the current indicator is the first resistance value.
  • Step S103 Obtain the equivalent resistance to ground when the PG pin is low, and calculate the pull-up resistance of the PG pin when the output voltage of the PG pin is equal to the preset interference voltage limit value based on the equivalent resistance to ground The value of is used as the second resistance value.
  • the equivalent resistance to ground there are many ways to obtain the equivalent resistance to ground.
  • the actual electrical timing of the VR chip can be obtained, and then the equivalent resistance to ground when the PG pin is at a low level can be determined.
  • the pull-up level of the VR chip is 3.3V
  • the voltage division of the PG pin at low level is 1.2V
  • the actual resistance of the pull-up resistor is 1000 ⁇
  • the interference voltage limit value refers to the maximum voltage value that the PG pin is allowed to output when the PG pin is low, for example, it is usually 200mv. That is to say, when the PG pin is low, the output voltage is lower than 200mv, which will not cause the subsequent circuit to malfunction.
  • the interference voltage limit value in other embodiments may have other specific values.
  • the VR chip when the PG pin is low, the VR chip usually controls the relevant switch circuit inside the chip to be turned on, that is, the PG pin is grounded.
  • the grounded PG pin will have a larger equivalent resistance, usually because in practical applications, the switching circuit may not be composed of a single switch tube, such as a single MOS. It may be a switch function formed by related circuits, resulting in
  • the PG pin also has a larger equivalent resistance to ground when it is low. Of course, in other specific occasions, there may be a larger equivalent resistance to ground when the PG pin is grounded due to other types of reasons.
  • the equivalent resistance to the ground is relatively large, so that when the PG pin is at a low level, it may also cause a malfunction of the subsequent circuit. This is the reason why the power-on sequence of the PG pin described in this application is unreasonable.
  • Step S104 When it is judged that the actual resistance value of the pull-up resistor is lower than the first resistance value or lower than the second resistance value, output the first resistance value indicating that the pull-up resistance value is unreasonable and that there is a hidden danger in the power-on sequence of the PG pin. A prompt message.
  • the actual resistance value of the pull-up resistor When it is determined that the actual resistance value of the pull-up resistor is lower than the first resistance value, it indicates that the current flowing into the VR chip at the pull-up level may exceed the withstand current of the VR chip.
  • the actual resistance value of the pull-up resistor is lower than the second resistance value, the subsequent circuit may malfunction when the PG pin is low. In other words, the actual resistance value of the pull-up resistor is higher than the first resistance value and higher than the second resistance value, which is a reasonable resistance value of the pull-up resistor, and the first prompt message will not be output.
  • the first prompt information is used to indicate that the resistance value of the pull-up resistor is unreasonable and there are hidden dangers in the power-on sequence of the PG pin, so as to remind relevant personnel to notice the situation, so that the resistance value of the pull-up resistor can be adjusted in time.
  • the adjustments described here may be adjustments made during the circuit design stage, or adjustments made to the hardware circuit actually produced, but generally speaking, adjustments are made during the design stage.
  • the applicant analyzes the rising trend of the waveform of the PG signal, considering that the rising trend of the waveform is basically the same as the trend of the pull-up level P3V3, so it is considered that the PG pin has a partial voltage when the PG pin is low, that is, the PG signal is low There is an equivalent resistance to ground at the level.
  • the equivalent resistance to ground is large, or the resistance of the pull-up resistor is low, due to the voltage division of the equivalent resistance to ground to the pull-up level, when the PG pin is low, the PG pin The output VOUT may also be higher, which may disturb the correct power-on sequence and cause malfunction of subsequent circuits. Therefore, when setting and selecting the resistance value of the pull-up resistor, it is necessary to consider whether the resistance value of the pull-up resistor is too low, which may cause an unreasonable power-on sequence of the PG pin.
  • this application determines that when the current value injected into the VR chip by the pull-up level is equal to the maximum withstand current of the VR chip, the value of the pull-up resistance of the PG pin is used as the first resistance value.
  • the first resistance represents the minimum value of the pull-up resistance when it is ensured that the current value injected into the VR chip by the pull-up level is less than or equal to the maximum withstand current of the VR chip.
  • this application obtains the equivalent resistance to ground when the PG pin is low, and calculates based on the equivalent resistance to ground when the output voltage of the PG pin is equal to the preset interference voltage limit, the upper limit of the PG pin is The value of the pull-up resistor is used as the second resistance value.
  • the second resistance represents the minimum value of the pull-up resistance when avoiding the malfunction of the subsequent circuit. Therefore, when it is determined that the actual resistance value of the pull-up resistor is lower than the first resistance value or lower than the second resistance value, the first prompt message is output. Therefore, the solution of the present application can effectively determine whether the power-on sequence of the PG pin in the VR chip is reasonable, and avoid misoperation of subsequent circuits.
  • it may further include:
  • the second prompt message is output.
  • two indicators are considered for the resistance of the pull-up resistor. One is to ensure that the current flowing into the VR chip is within the tolerance range of the VR chip, and the other is to prevent the PG pin from over-voltage when it is at a low level. Misoperation of subsequent circuits caused by high. In this embodiment, it is further considered that the resistance of the pull-up resistor will affect the edge rate of the signal.
  • the edge rate of the signal is lower, and correspondingly, when the resistance value of the pull-up resistor is lower, the edge rate of the signal is higher.
  • the VR chip usually presets a maximum edge rate and a minimum edge rate. Therefore, the third resistance value and the fourth resistance value are calculated in this embodiment of the present application. That is, when the actual resistance value of the pull-up resistor is greater than or equal to the third resistance value and less than or equal to the fourth resistance, it indicates that the edge rate is met.
  • the second prompt message can be output to remind the relevant personnel to notice the situation, and then the resistance value of the pull-up resistor can be adjusted in time.
  • the third prompt message is output.
  • the power loss of the pull-up resistor is also considered in this implementation. Specifically, the lower the resistance value of the pull-up resistor, the greater the power loss of the pull-up resistor. When it is determined that the actual resistance value of the pull-up resistor is lower than the fifth resistance value, it means that the power loss of the pull-up resistor will be higher than the loss. Threshold, so the third prompt message is output. To remind relevant personnel to notice the excessive power loss.
  • it may further include:
  • the value is greater than or equal to the first resistance value, and greater than or equal to the second resistance value, and greater than or equal to the third resistance value, and greater than or equal to the fifth resistance value, and less than or equal to the fourth resistance value. resistance.
  • the resistance selection range that satisfies the four indicators described in the foregoing embodiment is determined, and the pull-up resistor can be selected from the resistance selection range according to actual needs.
  • this application displays the resistance selection range, which is helpful for the staff to intuitively see the range and then set and adjust the resistance value of the pull-up resistor.
  • the resistance value of the pull-up resistor Adjusted from 1000 ohms to 10000 ohms, the timing waveform after adjustment can be seen in Figure 5. It can be seen that the step of the PG signal has become 168mv. After the output voltage reaches the critical value of 90%, after about 1ms, the PG signal changes from 168mv began to rise, meeting the requirements of the power-on sequence of the PG pin.
  • the resistance selection range that meets the above four indicators can be determined. In rare occasions, it may not be possible to meet the four indicators at the same time. At this time, you can also output prompt information. , So that the staff can weigh according to the importance of each index to select the preferred resistance value of the pull-up resistor. For example, the first priority is to ensure that the value of the pull-up resistor needs to be greater than or equal to the first resistance value and greater than the second resistance value, secondly, it should be greater than or equal to the third resistance value and less than or equal to the fourth resistance value, and finally, it should be greater than or equal to the fifth resistance value. Value this condition.
  • the embodiment of the present invention also provides a detection system for the rationality of the power-on sequence of the PG pin, which can be referred to above.
  • FIG. 6 is a schematic structural diagram of a detection system for the rationality of the power-on sequence of the PG pin in the present invention, including:
  • the pull-up level acquisition module 601 is used to acquire the pull-up level of the PG pin of the VR chip;
  • the first resistance value determination module 602 is used to determine the value of the pull-up resistance of the PG pin as the first resistance when the current value injected into the VR chip by the pull-up level is equal to the maximum withstand current of the VR chip value;
  • the second resistance value determining module 603 is used to obtain the equivalent resistance to ground when the PG pin is low, and calculate based on the equivalent resistance to ground when the output voltage of the PG pin is equal to the preset interference voltage limit value, The value of the pull-up resistance of the PG pin is used as the second resistance value;
  • the first prompt information output module 604 is used to output when it is determined that the actual resistance value of the pull-up resistor is lower than the first resistance value or lower than the second resistance value to indicate that the resistance value of the pull-up resistor is unreasonable and the PG pin The first prompt message that there is a hidden danger in the power-on sequence.
  • the third resistance value determining module is used to obtain the value of the pull-up resistance when the VR chip reaches the preset maximum edge rate as the third resistance value;
  • the fourth resistance value determining module is used to obtain the value of the pull-up resistance when the VR chip reaches the preset minimum edge rate as the fourth resistance value;
  • the second prompt information output module is configured to output second prompt information when it is determined that the actual resistance value of the pull-up resistor is lower than the third resistance value or higher than the fourth resistance value.
  • the fifth resistance value determining module is used to obtain the value of the pull-up resistance when the power loss of the pull-up resistance reaches a preset loss threshold, as the fifth resistance value;
  • the third prompt information output module is configured to output third prompt information when it is determined that the actual resistance value of the pull-up resistor is lower than the fifth resistance value.
  • the resistance value selection range display module is used to determine the resistance value selection range by using the first resistance value, the second resistance value, the third resistance value, the fourth resistance value and the fifth resistance value and display the resistance value selection range;
  • the value is greater than or equal to the first resistance value, and greater than or equal to the second resistance value, and greater than or equal to the third resistance value, and greater than or equal to the fifth resistance value, and less than or equal to the fourth resistance value. resistance.
  • the embodiments of the present invention also provide a device and a computer-readable storage medium for detecting the rationality of the power-on sequence of the PG pin, which can be cross-referenced with the above.
  • FIG. 7 is a schematic diagram of the structure of a detection device for PG pin power-on sequence rationality, including:
  • the memory 701 is used to store computer programs
  • the processor 702 is configured to execute a computer program to implement the steps of the method for detecting the rationality of the power-on sequence of the PG pin in any of the foregoing embodiments.
  • a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the method for detecting the rationality of the power-on sequence of the PG pin in any of the foregoing embodiments are implemented.
  • the computer-readable storage medium mentioned here includes random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, Or any other form of storage medium known in the technical field.

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Abstract

一种PG引脚上电时序合理性的检测方法、系统及相关组件，包括：获取VR芯片的PG引脚的上拉电平（S101）；确定出当上拉电平注入到VR芯片中的电流值等于VR芯片的最大耐受电流时，PG引脚的上拉电阻的取值，作为第一电阻值（S102）；获取PG引脚低电平时的对地等效电阻，并基于对地等效电阻计算出当PG引脚的输出电压等于预设的干扰电压限制值时，PG引脚的上拉电阻的取值，作为第二电阻值（S103）；当判断出上拉电阻的实际电阻值低于第一电阻值或者低于第二电阻值时，输出第一提示信息（S104）。应用上述方案，可以确定出VR芯片中的PG引脚上电时序是否合理，避免后续电路误动作。

Description

PG引脚上电时序合理性的检测方法、系统及相关组件
本申请要求于2019年09月29日提交至中国专利局、申请号为201910931266.0、发明名称为“PG引脚上电时序合理性的检测方法、系统及相关组件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及电路技术领域，特别是涉及一种PG引脚上电时序合理性的检测方法、系统及相关组件。
背景技术
电源芯片能否安全可靠地供电对产品的性能来说至关重要，其中，正确的上电时序是电源安全可靠供电的前提。
Power Good信号是VR(Voltage regulator，电源模块)芯片中的一个关键信号，该信号主要有两个作用，其一是向相关控制芯片反馈电源的工作状态，其二是用作其他电源芯片的Enable信号，从而让电源按设计好的时序上电。因此，PG信号如果在上电过程中出现异常，将会影响系统的正常运行。
现有的VR芯片的PG信号引脚通常为open-drain output类型，需要采用外部的上拉电平来实现高电平信号的输出，即在设计时，需要通过上拉电阻将PG信号与上拉电平相连。例如图1为利用TPS563210芯片将12V电压转换为3.3V电压的原理图，其PG信号采用输出P3V3作为上拉电平，上拉电阻PR3通常可以参照芯片引脚的耐受电流，选取为1k阻值的电阻。
图2为图1的芯片数据手册中所示的上电时序，由图2可知，当输出电压Vo上升到正常工作电压90％时，经过1ms左右的延迟后PG输出高电平信号。
图3为实际应用中检测出的时序波形，正常情况下，PG信号应该在b点前一直处于低电平状态，在检测到输出电压到达90％的临界值，再经过约1ms后从c点变为高电平信号。但是，从图3可以看出，实际上PG信 号从a点便开始上升，在到达b点时有了大约1.2V的电压抬升，由于PG信号需要作为后续电路的Enable信号，1.2V可能会高于后续芯片Enable的临界值，即可能会造成后续电路的误动作，进而影响系统的正常运行。
综上所述，如何有效地确定出VR芯片中的PG引脚上电时序是否合理，避免后续电路的误动作，是目前本领域技术人员急需解决的技术问题。
发明内容
本发明的目的是提供一种PG引脚上电时序合理性的检测方法、系统及相关组件，以有效地确定出VR芯片中的PG引脚上电时序是否合理，避免后续电路的误动作。
为解决上述技术问题，本发明提供如下技术方案：
一种PG引脚上电时序合理性的检测方法，包括：
获取VR芯片的PG引脚的上拉电平；
确定出当所述上拉电平注入到所述VR芯片中的电流值等于所述VR芯片的最大耐受电流时，所述PG引脚的上拉电阻的取值，作为第一电阻值；
获取所述PG引脚低电平时的对地等效电阻，并基于所述对地等效电阻计算出当所述PG引脚的输出电压等于预设的干扰电压限制值时，所述PG引脚的上拉电阻的取值，作为第二电阻值；
当判断出所述上拉电阻的实际电阻值低于所述第一电阻值或者低于所述第二电阻值时，输出用于表示所述上拉电阻阻值不合理以及所述PG引脚上电时序存在隐患的第一提示信息。
优选的，还包括：
获取当所述VR芯片达到预设的最大边沿速率时所述上拉电阻的取值，作为第三电阻值；
获取当所述VR芯片达到预设的最小边沿速率时所述上拉电阻的取值，作为第四电阻值；
当判断出所述上拉电阻的实际电阻值低于所述第三电阻值或者高于所述第四电阻值时，输出第二提示信息。
优选的，还包括：
获取当所述上拉电阻的功率损耗达到预设的损耗阈值时所述上拉电阻的取值，作为第五电阻值；
当判断出所述上拉电阻的实际电阻值低于所述第五电阻值时，输出第三提示信息。
优选的，还包括：
利用所述第一电阻值，所述第二电阻值，所述第三电阻值，所述第四电阻值以及所述第五电阻值确定出阻值选择范围并进行所述阻值选择范围的显示；
其中，针对所述阻值选择范围中的任意数值，该数值大于等于所述第一电阻值，且大于等于所述第二电阻值，且大于等于所述第三电阻值，且大于等于所述第五电阻值，且小于等于所述第四电阻值。
一种PG引脚上电时序合理性的检测系统，包括：
上拉电平获取模块，用于获取VR芯片的PG引脚的上拉电平；
第一电阻值确定模块，用于确定出当所述上拉电平注入到所述VR芯片中的电流值等于所述VR芯片的最大耐受电流时，所述PG引脚的上拉电阻的取值，作为第一电阻值；
第二电阻值确定模块，用于获取所述PG引脚低电平时的对地等效电阻，并基于所述对地等效电阻计算出当所述PG引脚的输出电压等于预设的干扰电压限制值时，所述PG引脚的上拉电阻的取值，作为第二电阻值；
第一提示信息输出模块，用于当判断出所述上拉电阻的实际电阻值低于所述第一电阻值或者低于所述第二电阻值时，输出用于表示所述上拉电阻阻值不合理以及所述PG引脚上电时序存在隐患的第一提示信息。
优选的，还包括：
第三电阻值确定模块，用于获取当所述VR芯片达到预设的最大边沿速率时所述上拉电阻的取值，作为第三电阻值；
第四电阻值确定模块，用于获取当所述VR芯片达到预设的最小边沿速率时所述上拉电阻的取值，作为第四电阻值；
第二提示信息输出模块，用于当判断出所述上拉电阻的实际电阻值低 于所述第三电阻值或者高于所述第四电阻值时，输出第二提示信息。
优选的，还包括：
第五电阻值确定模块，用于获取当所述上拉电阻的功率损耗达到预设的损耗阈值时所述上拉电阻的取值，作为第五电阻值；
第三提示信息输出模块，用于当判断出所述上拉电阻的实际电阻值低于所述第五电阻值时，输出第三提示信息。
优选的，还包括：
阻值选择范围显示模块，用于利用所述第一电阻值，所述第二电阻值，所述第三电阻值，所述第四电阻值以及所述第五电阻值确定出阻值选择范围并进行所述阻值选择范围的显示；
其中，针对所述阻值选择范围中的任意数值，该数值大于等于所述第一电阻值，且大于等于所述第二电阻值，且大于等于所述第三电阻值，且大于等于所述第五电阻值，且小于等于所述第四电阻值。
一种PG引脚上电时序合理性的检测设备，包括：
存储器，用于存储计算机程序；
处理器，用于执行所述计算机程序以实现上述任一项所述的PG引脚上电时序合理性的检测方法的步骤。
一种计算机可读存储介质，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现上述任一项所述的PG引脚上电时序合理性的检测方法的步骤。
申请人分析PG信号的波形上升趋势，考虑到该波形的上升趋势与上拉电平P3V3的趋势基本一致，因此考虑到是PG引脚在低电平时存在着分压情况，即PG信号为低电平时存在着对地的等效电阻。当该对地等效电阻较大时，或者上拉电阻的阻值较低时，由于对地等效电阻对上拉电平的分压，使得在PG引脚为低电平时，PG引脚的输出VOUT也可能较高，进而可能会扰乱正确的上电时序，导致后续电路的误动作。因此，在设定以及选取上拉电阻的电阻值时，应当要考虑上拉电阻的阻值是否过低，从而引起PG引脚上电时序不合理的情况。
具体的，本申请确定出当上拉电平注入到VR芯片中的电流值等于VR 芯片的最大耐受电流时，PG引脚的上拉电阻的取值，作为第一电阻值。第一电阻即表示在保证上拉电平注入到VR芯片中的电流值小于等于VR芯片的最大耐受电流时，上拉电阻的最小取值。同时，本申请获取了PG引脚低电平时的对地等效电阻，并基于对地等效电阻计算出当PG引脚的输出电压等于预设的干扰电压限制值时，PG引脚的上拉电阻的取值，作为第二电阻值。第二电阻即表示在避免造成后续电路的误动作时上拉电阻的最小取值。因此，当判断出上拉电阻的实际电阻值低于第一电阻值或者低于第二电阻值时，输出第一提示信息。因此，本申请的方案可以有效地确定出VR芯片中的PG引脚上电时序是否合理，避免后续电路的误动作。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为利用TPS563210芯片将12V电压转换为3.3V电压的原理图；
图2为图1的芯片数据手册中所示的上电时序示意图；
图3为图1的芯片实际应用中检测出的时序波形示意图；
图4为本发明中一种PG引脚上电时序合理性的检测方法的实施流程图；
图5为本发明一种具体实施方式中进行了上拉电阻的阻值调整后的时序波形示意图；
图6为本发明中一种PG引脚上电时序合理性的检测系统的结构示意图；
图7为本发明中一种PG引脚上电时序合理性的检测设备的结构示意图。
具体实施方式
本发明的核心是提供一种PG引脚上电时序合理性的检测方法，可以有效地确定出VR芯片中的PG引脚上电时序是否合理，避免后续电路的误动作。
为了使本技术领域的人员更好地理解本发明方案，下面结合附图和具体实施方式对本发明作进一步的详细说明。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
针对VR芯片中的PG引脚上电时序异常的情况，申请人首先验证是否是由于外部干扰导致的异常，具体的，采用了电路板割线处理，即，断开PG信号与后续电路的连接。但经过测试之后，上述异常情况依然存在，便可以排除外部干扰的影响，进而可以确定问题出于电压转换电路本身。
申请人进一步地分析PG信号的波形上升趋势，考虑到该波形的上升趋势与上拉电平P3V3的趋势基本一致。需要说明的是，图3中虽然未示出上拉电平P3V3的波形上升趋势，但上拉电平P3V3的波形上升趋势与VOUT的波形上升趋势基本相同。因此，申请人考虑到是PG引脚在低电平时存在着分压情况。即PG信号为低电平时存在着对地的等效电阻。当该对地等效电阻较大时，或者上拉电阻的阻值较低时，由于对地等效电阻对上拉电平的分压，使得在PG引脚为低电平时，PG引脚的输出VOUT也可能较高，例如图3中达到了1.2V，进而可能会扰乱正确的上电时序，导致后续电路的误动作。
请参考图4，图4为本发明中一种PG引脚上电时序合理性的检测方法的实施流程图，可以包括以下步骤：
步骤S101：获取VR芯片的PG引脚的上拉电平。
不同的VR芯片可以采用不同的上拉电平，通常，可以通过读取VR芯片的参数列表从而获取PG引脚的上拉电平，当然，也可以由相关工作人员通过输入装置进行上拉电平的输入，使得进行PG引脚上电时序合理性的检测系统可以获取到PG引脚的上拉电平。
步骤S102：确定出当上拉电平注入到VR芯片中的电流值等于VR芯片 的最大耐受电流时，PG引脚的上拉电阻的取值，作为第一电阻值。
可以理解的是，上拉电阻的取值会影响注入至VR芯片中的电流，并且上拉电阻的取值越大，注入的电流越低，反之，上拉电阻的取值越低，注入的电流越高。而对于具体的VR芯片而言，该VR芯片具有其设定的最大耐受电流，因此，上拉电阻不能设置地过低，即，上拉电阻的取值，需要保证上拉电平注入到VR芯片中的电流值小于等于VR芯片的最大耐受电流，满足这一指标的最小的上拉电阻的取值也就是本申请描述的第一电阻值。
例如，当上拉电平为3.3V，上拉电阻的阻值如果为400Ω，此时注入到VR芯片中的电流值等于VR芯片的最大耐受电流时，则400Ω便是本申请描述的第一电阻值。在后续进行上拉电阻的阻值选取以及调整时，需要将阻值设置为至少400欧姆。
还需要说明的是，由于传统方案中通常也是通过考虑VR芯片的最大耐受电流来划定上拉电阻的取值范围，因此，步骤S102可以参照相关的现有技术，从而计算出满足耐受电流这一指标的上拉电阻的临界值，即第一电阻值。
步骤S103：获取PG引脚低电平时的对地等效电阻，并基于对地等效电阻计算出当PG引脚的输出电压等于预设的干扰电压限制值时，PG引脚的上拉电阻的取值，作为第二电阻值。
对地等效电阻的获取方式可以有多种，例如，可以获取VR芯片参数表中的数据，例如获取到当PG＝0.5V时，PG引脚的灌电流为0.5mA-1mA，则可以确定PG引脚低电平时的对地等效电阻的范围为500-1000Ω，进而例如可以取中间值750欧姆作为获取到的对地等效电阻。又如考虑到是由于对地等效电阻的分压导致的PG引脚上电时序出错，则可以取最大值1000欧姆作为获取到的对地等效电阻，使得后续计算出的对地等效电阻的分压不会低于其实际的分压。
又如，在另一种实施方式中，可以获取VR芯片的实际上电时序，进而确定出PG引脚低电平时的对地等效电阻。具体的，例如在图3的实施例中，该VR芯片的上拉电平为3.3V，而PG引脚低电平时的分压为1.2V，上拉电 阻的实际阻值为1000Ω，则PG引脚低电平时的对地等效电阻＝1000*1.2/(3.3-1.2)＝572Ω。即PG引脚低电平时的对地等效电阻/上拉电阻＝PG引脚低电平时的输出电压/(上拉电平-PG引脚低电平时的输出电压)。
获取了PG引脚低电平时的对地等效电阻之后，便可以基于对地等效电阻计算出当PG引脚的输出电压等于预设的干扰电压限制值时，PG引脚的上拉电阻的取值，本申请将该取值记为第二电阻值。
干扰电压限制值指的是在PG引脚低电平时，所允许的PG引脚输出的最大电压值，例如通常为200mv。也就是说，当PG引脚低电平时，输出电压低于200mv，不会造成后续电路的误动作。当然，其他实施方式中干扰电压限制值可以有其他具体取值。
仍以对地等效电阻为572Ω，上拉电平为3.3V为例，当干扰电压限制值为200mv时，572/上拉电阻的取值＝0.2/3.3，即该具体实施例中，上拉电阻的取值＝572*3.3/0.2＝9438Ω，即第二电阻值为9438Ω。表示的是只有上拉电阻的取值大于等于9438Ω，PG引脚低电平时其输出端的电压才会低于干扰电压限制值200mv，从而不会造成后续电路的误动作。
还需要说明的是，在PG引脚低电平时，VR芯片通常会控制芯片内部的相关开关电路导通，即使得PG引脚接地。而接地的PG引脚会有较大的等效电阻，通常是由于在实际应用中，开关电路未必是由单个开关管，例如单个MOS构成，可能是由相关电路构成一个开关的功能，导致在PG引脚低电平时也有较大的对地等效电阻。当然，在其他具体场合中也可以是由于其他类型的原因导致的PG引脚接地时还存在较大的对地等效电阻。对地等效电阻较大，使得PG引脚低电平时也可能引起后续电路的误动作，这就是导致本申请描述的PG引脚上电时序不合理的原因所在。
步骤S104：当判断出上拉电阻的实际电阻值低于第一电阻值或者低于第二电阻值时，输出用于表示上拉电阻阻值不合理以及PG引脚上电时序存在隐患的第一提示信息。
当判断出上拉电阻的实际电阻值低于第一电阻值时，说明上拉电平流入VR芯片的电流可能会超过VR芯片的耐受电流。上拉电阻的实际电阻值低于第二电阻值时，在PG引脚低电平时也可能会引起后续电路的误动作。 也就是说，上拉电阻的实际电阻值高于第一电阻值且高于第二电阻值，才是合理的上拉电阻的阻值，才不会输出第一提示信息。
当然，无论是VR芯片的电流超过VR芯片的耐受电流，还是PG引脚低电平时导致的后续电路的误动作，均可以确定PG引脚上电时序存在隐患。因此，第一提示信息用于表示上拉电阻阻值不合理以及PG引脚上电时序存在隐患，以提示相关人员注意到该情况，进而可以及时进行上拉电阻的阻值调整。当然，此处描述的调整可以是在电路设计阶段便进行调整，也可以是对实际生产出的硬件电路进行调整，但通常来说是在设计阶段进行的调整。
申请人分析PG信号的波形上升趋势，考虑到该波形的上升趋势与上拉电平P3V3的趋势基本一致，因此考虑到是PG引脚在低电平时存在着分压情况，即PG信号为低电平时存在着对地的等效电阻。当该对地等效电阻较大时，或者上拉电阻的阻值较低时，由于对地等效电阻对上拉电平的分压，使得在PG引脚为低电平时，PG引脚的输出VOUT也可能较高，进而可能会扰乱正确的上电时序，导致后续电路的误动作。因此，在设定以及选取上拉电阻的电阻值时，应当要考虑上拉电阻的阻值是否过低，从而引起PG引脚上电时序不合理的情况。
具体的，本申请确定出当上拉电平注入到VR芯片中的电流值等于VR芯片的最大耐受电流时，PG引脚的上拉电阻的取值，作为第一电阻值。第一电阻即表示在保证上拉电平注入到VR芯片中的电流值小于等于VR芯片的最大耐受电流时，上拉电阻的最小取值。同时，本申请获取了PG引脚低电平时的对地等效电阻，并基于对地等效电阻计算出当PG引脚的输出电压等于预设的干扰电压限制值时，PG引脚的上拉电阻的取值，作为第二电阻值。第二电阻即表示在避免造成后续电路的误动作时上拉电阻的最小取值。因此，当判断出上拉电阻的实际电阻值低于第一电阻值或者低于第二电阻值时，输出第一提示信息。因此，本申请的方案可以有效地确定出VR芯片中的PG引脚上电时序是否合理，避免后续电路的误动作。
在本发明的一种具体实施方式中，还可以包括：
获取当VR芯片达到预设的最大边沿速率时上拉电阻的取值，作为第三 电阻值；
获取当VR芯片达到预设的最小边沿速率时上拉电阻的取值，作为第四电阻值；
当判断出上拉电阻的实际电阻值低于第三电阻值或者高于第四电阻值时，输出第二提示信息。
前述实施方式中，针对上拉电阻的阻值考虑了两个指标，其一是保证了流入VR芯片的电流在VR芯片的耐受范围内，其二是避免PG引脚在低电平时电压过高引起的后续电路的误动作。该种实施方式中，进一步地考虑到，上拉电阻的阻值会影响信号的边沿速率。
具体的，当上拉电阻的阻值越高时，信号的边沿速率越低，相应的，上拉电阻的阻值越低时，信号的边沿速率越高。而VR芯片通常会预设有最大边沿速率和最小边沿速率，因此本申请的该种实施方式中计算出第三电阻值和第四电阻值。即当上拉电阻的实际电阻值大于等于第三电阻值且小于等于第四电阻时，说明满足边沿速率这一指标，相应的，当判断出上拉电阻的实际电阻值低于第三电阻值或者高于第四电阻值时，便可以输出第二提示信息，以提示相关人员注意到该情况，进而可以及时进行上拉电阻的阻值调整。
在本发明的一种具体实施方式中，还包括：
获取当上拉电阻的功率损耗达到预设的损耗阈值时上拉电阻的取值，作为第五电阻值；
当判断出上拉电阻的实际电阻值低于第五电阻值时，输出第三提示信息。
除了前述实施例中描述的三个指标之外，该种实施方式中还考虑到了上拉电阻的功率损耗。具体的，上拉电阻的电阻值越低，上拉电阻的功率损耗越大，当判断出上拉电阻的实际电阻值低于第五电阻值时，说明上拉电阻的功率损耗会高于损耗阈值，因此输出第三提示信息。以提示相关人员注意到该功率损耗过高的情况。
进一步的，在一种具体实施方式中，还可以包括：
利用第一电阻值，第二电阻值，第三电阻值，第四电阻值以及第五电 阻值确定出阻值选择范围并进行阻值选择范围的显示；
其中，针对阻值选择范围中的任意数值，该数值大于等于第一电阻值，且大于等于第二电阻值，且大于等于第三电阻值，且大于等于第五电阻值，且小于等于第四电阻值。
也就是说，该种实施方式中，确定出满足上述实施例中描述的四个指标的阻值选择范围，上拉电阻可以根据实际需要，在该阻值选择范围中进行选取。并且，本申请将阻值选择范围显示出来，有利于工作人员直观地看出该范围进而进行上拉电阻的阻值设定和调整，例如针对图1的实施方式，将上拉电阻的阻值从1000欧姆调整为10000欧姆，调整之后的时序波形可参阅图5，可以看出，PG信号的台阶变为了168mv，在输出电压到达90％的临界值，再经过约1ms后，PG信号才从168mv开始上升，满足了PG引脚上电时序的要求。
还需要说明的是，通常情况下都能够确定出满足上述四个指标的阻值选择范围，在极少的场合中，可能会出现无法同时满足四个指标的情况，此时也可以输出提示信息，以使得工作人员根据各个指标的重要性进行权衡，以选取出优选的上拉电阻的电阻值。例如优先要保障上拉电阻的取值需要大于等于第一电阻值且大于第二电阻值，其次考虑要大于等于第三电阻值且小于等于第四电阻值，最后考虑要满足大于等于第五电阻值这一条件。
相应于上面的方法实施例，本发明实施例还提供了一种PG引脚上电时序合理性的检测系统，可与上文相互对应参照。
参见图6所示，为本发明中一种PG引脚上电时序合理性的检测系统的结构示意图，包括：
上拉电平获取模块601，用于获取VR芯片的PG引脚的上拉电平；
第一电阻值确定模块602，用于确定出当上拉电平注入到VR芯片中的电流值等于VR芯片的最大耐受电流时，PG引脚的上拉电阻的取值，作为第一电阻值；
第二电阻值确定模块603，用于获取PG引脚低电平时的对地等效电阻，并基于对地等效电阻计算出当PG引脚的输出电压等于预设的干扰电压限 制值时，PG引脚的上拉电阻的取值，作为第二电阻值；
第一提示信息输出模块604，用于当判断出上拉电阻的实际电阻值低于第一电阻值或者低于第二电阻值时，输出用于表示上拉电阻阻值不合理以及PG引脚上电时序存在隐患的第一提示信息。
在本发明的一种具体实施方式中，还包括：
第三电阻值确定模块，用于获取当VR芯片达到预设的最大边沿速率时上拉电阻的取值，作为第三电阻值；
第四电阻值确定模块，用于获取当VR芯片达到预设的最小边沿速率时上拉电阻的取值，作为第四电阻值；
第二提示信息输出模块，用于当判断出上拉电阻的实际电阻值低于第三电阻值或者高于第四电阻值时，输出第二提示信息。
在本发明的一种具体实施方式中，还包括：
第五电阻值确定模块，用于获取当上拉电阻的功率损耗达到预设的损耗阈值时上拉电阻的取值，作为第五电阻值；
第三提示信息输出模块，用于当判断出上拉电阻的实际电阻值低于第五电阻值时，输出第三提示信息。
在本发明的一种具体实施方式中，还包括：
阻值选择范围显示模块，用于利用第一电阻值，第二电阻值，第三电阻值，第四电阻值以及第五电阻值确定出阻值选择范围并进行阻值选择范围的显示；
其中，针对阻值选择范围中的任意数值，该数值大于等于第一电阻值，且大于等于第二电阻值，且大于等于第三电阻值，且大于等于第五电阻值，且小于等于第四电阻值。
相应于上面的方法和系统实施例，本发明实施例还提供了一种PG引脚上电时序合理性的检测设备以及计算机可读存储介质，可与上文相互对应参照。
参阅图7，为一种PG引脚上电时序合理性的检测设备的结构示意图，包括：
存储器701，用于存储计算机程序；
处理器702，用于执行计算机程序以实现上述任一实施例中的PG引脚上电时序合理性的检测方法的步骤。
计算机可读存储介质上存储有计算机程序，计算机程序被处理器执行时实现上述任一实施例中的PG引脚上电时序合理性的检测方法的步骤。这里所说的计算机可读存储介质包括随机存储器(RAM)、内存、只读存储器(ROM)、电可编程ROM、电可擦除可编程ROM、寄存器、硬盘、可移动磁盘、CD-ROM、或技术领域内所公知的任意其它形式的存储介质。
专业人员还可以进一步意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的技术方案及其核心思想。应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以对本发明进行若干改进和修饰，这些改进和修饰也落入本发明权利要求的保护范围内。

Claims (10)

  1. 一种PG引脚上电时序合理性的检测方法，其特征在于，包括：
    获取VR芯片的PG引脚的上拉电平；
    确定出当所述上拉电平注入到所述VR芯片中的电流值等于所述VR芯片的最大耐受电流时，所述PG引脚的上拉电阻的取值，作为第一电阻值；
    获取所述PG引脚低电平时的对地等效电阻，并基于所述对地等效电阻计算出当所述PG引脚的输出电压等于预设的干扰电压限制值时，所述PG引脚的上拉电阻的取值，作为第二电阻值；
    当判断出所述上拉电阻的实际电阻值低于所述第一电阻值或者低于所述第二电阻值时，输出用于表示所述上拉电阻阻值不合理以及所述PG引脚上电时序存在隐患的第一提示信息。
  2. 根据权利要求1所述的PG引脚上电时序合理性的检测方法，其特征在于，还包括：
    获取当所述VR芯片达到预设的最大边沿速率时所述上拉电阻的取值，作为第三电阻值；
    获取当所述VR芯片达到预设的最小边沿速率时所述上拉电阻的取值，作为第四电阻值；
    当判断出所述上拉电阻的实际电阻值低于所述第三电阻值或者高于所述第四电阻值时，输出第二提示信息。
  3. 根据权利要求2所述的PG引脚上电时序合理性的检测方法，其特征在于，还包括：
    获取当所述上拉电阻的功率损耗达到预设的损耗阈值时所述上拉电阻的取值，作为第五电阻值；
    当判断出所述上拉电阻的实际电阻值低于所述第五电阻值时，输出第三提示信息。
  4. 根据权利要求3所述的PG引脚上电时序合理性的检测方法，其特征在于，还包括：
    利用所述第一电阻值，所述第二电阻值，所述第三电阻值，所述第四 电阻值以及所述第五电阻值确定出阻值选择范围并进行所述阻值选择范围的显示；
    其中，针对所述阻值选择范围中的任意数值，该数值大于等于所述第一电阻值，且大于等于所述第二电阻值，且大于等于所述第三电阻值，且大于等于所述第五电阻值，且小于等于所述第四电阻值。
  5. 一种PG引脚上电时序合理性的检测系统，其特征在于，包括：
    上拉电平获取模块，用于获取VR芯片的PG引脚的上拉电平；
    第一电阻值确定模块，用于确定出当所述上拉电平注入到所述VR芯片中的电流值等于所述VR芯片的最大耐受电流时，所述PG引脚的上拉电阻的取值，作为第一电阻值；
    第二电阻值确定模块，用于获取所述PG引脚低电平时的对地等效电阻，并基于所述对地等效电阻计算出当所述PG引脚的输出电压等于预设的干扰电压限制值时，所述PG引脚的上拉电阻的取值，作为第二电阻值；
    第一提示信息输出模块，用于当判断出所述上拉电阻的实际电阻值低于所述第一电阻值或者低于所述第二电阻值时，输出用于表示所述上拉电阻阻值不合理以及所述PG引脚上电时序存在隐患的第一提示信息。
  6. 根据权利要求5所述的PG引脚上电时序合理性的检测系统，其特征在于，还包括：
    第三电阻值确定模块，用于获取当所述VR芯片达到预设的最大边沿速率时所述上拉电阻的取值，作为第三电阻值；
    第四电阻值确定模块，用于获取当所述VR芯片达到预设的最小边沿速率时所述上拉电阻的取值，作为第四电阻值；
    第二提示信息输出模块，用于当判断出所述上拉电阻的实际电阻值低于所述第三电阻值或者高于所述第四电阻值时，输出第二提示信息。
  7. 根据权利要求6所述的PG引脚上电时序合理性的检测系统，其特征在于，还包括：
    第五电阻值确定模块，用于获取当所述上拉电阻的功率损耗达到预设的损耗阈值时所述上拉电阻的取值，作为第五电阻值；
    第三提示信息输出模块，用于当判断出所述上拉电阻的实际电阻值低 于所述第五电阻值时，输出第三提示信息。
  8. 根据权利要求7所述的PG引脚上电时序合理性的检测系统，其特征在于，还包括：
    阻值选择范围显示模块，用于利用所述第一电阻值，所述第二电阻值，所述第三电阻值，所述第四电阻值以及所述第五电阻值确定出阻值选择范围并进行所述阻值选择范围的显示；
    其中，针对所述阻值选择范围中的任意数值，该数值大于等于所述第一电阻值，且大于等于所述第二电阻值，且大于等于所述第三电阻值，且大于等于所述第五电阻值，且小于等于所述第四电阻值。
  9. 一种PG引脚上电时序合理性的检测设备，其特征在于，包括：
    存储器，用于存储计算机程序；
    处理器，用于执行所述计算机程序以实现如权利要求1至4任一项所述的PG引脚上电时序合理性的检测方法的步骤。
  10. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1至4任一项所述的PG引脚上电时序合理性的检测方法的步骤。
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