WO2021052498A1 - 一种半导体外延结构及其应用与制造方法 - Google Patents

一种半导体外延结构及其应用与制造方法 Download PDF

Info

Publication number
WO2021052498A1
WO2021052498A1 PCT/CN2020/116501 CN2020116501W WO2021052498A1 WO 2021052498 A1 WO2021052498 A1 WO 2021052498A1 CN 2020116501 W CN2020116501 W CN 2020116501W WO 2021052498 A1 WO2021052498 A1 WO 2021052498A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
substrate
semiconductor
gallium nitride
semiconductor layer
Prior art date
Application number
PCT/CN2020/116501
Other languages
English (en)
French (fr)
Inventor
陈卫军
刘美华
Original Assignee
深圳市晶相技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市晶相技术有限公司 filed Critical 深圳市晶相技术有限公司
Publication of WO2021052498A1 publication Critical patent/WO2021052498A1/zh
Priority to US17/698,013 priority Critical patent/US20220223759A1/en

Links

Images

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C23C14/35—Sputtering by application of a magnetic field, e.g. magnetron sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/0617—AIII BV compounds, where A is Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C23C14/3407—Cathode assembly for sputtering apparatus, e.g. Target
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/50—Substrate holders
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/50—Substrate holders
    • C23C14/505—Substrate holders for rotation of the substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/54—Controlling or regulating the coating process
    • C23C14/541—Heating or cooling of the substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/54—Controlling or regulating the coating process
    • C23C14/542—Controlling the film thickness or evaporation rate
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/56—Apparatus specially adapted for continuous coating; Arrangements for maintaining the vacuum, e.g. vacuum locks
    • C23C14/564—Means for minimising impurities in the coating chamber such as dust, moisture, residual gases
    • C23C14/566—Means for minimising impurities in the coating chamber such as dust, moisture, residual gases using a load-lock chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the present disclosure relates to the field of semiconductors, and in particular to a semiconductor epitaxial structure and its application and manufacturing method.
  • the third-generation semiconductor materials such as gallium nitride or silicon carbide, have the advantages of large forbidden band width, high electron saturation rate, high breakdown electric field, high thermal conductivity, corrosion resistance and radiation resistance, they can be used as semiconductor materials , And obtain the semiconductor epitaxial structure.
  • the present disclosure proposes a semiconductor epitaxial structure to reduce the lattice mismatch between gallium nitride and silicon and improve the quality of the semiconductor epitaxial structure.
  • the semiconductor epitaxial structure includes:
  • the first aluminum gallium nitride layer is formed on the aluminum nitride layer
  • the second aluminum gallium nitride layer is formed on the first aluminum gallium nitride layer
  • the aluminum content of the first aluminum gallium nitride layer is higher than the aluminum content of the second aluminum gallium nitride layer.
  • the X value of the first aluminum gallium nitride layer (Al x Ga 1-x N) is greater than that of the second aluminum gallium nitride layer (Al Y Ga 1-Y N). Value.
  • the gallium nitride layer includes a first gallium nitride layer, a second gallium nitride layer, and a third gallium nitride layer.
  • the thickness of the first aluminum gallium nitride layer or the second aluminum gallium nitride layer is 600-1200 nanometers.
  • the present disclosure also provides a semiconductor device including the semiconductor epitaxial structure described above.
  • the present disclosure also provides an electronic device, which is characterized by comprising the above-mentioned semiconductor device.
  • a method for manufacturing a semiconductor epitaxial structure includes the steps:
  • the aluminum content of the first aluminum gallium nitride layer is higher than the aluminum content of the second aluminum gallium nitride layer.
  • the present disclosure proposes a semiconductor epitaxial structure and its application and manufacturing method, which can obtain a high-quality epitaxial structure, can improve the withstand voltage and have higher withstand voltage performance, and improve the quality of the semiconductor epitaxial structure.
  • Figure 1 A schematic diagram of the growth chamber proposed in this embodiment.
  • Figure 2 Another schematic diagram of the base in this embodiment.
  • Figure 3 Schematic diagram of the back of the base in this embodiment.
  • Figure 4 A schematic diagram of the heater in this embodiment.
  • Figure 5 Another schematic diagram of the heater in this embodiment.
  • FIG. 6 A brief schematic diagram of the temperature measuring device in this embodiment.
  • Figure 7 A schematic diagram of the magnet in this embodiment.
  • Figure 8 Another schematic diagram of the magnet in this embodiment.
  • Figure 9 Another schematic diagram of the magnet in this embodiment.
  • Figure 10 A schematic diagram of the reflector in this embodiment.
  • Figure 11 A schematic diagram of the clamp in this embodiment.
  • Figure 12 A schematic diagram of the cooling device in this embodiment.
  • Figure 13 A schematic diagram of the air inlet in this embodiment.
  • Figure 14 A schematic diagram of the intake duct in this embodiment.
  • Figure 15 A schematic diagram of the bottom of the intake duct in this embodiment.
  • Figure 16 Another schematic diagram of the air inlet in this embodiment.
  • Figure 17 Another schematic diagram of the air inlet in this embodiment.
  • Figure 18 Another schematic diagram of the air inlet in this embodiment.
  • Figure 19 Another schematic diagram of the air inlet in this embodiment.
  • Fig. 20 A schematic diagram of the semiconductor device proposed in this embodiment.
  • Figure 21 A schematic diagram of the transition cavity in this embodiment.
  • Figure 22 A schematic diagram of the cooling plate in this embodiment.
  • Figure 23 A schematic diagram of the base in this embodiment.
  • Figure 24 A schematic diagram of the carrier and the tray in this embodiment.
  • Figure 25 A schematic diagram of the cleaning cavity in this embodiment.
  • Figure 26 A schematic diagram of the lifting and rotating mechanism in this embodiment.
  • Figure 27 Another schematic diagram of the cleaning cavity in this embodiment.
  • Figure 28 A schematic diagram of the bushing and coil assembly in this embodiment.
  • Figure 29 A schematic diagram of the preheating cavity in this embodiment.
  • Figure 30 A schematic diagram of the heater in this embodiment.
  • Figure 31 A schematic diagram of the heating coil in this embodiment.
  • Figure 32 A brief schematic diagram of the temperature measurement points in this embodiment.
  • Fig. 33 A flowchart of the method of using the semiconductor device in this embodiment.
  • Figure 34 Analysis diagram of aluminum nitride coating in this embodiment.
  • Figure 35 Electron micrograph of the aluminum nitride film in this embodiment.
  • Fig. 36 A rocking curve diagram of the aluminum nitride film in this embodiment.
  • Fig. 37 A diagram of a semiconductor epitaxial structure in this embodiment.
  • Fig. 39 A diagram of another semiconductor epitaxial structure in this embodiment.
  • Fig. 40 A diagram of another semiconductor epitaxial structure in this embodiment.
  • Figure 41 A structural diagram of a light-emitting diode in this embodiment.
  • Fig. 42 A diagram of another semiconductor epitaxial structure in this embodiment.
  • Fig. 43 A structural diagram of a semiconductor power device in this embodiment.
  • Fig. 44 A structural diagram of a semiconductor work epitaxy in this embodiment.
  • Figure 45 A structural diagram of a semiconductor work epitaxy in this embodiment
  • Fig. 46 A structural diagram of a light-emitting diode in this embodiment.
  • Fig. 47 to Fig. 51 Formation diagrams of a micro light emitting diode in this embodiment.
  • Fig. 52 to Fig. 58 Formation diagrams of a micro light emitting diode chip in this embodiment.
  • Fig. 59 to Fig. 68 Forming diagrams of another micro light emitting diode chip in this embodiment.
  • Fig. 69 to Fig. 76 Formation diagrams of a micro light emitting diode panel in this embodiment.
  • Fig. 77 to Fig. 83 the formation diagram of another micro light emitting diode panel in this embodiment.
  • Fig. 84 A structural diagram of a micro light emitting diode panel in this embodiment.
  • Fig. 85 A structural block diagram of an electronic device in this embodiment.
  • Fig. 86 A structural diagram of a semiconductor device in this embodiment.
  • Figure 87 A block diagram of a radio frequency module in this embodiment.
  • Fig. 88 A structural diagram of another semiconductor device in this embodiment.
  • Figure 89 Block diagram of another radio frequency module in this embodiment.
  • Fig. 90 A structural diagram of another semiconductor device in this embodiment.
  • Figure 91 A block diagram of another radio frequency module in this embodiment.
  • Fig. 92 A structural diagram of another semiconductor device in this embodiment.
  • FIG. 93 A block diagram of another radio frequency module in this embodiment.
  • this embodiment provides a semiconductor device 100 which includes a growth chamber 110, a base 111, a target 123 and a magnet 122.
  • the susceptor 111 is arranged in the growth chamber 110.
  • the susceptor 111 can be arranged at the bottom end of the growth chamber 110.
  • One or more substrates 112 (for example, four, six or more) are allowed to be placed on the susceptor 111.
  • the diameter of the base 111 may range from 200 mm to 800 mm, for example.
  • the size of the base 111 is, for example, 2-12 inches.
  • the susceptor 111 may be formed of a variety of materials, including silicon carbide or graphite coated with silicon carbide.
  • the material of the substrate 112 may include sapphire, silicon carbide, silicon, gallium nitride, diamond, lithium aluminate, zinc oxide, tungsten, copper, and/or aluminum gallium nitride.
  • the substrate 112 may also be, for example, soda lime glass and/or High silica glass.
  • the substrate 112 may be composed of the following materials: materials with compatible lattice constants and thermal expansion coefficients, substrates compatible with the III-V materials grown on them, or thermally stable and chemically stable at III-V growth temperatures. Warm substrate.
  • the size of the substrate 112 may range from 50 mm to 100 mm (or more) in diameter.
  • the substrate 112 may be a silicon substrate, and a metal compound film may be formed on the silicon substrate, such as an aluminum nitride film or a gallium nitride film, such as a (002)-oriented aluminum nitride film.
  • the base 111 is also connected to a drive unit 113, which can be electrically connected to a control unit (not shown).
  • the drive unit 113 is used to drive the base 111 up or down.
  • a drive device such as a motor or a stepping motor.
  • the control unit is used to control the drive unit 113 to drive the base 111 up during the magnetron sputtering process, so that the distance between the target 123 and the base 111 can be maintained at a predetermined value.
  • the predetermined value can be set according to specific needs, so as to obtain the optimal value of the process result such as ideal film uniformity and deposition rate. Therefore, by controlling the driving unit 113 to drive the susceptor 111 to rise during the magnetron sputtering process with the help of the control unit, the target-base spacing can be kept constant, so as to improve the film uniformity and deposition rate, thereby improving the process quality.
  • the control unit can be, for example, a host computer or PLC.
  • the base 111 may also be connected to a rotating unit, which is used to rotate the base 111 during the film deposition, further improving the thickness uniformity of the coating film and the stress uniformity of the coating film.
  • the semiconductor device 100 may further include a load lock chamber, a carrier box, and an optional MOCVD reaction chamber (not shown) for a large number of applications.
  • the target 123 of the semiconductor device 100 can include, but is not limited to, Al-containing metals, alloys, compounds, such as Al, AlN, AlGa, Al 2 O 3, etc., and the target can be, for example, II/IV/VI Group elements are doped to improve layer compatibility and device performance.
  • the sputtering process gas may include, but is not limited to, nitrogen-containing gas such as N 2 , NH 3 , NO 2 , NO, etc., and inert gas such as Ar, Ne, Kr, etc.
  • the semiconductor device of the present disclosure can be used to form a high-quality buffer layer and a III-V family layer device and method, which can be used to form possible semiconductor components, such as Radio frequency components, power components, or other possible components.
  • the middle part of the base 111 may be convex relative to the edge, and the substrate 112 is disposed on the middle part of the base 111, so that a part of the substrate 112 covers the edge area and can be in contact with the edge.
  • the areas are spaced apart.
  • the middle part of the substrate 112 can be cooled by the susceptor 111, and the edges of the substrate 112 will not be directly contacted. Cool down and therefore withstand higher temperatures. This makes the edges of the film layer more stretchable, which again plays a role in the overall change of the stress on the film layer.
  • Fig. 3 shows the back of the base 111.
  • at least one heater may be provided on the back surface of the base 111, wherein the heater may include a plurality of heating electrodes 126 and a heating coil 127, and may also be provided at a position close to the heating electrode 126. 128 temperature measurement points.
  • a plurality of heating electrodes 126 are connected to one heating coil 127.
  • the heating coil 127 may include a first part and a second part. The first part and the second part are connected symmetrically about the center of the heating coil 127.
  • the first part includes the first arc edge 127a from the outside to the inside.
  • the two arc edges 127b and the third arc edge 127c, the first arc edge 127a, the second arc edge 127b and the third arc edge 127c may be concentric circles.
  • One end of the first arc 127a is connected to one end of the second arc 127b
  • the other end of the second arc 127b is connected to the third arc 127c
  • the first part is connected to the second part through the third arc 127c, forming a circular heating coil 127.
  • the other end of the first arc 127a is connected to the heating electrode 126,
  • the heating coil 127 starts to heat the susceptor 111.
  • the heating coil 127 may be arranged on a pyrolytic boron nitride substrate, for example. In some embodiments, in order to further improve the uniformity of heating, the shape and number of turns of the heating coil 127 can be adjusted.
  • the back surface of the base 111 may be provided with 7, 8, or more heating electrodes 126.
  • the heating coil 127 in order to further improve the heating uniformity of the base 111, can be adjusted.
  • the heating coil 127 is formed by bending an enameled wire 127d.
  • the cross section can be round or square or flat. According to actual conditions, the number of turns of the enameled wire 127d can be adjusted, or the heating coil 127 can be set in an asymmetrical shape, or the enameled wire can be made into other shapes.
  • a temperature measuring point 128 may be further provided at a position close to the heating electrode 126, and the temperature measuring point 128 is connected to the temperature measuring device.
  • the temperature measuring point 128 is The device includes a detection circuit 129a and a temperature acquisition module 129b connected in sequence.
  • the detection loop 129a can be composed of conductors of two different materials, for example, and one end (working end) of the detection loop 129a is in contact with the temperature measuring point 128 to generate a pyroelectric signal.
  • the temperature acquisition module 129b is configured to receive the pyroelectric signal through the first detection point and the second detection point at the other end (free end) of the detection loop 129a, and calculate the temperature of the temperature measurement point 128 according to the pyroelectric signal. Since the detection loop 129a is composed of conductors of a variety of different materials, the pyroelectric signal will affect the potential difference between the first detection point and the second detection point. The temperature acquisition module 129b calculates the potential difference between the first detection point and the second detection point. Calculate the temperature at the temperature measurement point 128.
  • the temperature measuring device may be, for example, a thermocouple.
  • thermometers can also be used to measure the temperature on the base 111
  • an infrared thermometer can also be used to measure the temperature on the base 111.
  • the temperature measurement device can know the temperature at each position of the susceptor 111 in real time, which can ensure that the temperature on the susceptor 111 is in a uniform and stable state, and it can also ensure that the substrate 112 on the susceptor 111 is uniform and stable. Temperature environment.
  • the target 123 can be set on the top of the growth chamber 110, and the target 123 is electrically connected to a sputtering power supply (not shown). During the magnetron sputtering process, the sputtering power supply The sputtering power is output to the target 123 so that the plasma formed in the growth chamber 110 etches the target 123.
  • the material of the target 123 is selected from but not limited to the following groups: substantially pure aluminum, aluminum alloy-containing, aluminum-containing compounds (such as AlN, AlGa, Al 2 O 3 ), and doped Aluminum-containing targets with II/IV/VI group elements to improve layer compatibility and device performance.
  • doping atoms can be added to the deposited film by using a doping target material and/or delivering a doping gas to the generated sputtering plasma to adjust the electrical characteristics and mechanical properties of the deposited PVD AlN buffer layer. Characteristics and optical characteristics, for example, to make the thin film suitable for manufacturing III-nitride devices thereon.
  • the thickness of the thin film (for example, the AlN buffer layer) formed in the growth chamber 110 is between 0.1-1000 nanometers.
  • the magnet 122 may be located above the target 123, and the magnet 122 rotates around the central axis of the target 123.
  • the magnet 122 rotates 90° or 180° around the central axis of the target 123 or 360° or any angle, or the magnet 122 can rotate around the center axis of the target 123 by any angle.
  • the magnet 122 is connected to a driving mechanism, and the driving mechanism drives the magnet 122 to rotate while also performing up and down reciprocating motions.
  • the driving mechanism includes a first motor 114, a transmission rod 115, a second motor 116 and a lifting assembly.
  • the first motor 114 is connected to the second motor 116 through the transmission rod 115.
  • the first motor 114 is, for example, a servo motor or a stepping motor.
  • the transmission rod 115 may be, for example, a screw rod
  • the second motor 116 is, for example, a rotary servo motor.
  • a motor 114 can drive the second motor 116 to reciprocate up and down through the transmission rod 115.
  • the first motor 114 drives the transmission rod 115 in a forward or reverse direction to make the second motor 116 reciprocate.
  • the lifting assembly includes an outer shaft 118 and an inner shaft 119.
  • the inner shaft 119 is provided in the outer shaft 118, the inner shaft 119 is allowed to move along the outer shaft 118, and the outer shaft 118 is provided on the growth chamber 110.
  • Part of the inner shaft 119 is set in the growth chamber 110, and a fixing device 121 is also provided on one end of the inner shaft 119.
  • the magnet 122 is fixed on one end of the inner shaft 119 by the fixing device 121, and at the same time, the outer shaft 118 is in contact with the growth chamber.
  • a sealing device 120 is also provided around the body 110 in contact, and vacuum sealing is achieved by the sealing device 120.
  • the sealing device 120 may be, for example, a sealing ring.
  • the second motor 116 is connected to the inner shaft 119 through the output shaft 117, and the output shaft 117 is partially located in the outer shaft 118.
  • the second motor 116 can drive the inner shaft 119 to rotate through the output shaft 117, and the first motor 114 drives the second motor 116 through the transmission rod 115 to reciprocate up and down, so that when the first motor 114 and the second motor 116 are turned on at the same time, the inner shaft 119 can reciprocate up and down while also performing rotational movement. Therefore, the magnet 122 on the inner shaft 119 can be driven to move accordingly.
  • the inner shaft 119 can only reciprocate up and down.
  • the first motor 114 is turned off and the second motor 116 is turned on
  • the inner shaft 119 can only perform rotational movement. Therefore, the worker can choose to turn on and/or turn off the first motor 114 and/or the second motor 116 according to the implementation situation.
  • the target 123 when the magnet 122 is rotating, the target 123 can remain stationary or can rotate around its own central axis, but there may be a rotation speed difference between the target 123 and the magnet 122.
  • the target 123 can be driven to rotate around its own central axis by a power source such as a motor, so that there is a speed difference between the target 123 and the magnet 122.
  • the relative movement of the target 123 and the magnet 122 can make the magnetic field generated by the magnet 122 evenly scan the sputtering surface of the target 123, and since the electric field and the magnetic field uniformly distributed on the sputtering surface of the target 123 in this embodiment are simultaneously Acting on the secondary electrons, the trajectory of the secondary electrons can be adjusted to increase the number of collisions between the secondary electrons and argon atoms, so that the argon atoms near the sputtering surface of the target 123 are fully ionized to generate more argon ions; and By bombarding the target material 123 with more argon ions, the sputtering utilization rate and sputtering uniformity of the target material 123 can be effectively improved, and the quality and uniformity of the deposited film can be further improved.
  • the magnet 122 includes a first part, a second part, and a plurality of third parts, and the plurality of third parts are connected between the first part and the second part.
  • the first part includes a first magnetic unit 1221
  • the second part includes a second magnetic unit 1222, a third magnetic unit 1223 and a fourth magnetic unit 1224
  • the third part includes a fifth magnetic unit 1225, a sixth magnetic unit 1226 and a seventh magnetic unit.
  • Unit 1227 In this embodiment, a plurality of magnetic units are spliced into a symmetrical ring-shaped magnet 122.
  • an arc-shaped magnetic field can be formed, and when the magnet 122 rotates around the target 123, a uniform magnetic field can be formed.
  • the uniform magnetic field can provide the sputtering uniformity of the target material, thereby achieving the uniformity of the coating film.
  • the magnet 122 may also have an arc structure.
  • the magnet 122 includes a first magnetic unit 1221, a second magnetic unit 1222, and a plurality of third magnetic units 1223.
  • the first magnetic unit 1221 The second magnetic unit 1222 is connected through the third magnetic unit 1223, wherein the first magnetic unit 1221 and the second magnetic unit 1222 are, for example, arc-shaped, and the first magnetic unit 1221 and the second magnetic unit 1222 have the same arc-shaped structure,
  • the third magnetic unit 1223 is connected between the first magnetic unit 1221 and the second magnetic unit 1222 and is symmetrical about the central axis of the first magnetic unit 1221 and the second magnetic unit 1222.
  • an arc-shaped magnetic field can be formed, and when the magnet 122 rotates around the target material 1223, a uniform magnetic field can be formed.
  • the uniform magnetic field can provide the sputtering uniformity of the target material, thereby achieving the uniformity of the coating film.
  • the magnet 122 may also have an approximately rectangular structure.
  • the magnet 122 includes a plurality of first magnetic units 1221 arranged oppositely and a plurality of second magnetic units 1222 arranged oppositely.
  • the magnetic unit 1221 is connected to the second magnetic unit 1222.
  • the first magnetic unit 1221 can have an arc-shaped structure, and the first magnetic unit 1221 can be recessed inward or outward. Multiple first magnetic units 1221 can also be inward or outward at the same time.
  • the plurality of first magnetic units 1221 may also include different arc-shaped structures.
  • the magnet 122 can have a symmetrical structure or an asymmetrical structure.
  • an arc-shaped magnetic field can be formed, and when the magnet 122 rotates around the target 123, a uniform magnetic field can be formed.
  • the uniform magnetic field can provide the sputtering uniformity of the target material, thereby achieving the uniformity of the coating film.
  • the growth chamber 110 may include an outer wall 110a and an inner wall 110b, the inner wall 110b is disposed in the outer wall 110a, the inner wall 110b is fixed in the outer wall 110a by a plurality of bolts, so the outer wall 110a and the inner wall 110b A ring-shaped structure is formed.
  • the ring-shaped structure can slow down heat loss.
  • the inner wall 110b is also provided with a multi-layer reflector, for example, the inner wall 110b is sequentially provided with a first reflector 111a and a second reflector 111b from the inside to the outside. The first reflector 111a and the second reflector 111b are attached in sequence, and the deposition is performed.
  • the radiant heat can be isolated in time by arranging a multilayer reflector on the inner wall 110b to prevent the heat from escaping outward.
  • the first reflecting plate 111a and the second reflecting plate 111b are circularly arranged on the inner wall 110b.
  • the first reflection plate 111a and the second reflection plate 111b may be composed of an integral heat preservation material or a plurality of heat preservation materials.
  • two reflective plates are provided on the inner wall 110b, and in some embodiments, three or four or more or fewer reflective plates can be provided.
  • a plurality of clamps 132 are provided on the inner wall 110b of the growth chamber 110, and the clamps 132 are used to fix the first reflector 111a and the second reflector 111b.
  • the clamp 132 includes a plurality of limit bars 1321, two adjacent limit bars 1321 form a slot 1322, the limit bar 1321 at one end of the clamp 132 is arranged on the inner wall 110b, and then the first reflection The plate 111a and the second reflecting plate 111b are arranged in the corresponding slot 1322.
  • the first reflection plate 111a and the second reflection plate 111b are arranged in the adjacent slot 1322.
  • the first reflection plate 111a and the second reflection plate 111b can be arranged in the corresponding card slots at intervals. Slot 1322. Both ends of the first reflector 111a and the second reflector 111b each include a bent portion (not shown). The bent portions at both ends of the first reflector 111a protrude from the slot 1322, so the first reflector 111a is round
  • the shape is arranged on the inner wall 110b. In this embodiment, for example, six clamps 132 are provided on the inner wall 110b, and the clamps 132 are evenly arranged on the inner wall 110b.
  • the outer wall 110a, the inner wall 110b, the first reflecting plate 111a, and the second reflecting plate 111b are provided with through holes 130 of the same size at the same positions.
  • the through holes 130 are located higher than the base 111.
  • the through holes 130 of the outer wall 110a and the inner wall 110b are provided with a high temperature resistant transparent material. In this way, the staff can understand the growth situation in the growth cavity 110 from the outside of the growth cavity 110.
  • a baffle 131 is also provided on the inner wall 110b.
  • a cooling device 140 is also provided on the outer wall 110a of the growth chamber 110.
  • the cooling device 140 is used to absorb the heat lost to the outer wall 110a and prevent the outer wall 110a from deforming due to high temperature.
  • the cooling device 140 is, for example, a water pipe surrounding the outer wall 110a. One end of the water pipe is a water inlet, and the other end of the water pipe is a water outlet. By forming the water pipe into a circulating water path, it effectively absorbs the outer wall. The temperature on 110a.
  • the growth chamber 110 includes at least one air inlet, the air inlet is connected to an external air source 124, the external air source 124 through the air inlet Gas is fed into the growth chamber 110.
  • the growth chamber 110 includes at least one suction port, and the suction port is connected to a vacuum pump 125, and the vacuum pump 125 vacuumizes the growth chamber 110 through the suction port.
  • the growth chamber 110 includes at least two air inlets, for example, a first air inlet 119a and a second air inlet 119b, the first air inlet 119a and the second air inlet 119b, respectively Set on opposite sides of the growth chamber 110, the first air inlet 119a and the second air inlet 119b are symmetrical to each other, and input into the growth chamber 110 can be achieved through the first air inlet 119a and the second air inlet 119b gas.
  • the first air inlet 119a and the second air inlet 119b are respectively connected to an air inlet pipe 200.
  • the air inlet pipe 200 includes an outer sleeve 210 and an inner sleeve 220.
  • the inner sleeve 220 is arranged in parallel on the outer sleeve.
  • one end of the inner sleeve 220 can be connected with one end of the outer sleeve 210 to form a closed annular cavity.
  • One end of the air inlet pipe 200 is connected to the air inlet, and the other end of the air inlet pipe 200 can contact the inner wall of the growth cavity 110 or the other end of the air inlet pipe 200 has a certain gap with the inner wall of the growth cavity 110.
  • the outer sleeve 210 includes a plurality of first exhaust holes 211, and the inner sleeve 210 includes a plurality of second exhaust holes 221.
  • the plurality of first exhaust holes 211 are respectively uniformly arranged on the outer sleeve 210, and the plurality of second exhaust holes
  • the vent holes 221 are uniformly arranged on the inner sleeve 220 respectively, wherein the size of the second vent hole 221 is greater than or equal to the size of the first vent hole 211, so the first vent hole 211 and the second vent hole 221 Can be staggered or partially overlapped or overlapped.
  • the size of the first vent hole 211 is smaller than the size of the second vent hole 221, and the first vent hole 211 and the second vent hole 221 are staggered, and the first vent hole 211 and the second vent hole 221 are staggered.
  • the vent hole 221 is, for example, a circle, a rectangle, a triangle, or one of other shapes or a combination thereof.
  • the external airflow first enters the inner sleeve 220, then enters the annular cavity through the second exhaust hole 221 on the inner sleeve 220, and then enters the growth chamber more evenly from the first exhaust hole 211 on the outer sleeve 210 In this way, the flow rate of the airflow entering the growth chamber 110 can be greatly slowed down without being disordered, thereby greatly reducing the vibration of equipment and products caused by the impact of airflow, and avoiding equipment damage The phenomenon of product damage and uniform air flow into the growth chamber 110 can also improve the uniformity of the coating.
  • the air inlet pipe 200 is connected to the air inlet through a branch pipe 230, the branch pipe 230, one end of the branch pipe 230 is fixed on the air inlet, and the other end of the branch pipe 230 is connected to the outer jacket
  • an exhaust pipe 240 is further provided on the outer wall of the growth chamber 110, and the exhaust pipe 240 is kept in a sealed state with the outer wall of the growth chamber 110.
  • the exhaust pipe 240 is arranged on the air inlet, and the exhaust pipe 240 An external gas source 250 is also connected, through which gas is delivered into the branch pipe 230 through the exhaust pipe 240, and when the gas enters the inner sleeve 220, it passes through a plurality of second exhaust holes on the inner sleeve 220 221 enters into the outer sleeve 210, and then enters into the growth chamber 110 through the plurality of first exhaust holes 211 on the outer sleeve 210, so that the flow rate of the airflow entering the growth chamber 110 can be greatly slowed down , And will not be disordered, thereby greatly reducing the vibration of equipment and products caused by the impact of airflow, avoiding equipment damage and product damage, and at the same time, the airflow into the growth chamber 110 is uniform, which can also improve the uniformity of the coating Sex.
  • an air flow regulator may be provided on the branch pipe 230 or the exhaust pipe 240, and the air flow regulator may be used to adjust the gas flow
  • FIG. 15 there is a certain gap between the bottom of the inner sleeve 220 and the bottom of the outer sleeve 210, for example, 2-3 mm.
  • a plurality of second exhaust holes 221 are provided on the bottom of the inner sleeve 220, and a plurality of first exhaust holes 211 are provided on the bottom of the outer sleeve 210, and the diameter of the second exhaust holes 221 is larger than that of the first row.
  • the diameter of the air holes 211 so the relative density of the first air holes 211 is greater than the relative density of the second air holes 221, and the first air holes 211 and the second air holes 221 are staggered or overlapped or partially overlapped.
  • a plurality of through holes are provided on one end of the air inlet pipe 200, which can further improve the uniformity of the air flow into the growth chamber 110.
  • multiple air inlets are provided on the side wall of the growth chamber 110, for example, a first air inlet 119a, a second air inlet 119b, and a third air inlet 119c. And the fourth air inlet 119d.
  • the four air inlets are respectively connected to an air inlet pipe 200, and gas is input to the growth chamber 110 through the four air inlets, thereby improving the uniformity of the gas in the growth chamber 110, thereby improving the coating film The uniformity.
  • two air inlets are provided on the side wall of the growth chamber 110, namely, a first air inlet 119a and a second air inlet 119b.
  • the first air inlet 119a and the second air inlet 119b are offset from each other.
  • the first air inlet 119a and the second air inlet 119b are respectively connected to an air inlet pipe 200, and the air inlet pipe 200 includes a plurality of exhaust holes 201, so that the gas becomes more uniform after entering the growth chamber 110.
  • the diameter of the air inlet pipe 200 connected to the first air inlet 119a and the second air inlet 119b may be the same or different in order to adjust the flow rate of the gas.
  • an air inlet 119a is provided on the side wall of the growth chamber 110, an air inlet pipe 200 is connected to the first air inlet 119a, and the air inlet pipe 200 includes multiple Each exhaust hole 201, the diameter of the plurality of exhaust holes 201 can be the same or different, so as to adjust the gas flow rate.
  • a plurality of air inlets are provided on the top of the growth chamber 110, namely, a first air inlet 119a and a second air inlet 119b.
  • the two air inlets 119b are respectively connected to an air inlet pipe 200.
  • the air inlet pipe 200 is located above the target 112.
  • the air inlet pipe 200 includes a plurality of exhaust holes 201, so that the gas enters the growth chamber 110 and becomes more Uniformity, which improves the sputtering uniformity of the target material 112 and the utilization rate of the target material 112 to improve the uniformity of the coating film.
  • the diameter of the air inlet pipe 200 connected to the first air inlet 119a and the second air inlet 119b may be the same or different in order to adjust the flow rate of the gas.
  • a semiconductor device 300 is also provided.
  • the semiconductor device 300 includes a transfer cavity 310, a transition cavity 320, a cleaning cavity 330, a preheating cavity 340, and a plurality of growth cavities. ⁇ 350.
  • the transfer cavity 310 may include a substrate loading and unloading robotic arm 311, which can operate the substrate loading and unloading robotic arm 311 for transferring substrates between the transition cavity 320 and the growth cavity 350.
  • the semiconductor device further includes a manufacturing interface 313.
  • the manufacturing interface 313 includes a cassette and a substrate handling robot (not shown).
  • the cassette contains a substrate to be processed, and the substrate handling robot may include The substrate planning system is used to load the substrate in the cassette into the transition cavity 320.
  • the transition cavity 320 is connected to the transfer cavity 310, and the transition cavity 320 is located between the manufacturing interface 313 and the transfer cavity 310.
  • the transition cavity 320 provides a vacuum interface between the manufacturing interface 313 and the transfer cavity 310.
  • the transition cavity 320 may include a housing 320a, which is, for example, a sealed cylinder, and a suction port and an exhaust port are provided on the side wall of the housing 320a.
  • a cooling plate 322 is provided in the transition cavity 320, and the cooling plate 322 is fixed to the bottom of the casing 320 a through a plurality of brackets 321.
  • the cooling plate 322 can cool the substrate.
  • the cooling plate 322 may be cylindrical or rectangular or other shapes, for example, and the cooling plate 322 may be fixed in the housing 320a by four brackets 321, for example.
  • the cooling plate 322 may be cylindrical, and the cooling plate 322 includes a plurality of internally threaded holes 322a, for example, four internally threaded holes 322a. Corresponding external threads are provided on both ends of the bracket 321, so that one end of the bracket 321 can be arranged in the internal threaded hole 322a.
  • the base 3211 includes a plurality of first threaded holes 3211a and a second threaded hole 3211b.
  • the second threaded hole 3211b is located on the base 3211.
  • a plurality of first threaded holes 3211a are evenly arranged around the second threaded holes 3211b.
  • the other end of the bracket 321 is arranged in the second threaded hole 3211b, and the plurality of first threaded holes 3211a are used for placing a plurality of nuts, so that the base 3211 can be fixed in the housing 320a.
  • the base 3211 includes six first threaded holes 3211a. In some embodiments, four or more first threaded holes 3211a may be provided on the base 3211.
  • At least one carrier 325 is provided in the housing 320a, for example, two carriers are provided, such as a first carrier 325 and a second carrier 328, and a first carrier 325 and a second carrier 328 is fixed on the supporting plate 323, and the first carrier 325 is located on the second carrier 328.
  • the supporting plate 323 includes a main pole and two side plates. The two side plates are respectively arranged at two ends of the main pole. The first carrier 325 and the second carrier 328 are arranged between the two side plates.
  • the support plate 323 is also connected to a control rod 324. Specifically, the control rod 324 is connected to the main rod of the support plate 323, and one end of the control rod 324 is also located outside the housing 320a.
  • the control rod 324 can drive the support plate 114 rise and/or fall.
  • the control rod 324 is connected to a driving unit (not shown), and the driving unit is used to control the control rod 324 to rise and/or fall.
  • the control rod 324 is connected to a driving unit (not shown), and the driving unit is used to control the control rod 324 to rise and/or fall.
  • the driving unit controls the lever 324 to descend, the second stage 328 can contact the cooling plate 322.
  • At least one tray can be placed on the first carrier 325 and the second carrier 328, and the tray is used for placing substrates.
  • the tray is used for placing substrates.
  • the tray 3251 for example, two or three or more trays 3251 are placed.
  • the transition cavity 320 may further include an air extraction port, which is connected to a vacuum pump 327, and the transition cavity 320 is evacuated by the vacuum pump 327.
  • vacuum processing is achieved through multiple steps.
  • a dry pump (Dry Pump) is used to pump the transition chamber 320 to 1 ⁇ 10 -2 Pa, and then a turbo molecular pump (Turbo Molecular Pump) is used to transfer the transition chamber 320 to 1 ⁇ 10 -2 Pa.
  • the cavity 320 is pumped to 1 ⁇ 10 -4 Pa or less than 1 ⁇ 10 -4 Pa.
  • the control rod 324 drives the first stage 325 and the second stage 328 along The preset path moves, for example, the control rod 324 drives upward movement.
  • the transition cavity 320 is connected to the transfer cavity, and the substrate loading and unloading robot in the transfer cavity transfers the substrate from the transition cavity 320 to the transfer cavity, and then the substrate is transferred to the transfer cavity by the substrate loading and unloading robot.
  • Other cavities such as preheating cavity, cleaning cavity or growth cavity, can form a thin film on the surface of the substrate in the growth cavity.
  • the substrate loading and unloading robot in the transfer cavity transfers the substrate to the second stage 328 in the transition cavity 320, and then the control rod 324 drives the first stage 325 and the second stage 328 moves in a direction opposite to the preset path, for example, downwards, the second stage 328 is in contact with the cooling plate 322, and the second stage 328 and the substrate on the second stage 328 are applied to the second stage Cool down.
  • an exhaust port is also included on one side of the housing 320a. The exhaust port is connected to an air source 326.
  • the second carrier 328 is first driven by the control rod 324 Keep away from the cooling plate 322, so that there is a preset distance between the second carrier 328 and the cooling plate 322, the preset distance is, for example, 5-10 mm, and then the gas source 326 passes through the exhaust port to the transition cavity 320.
  • Nitrogen or argon gas is introduced to perform vacuum breaking treatment on the transition cavity 320, so as to prevent the substrate from being cooled and causing cracks on the substrate due to the introduction of nitrogen. After the transition cavity 320 has broken the vacuum, the substrate can be taken out for storage and analysis.
  • the cleaning cavity 330 is connected to the transfer cavity 310.
  • the cleaning cavity 330 is located on the side wall of the transfer cavity 310.
  • a substrate support assembly 331 is disposed in the cleaning cavity 330, the substrate support assembly 331 is disposed at the bottom of the cleaning cavity 330, and the substrate support assembly 331 does not contact the cleaning cavity 330.
  • the substrate support assembly 331 includes a pedestal electrode 3311 and an electrostatic chuck 3312.
  • the electrostatic chuck 3312 is disposed on the pedestal electrode 3311.
  • the electrostatic chuck 3312 is used to place a substrate. At least one substrate can be placed on the electrostatic chuck 3312. In an example, multiple substrates can be set on the electrostatic chuck 3312, and the multiple substrates can be cleaned at the same time, thereby improving work efficiency.
  • the substrate support assembly 331 is also connected to a lifting and rotating mechanism 334.
  • the lifting and rotating mechanism 334 is connected to the pedestal electrode 3311, and the substrate supporting assembly 331 can be lifted or rotated by the lifting and rotating mechanism 334. , Indirectly realize the lifting or rotating of the substrate.
  • the distance between the substrate and the electrode 332 changes to adjust the intensity of the electric field between the pedestal electrode 3311 and the electrode 332, so that the plasma can better clean the substrate.
  • the lifting and rotating mechanism 334 includes a lifting mechanism that drives the pedestal electrode 3311 to rise or fall, and a rotating mechanism that drives the pedestal electrode 3311 to rotate.
  • the lifting mechanism includes a lifting motor 3341 and a guide rod 3342.
  • one end of the guide rod 3341 is arranged in the cleaning cavity 330 and is connected to the pedestal electrode 3311, and the guide rod 3342 and the pedestal electrode 3311 are sealed by a sealing ring 3343.
  • the output shaft of the lifting motor 3341 is connected to the guide rod 3342, so that the lifting motor 3341 can drive the pedestal electrode 3311 to rise or fall.
  • the rotating mechanism includes a rotating electric machine 3344, a worm 3345, and a worm gear 3346.
  • the output shaft of the rotating electric machine 3344 is connected to a worm 3345
  • the worm 3345 is connected to a worm wheel 3346.
  • the worm wheel 3346 is fixed on the guide rod 3342.
  • the worm wheel 3346 and the worm 3345 mesh for transmission.
  • the cleaning cavity 330 further includes an electrode 332, which is disposed oppositely above the substrate support assembly 331.
  • the electrode 332 does not touch the top of the cleaning cavity 330.
  • the electrode The distance between the 332 and the substrate support assembly 331 may be 2-25 cm, such as 10-20 cm, or 16-18 cm.
  • the electrode 332 is also connected to an elevating and rotating mechanism 333, and the structure of the elevating and rotating mechanism 333 is the same as that of the elevating and rotating mechanism 334.
  • the elevating and rotating mechanism 333 will not be described in this embodiment.
  • the distance between the electrode 332 and the substrate changes to adjust the intensity of the electric field between the electrode 332 and the substrate, so that the plasma can uniformly clean the substrate.
  • the rotation speed of the electrode 332 and the rotation speed of the substrate support assembly 331 may be the same or there is a certain speed difference, so that the plasma cleans the substrate uniformly.
  • the substrate support assembly 331 is also connected to at least one RF bias power source 338, specifically, the RF bias power source 338 is connected to the pedestal electrode 3311.
  • the radio frequency of the radio frequency bias power supply 338 can be high frequency, intermediate frequency or low frequency.
  • the high frequency can be a 13.56 MHZ radio frequency bias source;
  • the intermediate frequency can be a 2 MHZ radio frequency bias source, and
  • the low frequency can be a few 300-500 KHZ radio frequency bias source.
  • the high-frequency radio frequency can be used to etch silicon;
  • the intermediate frequency or low-frequency radio frequency can be used to etch the dielectric.
  • radio frequency bias power supplies 338 of different frequencies can be connected to the pedestal electrode 3311 at the same time to achieve simultaneous etching of silicon and dielectric.
  • the electrode 332 is also connected to at least one radio frequency power supply 337, and the radio frequency of the radio frequency power supply 337 is, for example, 13.56 MHz.
  • Both the RF power supply 337 and the RF bias power supply 338 are driven by synchronous pulses, which can be switched on and off at the same time to reduce the electronic temperature in the cleaning cavity 330, and the synchronous pulses have good control over the cleaning (etching depth) of dense areas of the substrate.
  • the cleaning chamber 330 also includes an air inlet, which is close to the electrode 332.
  • the air inlet is connected to a gas source 335.
  • the gas source 335 delivers gas into the cleaning chamber 330.
  • the gas is
  • the precursor gases used for cleaning applications include, for example, chlorine-containing gas, fluorine-containing gas, iodine-containing gas, bromine-containing gas, nitrogen-containing gas, and/or other suitable reactive elements.
  • a bias of about -5 volts to -1000 volts is applied to the pedestal electrode 3311 provided in the substrate support assembly 331 for about 1 second to 15 minutes, and the substrate is set on the substrate support assembly 331.
  • the frequency of the power delivered to the processing area of the cleaning chamber 330 can vary from about 10 kilohertz to 100 megahertz, and the power level can be between about 1 kilowatt and 10 kilowatts.
  • the cleaning chamber 330 may further include an air extraction port close to the substrate support assembly 331, and the air extraction port is connected to a vacuum pump 336, which is used to extract the gas in the cleaning chamber 330 so that the pressure of the cleaning chamber 330 is increased.
  • the predetermined background vacuum range for example, 10 -5 -10 -3 Pa
  • mix and pass the precursor gas for cleaning applications into the cleaning chamber 330 and adjust the pumping speed of the cleaning chamber 330 , So that the pressure of the cleaning cavity 330 enters the predetermined working pressure range, and the predetermined working pressure range is, for example, 1Pa-20Pa.
  • another cleaning chamber including a reaction chamber 200, a bottom electrode 201, a bushing 203, a coil assembly 204, and a radio frequency bias source 206.
  • the reaction chamber 200 has a reaction space in which the generated plasma and other components can be accommodated.
  • the wall of the reaction chamber 200 may be a quartz window 205.
  • the lower electrode 201 may be disposed at the bottom of the reaction chamber 200 but not in contact with the bottom of the reaction chamber 200.
  • the bottom electrode 201 is used to support the substrate 202 to be etched, and the bottom electrode 201 is a conductive plate, for example, an iron plate, etc., but is not limited thereto.
  • the bottom electrode 201 can be connected to a temperature controller (not shown), the temperature controller controls the temperature of the bottom electrode 201 in the range of 0-100 °C, through the bottom electrode 201 can indirectly control the substrate 202 to reach the process The desired temperature.
  • the liner 203 is disposed at the top center area of the reaction chamber 200, that is, the liner 203 is located on the upper cavity wall of the reaction chamber 200 and does not contact the upper cavity wall.
  • the bushing 203 may be cylindrical or other shapes.
  • the bushing 203 is a conductive plate, for example, an iron plate, etc., but is not limited thereto.
  • the bushing 203 is a rotatable bushing, and its rotation axis is perpendicular to the upper wall of the reaction chamber 200. Of course, it can also be deflected at a certain angle.
  • the position between the bushing 203 and the coil assembly 204 is not a fixed connection, and its relative position is changed by the rotation of the bushing 203 during the etching process, which will increase the etching rate (cleaning rate) of each position on the substrate 202. balanced.
  • the bushing 203 is also connected to a radio frequency power supply (not shown in the figure).
  • the frequency of the radio frequency power supply is, for example, 13.56 MHz.
  • the lower electrode 201 is connected to at least one RF bias source 206, and only one RF bias source 206 is shown in FIG. 27.
  • the radio frequency of the radio frequency bias source 206 can be high frequency, intermediate frequency or low frequency.
  • the high frequency can be a 13.56MHz RF bias source
  • the intermediate frequency can be a 2MHz RF bias source
  • the low frequency can be a 400-600KHZ RF bias source.
  • the preheating cavity 340 is connected to the transfer cavity 310.
  • the preheating cavity 340 is located on the sidewall of the transfer cavity 310. After the substrate has completed the necessary semiconductor processes in the preheating cavity 340, the transfer The substrate loading and unloading robot 311 in the cavity 310 transfers the substrate into the preheating cavity 340 to preheat the substrate.
  • the preheating cavity 340 includes a shell 340a, and a bracket 341 is provided at the bottom of the shell 340a.
  • the bracket 341 may be a hollow structure, for example, and the wire is placed in the internal structure of the bracket 341. Connect the wires to the heater 342.
  • the bracket 341 may be made of high temperature resistant material, for example.
  • a heater 342 is arranged in the preheating cavity 340, and the heater 342 is fixed on the bracket 341.
  • the heater 342 includes a chassis 3421 and a heating coil 3424.
  • the chassis 3421 includes a plurality of limits.
  • the position bar 3422, a plurality of limit bars 3422 are fan-shaped and divided on the chassis 3421, and an interval cavity is arranged between two adjacent limit bars 3422, and the interval cavity can facilitate the heat dissipation of the enameled wire.
  • the multiple limit bars 3422 and the chassis 3421 can be integrally formed.
  • a plurality of baffles 3423 are also provided on the plurality of limit bars 3422, and the plurality of baffles 3423 are distributed on the plurality of limit bars in a fan shape to form a concentric circle structure.
  • the cross section of the heating coil 3424 is circular, and the height of the baffle 3423 is greater than the height of the heating coil 3424.
  • the tray 343 is also provided with a plurality of measuring points on the side close to the substrate 344, and then the plurality of measuring points are connected to a temperature measuring device, which can be arranged in the preheating cavity 340 or On the outside of the preheating cavity 340, the temperature on the substrate 344 can be measured in real time by the temperature measuring device, so that the surface temperature of the substrate 344 and its thermal uniformity can be controlled.
  • a temperature measuring device which can be arranged in the preheating cavity 340 or On the outside of the preheating cavity 340, the temperature on the substrate 344 can be measured in real time by the temperature measuring device, so that the surface temperature of the substrate 344 and its thermal uniformity can be controlled.
  • an air extraction port may also be provided at the bottom of the preheating cavity 340.
  • the air extraction port is connected to a vacuum pump 345, and the preheating cavity 340 is evacuated by the vacuum pump 345 to obtain a vacuum state of preheating.
  • a heater 342 is provided in the preheating cavity 340. It should be noted that multiple heaters 342 can also be provided on the side wall of the preheating cavity 340, and multiple heaters 342 can also be provided on the top of the preheating cavity 340. A heater to ensure the uniformity of the overall temperature of the preheating cavity 340.
  • a plurality of growth chambers 350 are provided on the sidewall of the transfer cavity 310. After the substrates are processed in the preheating cavity 340, the substrate loading and unloading robot 311 in the transfer cavity 310 The substrate is transferred to the growth chamber 350 for operation. Since a uniform arc-shaped magnetic field is formed in the growth chamber 350, uniform sputtering ions can be formed on the surface of the substrate, thereby forming a uniform thin film on the substrate.
  • this embodiment also proposes a method for using semiconductor equipment, including: S1: placing the substrate on the tray;
  • S2 Perform a vacuuming process, and the stage is moved up to transport the substrate into the growth chamber to form a thin film on the substrate;
  • the thin film (such as aluminum nitride coating) on the substrate is analyzed. It can be seen from the figure that when the relative temperature is less than 0.1, the A1 area appears as loose fibrous crystallites. The structure is an inverted cone-shaped fiber, and there are a lot of gaps in the grain boundary, and the film strength is poor. When the relative temperature is 0.1-0.3, the A2 zone appears as dense fibrous crystallites. When the relative temperature is between 0.3 and 0.5, the A3 zone is characterized by columnar crystals. In this area, each crystal grain grows to obtain uniform columnar crystals. The density of defects in the columnar crystals is low, and the density of grain boundaries is high, showing a crystallographic plane. feature.
  • the relative temperature is greater than 0.5
  • the A4 zone appears as coarse equiaxed crystals
  • the defect density in the equiaxed crystals is very low
  • the film crystallization is very complete, and the strength is high. Therefore, when the relative temperature is low, that is, 0-0.3, after the sputtering ions are incident on the surface of the substrate, sufficient surface diffusion cannot occur, and they are continuously covered by subsequent sputtering ions, thus forming mutually parallel growth.
  • the denser fibrous structure is surrounded by relatively loose boundaries between fibers.
  • the fibrous structure has low density, low bonding strength, weak and easy to crack, and shows obvious bundle-like fiber characteristics in the cross-sectional morphology.
  • the semiconductor device of the present disclosure deposits a coating film at a uniform high temperature, and can form a film at a fast speed.
  • the crystal lattice arrangement of the film (for example, aluminum nitride) exhibits columnar crystal growth, the crystallinity of the film formation is good, and the film formation uniformity is also obtained. improve.
  • the relative temperature is the ratio of the substrate temperature to the melting temperature of the film. If the substrate temperature is lower, the relative temperature is lower, and if the substrate temperature is higher, the relative temperature is higher.
  • this embodiment analyzes the aluminum nitride film 401 formed on the substrate 400. It can be seen from the figure that the aluminum nitride film 401 has a columnar crystal structure, and the aluminum nitride film 401 has a dense interior. High and low defect density, therefore, the aluminum nitride film formed by the semiconductor device is of high quality.
  • FIG. 36 shows the rocking curves of aluminum nitride films formed under two different film forming conditions. Then, the dislocation density of the (002) crystal plane of the aluminum nitride film is studied through the rocking curves. It should be noted that the difference between the two film forming conditions is only the pretreatment of the substrate. It can be seen from Fig. 36 that the half-value width of the C1 curve is 227 arc angles, and the half-value width of the C2 curve is 259 arc angles. It can be concluded that the growth rate of the aluminum nitride film obtained without pretreatment of the substrate is fast.
  • the dislocation density is large, the growth rate of the aluminum nitride film obtained by pre-processing the substrate is slow, and the dislocation density is small. Therefore, after the substrate is pre-treated, the quality of the aluminum nitride film formed under the same conditions is improved.
  • the equipment or manufacturing method of the present application can also be applied to other films of this quality, such as metal films, semiconductor films, insulating films, compound films, or films of other materials.
  • the high-quality thin film formed in this application can be applied to various semiconductor structures, electronic components or electronic devices, such as switching elements, power elements, radio frequency elements, light-emitting diodes, miniature light-emitting diodes, display panels, mobile phones, and watches. , Laptops, drop-in devices, charging devices, charging piles, virtual reality (VR) devices, augmented reality (AR) devices, portable electronic devices, game consoles, or other electronic devices.
  • the semiconductor epitaxial structure may include a substrate 1000, an aluminum nitride layer 1001, a first aluminum gallium nitride layer 1002, and a second aluminum nitride layer.
  • the aluminum nitride layer 1001 is formed on the substrate 1000
  • the first aluminum gallium nitride layer is formed on the aluminum nitride layer 1001
  • the second aluminum gallium nitride layer 1003 is formed on the first aluminum gallium nitride layer 1002.
  • the gallium nitride layer 1004 is formed on the second aluminum gallium nitride layer 1003, and the aluminum content of the first aluminum gallium nitride layer 1002 may be higher than the aluminum content of the second aluminum gallium nitride layer 1003.
  • the substrate 1000 may be a silicon-based material substrate, such as silicon (Si) or silicon carbide (SiC). In other embodiments, the substrate 1000 may also be sapphire ((Al2O3), gallium arsenide (GaAs), lithium aluminate (LiAlO2), gallium nitride (GaN) or other semiconductor substrate materials.
  • a plurality of micro-recesses 1000a may be provided on the upper surface of the silicon substrate, and the cross-section of the micro-recesses 1000a is an inverted triangle or other shapes.
  • the cross-section of the micro-recesses 1000a includes an ellipse or Polygon.
  • the dimple 1000a divides the substrate 1000 into a plurality of dielectric columns, the cross-section of the dielectric columns includes a triangle, an ellipse, or other polygons, and the cross-sectional area of the dielectric columns is consistent from top to bottom, or gradually decreases from bottom to top.
  • the inverted triangular dimple 1000a has a larger diameter and a larger depth to relieve accumulation stress.
  • the aluminum nitride layer 1001 may be filled in the dimple 1000a.
  • the aluminum nitride layer 1001 is provided between the substrate 1000 and the first aluminum gallium nitride layer 1002 to prevent the silicon in the substrate 1000 from reacting with the gallium in the first aluminum gallium nitride layer 1002.
  • the semiconductor device 100 may be used to sputter an aluminum nitride film on the surface of the substrate 1000 to form an aluminum nitride layer 1001.
  • the temperature of the substrate 1000 is controlled between, for example, 800-1000°C.
  • the thickness of the aluminum nitride layer 1001 can be, for example, 0.01- 1.6 ⁇ m.
  • the formed epitaxial structure may be subjected to high temperature annealing treatment to improve the quality of the aluminum nitride layer 1001.
  • the conditions of the high-temperature annealing treatment are, for example, the annealing temperature is, for example, 1100-1200° C., and the annealing gas is H 2 +NH 3 .
  • the aluminum content of the first aluminum gallium nitride layer 1002 may be higher than the aluminum content of the second aluminum gallium nitride layer 1003.
  • the decrease in the aluminum content is a gradient decrease, resulting in an increase in the lattice parameter, thereby improving the quality of the semiconductor epitaxial structure.
  • an aluminum nitride layer 1001 is formed on, for example, a silicon substrate 1000, the lattice mismatch between aluminum nitride and silicon can reach 19%, and the dislocation density of the aluminum nitride layer 1001 is very high.
  • the relatively straight gradient of the decrease in the aluminum content in the aluminum gallium nitride layer leads to an increase in the lattice parameter, thereby applying compressive stress in the subsequent layer during the growth process.
  • the aluminum nitride layer 1001 has the problem of high dislocation density, which can be improved by the design of the first aluminum gallium nitride layer 1002 and the second aluminum gallium nitride layer 1003 to improve the quality of the buffer layer.
  • the first aluminum gallium nitride layer 1002 and the second aluminum gallium nitride layer 1003 can be prepared by using a semiconductor device 100 or a chemical vapor deposition method.
  • the thickness of the aluminum gallium nitride layer 1002 or the second aluminum gallium nitride layer 1003 may be, for example, 600-1200 nm.
  • the value of X in the first aluminum gallium nitride layer (Al x Ga 1-x N.) 1002 is greater than the value of Y in the second aluminum gallium nitride layer (Al Y Ga 1-Y N.) 1003.
  • the semiconductor epitaxial structure further includes a gallium nitride layer 1004.
  • the gallium nitride layer 1004 is disposed on the second aluminum gallium nitride layer 1003.
  • the high-resistance gallium nitride layer 1004 can improve the device performance. Pressure resistance.
  • the gallium nitride layer 1004 may include a multilayer structure, which includes at least a first gallium nitride layer, a second gallium nitride layer, and a third gallium nitride layer.
  • the first gallium nitride layer can be grown in a high-pressure and high-temperature environment, such as a growth temperature of 1000-1050°C, a reaction chamber pressure of 400-500torr, a growth rate of 1-1.5um/h, and a growth thickness of 300-500nm;
  • the GaN layer can be grown in a medium-pressure and low-temperature environment, such as a growth temperature of 900-1000°C, a reaction chamber pressure of 200-250torr, a growth rate of 2.5-3.5um/h, and a growth thickness of 1-4um;
  • third nitride The gallium layer can be grown in a low-pressure and high-temperature environment, such as a growth temperature of 1000-1050°C, a reaction chamber pressure of 100-200torr, a growth rate of 0.5-1um/h, and a growth thickness of 300-500nm.
  • the quality of the semiconductor epitaxial structure is improved by setting the aluminum content in the first aluminum gallium nitride layer 1002 and the second aluminum gallium nitride layer 1003.
  • the semiconductor epitaxial structure may include a substrate 1100, a first aluminum nitride layer 1101, a first gallium nitride layer 1102, a second aluminum nitride layer 1103, and a second gallium nitride layer 1104 .
  • the first aluminum nitride layer 1101 is formed on the substrate 1100
  • the first gallium nitride layer 1102 is formed on the first aluminum nitride layer 1101
  • the second aluminum nitride layer 1103 is formed on the first gallium nitride layer 1102.
  • the second gallium nitride layer 1104 is formed on the second aluminum nitride layer 1103.
  • the material of the substrate 1100 may be a semiconductor substrate material such as silicon (Si), silicon carbide (SiC), sapphire ((Al2O3), gallium arsenide (GaAs), lithium aluminate (LiAlO2), etc.
  • the substrate 1100 is, for example, It is a silicon (Si)-based material, such as silicon (Si) or silicon carbide (SiC).
  • the method of forming the aluminum nitride layer 1101 and/or 1103 includes, for example, using the semiconductor device 100 of the present disclosure to form an aluminum nitride film on the surface of the substrate.
  • the method of forming the gallium nitride layer 1102 and/or 1104 includes: growing gallium nitride on the aluminum nitride layer by a chemical vapor deposition method or a metal organic chemical vapor deposition method.
  • a chemical vapor deposition method or a metal organic chemical vapor deposition method First, in the reaction chamber of the gallium nitride growth equipment, one or more of, for example, helium, argon, nitrogen, and hydrogen is introduced into the reaction chamber, and then the temperature of the reaction chamber is increased to a preset temperature, where, The predetermined temperature is the growth temperature of the gallium nitride layer, under this condition, the first gallium nitride layer 1102 and/or the second gallium nitride layer 1104 of a predetermined thickness are grown.
  • a plurality of aluminum nitride interlayers may be further arranged in the first gallium nitride layer 1102 or the second gallium nitride layer 1104 at intervals, for example, the third gallium nitride layer
  • the fourth gallium nitride layer and the fourth gallium nitride layer are respectively disposed inside the first gallium nitride layer 1102 and the second gallium nitride layer 1104.
  • the first aluminum nitride layer 1101 and the first gallium nitride layer 1102 may include a first aluminum gallium nitride layer 1105 and a second aluminum gallium nitride layer 1106.
  • the first aluminum gallium nitride layer 1105 is disposed on the first aluminum nitride layer 1101
  • the second aluminum gallium nitride layer 1106 is disposed on the first aluminum gallium nitride layer 1105
  • the first gallium nitride layer 1102 is disposed on the second aluminum gallium nitride layer 1105.
  • the aluminum content of the first aluminum gallium nitride layer 1105 is higher than the aluminum content of the second aluminum gallium nitride layer 1106.
  • the relatively straight gradient of the decrease in the aluminum content results in an increase in the lattice parameter.
  • the semiconductor device and semiconductor epitaxial structure of the present disclosure are used to form a light emitting diode structure.
  • the light emitting diode structure may include a semiconductor epitaxial structure, the first semiconductor layer 1107, the light emitting layer 1108, the second semiconductor layer 1109, the first electrode 1111 and the second electrode 1112, the first semiconductor layer 1107 is located in the second nitride layer.
  • the light-emitting layer 1108 is located on the first semiconductor layer 1107
  • the second semiconductor layer 1109 is located on the light-emitting layer 1108, and a transparent conductive layer 1110 is also provided on the second semiconductor layer 1109, on one side of the second semiconductor layer 1109
  • a recess is provided that passes through the transparent conductive layer 1110, the second semiconductor layer 1109, and the light-emitting layer 1108 in order to the first semiconductor layer 1107, and the recess is in contact with the first semiconductor layer 1107.
  • the first electrode 1111 is formed on the transparent conductive layer 1110
  • the second electrode 1112 is formed on the first semiconductor layer 1107 in the recess.
  • the semiconductor epitaxial structure may include: a substrate 1100, a first aluminum nitride layer 1101, a first aluminum gallium nitride layer 1105, a second aluminum gallium nitride layer 1106, and a second aluminum gallium nitride layer 1105.
  • the first aluminum nitride layer 1101 is formed on the substrate 1100, the first aluminum gallium nitride layer 1105 is formed on the first aluminum nitride layer 1101, and the second aluminum gallium nitride layer 1106 is formed on the first aluminum gallium nitride layer 1105
  • the first gallium nitride layer 1102 is formed on the second aluminum gallium nitride layer 1106, the second aluminum nitride layer 1103 is formed on the first gallium nitride layer 1102, and the second gallium nitride layer 1104 is formed on the second gallium nitride layer.
  • a first semiconductor layer 1107, a light emitting layer 1108, and a second semiconductor layer 1109 may be provided on the semiconductor epitaxial structure.
  • the first semiconductor layer 1107 may be an N-type semiconductor layer doped with a first impurity, or a P-type semiconductor layer doped with a second impurity
  • the corresponding second semiconductor layer 1109 may be a P-type semiconductor layer doped with a second impurity.
  • the first impurity is, for example, a donor impurity
  • the second impurity is, for example, an acceptor impurity.
  • the first impurity and the second impurity may be different elements.
  • the first semiconductor layer 1107 may be For the gallium nitride half-layer, the first impurity may be silicon (Si) element, and the second impurity may be magnesium (Mg) element.
  • the first semiconductor layer 1107 and the second semiconductor layer 1109 may be nitride compounds.
  • the first semiconductor layer 1107 is N-type doped gallium nitride
  • the second semiconductor layer 1109 is P-type doped nitride. gallium.
  • the first semiconductor layer 1107 and the second semiconductor layer 1109 may also be formed of other suitable transparent materials.
  • the light-emitting layer 1108 is an intrinsic semiconductor layer or a low-doped semiconductor layer.
  • the doping concentration of the light-emitting layer 1108 is lower than that of adjacent semiconductor layers of the same doping type.
  • the light emitting layer 1108 may be a quantum well light emitting layer.
  • indium gallium nitride (InGaN) can be selected.
  • the light-emitting layer may be, for example, a quantum well emitting different light color bands
  • the material of the light-emitting layer may be indium gallium nitride (InGaN), zinc selenide (ZnSe), indium gallium nitride/gallium nitride ( InGaN/GaN), indium gallium nitride/gallium nitride (InGaN/GaN), gallium phosphide (GaP), aluminum gallium phosphide (AlGaP), aluminum gallium arsenide (AlGaAs), gallium arsenide phosphorous (GaAsP), One or more of gallium phosphide (GaP) and other materials.
  • InGaN indium gallium nitride
  • ZnSe zinc selenide
  • InGaN/GaN indium gallium nitride/gallium nitride
  • the light emitting diode structure further includes a transparent conductive layer 1110 disposed on the second semiconductor 1109 and located between the first electrode 1111 and the second semiconductor structure 1109.
  • the transparent conductive layer 1110 can make a good ohmic contact between the second semiconductor layer 1109 and the first electrode 1111.
  • the material of the transparent conductive layer 1110 can be indium tin oxide (ITO) or indium zinc oxide. (indium zinc oxide, IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), aluminum tin oxide (ATO), aluminum zinc oxide Material (aluminum zinc oxide, AZO for short) or other appropriate transparent conductive materials.
  • the light-emitting diode structure further includes a concave portion located on one side of the transparent conductive layer 1110, the second semiconductor layer 1109, and the light-emitting layer 1108.
  • the transparent conductive layer 1110 is provided with a first electrode 1111, and a second electrode 1112 is provided in the concave portion.
  • the material of the first electrode 1111 and the second electrode 1112 may be an opaque conductive material, and the opaque conductive material may include titanium ( Ti), platinum (Pt), gold (Au), chromium (Cr) and other metal materials, opaque conductive materials can also be highly reflective materials such as aluminum (Al) and silver (Ag), so that the first electrode 1111 and the second electrode 1112 is a highly reflective electrode.
  • the first electrode 1111 and the second electrode 1112 may be formed on the transparent conductive layer 1110 and the first semiconductor layer 1107 by evaporation and/or sputtering technology, respectively.
  • the semiconductor epitaxial structure may include a substrate 1200, an aluminum nitride layer 1201, a superlattice structure 1202, and a gallium nitride layer 1203.
  • the superlattice structure 1202 includes a plurality of aluminum nitride interlayers and a plurality of aluminum gallium nitride interlayers.
  • the aluminum nitride layer 1201 is formed on the substrate 1200
  • the superlattice structure 1202 is formed on the aluminum nitride layer 1201
  • the gallium nitride layer 1203 is formed on the superlattice structure 1202.
  • the semiconductor device 100 of the present disclosure may be used to form the aluminum nitride layer 1201.
  • a superlattice structure 1202 is provided on the aluminum nitride layer 1201.
  • the superlattice structure 1202 can be made of two different semiconductor materials with different band gaps, and the two different semiconductor materials alternately grow to form a periodic structure.
  • the two different semiconductor materials are, for example, aluminum nitride and aluminum gallium nitride.
  • the superlattice structure 1202 includes a plurality of aluminum nitride interlayers and a plurality of aluminum gallium nitride interlayers. The interlayer and the aluminum gallium nitride interlayer are periodically grown on the aluminum nitride layer.
  • the two different semiconductor materials may be, for example, aluminum nitride and gallium nitride, and the superlattice structure 1202 includes an aluminum nitride interlayer and a gallium nitride interlayer.
  • the thickness of the aluminum nitride interlayer and the aluminum gallium nitride interlayer may be nanometer-sized, and the growth period is, for example, 15-20.
  • the thickness of the aluminum nitride layer is, for example, 4 nm
  • the thickness of the aluminum gallium nitride layer is, for example, 20 nm.
  • the thickness of the aluminum nitride layer is, for example, 4 nm
  • the thickness of the gallium nitride interlayer is, for example, 20 nm.
  • This superlattice structure 1202 has good vertical leakage and breakdown characteristics, and is suitable for power devices, for example.
  • the method for generating the aluminum nitride interlayer and the aluminum gallium nitride interlayer in the superlattice structure 1202 includes: sequentially forming the aluminum nitride interlayer and the aluminum nitride interlayer on the aluminum nitride layer by a deposition process The aluminum gallium nitride interlayer is then repeatedly deposited alternately on the two interlayers to form a periodic structure in the growth direction.
  • the aluminum nitride interlayer is grown in a single cycle, the growth thickness of the aluminum nitride interlayer may be, for example, 4 nm, and the growth thickness of the aluminum gallium nitride interlayer is, for example, 20 nm.
  • a gallium nitride layer 1203 may be disposed on the superlattice structure 1202.
  • the growth condition for growing the gallium nitride layer 1203 is, for example, the growth temperature is, for example, 950-1000°C, and in this embodiment, the growth temperature is, for example, 980°C.
  • III-V nitride materials can be grown as a single crystal (epitaxial) layer on a suitable substrate 1200, where the gallium nitride layer 1203 has a different thermal expansion coefficient from the substrate 1200, therefore, When cooled after processing, the gallium nitride layer 1203 has a tendency to crack due to the constraints imposed by the thicker substrate 1200 on them. Fragmentation of the gallium nitride layer 1203 will limit their ultimate application.
  • the aluminum nitride layer 1201 and the superlattice structure 1202 provided in the present application can adjust the thermal mismatch, and prevent the wafer deformation and the cracking of the gallium nitride layer 1203 in the heating and subsequent cooling of the substrate 1200.
  • the semiconductor device when the semiconductor device and the epitaxial structure of the present disclosure are used to manufacture a semiconductor device, the semiconductor device may include, for example, the aforementioned semiconductor epitaxial structure, its source 1204, drain 1205, and gate 1206.
  • the source 1204 and the drain 1205 are located on the gallium nitride layer 1023, and are respectively located on both sides of the gallium nitride layer 1203, the gate 1206 is located between the source 1204 and the drain 1205, and the gate 1026 can be inserted into the gallium nitride layer , And have a predetermined distance from the superlattice structure 1202.
  • the epitaxial structure includes a substrate 1200, an aluminum nitride layer 1201, a superlattice structure 1202, and a gallium nitride layer 1203.
  • the aluminum nitride layer 1201 is located on the substrate 1200.
  • the lattice structure 1202 is disposed on the aluminum nitride layer 1201, and the gallium nitride layer 1203 is disposed on the superlattice structure 1202.
  • the aluminum content in the superlattice structure 1202 in the epitaxial structure can be lower than the aluminum content in the aluminum nitride layer 1201.
  • this epitaxial structure has good vertical leakage and breakdown characteristics, and the formed Semiconductor devices (such as semiconductor power devices) also have good vertical leakage and breakdown characteristics.
  • the semiconductor epitaxial structure may include a first gallium nitride layer 1207 and a second gallium nitride layer 1208.
  • the second gallium nitride layer 1208 is formed on the first gallium nitride layer 1207, and the lattice structure (for example, a polycrystalline structure or a single crystal structure) of the first gallium nitride layer 1207 may be different from that of the second gallium nitride layer 1207.
  • the layer 1208 has a lattice structure (for example, an amorphous structure).
  • the growth method of the semiconductor epitaxial structure includes: forming an aluminum nitride layer 1201 on a substrate 1200, where the substrate 1200 may be a silicon (Si)-based material, such as silicon (Si) or silicon carbide (SiC) .
  • the method of forming the aluminum nitride layer 1201 includes, for example, using the semiconductor device of the present disclosure to form a layer of aluminum nitride film on the surface of the substrate 1200, and controlling the sputtering rate, substrate temperature, sputtering thickness and other parameters to ensure that the substrate 1200 is spread on the surface.
  • the aluminum nitride material is filled to obtain a certain thickness of aluminum nitride layer 1201.
  • the aluminum nitride layer 1201 is subjected to a high-temperature annealing treatment to improve the quality of the aluminum nitride layer 1201.
  • the first gallium nitride layer 1207 and the second gallium nitride layer 1208 of the semiconductor epitaxial structure can be formed by using different process methods or different process equipment, respectively.
  • the semiconductor device of the present disclosure can be used and the first aluminum nitride layer 1201 can be formed on the aluminum nitride layer 1201 by a physical vapor deposition method.
  • a metal organic compound chemical vapor deposition method can be used to form the second gallium nitride layer 1208 on the first gallium nitride layer 1207.
  • the first gallium nitride layer 1207 and the second gallium nitride layer 1208 may be peeled off the substrate 1200 to obtain a gallium nitride epitaxial structure.
  • the epitaxial structure (1207, 1208) and the substrate 1200 can be separated by etching or grinding the growth substrate 1200 and the aluminum nitride layer 1201.
  • the obtained gallium nitride epitaxial structure includes a first gallium nitride layer 1207 and a gallium nitride layer 1208.
  • the above-mentioned gallium nitride epitaxial structure can be applied to a vertical conduction semiconductor device.
  • electrodes and other semiconductor layers can be formed on the upper and lower sides of the first gallium nitride layer 1207 and the gallium nitride layer 1208, thereby forming a vertical conduction semiconductor device.
  • the light-emitting diode structure when the semiconductor device and the epitaxial structure of the present disclosure are used to manufacture a light-emitting diode structure, at least includes: a carbon-containing substrate 1300, a low-temperature aluminum nitride layer 1301, a high-temperature gallium nitride buffer layer 1302, and a first The semiconductor layer 1303, the light emitting layer 1304, the second semiconductor layer 1305, the N-type electrode 1306, and the P-type electrode 1307.
  • the low-temperature aluminum nitride layer 1301 is formed on the carbon-containing substrate 1300
  • the high-temperature gallium nitride buffer layer 1302 is formed on the low-temperature aluminum nitride layer 1301
  • the first semiconductor layer 1303 is formed on the high-temperature gallium nitride buffer layer 1302.
  • the light-emitting layer 1304 is formed on the first semiconductor layer 1303, and the second semiconductor layer 1305 is formed on the light-emitting layer 1304.
  • a penetrating through the second semiconductor layer 1305, the light-emitting layer 1304 and the first semiconductor layer are provided.
  • the concave portion 1303 is in contact with the first semiconductor layer 1303, the N-type electrode 1306 is formed on the first semiconductor layer 1303 in the concave portion, and the P-type electrode is formed on the second semiconductor layer 1305.
  • a silicon-based substrate with a carbon-containing layer can be used as the substrate of the light emitting diode structure to improve the quality, performance and reliability of the light emitting diode structure device.
  • the carbon-containing layer in the carbon-containing substrate 1300 can prevent or reduce the inter-mixing of the silicon atoms of the substrate and the metal atoms of the light-emitting diode structure, thereby improving the quality of the third group nitride crystal.
  • the improved quality of the above-mentioned Group III nitride crystal can improve the performance and reliability of the light emitting diode structure device.
  • the carbon-containing layer is disposed along the surface of the carbon-containing substrate 1300 and extends into the substrate to a depth less than about 20 ⁇ m.
  • other atoms such as silicon, germanium or similar atoms can be selectively introduced into the substrate.
  • the carbon-containing substrate 1300 may be cleaned to remove natural oxides on the surface of the carbon-containing substrate 1300.
  • the cleaning process includes: firstly, at 1100° C., the carbon-containing substrate 1300 is subjected to in-situ thermal cleaning in a hydrogen environment for a certain period of time, for example, 10 to 20 minutes, and the cleaning solution may be H2SO4:H2O2 (3: 1) Solution, which can remove particles and organic pollutants; then wash with 2% hydrofluoric acid (HF) and deionized water to remove metal pollutants; finally, it can be dried under N2 conditions.
  • H2SO4:H2O2 3: 1 Solution
  • the thickness of the low-temperature aluminum nitride layer 1301 of the light emitting diode is, for example, 5-30 nm.
  • the forming process of the aluminum nitride layer 1301 may specifically include: for example, using the semiconductor device 100 of the present disclosure to form a layer of aluminum nitride film on the surface of the carbon-containing substrate 1300, and the temperature of the carbon-containing substrate 1300 is controlled at, for example, 600-1200°C, By controlling parameters such as sputtering rate, substrate temperature, and sputtering thickness, it is ensured that the surface of the carbon-containing substrate 1300 is covered with aluminum nitride material to form a high-quality low-temperature aluminum nitride layer 1301.
  • a high temperature gallium nitride buffer layer 1302 may be formed on the low temperature aluminum nitride layer 1301.
  • the high temperature gallium nitride buffer layer 1302 includes a first high temperature gallium nitride buffer layer 1302a and a second high temperature gallium nitride buffer layer 1302b .
  • the process includes, for example, two stages:
  • the first stage increase the temperature to a preset temperature, for example, 1050 ⁇ 1100°C, and use low-temperature chemical vapor deposition methods such as plasma enhanced chemical vapor deposition (PECVD) at a low V/III ratio to grow a certain thickness of unintentional
  • PECVD plasma enhanced chemical vapor deposition
  • the doped gallium nitride layer is the first high temperature gallium nitride buffer layer 1302a, and the thickness of the first high temperature gallium nitride buffer layer 1302a is, for example, 200-400 nm;
  • the second stage at the temperature of the first stage, for example, 1050 ⁇ 1100 °C, low-temperature chemical vapor deposition method such as plasma enhanced chemical vapor deposition (PECVD) is used at a high V/III ratio to grow a certain thickness of unintentional doping
  • PECVD plasma enhanced chemical vapor deposition
  • the hetero gallium nitride layer is the second high temperature gallium nitride buffer layer 1302b, and the thickness of the second high temperature gallium nitride buffer layer 1302b is, for example, 0.1 to 0.5 mm.
  • a first semiconductor layer 1303 can be formed on the high-temperature gallium nitride buffer layer 1302, the first semiconductor layer 1303 is a silicon-doped N-type gallium nitride layer, and the silicon-doped material can be, for example, silane (SiH4).
  • the formation process of the first semiconductor layer 1303 includes: at the same temperature as the formation of the high-temperature gallium nitride buffer layer 1302, using a low-temperature chemical vapor deposition method at a high V/III ratio, such as plasma enhanced chemical vapor deposition (PECVD), with a certain growth rate
  • PECVD plasma enhanced chemical vapor deposition
  • the thickness of the silicon-doped N-type gallium nitride layer is the first semiconductor layer 1303.
  • the thickness of the first semiconductor layer 1303 may be, for example, 2 mm, and at the same time, a flat and smooth first semiconductor layer 1303 can be obtained at a high V/III ratio.
  • a light-emitting layer 1304 can be formed on the first semiconductor layer 1303.
  • the light-emitting layer 1304 is a periodic well layer and a barrier layer, and the light-emitting layer 1304 is periodically grown according to the well layer and the barrier layer.
  • the material of the well layer is, for example, In0.15Ga0.85N
  • the material of the barrier layer is, for example, In0.02Ga0.98N.
  • the formation process of the light-emitting layer 1304 may include, for example, a long well layer in a single growth period, the growth temperature is, for example, 700-800°C, the thickness of the well layer may be, for example, 3-5 nm, and then the growth temperature is increased to 800-900°C.
  • the barrier layer is grown under this condition, and the thickness of the barrier layer may be, for example, 9-15 nm. In this embodiment, the growth period is, for example, five.
  • the light-emitting layer 1304 is obtained by growing periodic well layers and barrier layers. In the process of growing the light-emitting layer 1304, in order to increase the incorporation rate of indium, nitrogen is used as a carrier gas.
  • a second semiconductor layer 1305 may be formed on the light-emitting layer 1304, and the second semiconductor layer 1305 is a P-doped P-type gallium nitride layer.
  • the P doping material may specifically be biscyclopentadienyl magnesium (CP2Mg).
  • the formation process of the second semiconductor layer 1305 includes, for example, after the light-emitting layer 1304 is grown, the substrate temperature is increased to, for example, 1000° C., and a magnesium-doped P-type gallium nitride layer with a certain thickness is deposited on the light-emitting layer 1304.
  • the thickness of the second semiconductor layer 1305 may be, for example, 200-400 nm.
  • the light-emitting diode structure further includes an N-type electrode 1306 and a P-type electrode 1307.
  • the Mg-doped P-type gallium nitride layer that is, the second semiconductor layer 1305, can also be activated.
  • the activation process includes, for example, annealing the prepared light-emitting diode structure at, for example, 730° C.
  • the growth can be monitored in situ by reflection measurement.
  • the light-emitting diode structure further includes an N-type electrode 1306 and a P-type electrode 1307.
  • the N-type electrode 1306 is formed on the silicon-doped N-type gallium nitride layer, that is, forming On the first semiconductor layer 1303.
  • the P-type electrode 1307 is formed on the P-type gallium nitride layer, that is, on the second semiconductor layer 1305.
  • the formation process of the N-type electrode 1306 and the P-type electrode 1307 includes, for example, after annealing, using inductively coupled plasma etching to partially etch the surface of the structure until the first semiconductor layer 1303 is exposed and continue to etch a portion of the first semiconductor
  • the layer 1303 forms a recess, and Ni/Au contacts are deposited on the recess and then evaporated to form an N-type electrode 1306.
  • a Ti/Al/Ni/Au contact is deposited as a P-type electrode 1307 on the exposed second semiconductor layer 1305.
  • the substrate 1300, the low-temperature aluminum nitride layer 1301, and the high-temperature gallium nitride buffer layer 1302 can be removed to expose the first semiconductor layer 1303 without etching part of the first semiconductor layer. 1303 forms a recess.
  • an N-type electrode 1306 is formed on the first semiconductor layer 1303, thereby forming a vertical conduction type light emitting diode structure.
  • a low-temperature aluminum nitride layer 1301 and a high-temperature gallium nitride buffer layer 1302 can be used to obtain a high-quality light-emitting diode structure with relatively no cracks and a smooth surface.
  • the manufacturing method of the micro-LED structure may include the following steps: provide a Growth substrate 500; forming a buffer layer 501 on the growth substrate, forming a first semiconductor layer 502 on the buffer layer 501, forming a light-emitting layer 503 on the first semiconductor layer, forming a second semiconductor layer 504 and the light-emitting layer 503;
  • the first semiconductor layer 502, the light emitting layer 503, and the second semiconductor layer 504 are divided into a plurality of light emitting diode structures 505.
  • the growth substrate 500 may be various suitable growth substrates.
  • the material of the growth substrate may be silicon (Si), silicon carbide (SiC), sapphire ((Al2O3), gallium arsenide (GaAs), lithium aluminate (LiAlO2), etc.
  • the growth substrate 500 is, for example, a silicon (Si)-based material, such as silicon (Si) or silicon carbide (SiC).
  • the buffer layer 501 when the buffer layer 501 is formed on the substrate 500, for example, the semiconductor device 100 of the present disclosure can be used, and a high-quality growth substrate 500 can be formed on the growth substrate 500 through a physical vapor deposition (PVD) process.
  • the material of the buffer layer 501 may be a low-temperature nucleation layer formed of aluminum nitride (AlN) or gallium nitride (GaN).
  • AlN aluminum nitride
  • GaN gallium nitride
  • the buffer layer 501 can be used to reduce the lattice mismatch between the growth substrate and the first semiconductor layer, so as to reduce the lattice defects caused by the lattice mismatch, reduce the dislocation density, and improve the quality of the micro light emitting diode.
  • the first semiconductor layer 502 may be an N-type semiconductor doped with a first impurity.
  • the corresponding second semiconductor layer 504 may be a P-type semiconductor layer doped with a second impurity, or an N-type semiconductor layer doped with a first impurity.
  • a light-emitting layer 503 can be formed on the first semiconductor layer 502.
  • the light-emitting layer 503 can be, for example, an intrinsic semiconductor layer or a low-doped semiconductor layer (the doping concentration of which is lower than that of adjacent semiconductor layers of the same doping type) , Or it may be a light-emitting layer formed by a quantum well. In different embodiments, the light-emitting layer 503 is, for example, a quantum well light-emitting layer. For example, indium gallium nitride (InGaN) can be selected.
  • InGaN indium gallium nitride
  • the light-emitting layer 503 can emit blue light, and the material of the blue light-emitting layer can be indium gallium nitride (InGaN), zinc selenide (ZnSe), indium gallium nitride/gallium nitride (InGaN/GaN) One or more of other materials. However, it is not limited to this. In different embodiments, the light-emitting layer 503 may also be a light-emitting layer material that emits green light or red light.
  • the first semiconductor layer 502, the light emitting layer 503, and the second semiconductor layer 504 can be divided into a plurality of light emitting diode structures by etching, laser scribing or other methods, and each light emitting diode includes a part of the first semiconductor layer 502, The light emitting layer 503 and the second semiconductor layer 504.
  • the light emitting diode structure 505 when the light emitting diode structure 505 is divided into a plurality of light emitting diode structures 505, specifically, a recess or groove is formed on the structure after the second semiconductor layer 504 is formed, so that the first semiconductor layer 502, the light-emitting layer 503, and the second semiconductor layer 504 are divided into multiple light-emitting diode structures. Thereafter, a first electrode 505 may be formed on the separated first semiconductor layer 502, and a second electrode 506 may be formed on the separated second semiconductor layer 504. After that, a passivation layer 507 is formed on the separated second semiconductor layer 502. After that, the growth substrate 500 and the buffer layer 501 may be removed (for example, etched) to form a plurality of separated light emitting diode structures (for example, micro light emitting diode structures or micro light emitting diode chips).
  • a recess or groove is formed on the structure after the second semiconductor layer 504 is formed, so that the first semiconductor layer 502, the light-
  • the recess when divided into multiple light-emitting diode structures, specifically, a recess is formed on the second semiconductor 504, the recess may include a first recess and a second recess, the first recess is formed from the second semiconductor layer 504 To the growth substrate 500, the second recess extends from the second semiconductor layer 504 to the first semiconductor layer 502, and the first recess and the second recess may be formed by etching or laser scribing.
  • a layer of photoresist is formed on the second semiconductor layer 504, and the photoresist is dissolved by a photolithography process to obtain a photoresist pattern with a set pattern.
  • the present embodiment uses, for example, an inductively coupled plasma etching process to open the first recess from the second semiconductor layer 504 to the growth substrate 500 on the second semiconductor layer 504, wherein the first recess passes through the second semiconductor layer 504.
  • the semiconductor layer 504, the light emitting layer 503, the first semiconductor layer 502, and the buffer layer 501 reach the growth substrate 500.
  • the first recess passes through the second semiconductor layer 504 and the light-emitting layer 503 and contacts the first semiconductor layer 502. , Wherein the first concave portion and the second concave portion are connected to form a step shape.
  • first electrode 505 when the first electrode 505 is formed on the first semiconductor layer 502, and the second electrode 506 is formed on the second semiconductor layer 504, specifically, evaporation and/or sputtering techniques can be used in each A first electrode 505 is formed on the exposed first semiconductor layer 502, and a second electrode 506 is formed on the second semiconductor layer 504.
  • the first electrode 505 may be located in the second recess.
  • the material of the first electrode 505 and the second electrode 506 may be an opaque conductive material, and the opaque conductive material may include metal materials such as titanium (Ti), platinum (Pt), gold (Au), chromium (Cr), etc., which are opaque
  • the conductive material can also be highly reflective materials such as aluminum (Al) and silver (Ag), so that the first electrode 505 and the second electrode 506 are highly reflective electrodes.
  • solder balls can also be formed by reflow soldering on the first semiconductor layer 502 and the second semiconductor layer 504 through a protective gas flow.
  • a passivation layer 507 is first formed on the surface of the second semiconductor layer 504, and then a passivation layer 507 can be formed on the passivation layer 507.
  • the patterned photoresist layer is etched according to the patterned photoresist layer to form a patterned passivation layer 507, and then the patterned photoresist layer is removed and cleaned.
  • the passivation layer 507 is also located near the first electrode 505 and the second electrode 506.
  • the material of the passivation layer 507 includes silicon oxide or aluminum oxide, for example, to protect the micro light emitting diode structure, avoid problems such as reverse leakage, and improve the reliability of the diode structure.
  • the passivation layer 507 The material of can be selected as silicon oxide to facilitate the etching of the openings.
  • the passivation layer 507 can be etched by a buffered silicon oxide etching solution or dry etching.
  • the growth substrate 500 and the buffer layer 501 can be etched using, for example, an etching technique to obtain a plurality of micro light emitting diode structures.
  • the etching technique includes a dry method. Etching and wet etching. In wet etching, an etchant is needed.
  • the etchant may be, for example, nitric acid, hydrofluoric acid, peroxide, alkali, ethylenediamine catechol, amine gallate ), TMAH, hydrazine, etc.
  • the first electrode 505 can be formed on the exposed bottom surface of the first semiconductor layer 502, thereby forming a vertical conduction type light emitting. Diode structure.
  • micro light emitting diode structure and a manufacturing method thereof provided in this embodiment multiple micro light emitting diode structures can be obtained at the same time, and the manufacturing efficiency of obtaining the micro light emitting diode is improved.
  • the first semiconductor layer 502, the light emitting layer 503, and the second semiconductor layer 504 are divided into a plurality of light emitting diode structures 505, specifically, etching the growth substrate 500 and Buffer layer 501, forming multiple first channels; using conductive material to fill the first channel; etching growth substrate 500, buffer layer 501, first semiconductor layer 502, conductive layer 503, forming multiple second channels; using conductive material Filling the second channel; forming a first solder ball 508 on the conductive material of the first channel, forming a second solder ball 509 on the conductive material of the second channel; forming a passivation layer on the second semiconductor layer 504; A recess is provided on the second semiconductor layer 504 to divide the first semiconductor layer 502, the light-emitting layer 503, and the second semiconductor layer 504 into a plurality of light-emitting diode structures. The recesses pass through the passivation layer 507, the second semiconductor layer 504, and emit light
  • the conductive material can be filled into the first channel.
  • a vapor deposition method under vacuum, a film, a paste, or a liquid coating can be used. , Casting or their combination.
  • a reflective metal layer is deposited on the first semiconductor layer 502 through the first channel, and then a conductive material is used to fill the channel and form a contact.
  • the conductive material may include conductive metals and metal oxides, such as Al, Au, Cu, Ag, Pt, and the like.
  • the growth substrate 500, the buffer layer 501, the first semiconductor layer 502, and the conductive layer 503 are etched to form a plurality of second channels, specifically, the growth substrate 500, the buffer layer 501,
  • the etching techniques include dry etching and wet etching.
  • the second channel may have any desired shape.
  • the first channel passes through the growth substrate 500, the buffer layer 501, the first semiconductor layer 502, and the conductive layer 503 to reach the second semiconductor layer 504.
  • the conductive material is filled into the second channel, which may include a vapor deposition method, a film, a paste, and a liquid optionally under vacuum. Coating, casting or their combination.
  • a reflective metal layer is deposited on the second semiconductor layer 504 through the second channel, and then a conductive material is used to fill the channel and form a contact.
  • the protective airflow is connected to the first channel
  • the first solder ball 508 is formed by reflow soldering on the conductive material of
  • the second solder ball 509 is formed on the conductive material of the second channel
  • the first solder ball 508 and the second solder ball 509 can be arranged on the same horizontal plane.
  • other electrical connections such as pins, can also be formed on the electrodes.
  • the material of the passivation layer 507 may include, for example, silicon oxide or aluminum oxide, which can protect the diode structure and avoid problems such as reverse leakage. , Improve the reliability of the diode structure.
  • the material of the passivation layer can be silicon oxide, which is convenient to etch the holes.
  • the passivation layer can be etched by buffering silicon oxide etching solution or dry etching.
  • a plurality of micro light emitting diode structures can be integrated into a micro light emitting diode chip through a passivation layer 507, a package body or a packaging glue.
  • the multiple micro light emitting diode structures of the micro light emitting diode chip may have the same light color (for example, blue light) or different light colors.
  • FIGS. 57 to 58 when a recess is formed on the second semiconductor layer 504 to divide the first semiconductor layer 502, the light emitting layer 503, and the second semiconductor layer 504 into a plurality of light emitting diode structures, specifically, A recess is formed on the second semiconductor, and the recess penetrates the passivation layer 507, the second semiconductor layer 504, the light-emitting layer 503, the first semiconductor layer 502, the buffer layer 501 and the growth substrate 500.
  • the opening process can be etching or laser scribing.
  • the recesses pass through the second semiconductor layer 504, the light emitting layer 503, the first semiconductor layer 502, the buffer layer 501 and the growth substrate 500 to obtain a plurality of micro light emitting diode structures.
  • the first semiconductor layer 502, the light emitting layer 503, and the second semiconductor layer 504 are divided into a plurality of light emitting diode structures 505, specifically, in the second semiconductor layer A second electrode 506 is grown on 504; a first recess 510 is etched on one side of the second electrode 506, and the first recess 510 passes through the second semiconductor layer 504, the light emitting layer 503, the first semiconductor layer 502 and a part of the buffer layer 501;
  • the insulating layer 511 is filled in the first recess 510, and the insulating layer 511 fills the first recess 510 and part of the second semiconductor layer 504, and the insulating layer 511 is connected to the side of the second electrode 506; it is formed on the side close to the first recess 510
  • the second recess 512, the second recess 512 passes through the second semiconductor layer 504, the light emitting layer 503, the first semiconductor layer 502, and a portion of the buffer layer
  • a plurality of second electrodes 506 may be formed on the second semiconductor layer 504 by evaporation and/or sputtering technology. There is a certain preset distance between the second electrodes 506.
  • a photoresist pattern with a set pattern can be formed on the second semiconductor layer 504, under the protection of the photoresist Using, for example, a dry etching or wet etching process, a first recess 510 is formed on the second semiconductor layer 504, and the first recess 510 passes through the first recess 510, passes through the second semiconductor layer 504, the light emitting layer 503, the first semiconductor layer 502, and Part of the buffer layer 501.
  • the first recess 510 is filled with an insulating material, and the insulating material is connected to the side surface of the second electrode 506 to form the insulating layer 511.
  • the insulating material includes, for example, SiOx, SiNx, and SiON, or other inorganic insulating materials.
  • a photoresist pattern with a predetermined pattern is formed on the second semiconductor layer 504, under the protection of the photoresist, Using, for example, a dry etching or wet etching process, a second recess 512 is formed on the second semiconductor layer 504.
  • the second recess 512 passes through the second semiconductor layer 504, the light emitting layer 503, the first semiconductor layer 502 and a portion of the buffer layer 501.
  • the depth of the recess 512 and the first recess 510 may be the same or different.
  • the second recess 512 when the second recess 512 is filled with a conductive material to form the second electrode extension structure 513, specifically, the second recess 512 is filled with a conductive material, and the conductive material fills the second recess 512 and covers
  • the insulating layer 511 is connected to the side of the second electrode 506 opposite to the second semiconductor 504 to form a second electrode extension structure 513.
  • the conductive material may be, for example, a conductive metal or alloy.
  • a passivation layer 507 when a passivation layer 507 is grown on the second semiconductor layer 504, specifically, a passivation layer 507 is formed on the second semiconductor layer 504, and the passivation layer 507 can cover the second electrode extension structure 513 And the second semiconductor layer 504.
  • the passivation layer 507 may be a material such as silicon oxide. However, it is not limited to this. In some embodiments, the passivation layer 507 can be used as a protective layer or a package and formed on the second semiconductor layer 504 and the second electrode 506.
  • the growth substrate 500 and the buffer layer 501 are removed (eg, etched), specifically, the growth substrate 500 and the buffer layer 501 are etched using, for example, an etching technique.
  • the etching technique includes dry etching and wet etching. By etching the growth substrate 500 and the buffer layer 501, the first semiconductor layer 502, part of the insulating layer 511, and the second electrode extension structure 513 are exposed.
  • first electrode 505 when the first electrode 505 is formed on the first semiconductor layer 502, specifically, a plurality of first electrodes 505 are formed on the first semiconductor layer 502 by evaporation and/or sputtering technology.
  • the length of 505 is, for example, equal to the thickness of the insulating layer 511 extending to the buffer layer 501.
  • first solder ball 508 is formed on the first electrode 505, and a second solder ball 507 is formed on the second electrode extension structure 513, specifically, a protective air flow can be used to reflow on the first electrode 505
  • a first solder ball 508 is formed by soldering, and a second solder ball 509 is formed on the second electrode extension structure 513, and the first solder ball 508 and the second solder ball 509 can be arranged on the same horizontal plane.
  • other electrical connections such as pins, can also be formed on the electrodes.
  • a concave portion can be opened, and the concave portion passes through the first semiconductor layer 502, the light emitting layer 503, and the second semiconductor layer 505 to reach The passivation layer 507 thus obtains a plurality of micro light emitting diode structures.
  • a plurality of micro light emitting diode structures can be integrated into a micro light emitting diode chip through a passivation layer 507, a package body or a packaging glue.
  • the multiple micro light emitting diode structures of the micro light emitting diode chip may have the same light color (for example, blue light) or different light colors.
  • the micro light emitting diode chip panel may include: a circuit substrate 700 and a substrate layer 701 , Multiple micro light emitting diode chips 703, multiple electrical connectors 702 and planarization layer 704, light blocking layer 705, red wavelength conversion layer 706, green wavelength conversion layer 707, transparent photoresist 707a, protective layer 708 and protective substrate 709.
  • the substrate layer 701 is arranged on the circuit substrate 700, the plurality of micro light emitting diode chips 703 are arranged on the substrate layer 701, the plurality of electrical connectors 702 are arranged between the substrate layer 701 and the plurality of micro light emitting diode chips 703, and the planarization layer 704 is arranged on a plurality of micro light emitting diode chips 703, the light blocking layer 705, the red wavelength conversion layer 706, and the green wavelength conversion layer 707 are arranged on the planarization layer 704, and the protective layer 708 is arranged on the light blocking layer 705 and the red wavelength conversion layer 706. On the green wavelength conversion layer 707 and in the gap, the protective substrate 709 is disposed on the protective layer 708.
  • the circuit substrate 700 may be, for example, a TFT driving circuit substrate.
  • a substrate layer 701 may be provided on the circuit substrate 700.
  • the substrate layer 701 may be a substrate layer formed of polyimide (PI) material.
  • the heat resistance of the polyimide (PI) material ensures that the high temperature (>400 °C), the display panel is not damaged, and the low thermal expansion coefficient of polyimide (PI) material ensures high resolution (>300ppi) and process alignment accuracy required in the panel manufacturing process.
  • the polyimide (PI) material's strong absorption characteristics of ultraviolet light the polyimide (PI) material can be peeled off by irradiating the polyimide (PI) material through the glass with an ultraviolet band laser.
  • a driving circuit is further provided on a surface of the circuit substrate 700 close to the substrate layer.
  • the driving circuit is partially disposed on the circuit substrate 700 and partially disposed on the substrate layer 701.
  • the function of the driving circuit is to light up the micro light emitting diode chip 703 that is electrically connected to it, wherein a plurality of micro light emitting diode chips 703 may have the same or different light colors, for example, a plurality of micro light emitting diode chips 703 may emit blue, red or green light.
  • the switch of each micro light emitting diode chip 703 is controlled by a driving circuit. Without changing the magnitude of the current, the brightness of the micro-light-emitting diode panel can be changed by controlling the number of micro-light-emitting diode chips 703 to be lit.
  • a plurality of micro light emitting diode chips 703 can be arranged in an array on the circuit substrate 700, and each micro light emitting diode chip 703 is equally spaced, and the distance between adjacent micro light emitting diode chips 703 is smaller than that of the micro light emitting diode chips 703.
  • the length or width of the micro light emitting diode chip makes the display device composed of the micro light emitting diode chip have a higher resolution.
  • the width of the micro light emitting diode chip 703 is, for example, less than or equal to 10 micrometers, and the adjacent micro light emitting diode chip 703 is less than or equal to 10 micrometers. In other embodiments, the width of the micro light emitting diode chip 703 is, for example, less than or equal to 5 micrometers, and the adjacent micro light emitting diode chip 703 is less than or equal to 5 micrometers.
  • a plurality of electrical connectors 702 are further included between the substrate layer 701 and the plurality of micro light emitting diode chips 703.
  • the driving circuit on the substrate layer 701 is connected to The micro light emitting diode chip 703 is connected.
  • the driving circuit is provided with electrical connection points on the side of the substrate layer 701 away from the circuit substrate 700, and the side of the micro light emitting diode chip 703 close to the substrate layer 701 has electrodes.
  • the electrical connectors 702 can connect the electrical connection points. Connect with the electrode.
  • the electrical connector 702 may be a metal connector, for example, an indium/tin connector.
  • a planarization layer 704 is provided between and above the plurality of micro light emitting diode chips 703.
  • the planarization layer 704 may include a polymer-based material, and the polymer-based material may be transparent, for example, may include silicon.
  • a planarization layer 704 is formed between the micro light emitting diode chips 703 and the upper part of the micro light emitting diode chips 703 through exposure and development processes.
  • the planarization layer 704 further includes a first insulating layer and a second insulating layer (not shown), wherein the first insulating layer is disposed on the planarization layer 704 close to the plurality of micro light emitting diodes.
  • the second insulating layer is disposed on the side away from the plurality of micro light emitting diode chips 703.
  • external impurities for example, moisture may damage the micro light emitting diode chip 703.
  • the first insulating layer and the second insulating layer include inorganic insulating materials such as SiOx, SiNx, and SiON.
  • the first insulating layer and the second insulating layer may include the same material as each other or different materials from each other.
  • the second insulating layer may have a thickness greater than that of the first insulating layer. In various embodiments, the thickness of the second insulating layer may be equal to or less than the thickness of the first insulating layer.
  • One micro-light-emitting diode chip 703 includes multiple micro-light-emitting micro-diodes. During the process of forming the micro-light-emitting diode panel, the number of massive transfers can be reduced, the error loss is reduced, and the yield rate in manufacturing is improved. .
  • a light blocking layer 705 is provided on the planarization layer 704, wherein the light blocking layer 705 includes a plurality of light blocking layer blocks, the light emitting diode chip 703 is located in the gap between adjacent light blocking layer blocks, and the micro light emitting diode chip The light emitted by 703 passes through the gap.
  • the method for forming the light barrier layer 705 includes: forming a light barrier layer material layer on the planarization layer 704; processing the light barrier layer material layer by a patterning process to obtain a light barrier layer pattern, that is, a plurality of light barrier layers.
  • the light barrier layer block is located between the micro light emitting diode chips 703; coating, magnetron sputtering or plasma enhanced chemical vapor deposition method is used to form a photoresist on the material layer of the light barrier layer Layer; expose and develop the photoresist layer to obtain a photoresist pattern; etch the material layer of the photoresist layer through the photoresist pattern, and peel off the photoresist pattern to obtain a patterned photoresist layer 705, that is, multiple Light blocking layer composed of light blocking layer blocks.
  • the surface of the light blocking layer 705 may be fluorinated using a plasma fluorination process.
  • the plasma fluorination process is used to perform fluorination treatment on the surface of the light barrier layer 705, thereby reducing the surface tension of the resulting light barrier layer 705.
  • the micro light emitting diode panel further includes a red wavelength conversion layer 706, a green wavelength conversion layer 707, and a transparent photoresist 707a, which are used to The luminescence of the light-emitting diode is converted into red or green light, which can form a full color.
  • the red wavelength conversion layer 706 and the green wavelength conversion layer 707 are respectively disposed between the light blocking layers 705 and can cover the edges of the light blocking layer 705 to prevent optical light leakage.
  • a blue wavelength conversion layer is further included, which may be disposed at the gap of the light barrier layer 705 and cover the edge of the light barrier layer 705.
  • the step of forming the red wavelength conversion layer 706 may include: forming a red color resist film on the planarization layer 704 with the photo-blocking layer 705; coating photoresist on the insulating layer formed with the red color resist film , Form a photoresist layer; use a mask to expose the photoresist layer from the side of the photoresist layer away from the insulating layer; develop the exposed photoresist layer; etch and peel off the photoresist layer to obtain Patterned red wavelength conversion layer 706.
  • the process of forming the red color resist film may include: uniformly scraping the red color resist material over the entire insulating layer with a squeegee; spin coating, vacuum adsorption of the insulating layer coated with the red color resist material Set on the spin coater, the center drops liquid and controls the spin coater to rotate at a high speed to form a certain thickness of red color resist film on the insulating layer; pre-baking makes the solvent in the red color resist film volatilize and enhances the red color resist film and insulation The viscosity of the layer.
  • the red wavelength conversion layer 706 and the green wavelength conversion layer 707 are arranged at intervals, and the red wavelength conversion layer 706, the green wavelength conversion layer 707, and the light blocking layer 705 can also prevent light reflection.
  • the micro light emitting diode chip further includes providing a protective layer 708 on the light blocking layer 705, the red wavelength conversion layer 706, the green wavelength conversion layer 707, and the transparent photoresist 707a. It is located above the light blocking layer 705, the red wavelength conversion layer 706, the green wavelength conversion layer 707, and the transparent photoresist 707a.
  • the material of the protective layer 708 may be a transparent resin material. In this embodiment, the material of the protective layer 708 may be a propionate polymer.
  • the process of forming a micro-LED panel of the light emitting diode further includes setting a protective substrate 709 on the protective layer 708, and the protective substrate 709 is bonded to the protective layer 708 to form a hermetic cavity.
  • the present disclosure also provides another micro light emitting diode panel and its forming process.
  • the circuit substrate 800 is further provided with a driving circuit on the side surface close to the substrate layer, and the driving circuit is partially disposed on the circuit substrate 800 and partially disposed on the substrate layer 801.
  • the micro light emitting diode chip 803 electrically connected to the micro light emitting diode chip 803 can be lighted up by the function of the driving circuit. Without changing the magnitude of the current, the brightness of the micro-light-emitting diode panel can be changed by controlling the number of micro-light-emitting diode chips 803 to be lit.
  • a plurality of electrical connectors 802 are also included between the substrate layer 801 and the plurality of micro-light-emitting diode chips 803.
  • the driving circuit on the substrate layer 801 is connected to the micro-light-emitting diode chips.
  • the chip 703 is connected.
  • the driving circuit is provided with an electrical connection point on the side of the substrate layer 801 away from the circuit substrate 800, and the micro light emitting diode chip 803 has an electrode on the side close to the substrate layer 801, and the electrical connector 802 can connect the electrical connection point Connect with the electrode.
  • the electrical connector 802 may be a metal connector, such as an indium/tin connector or a tin ball.
  • a planarization layer 804 is provided between and above the micro LED chips 803, and the planarization layer 804 is formed between and on the micro LED chips 803 through exposure and development processes.
  • the planarization layer 804 may include an optical layer.
  • the optical layer can improve the luminous efficiency of the light emitted from the micro-light-emitting diode structure or reduce the chromatic aberration, so that the divergent light can be kept smaller. The divergence angle shoots out.
  • the optical layer may include a layer having a concave lens or a convex lens shape and may include a plurality of layers having different refractive indexes.
  • a light-transmitting substrate 809 is provided.
  • a light-blocking layer 805 is provided on the light-transmitting substrate 809.
  • the light-blocking layer 805 includes a plurality of light-blocking layer blocks.
  • the light-blocking layer 805 is formed The method includes: forming a light barrier layer material layer on a transparent substrate 809; processing the light barrier layer material layer by a patterning process to obtain a light barrier layer pattern, that is, a plurality of light barrier layer blocks, wherein each of the light barrier layers There are gaps between the layer blocks.
  • a micro light emitting diode panel when the micro light emitting diode in the micro light emitting diode chip 803 emits blue light, a micro light emitting diode panel further includes a red wavelength conversion layer 806, a green wavelength conversion layer 807, and a transparent photoresist 807a, and a red wavelength conversion layer 806, the green wavelength conversion layer 807, and the transparent photoresist 807a are respectively arranged at the gaps of the light barrier layer 805 and cover the edges of the light barrier layer 805 to prevent optical light leakage, and the red wavelength conversion layer 806 and the green wavelength conversion layer 807 are separated Set up.
  • the step of forming the red wavelength conversion layer 806 includes: forming a red color resist film on the transparent substrate 808 with a light blocking layer; coating photoresist on the insulating layer formed with the red color resist film to form Photoresist layer; use a mask to expose the photoresist layer from the side of the photoresist layer away from the insulating layer; develop the exposed photoresist layer; etch and strip the photoresist layer to obtain patterning The red wavelength conversion layer 806.
  • the red wavelength conversion layer 806 and the green wavelength conversion layer 807 are arranged at intervals, and the reflection of light can be prevented by the red wavelength conversion layer 806, the green wavelength conversion layer 807, and the light blocking layer 805.
  • the protective layer 808 is located in the light blocking layer 805, red wavelength conversion layer 806, green wavelength conversion layer 807 and transparent photoresist 807a Above.
  • the material of the protective layer 808 can be a transparent resin material.
  • the material of the protective layer 808 can be a propionate polymer, and the protective layer 808 can be deposited by sputtering or evaporation.
  • the process of forming a micro-light emitting diode chip also includes forming a transparent conductive layer 809 on the protective layer 808.
  • the material of the transparent conductive layer 809 can be, but is not limited to, indium tin oxide, indium zinc For oxides, etc., the transparent conductive layer 809 can be deposited by sputtering or evaporation.
  • the transparent substrate 808 and the structure included thereon include a light blocking layer 805, a red wavelength conversion layer 806, a green wavelength conversion layer 805, a protective layer 808, a transparent conductive layer 809 and a circuit substrate 800 and the The micro light emitting diode structure 801 and the deflection layer 802 are bonded to form the micro light emitting diode chip.
  • the micro-light-emitting diode panel may include a circuit substrate, a plurality of micro-light-emitting diode chips 903, and a wavelength conversion layer 906.
  • the circuit substrate may be a film transistor array substrate, and the thin film transistor array substrate has a plurality of thin film transistors (TFT).
  • the circuit substrate includes a base 900 and a circuit layer 901, and the circuit layer 901 is generally disposed on the upper portion of the base 900.
  • the base 900 may be a glass substrate, a sapphire substrate, etc., and the base 900 has a fixed property and a flat surface.
  • the circuit layer 901 includes a driving circuit and a plurality of switching elements.
  • the substrate 900 includes a display area and a non-display area, the non-display area includes a driving circuit, and the display area includes a plurality of micro light emitting diode chips 903.
  • a plurality of micro light emitting diode chips 903 are arranged on the circuit substrate, the micro light emitting diode chips 903 are electrically connected to the circuit layer 901 on the circuit substrate, and the driving circuit on the circuit substrate can drive the plurality of micro light emitting diode chips 903 shines.
  • a plurality of micro light emitting diode chips 903 arranged on a circuit substrate can form a pixel structure.
  • the circuit substrate includes a plurality of pixel structures, and the plurality of pixel structures are arranged in an array in a display area of the circuit substrate.
  • a plurality of bonding contacts 902 are further provided on the circuit layer 901, and a plurality of micro light emitting diode chips 903 are specifically provided on the plurality of bonding contacts 902, specifically, electrodes are provided on the micro light emitting diode chips 903, The plurality of electrodes are electrically connected to the plurality of bonding contacts 902.
  • the multiple light-emitting diode chips are electrically connected to the circuit substrate through the bonding contacts 902.
  • the driving circuit on the circuit substrate can light up the micro light emitting diode chip 903 connected to it.
  • the bonding contact 902 may be a metal bonding contact 902, such as an indium/tin bonding contact 902.
  • the bond contact 902 may include benzocyclobutene (BCB).
  • the low-light-emitting diode chip 903 includes a plurality of micro-light-emitting diode structures 903a, and the plurality of micro-light-emitting diode structures 903a are arranged in the micro-light-emitting diode chip 903 in an array form.
  • the distance between adjacent micro light emitting diode structures 903a is smaller than the width of the micro light emitting diode structure 903a.
  • the width of the micro light emitting diode structure 903a is, for example, 5 micrometers, and the distance between adjacent micro light emitting diode structures 903a is less than 5 micrometers.
  • a light blocking layer 905 is provided above the micro light emitting diode chip 903, and the light blocking layer 905 is located at a gap between adjacent micro light emitting diode structures 903a.
  • the orthographic projection of the light blocking layer 905 on the circuit substrate and the orthographic projection of the micro light emitting diode structure 903a on the circuit substrate do not overlap.
  • the light blocking layer 905 has the characteristics of reflectivity, scattering or light absorption. Disposing the light blocking layer 905 between the adjacent micro LED structures 903a can prevent the light emitted by the micro LED structures 903a from interfering with each other and reduce the problem of light leakage.
  • a wavelength conversion layer is provided above the micro light emitting diode chip 903, and the multiple wavelength conversion layers 906 are provided directly above the multiple micro light emitting diode structures 903a, and are located on the other side of the circuit substrate relative to the micro light emitting diode chip 903. side.
  • the wavelength conversion layer is located between the adjacent light blocking layers 905, and the orthographic projection of the wavelength conversion layer overlaps the orthographic projection of the micro light emitting diode structure 903a on the circuit substrate.
  • the wavelength conversion layer 906 covers a part of the light blocking layer 905, which can reduce light leakage.
  • At least one wavelength conversion layer 906 is formed on the plurality of micro light emitting diode chips 903, and the materials used to make the wavelength conversion layer 906 include phosphors and quantum dots.
  • the wavelength conversion layer 906 may include, for example, a first wavelength conversion layer 906a, a second wavelength conversion layer 906b, and a third wavelength conversion layer 906c.
  • the micro-light-emitting diode structure 903a is, for example, a micro-light-emitting diode structure 903a that emits blue light
  • the first wavelength conversion layer 906a may be, for example, a red wavelength conversion layer 906, and the second wavelength conversion layer 906b may be a green wavelength conversion layer or a third wavelength.
  • the conversion layer 906c may be a wavelength conversion layer 906 composed of a scattering material and a wavelength conversion structure, but does not change the light output of the micro light emitting diode structure 903a. Red light can be presented through the first wavelength conversion layer 906a, green light can be presented through the second wavelength conversion layer 906b, blue light can be presented through the third wavelength conversion layer 906c, and blue light can be presented through the first wavelength conversion layer 906a, the second wavelength conversion layer 906b, and the second wavelength conversion layer 906b.
  • the three-wavelength conversion layer 906c makes the pixel structure exhibit a full-color display effect.
  • the wavelength conversion layer 906 may further include a blue wavelength conversion layer 906.
  • the multiple wavelength conversion layers 906 have the same thickness, so that the light conversion quality can be optimized and the light extraction efficiency can be uniform.
  • the micro light emitting diode chip 903 is, for example, a red light emitting micro light emitting diode chip 903, the first wavelength conversion layer 906a may be a green wavelength conversion layer, and the second wavelength conversion layer 906b may be Blue wavelength conversion layer.
  • the micro light emitting diode chip 903 is, for example, a green light emitting micro light emitting diode chip 903, the first wavelength conversion layer 906a may be a red wavelength conversion layer, and the second wavelength conversion layer 906b may be a blue wavelength conversion layer.
  • the micro light emitting diode chip 903 is, for example, a micro light emitting diode chip 903 emitting ultraviolet light
  • the first wavelength conversion layer 906a may be a red light wavelength conversion layer
  • the second wavelength conversion layer 906b may be a green light wavelength conversion layer
  • the third wavelength conversion layer 906c may be a blue wavelength conversion layer.
  • the wavelength conversion layer may be formed of photoresist materials or quantum dot materials of different colors, and the wavelength conversion layer may be formed on a micro light emitting diode chip or individual micro light emitting diodes to convert micro light emission.
  • the wavelength of the light emitted by the diode that is, the light color emitted by the micro light emitting diode is converted.
  • the micro-luminescence display panel includes a protective layer 904, which is disposed between adjacent pixels and above the light blocking layer 905 and the wavelength conversion layer 906.
  • the protective layer 904 can prevent the micro-luminescence diode panel from generating moisture or oxidation.
  • the micro-luminescence display panel includes a protective substrate 907 disposed on the protective layer 904, and the protective substrate 907 and the protective layer 904 are bonded to form a hermetic cavity.
  • the above-mentioned light blocking layer is arranged between the micro light emitting diode chip or the micro light emitting diode to block different light colors.
  • the above-mentioned light blocking layer may be, for example, a white light blocking layer or a highly reflective blocking layer to reflect the light emitted by the micro light emitting diode.
  • the white or high-reflective light blocking layer may be, for example, a cone-shaped, so as to reflect the light emitted by the micro-light emitting diode upward and improve the light extraction efficiency.
  • the present disclosure also provides an electronic device.
  • the electronic device includes a micro LED panel 910 and an electronic device body 911.
  • the micro LED panel 910 is connected to the electronic device body 911, wherein the micro LED panel 910 includes a circuit A substrate, a plurality of micro light emitting diode chips 903, and at least one wavelength conversion layer 906.
  • the electronic device body 911 includes a controller 911a, a memory 911b, and a power supply 911c.
  • the power supply 911c can convert the mains power (220V alternating current) into the direct current required by the controller 911a and the memory 911b, and at the same time provide power for the micro light emitting diode panel 910.
  • the memory 911b is connected to the power supply 911c and used to store data related to the operation of the electronic device.
  • the controller 911a is connected to the power supply 911c and connected to the memory 911b at the same time.
  • the power supply 911c is used to supply power to the controller 911a.
  • the program controls the electronic device.
  • the electronic device can be, for example, a display panel, a mobile phone, a watch, a notebook computer, a drop-in device, a charging device, a charging station, a virtual reality (VR) device, an augmented reality (AR) device, a portable electronic device, a game console Or other electronic devices.
  • VR virtual reality
  • AR augmented reality
  • the semiconductor device when the semiconductor epitaxial structure of the present disclosure is applied to manufacture a semiconductor device, the semiconductor device includes a substrate 1400, a buffer layer 1401, a first semiconductor layer 1402, a second semiconductor layer 1403, a source electrode 1404, and a drain electrode 1405. And the gate 1406.
  • the buffer layer 1401 is disposed on the substrate
  • the first semiconductor layer 1402 is disposed on the buffer layer 1401
  • the second semiconductor layer 1403 is disposed on the first semiconductor layer 1402
  • the source electrode 1404 is formed on the second semiconductor layer 1403
  • the drain electrode 1404 is formed on the second semiconductor layer 1403.
  • 1405 is formed on the second semiconductor layer 1403
  • the gate 1406 is formed on the second semiconductor layer 1403 and is located between the source 1404 and the drain 1405.
  • the substrate 1400 can be any suitable growth substrate 1400.
  • the material of the substrate 1400 can be a semiconductor substrate such as silicon (Si), silicon carbide (SiC), sapphire ((Al2O3), gallium arsenide (GaAs), lithium aluminate (LiAlO2), etc. 1400 material.
  • the substrate 1400 is, for example, a silicon (Si)-based material, such as silicon (Si) or silicon carbide (SiC).
  • the buffer layer 1401 is disposed between the substrate 1400 and the first semiconductor layer 1402, which can alleviate the lattice mismatch between the substrate 1400 and the first semiconductor layer 1401.
  • the material of the first semiconductor layer 1402 may be, for example, a gallium nitride layer containing indium.
  • the buffer layer 1401 is, for example, a gallium nitride layer, and the thickness of the gallium nitride layer can be set to, for example, 5-10 nm.
  • the buffer layer 1401 provided between the substrate 1400 and the first semiconductor layer 1402 facilitates the growth of subsequent epitaxial structures and improves the quality of the semiconductor device.
  • the material of the first semiconductor layer 1402 is, for example, an indium-containing gallium nitride layer (InGaN).
  • InGaN indium-containing gallium nitride layer
  • Using a gallium nitride layer containing indium as the first semiconductor layer 1402 can reduce the noise figure of the semiconductor device, and when the first semiconductor layer 1402 contains indium, the electron affinity increases, providing high leakage current for the semiconductor device and Higher cut-off frequency.
  • the thickness of the first semiconductor layer 1402 can be set to, for example, 70 to 80 nm. However, it is not limited to this. In other embodiments, the first semiconductor layer 1402 may also be a gallium nitride layer.
  • the semiconductor device includes a second semiconductor layer 1403, and the second semiconductor layer 1403 is located on the first semiconductor layer 1402.
  • the material of the second semiconductor layer 1403 may be an indium-containing aluminum nitride layer (InAlN), and the thickness of the second semiconductor layer 1403 may be, for example, 15-25 nm.
  • InAlN indium-containing aluminum nitride layer
  • a higher aluminum content has a higher carrier density, so that the semiconductor device has a higher leakage current and transconductance, and at the same time, a lower minimum noise figure is obtained.
  • the second semiconductor layer 1403 adopts an aluminum nitride layer containing indium, which can improve the lattice mismatch with the buffer layer 1401.
  • the principle of low melting point of indium can be used, and InAlN can be obtained by easy diffusion at high temperature.
  • the method of the second semiconductor layer 1403 includes: periodically growing a first AlN layer, a first InN layer, and a second AlN layer to obtain the second semiconductor layer 1403. In the process of growing the second semiconductor, by controlling the growth temperature and the first AlN layer. The thickness of an AlN layer, the first InN layer and the second AlN layer adjust the content of indium in the second semiconductor layer 1403.
  • the second semiconductor layer 1403 uses the principle of low melting point of indium and easy diffusion at high temperature to obtain InAlN as the second semiconductor layer 1403.
  • the second semiconductor layer 1403 can effectively reduce the dark current of the semiconductor device, thereby reducing the noise of the semiconductor device The current improves the signal-to-noise ratio and the quality of the semiconductor device.
  • the semiconductor device includes a source 1404, a drain 1405, and a gate 1406.
  • the source 1404, the drain 1405, and the gate 1406 are all disposed on the second semiconductor layer 1403, and the gate 1406 is located at the source. Between the pole 1404 and the drain 1405.
  • One side of the semiconductor device is provided with a first recess and a second recess.
  • the first recess is provided with a source electrode 1404, and the second recess is provided with a drain electrode 1405.
  • the first recess is located on one side of the semiconductor device, and the first recess is etched on the second semiconductor layer 1403.
  • the depth of the first recess is smaller than the thickness of the second semiconductor layer 1403, that is, the depth of the first recess is smaller than the thickness of the second semiconductor layer 1403.
  • the bottom has a certain preset distance from the bottom of the second semiconductor layer 1403, that is, the first preset distance; the second recess is disposed on the second semiconductor layer 1403, and is located on the opposite side of the first recess, in the second
  • the second recess is etched on the semiconductor layer 1403, and the depth of the second recess is smaller than the thickness of the second semiconductor layer 1403, that is, the bottom of the second recess and the bottom of the second semiconductor layer 1403 have a certain preset distance, that is, the second Preset distance.
  • the first preset distance is equal to the second preset distance.
  • the source electrode 1404 is disposed in the first recess and higher than the first recess
  • the drain 1405 is disposed in the second recess and higher than the second recess
  • the gate 1406 is disposed on the second semiconductor layer 1403 .
  • the gate 1406 is located between the source 1404 and the drain 1405, and is closer to the source 1404 side.
  • the gate 1406 may have a "T" shape to improve noise.
  • an oxide layer 1407 is further included between the gate 1406 and the second semiconductor layer 1403.
  • the oxide layer 1407 may include at least one of ITO, ZnO, RuOx, TiOx, or IrOx.
  • the oxide layer 1407 is a titanium dioxide layer (TiO2). Compared with other oxides, the current and cut-off frequency of the semiconductor device can be improved by setting the titanium dioxide layer as the oxide layer 1407. At the same time, the oxide layer 1407 can reduce the contact resistance between the gate 1406 and the second semiconductor layer 1403, thereby improving the noise of the semiconductor device and making it less noise at the maximum effective current.
  • the side of the source electrode 1404 in contact with the second semiconductor layer 1403 includes a first N-type heavily doped region 1409, and the first N-type heavily doped region 1409 is located in the first trench. Inside the groove, and the height of the first N-type heavily doped region 1409 is higher than the second semiconductor layer 1403 to ensure that the first N-type heavily doped region 1409 is in complete contact with the second semiconductor layer 1403.
  • the side of the drain electrode 1405 in contact with the second semiconductor layer 1403 includes a second N-type heavily doped region 1408, the second N-type heavily doped region 1408 is located in the second trench, and the second N-type heavily doped region
  • the height of 1408 is higher than the second semiconductor layer 1403, which ensures that the second N-type heavily doped region 1408 is in full contact with the second semiconductor layer 1403.
  • the first N-type heavily doped region 1409 and the second N-type heavily doped region 1408 are both highly doped regions, which form a good ohmic contact with the second semiconductor layer 1043.
  • the radio frequency module when the semiconductor device of the present disclosure is applied to a radio frequency module, the radio frequency module includes the semiconductor device.
  • the radio frequency module mainly includes a radio frequency (RF) switching device 1411, a radio frequency (RF) active device 1414, a radio frequency (RF) passive device 1412, and a control device 1413.
  • the radio frequency (RF) active device 1414 may be the semiconductor device described in this application, and the radio frequency (RF) passive device 1412 may be passive devices such as capacitors, resistors, and inductors.
  • a radio frequency (RF) switching device 1411, a radio frequency (RF) active device 1414, a radio frequency (RF) passive device 1412, and a control device 1413 are all formed on a semiconductor substrate 1410.
  • the semiconductor device when the semiconductor device and epitaxial structure provided by the present disclosure are used to manufacture a semiconductor device, the semiconductor device includes a substrate 1400, a buffer layer 1501, a first semiconductor layer 1502, and a second semiconductor layer 1504. , The source 1506, the drain 1505, the gate 1507, and the first semiconductor mesa 1509.
  • the buffer layer 1501 is disposed on the substrate 1400, the first semiconductor layer 1502 is disposed on the buffer layer 1501, the second semiconductor layer 1504 is disposed on the first semiconductor layer 1502, and the source electrode 1506 and the drain electrode 1505 are formed on the second semiconductor layer 1504 , And located on opposite sides, the first semiconductor mesa 1509 is formed on the second semiconductor layer 1504 and is located between the source 1506 and the drain 1505, and the gate 1507 is formed on the first semiconductor mesa 1509, The length or width of the gate 1507 is greater than the length or width of the first semiconductor mesa 1509.
  • the material of the substrate 1400 may be a semiconductor substrate 1400 material such as silicon (Si), silicon carbide (SiC), sapphire ((Al2O3), gallium arsenide (GaAs), lithium aluminate (LiAlO2), etc., in some embodiments, the substrate 1400 For example, it is a silicon (Si)-based material, such as silicon (Si) or silicon carbide (SiC).
  • the first semiconductor layer 1502 is located on the buffer layer 1501, and the first semiconductor layer 1502 is located on the buffer layer 1501 and the second Between the semiconductor layers 1504.
  • the first semiconductor layer 1502 is, for example, a gallium nitride layer, and the thickness of the first semiconductor layer 1502 can be set to, for example, 200-300 nm.
  • the second semiconductor layer 1504 is located on the first semiconductor layer 1502 Above, in this embodiment, the second semiconductor layer 1504 is, for example, an aluminum gallium nitride layer (AlGaN), and the thickness of the aluminum gallium nitride layer may be, for example, 10-15 nm.
  • the first semiconductor layer 1502 is a gallium nitride layer (GaN)
  • the second semiconductor layer 1504 is an aluminum gallium nitride layer (AlGaN).
  • the gallium nitride layer and aluminum gallium nitride The layers may constitute a heterogeneous semiconductor structure, which is an enhanced semiconductor structure. Relying on the strong spontaneous and piezoelectric polarization effects of the first semiconductor layer 1502 (gallium nitride layer) and the second semiconductor layer 1504 (aluminum gallium nitride layer), the first semiconductor layer 1502 and the second semiconductor layer 1504 are heterogeneous A layer of two-dimensional electron gas 1503 is induced in the structure.
  • the half structure further includes a patterned passivation layer 1510, and the passivation layer 1510 is disposed on the second semiconductor layer 1504.
  • the formation process of the passivation layer 1510 includes: first forming a passivation layer 1510 on the second semiconductor layer 1504, then forming a patterned photoresist layer on the passivation layer 1510, and then according to the patterned photoresist layer to the passivation layer 1510 is etched to form a patterned passivation layer 1510, and then the patterned photoresist layer is removed and cleaned.
  • the material of the passivation layer 1510 can be silicon oxide or aluminum oxide, which can protect the semiconductor device, avoid the problem of reverse leakage, and improve the reliability of the chip.
  • the passivation layer 1510 can be made of SiO2, which is convenient to etch the holes. During etching, part of the passivation layer 1510 can be removed by buffered silicon oxide etching solution or dry etching.
  • two openings are etched on the passivation layer 1510, a first opening and a second opening, and a recess is etched on the passivation layer 1510 at the same time.
  • the recess is located in the middle of the passivation layer 1510 and passes through the passivation layer 1510 to contact the second semiconductor layer 1504.
  • the first opening and the second opening are respectively located on two sides of the concave portion, and the first opening and the second opening are arranged opposite to each other. Both the first opening and the second opening pass through the passivation layer 1510 and contact the second semiconductor layer 1504.
  • the source electrode 1506 is provided in the first opening
  • the drain electrode 1505 is provided in the second opening.
  • the height of the source electrode 1506 and the drain electrode 1505 are both smaller than the thickness of the passivation layer 1510.
  • the semiconductor device further includes a gate 1507.
  • the gate 1507 is disposed between the source 1506 and the drain 1505, is located in the recess, and is disposed on the first semiconductor mesa 1509.
  • the first semiconductor mesa 1509 is located on the second semiconductor layer 1504 and is arranged in the recess.
  • the height of the first semiconductor mesa 1509 is greater than the depth of the recess, and the first semiconductor mesa 1509 is
  • the portion 1509 has a certain predetermined distance from the sidewall of the concave portion, and the material of the first semiconductor mesa portion 1509 is, for example, P-type gallium nitride (P-GaN).
  • P-GaN P-type gallium nitride
  • the unmetallized semiconductor structure shows high leakage current under reverse bias, and after activation, high current leakage can be suppressed.
  • the activation process is, for example, annealing in a dry air atmosphere at 725° C. for 30 minutes for activation.
  • the gate 1507 is disposed on the first semiconductor mesa 1509, and the length or width of the gate 1507 is greater than the length or width of the first semiconductor mesa 1509.
  • the gate 1507 is disposed on the first semiconductor mesa 1509 and the second semiconductor layer 1504, and the gate 1507 fills the channel between the first semiconductor mesa 1509 and the concave sidewall.
  • the cross section of the gate 1507 is buckled on the first semiconductor mesa 1509 in an inverted "concave" shape, and the length or width of the gate 1507 is greater than the length or width of the first semiconductor mesa 1509.
  • the gate 1507 When the length or width of the gate 1507 is greater than the length or width of the first semiconductor mesa 1509, it is easier to open the two-dimensional electron gas of the channel, thereby generating higher leakage current, and the first semiconductor mesa
  • the gate 1507 between the portion 1509 and the sidewall of the recess has better gate control, better transconductance, and lower gate leakage current, thereby improving the performance of the semiconductor device.
  • an oxide layer 1508 is further included between the gate 1507 and the first semiconductor mesa 1509.
  • the oxide layer 1508 is disposed between the gate 1507 and the first semiconductor mesa 1509. Gate leakage current.
  • the oxide layer 1508 is, for example, an aluminum oxide layer.
  • the radio frequency module when the semiconductor device of the present disclosure is applied to a radio frequency module, the radio frequency module includes the semiconductor device.
  • the radio frequency module mainly includes a radio frequency (RF) switching device 1511, a radio frequency (RF) active device 1514, a radio frequency (RF) passive device 1512, and a control device 1513.
  • the radio frequency (RF) active device 1514 may be the semiconductor device described in this application, and the radio frequency (RF) passive device 1512 may be passive devices such as capacitors, resistors, and inductors.
  • a radio frequency (RF) switching device 1511, a radio frequency (RF) active device 1514, a radio frequency (RF) passive device 1512, and a control device 1513 are all formed on a semiconductor substrate 1515.
  • the semiconductor device when the semiconductor device and epitaxial structure provided by the present disclosure are used to manufacture a semiconductor device, the semiconductor device includes a substrate 1400, a buffer layer 1601, a first semiconductor layer 1603, and a second semiconductor layer 1604. , The third semiconductor layer 1602 and the source electrode 1607, the drain electrode 1608 and the gate electrode 1609.
  • the buffer layer 1601 is formed on the substrate 1400, the first semiconductor layer 1603 is formed on the buffer layer 1601, the second semiconductor layer 1604 is formed on the first semiconductor layer 1603, and the third semiconductor layer 1602 is formed on the first semiconductor layer 1603 and Between the buffer layer 1601.
  • the source electrode 1607 is formed on one side of the first semiconductor layer 1603 and extends from the second semiconductor layer 1604 to the buffer layer 1601
  • the drain electrode 1608 is formed on the other side of the first semiconductor layer 1603 and extends from the second semiconductor layer 1604 To the buffer layer 1601
  • the gate 1609 is formed on the second semiconductor layer 1604 and is located between the source 1607 and the drain 1608.
  • the semiconductor device includes a substrate 1400.
  • the substrate 1400 can generally be any suitable growth substrate 1400.
  • the material of the substrate 1400 can be silicon (Si), silicon carbide (SiC), sapphire ((Al2O3), Semiconductor substrate materials such as gallium arsenide (GaAs) and lithium aluminate (LiAlO2).
  • the substrate 1400 is, for example, a silicon (Si)-based material, such as silicon (Si) or silicon carbide (SiC), etc. .
  • the semiconductor device includes a buffer layer 1601, the buffer layer 1601 is disposed on the substrate 1400, and the buffer layer 1601 is disposed between the substrate 1400 and the semiconductor layer, which can alleviate the crystal lattice difference between the substrate 1400 and the semiconductor layer.
  • the material of the buffer layer 1601 is generally determined according to the material of the substrate 1400 and the semiconductor material on the substrate 1400.
  • the buffer layer 1601 may be a gallium aluminum nitride layer, and the thickness of the gallium aluminum nitride layer is set between 115 and 125 angstroms, for example, 120 angstroms.
  • growing the buffer layer 1601 on the substrate 1400 facilitates the growth of the epitaxial structure provided thereon, and improves the quality of the semiconductor device.
  • the semiconductor device includes a third semiconductor layer 1602, and the third semiconductor layer 1602 is disposed above the buffer layer 1601.
  • the third semiconductor layer 1602 includes a third donor layer 1602a and a third spacer layer 1602b.
  • the third donor layer 1602a is an aluminum gallium nitride layer.
  • the third donor layer 1602a is disposed on the buffer layer 1601.
  • the thickness of the donor layer 1602a is set between 48 and 52 angstroms, for example, 50 angstroms.
  • the ion doping concentration of the third donor layer 1602a is, for example, 1 ⁇ 10 24 m -3 to 2 ⁇ 10 24 m -3 .
  • the third spacer layer 1602b is disposed between the third donor layer 1602a and the first semiconductor layer 1603, the third spacer layer 1602b is an aluminum gallium nitride layer, and the thickness of the third spacer layer 1602b is the same as the thickness of the third donor layer 1602a. , For example, 50 angstroms.
  • the semiconductor device includes a first semiconductor layer 1603, and the first semiconductor layer 1603 is disposed on the third semiconductor layer 1602.
  • the first semiconductor layer 1603 is, for example, a gallium nitride layer, and the thickness of the first semiconductor layer 1603 is set to, for example, 195-205 angstroms, for example, 200 angstroms.
  • Gallium nitride is a third-generation wide-bandgap semiconductor material with a large forbidden band width (3.4eV), high electron saturation rate, high breakdown electric field, high thermal conductivity, corrosion resistance and radiation resistance, and it is also nitrided
  • the gallium layer can form an AlGaN/GaN heterojunction with the aluminum gallium nitride layer to form a high-concentration, high-mobility two-dimensional electron gas to facilitate the fabrication of semiconductor devices.
  • the semiconductor device includes a second semiconductor layer 1604, and the second semiconductor layer 1604 is formed on the first semiconductor layer 1603.
  • the second semiconductor layer 1604 includes a second donor layer 1604a and a second spacer layer 1604b, the second donor layer 1604a is disposed on the first semiconductor layer 1603, and the second donor layer 1604a is also a gallium aluminum nitride layer,
  • the thickness of the second donor layer 1604a is the same as that of the third donor layer 1602a, for example, it is set to 50 angstroms.
  • the ion doping concentration of the second donor layer 1604a is the same as the ion doping concentration of the third donor layer, for example, 1 ⁇ 10 24 m -3 to 2 ⁇ 10 24 m -3 .
  • the second spacer layer 1604b is disposed between the first semiconductor layer 1603 and the second donor layer 1604a.
  • the second spacer layer 1604b is also a gallium aluminum nitride layer with the same thickness as the second spacer layer 1604b, for example, 50 angstroms.
  • the semiconductor device includes two two-dimensional electron gas layers, a first two-dimensional electron gas layer 1610 and a second two-dimensional electron gas layer 1611.
  • the first two-dimensional electron gas layer 1610 is formed between the first semiconductor layer 1603 and the third semiconductor layer 1602, and the second two-dimensional electron gas layer 1611 is formed between the first semiconductor layer 1603 and the second semiconductor layer 1604.
  • the two two-dimensional electron gas layers make the semiconductor device have higher withstand voltage, and are also more conducive to opening the two-dimensional electron gas of the channel.
  • the semiconductor device includes a barrier layer 1605, and the barrier layer 1605 is disposed on the second semiconductor layer 1604.
  • the barrier layer 1605 is a gallium aluminum nitride layer
  • the thickness of the barrier layer 1606 is set between 115-125 angstroms, for example, 120 angstroms.
  • the semiconductor device further includes a gallium nitride capping layer 1606.
  • the gallium nitride capping layer 1606 is located above the barrier layer.
  • the thickness of the gallium nitride capping layer 1606 is set at, for example, 95-105. Between angstroms, for example, 100 angstroms.
  • the semiconductor device structure includes a source electrode 1607, a drain electrode 1608, and a gate electrode 1609.
  • the source electrode 1607 is arranged on one side of the first semiconductor, and the source electrode 1607 is extended from the second semiconductor layer 1604 to the buffer layer 1601, the drain electrode 1608 is arranged on the other side of the first semiconductor layer 1603, and the drain electrode 1608 is formed by the second semiconductor layer.
  • the layer 1604 extends to the buffer layer 1601.
  • the gate 1609 is disposed between the source 1607 and the drain 1608, and the gate 1609 is disposed on the second semiconductor layer 1604.
  • the source electrode 1607 sequentially passes through the second semiconductor layer 1604, the first semiconductor layer 1603, and the third semiconductor layer 1602 to reach the buffer layer 1601, and the drain electrode 1608 also sequentially passes through the second semiconductor layer.
  • the first semiconductor layer 1603 and the third semiconductor layer 1602 reach the buffer layer 1601, and the source electrode 1607 and the drain electrode 1608 are both ohmically connected to the first two-dimensional electronic layer 1610 and the second two-dimensional electronic layer 1611. It is easier to open the two-dimensional electron gas of the channel.
  • the gate 1609 is disposed on the second semiconductor layer 1604, and the cross-sectional width of the gate 1609 is smaller than the width of the source 1607 and the drain 1608.
  • the radio frequency module includes the semiconductor device.
  • the radio frequency module mainly includes a radio frequency (RF) switching device 1615, a radio frequency (RF) active device 1618, a radio frequency (RF) passive device 1616, and a control device 1617.
  • the radio frequency (RF) active device 1618 may be the semiconductor device described in this application, and the radio frequency (RF) passive device 1616 may be passive devices such as capacitors, resistors, and inductors.
  • a radio frequency (RF) switching device 1615, a radio frequency (RF) active device 1618, a radio frequency (RF) passive device 1616, and a control device 1617 are all formed on a semiconductor substrate 1619.
  • the semiconductor device when the semiconductor device and epitaxial structure provided by the present disclosure are used to manufacture a semiconductor device, the semiconductor device includes a substrate 1400, a buffer layer 1701, a first semiconductor layer 1702, and a second semiconductor layer 1704. , And the source electrode 1705, the drain electrode 1707, and the gate electrode 1706 on the second semiconductor layer 1704.
  • the buffer layer 1701 is disposed on the substrate 1400
  • the first semiconductor layer 1702 is disposed on the buffer layer 1701
  • the second semiconductor layer 1704 is disposed on the first semiconductor layer 1702.
  • the source electrode 1705 and the drain electrode 1707 are formed on the second semiconductor layer 1704, and the source electrode 1705 and the drain electrode 1707 are located on opposite sides, and the gate electrode 1706 is located between the source electrode 1705 and the drain electrode 1707.
  • a two-dimensional electron gas layer 1702 is formed between the semiconductor layer 1702 and the second semiconductor layer 1704.
  • the material of the substrate 1400 can be silicon (Si), silicon carbide (SiC), sapphire ((Al2O3), gallium arsenide (GaAs), lithium aluminate (LiAlO2), etc.).
  • the semiconductor provided by the present disclosure is utilized.
  • the equipment uses physical vapor deposition to form a buffer layer 1701 on the substrate 1400.
  • the buffer layer 1701 is disposed between the substrate 1400 and the semiconductor layer, which can alleviate the lattice mismatch between the substrate 1400 and the semiconductor layer.
  • Growing the buffer layer 1701 on the substrate 1400 facilitates the growth of the epitaxial structure provided thereon and improves the quality of the semiconductor device.
  • the material of the buffer layer 1701 is determined according to the material of the substrate 1400 and the semiconductor material on the substrate 1400.
  • the buffer layer 1701 may be, for example, It is a gallium nitride buffer layer, and the gallium nitride buffer layer 1701 has a relatively large thickness, and the thickness of the aluminum nitride buffer layer 1701 can be set to be greater than 60 nm, for example.
  • the first semiconductor layer 1702 is disposed on the buffer layer 1701, wherein the first semiconductor layer 1702 is an unintentionally doped gallium nitride layer.
  • the second semiconductor layer 1704 is disposed on the first semiconductor layer 1702, and the second semiconductor layer 1704 is an aluminum gallium nitride layer.
  • the formed semiconductor device has better vertical leakage and breakdown characteristics.
  • the second semiconductor layer 1704 includes a source electrode 1705, a drain electrode 1707, and a gate electrode 1706.
  • the source electrode 1705 is formed on one side of the second semiconductor layer 1704, and the drain electrode 1707 is located on the side opposite to the source electrode 1705.
  • the gate 1706 is arranged between the source 1705 and the drain 1707.
  • the radio frequency module includes the semiconductor device.
  • the radio frequency module mainly includes a radio frequency (RF) switching device 1715, a radio frequency (RF) active device 1718, a radio frequency (RF) passive device 1716, and a control device 1717.
  • the radio frequency (RF) active device 1718 may be the semiconductor device described in this application
  • the radio frequency (RF) passive device 1716 may be passive devices such as capacitors, resistors, and inductors.
  • a radio frequency (RF) switching device 1715, a radio frequency (RF) active device 1718, a radio frequency (RF) passive device 1716, and a control device 1717 are all formed on a semiconductor substrate 1719.
  • this application proposes a semiconductor device that can improve the uniformity of the coating film.
  • the equipment or manufacturing method of the present application can also be applied to other quality films or epitaxial structures, such as metal films, semiconductor films, insulating films, compound films, or films made of other materials.
  • the high-quality thin films and epitaxial structures formed in this application can be applied to various semiconductor structures, electronic components or electronic devices, such as switching components, power components, radio frequency components, light emitting diodes, micro light emitting diodes, display panels, Mobile phones, watches, laptops, drop-in devices, charging devices, charging piles, virtual reality (VR) devices, augmented reality (AR) devices, portable electronic devices, game consoles, or other electronic devices.
  • VR virtual reality
  • AR augmented reality

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physical Vapour Deposition (AREA)

Abstract

本公开提出一种半导体外延结构及其应用与制造方法，所述半导体外延结构包括基板，形成于所述基板上的氮化铝层，形成于所述氮化铝层上的氮化镓层。半导体外延结构可应用于半导体器件及电子装置。

Description

一种半导体外延结构及其应用与制造方法 技术领域
本公开涉及半导体领域，特别涉及一种半导体外延结构及其应用与制造方法。
背景技术
由于第三代半导体材料，例如氮化镓或碳化硅，具有大禁带宽度、高电子饱和速率、高击穿电场、较高热导率、耐腐蚀以及抗辐射性能等优点，从而可以作为半导体材料，而获得半导体外延结构。
但是在第三代半导体材料，例如氮化镓作为半导体外延结构时，仍具有多种问题，例如晶格失配等问题等问题。
公开内容
鉴于上述现有技术的缺陷，本公开提出一种半导体外延结构，以降低氮化镓与硅之间的晶格失配，提高所述半导体外延结构的质量。
为实现上述目的及其他目的，本公开提出一种半导体外延结构，该半导体外延结构包括：
基板；
氮化铝层，形成于所述基板上；
第一氮化铝镓层，形成于所述氮化铝层上；
第二氮化铝镓层，形成于所述第一氮化铝镓层上；
氮化镓层，形成于所述第二氮化铝镓层上；
其中，所述第一氮化铝镓层的铝含量高于所述第二氮化铝镓层的铝含量。
在本公开一实施例中，所述第一氮化铝镓层(Al xGa 1-xN)的X值大于所述第二氮化铝镓层(Al YGa 1-YN)中Y的值。
在本公开一实施例中，所述氮化镓层包括第一氮化镓层、第二氮化镓层以及第三氮化镓层。
在本公开一实施例中，所述第一氮化铝镓层或第二氮化铝镓层的厚度为600-1200纳米。
本公开还提供一种半导体器件，包括上述所述的半导体外延结构。
本公开还提供一种电子装置，其特征在于，包括上述所述的半导体器件。
一种半导体外延结构的制造方法，包括步骤：
提供一基板；
形成氮化铝层于所述基板上；
形成第一氮化铝镓层于所述氮化铝层上；
形成第二氮化铝镓层于所述第一氮化铝镓层上；以及
形成氮化镓层于所述第二氮化铝镓层上；
其中，所述第一氮化铝镓层的铝含量高于所述第二氮化铝镓层的铝含量。
综上所述，本公开提出一种半导体外延结构及其应用与制造方法，可以获得高质量的外延结构，可以提高耐压具有较高的耐压性能，提高所述半导体外延结构的质量。
附图说明
图1：本实施例提出的生长腔体的简要示意图。
图2：本实施例中基座的另一简要示意图。
图3：本实施例中基座的背面示意图。
图4：本实施例中加热器的简要示意图。
图5：本实施例中加热器另一简要示意图。
图6：本实施例中测温装置的简要示意图。
图7：本实施例中磁体的简要示意图。
图8：本实施例中磁体的另一简要示意图。
图9：本实施例中磁体的另一简要示意图。
图10：本实施例中反射板的简要示意图。
图11：本实施例中卡箍的简要示意图。
图12：本实施例中冷却装置的简要示意图。
图13：本实施例中进气口的简要示意图。
图14：本实施例中进气管道的简要示意图。
图15：本实施例中进气管道的底部简要示意图。
图16：本实施例中进气口的另一简要示意图。
图17：本实施例中进气口的另一简要示意图。
图18：本实施例中进气口的另一简要示意图。
图19：本实施例中进气口的另一简要示意图。
图20：本实施例提出的半导体设备的简要示意图。
图21：本实施例中过渡腔体的简要示意图。
图22：本实施例中冷却板的简要示意图。
图23：本实施例中底座的简要示意图。
图24：本实施例中载台及托盘的简要示意图。
图25：本实施例中清洗腔体的简要示意图。
图26：本实施例中升降旋转机构的简要示意图。
图27：本实施例中清洗腔体的另一简要示意图。
图28：本实施例中衬套及线圈组件的简要示意图。
图29：本实施例中预热腔体的简要示意图。
图30：本实施例中加热器的简要示意图。
图31：本实施例中加热线圈的简要示意图。
图32：本实施例中测温点的简要示意图。
图33：本实施例中半导体设备的使用方法流程图。
图34：本实施例中氮化铝镀膜的分析图。
图35：本实施例中氮化铝薄膜的电镜图。
图36：本实施例中氮化铝薄膜的摇摆曲线图。
图37：本实施例中一种半导体外延结构图。
图39：本实施例中另一种半导体外延结构图。
图40：本实施例中另一种半导体外延结构图。
图41：本实施例中一种发光二极管结构图。
图42：本实施例中另一种半导体外延结构图。
图43：本实施例中一种半导体功率器件结构图。
图44：本实施例中一种半导体功外延结构图。
图45：本实施例中一种半导体功外延结构图
图46：本实施例中一种发光二极管结构图。
图47至图51：本实施例中一种微发光二极管形成图。
图52至图58：本实施例中一种微发光二极管芯片形成图。
图59至图68：本实施例中另一种微发光二极管芯片形成图。
图69至图76：本实施例中一种微发光二极管面板形成图。
图77至图83：本实施例中另一种微发光二极管面板形成图。
图84：本实施例中一种微发光二极管面板结构图。
图85：本实施例中一种电子装置结构框图。
图86：本实施例中一种半导体器件结构图。
图87：本实施例中一种射频模组框图。
图88：本实施例中另一种半导体器件结构图。
图89：本实施例中另一种射频模组框图。
图90：本实施例中另一种半导体器件结构图。
图91：本实施例中另一种射频模组框图。
图92：本实施例中另一种半导体器件结构图。
图93：本实施例中另一种射频模组框图。
具体实施方式
以下通过特定的具体实例说明本公开的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本公开的其他优点与功效。本公开还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本公开的精神下进行各种修饰或改变。
请参阅图1，本实施例提出一种半导体设备100，该半导体设备100包括生长腔体110，基座111，靶材123及磁体122。基座111设置在生长腔体110内，基座111可设置在生长腔体110的底端，在基座111上允许放置一个或多个基板112(例如四个、六个或更多个)。在一些实施例中，基座111的直径范围可例如在200mm-800mm。在一些实施例中，基座111的尺寸例如为2-12英寸。基座111可由多种材料形成，包括碳化硅或涂有碳化硅的石墨。基板112的材料可包括蓝宝石，碳化硅，硅，氮化镓，金刚石，铝酸锂，氧化锌，钨，铜和/或铝氮化镓，该基板112还可例如为钠钙玻璃和/或高硅玻璃。一般而言，基板112可能由以下各种组成：具有兼容的晶格常数和热膨胀系数的材料，与生长其上的III-V族材料兼容的基板或在III-V生长温度下热稳定和化学温定的基板。基板112的尺寸在直径上可从50mm至100mm(或更大)的范围。例如，该基板112可为硅衬底，并可在硅衬底上形成金属化合物膜，例如为氮化铝薄膜或氮化镓薄膜，例如为(002)取向的氮化铝膜。如图1所示，基座111还连接一驱动单元113，驱动单元113可电性连接控制单元(未显示)，驱动单元113用于驱动基座111上升或下降，驱动单元113可以采用诸如伺服电机或步进电机等的驱动装置，控制单元用于在磁控溅射的过程中控制驱动单元113驱动基座111上升，以使靶材123与基座111的间距可保持预定值不变，该预定值可以根据具体需要设定，以获得理想的薄膜均匀性、沉积速率等的工艺结果的最优值。因此，通过借助控制单元在磁控溅射的过程中控制驱动单元113驱动基座111上升，可使靶基间距保持不变，以提高薄膜均匀性和沉积速率，进而可以提高工艺质量。控制单元可以例如采用上位机或PLC等。在一些实施例中，基座111还可连 接一旋转单元，旋转单元用于在膜沉积期间使基座111旋转，进一步改善镀膜的厚度均匀性，及改善镀膜的应力均匀性。
值得说明的是，在一些实施例中，半导体设备100还可例如包括负载锁定室、承载盒和选择性附加的MOCVD反应腔室(未显示)以供大量应用。在一些实施例中，半导体设备100的靶材123可包括，但不限于含Al金属，合金，化合物，比如Al、AlN，AlGa，Al 2O 3等，且靶材可例如II/IV/VI族元素掺杂，以改善层相容性与装置性能。在一些实施例中，溅射工艺气体可包括，但不限于，比如N 2，NH 3，NO 2，NO等的含氮气体和比如Ar，Ne，Kr等的惰性气体。
在一些实施例中，本公开的半导体设备可用于形成高质量缓冲层和III-V族层的设备和方法，所述高品质缓冲层和III-V族层可用来形成可能的半导体组件，如射频组件、功率组件、或其它可能组件。
请参阅图2，在一些实施例中，基座111的中间部分可相对于边缘是凸起的，基板112设置在基座111的中间部分上，从而基板112的一部分覆盖边缘区域并且可与边缘区域间隔开。在基板112的边缘处，基座111与基板112之间没有直接的接触，这被认为能够减少基座111对基板112的接触冷却。当基板112在整个沉积过程因离子轰击而被加热时，由于基板112与基座111的中间部分热接触，所以基板112的中间部分可被基座111冷却，基板112的边缘不会受到直接接触冷却，因此经受较高的温度。这使得膜层的边缘更具拉伸性，从而再次起到膜层上应力的总体变化的作用。
请参阅图3-4，图3显示为基座111的背面。在一些实施例中，在基座111的背面上可设置有至少一个加热器，其中，加热器可包括多个加热电极126及一个加热线圈127，在靠近加热电极126的位置上还可设有测温点128。在本实施例中，多个加热电极126连接在一个加热线圈127。在一些实施例中，加热线圈127可包括第一部分及第二部分，第一部分及第二部分关于该加热线圈127的中心对称连接，其中第一部分从外至内依次包括第一弧边127a，第二弧边127b及第三弧边127c，第一弧边127a，第二弧边127b及第三弧边127c可以为同心圆形状。第一弧边127a的一端连接第二弧边127b的一端，第二弧边127b的另一端连接第三弧边127c，第一部分通过第三弧边127c连接第二部分，形成圆形的加热线圈127。第一弧边127a的另一端连接加热电极126，
如图3所示，在多个加热电极126连接外部电源后，该加热线圈127开始对该基座111进行加热。通过加热线圈127，能够保证对基座111的加热均匀性，从而能够保证基板112的温度均匀性。该加热线圈127可例如设置在热解氮化硼基底上。在一些实施例中，为进一步提高加热的均匀性，可对该加热线圈127的形状及圈数进行调整。在一实施例中，基座111 的背面可设置7个、8个或更多個加热电极126。
请参阅图5，在一些实施例中，为进一步提高基座111的加热均匀性，可对该加热线圈127进行调整，例如该加热线圈127通过一漆包线127d经过弯折形成的，该漆包线127d的横截面可为圆形或方形或扁平形。可根据实际情况，调整该漆包线127d的饶制圈数，或者将该加热线圈127设置成非对称形状，或者将漆包线饶制成其他形状。
请参阅图3及图6，在本实施例中，靠近加热电极126的位置上还可设有测温点128，该测温点128连接至测温装置，在本实施例中，该测温装置包括依次连接的检测回路129a以及温度采集模块129b。其中，检测回路129a可例如由两种不同材质的导体构成，该检测回路129a的一端(工作端)与测温点128接触，以产生热电信号。温度采集模块129b用于通过检测回路129a的另一端(自由端)的第一检测点和第二检测点，接收热电信号，并根据该热电信号计算测温点128的温度。由于检测回路129a由多种不同材质的导体构成，该热电信号对第一检测点和第二检测点的电势差会产生影响，温度采集模块129b通过计算第一检测点和第二检测点的电势差来计算测温点128的温度。本实施例中，该测温装置可例如为热电偶。在一些实施例中，还可以使用其他测温仪来测量基座111上的温度，例如还可以通过红外感温仪来测量基座111上的温度。本实施例中通过测温装置可实时得知基座111各个位置上的温度情况，可以保证基座111上的温度处于均匀稳定的状态，同时还可以保证基座111上的基板112处于均匀稳定的温度环境中。
请再参阅图1，在本实施例中，靶材123可设置在生长腔体110的顶部，靶材123与溅射电源(未显示)电连接，在磁控溅射过程中，溅射电源向靶材123输出溅射功率，以使在生长腔体110内形成的等离子体刻蚀靶材123。在一些实施例中，靶材123的材料选自但不限于以下各者的群组：大体上的纯铝、含铝合金、含铝化合物(如AlN、AlGa、Al 2O 3)和掺杂有II/IV/VI族元素以改良层兼容性和装置性能的含铝靶材。在一些实施例中，可通过用掺杂靶材料和/或将掺杂气体输送至所产生溅射等离子体来将掺杂原子添加至沉积薄膜，以调节沉积PVD AlN缓冲层的电特性、机械特性和光学特性，例如以使得薄膜适合在其上制造III族氮化物装置。在一些实施例中，在生长腔体110内形成的薄膜(例如AlN缓冲层)的厚度在0.1-1000纳米之间。
请参阅图1，在本实施例中，磁体122可位于靶材123的上方，磁体122围绕靶材123的中心轴进行旋转，例如磁体122围绕靶材123的中心轴旋转90°或180°或360°或任意角度，或者磁体122可围绕靶材123的中心轴旋转任一角度。在本实施例中，该磁体122连接一驱动机构，该驱动机构带动该磁体122进行旋转的同时，还可以进行上下往复运动。该驱动机构包括第一电机114，传动杆115，第二电机116及升降组件。其中第一电机114通过 传动杆115连接第二电机116，第一电机114例如为伺服电机或步进电机，传动杆115可例如为丝杆，第二电机116例如为旋转伺服电机，由此第一电机114可通过传动杆115带动第二电机116进行上下往复运动，第一电机114驱动传动杆115正向，或反向转动可使第二电机116作往复运动。在不同实施例中，该升降组件包括外轴118及内轴119，内轴119设置在外轴118内，内轴119允许沿着外轴118运动，同时外轴118设置在生长腔体110上，部分内轴119设置在生长腔体110内，在内轴119的一端上还设有一固定装置121，磁体122通过该固定装置121固定在内轴119的一端上，同时在外轴118在与生长腔体110接触的周围还设置有密封装置120，通过该密封装置120来实现真空密封，该密封装置120可例如为密封圈。在不同实施例中，第二电机116通过输出轴117连接内轴119，输出轴117部分位于外轴118内，第二电机116通过该输出轴117可带动内轴119进行旋转，同时第一电机114通过传动杆115带动第二电机116进行上下往复运动，由此当同时打开第一电机114及第二电机116时，该内轴119可在进行上下往复运动的同时，还可以进行旋转运动，从而可以带动内轴119上的磁体122也作相应的运动。当打开第一电机114，关闭第二电机116时，该内轴119可只进行上下往复运动。当关闭第一电机114，打开第二电机116时，该内轴119可只进行旋转运动。由此工作人员可根据实现情况选择打开和/或关闭第一电机114和/或第二电机116。
在一些实施中，磁体122在作旋转运动时，靶材123可保持静止状态，也可绕自身中心轴旋转，但是靶材123和磁体122之间可存在旋转速度差。当磁体122进行旋转时，可以通过动力源如电机来驱动靶材123环绕自身中心轴旋转，以使靶材123和磁体122之间存在速度差。靶材123和磁体122的相对运动，可使得磁体122所产生的磁场均匀地扫描过靶材123的溅射面，且由于本实施例中电场与均匀分布于靶材123溅射面的磁场同时作用于二次电子，可调整二次电子的运动轨迹以增加二次电子与氩原子的碰撞次数，使得靶材123溅射面附近的氩原子被充分电离，以产生更多的氩离子；且通过更多的氩离子轰击靶材123，可有效地提高靶材123的溅射利用率和溅射均匀性，进一步提高沉积薄膜的质量和均匀性。
请参阅图7，在本实施例中，该磁体122包括第一部分，第二部分及多个第三部分，多个第三部分连接在第一部分及第二部分之间。第一部分包括第一磁性单元1221，第二部分包括第二磁性单元1222，第三磁性单元1223及第四磁性单元1224，第三部分包括第五磁性单元1225，第六磁性单元1226及第七磁性单元1227。本实施例通过多个磁性单元拼接成对称的环形的磁体122，当磁体122静止时可形成弧形的磁场，当磁体122围绕靶材123旋转时可形成均匀磁场。通过该均匀的磁场可以提供靶材的溅射均匀性，从而实现镀膜的均匀性。
请参阅图8，在一些实施例中，该磁体122还可以为弧形结构，该磁体122包括第一磁 性单元1221，第二磁性单元1222及多个第三磁性单元1223，第一磁性单元1221通过第三磁性单元1223连接第二磁性单元1222，其中，第一磁性单元1221和第二磁性单元1222例如为弧形，且第一磁性单元1221和第二磁性单元1222为相同的弧形结构，第三磁性单元1223连接在第一磁性单元1221及第二磁性单元1222之间，且关于第一磁性单元1221及第二磁性单元1222的中心轴对称。当磁体122静止时可形成弧形的磁场，该磁体122围绕靶材1223旋转时可以形成均匀的磁场。通过该均匀的磁场可以提供靶材的溅射均匀性，从而实现镀膜的均匀性。
请参阅图9，在一些实施例中，该磁体122还可以为近似矩形结构，该磁体122包括相对设置的多个第一磁性单元1221及相对设置的多个第二磁性单元1222，其中第一磁性单元1221连接第二磁性单元1222，第一磁性单元1221可以为弧形结构，且第一磁性单元1221可以向内或向外凹进，多个第一磁性单元1221还可以同时为向内或向外凹进的弧形结构，多个第一磁性单元1221也可以包括不同的弧形结构。该磁体122可以我对称结构或者非对称结构，当磁体122静止时可形成弧形的磁场，该磁体122围绕靶材123旋转时可以形成均匀磁场。通过该均匀磁场可以提供靶材的溅射均匀性，从而实现镀膜的均匀性。
请参阅图10，在一些实施例中，该生长腔体110可包括外壁110a及内壁110b，内壁110b设置在外壁110a内，内壁110b通过多个螺栓固定在外壁110a内，因此外壁110a及内壁110b形成环形的结构，当该半导体设备100工作时，该环形结构可减缓热量的散失。在内壁110b还设置多层反射板，例如内壁110b从内至外依次设置第一反射板111a及第二反射板111b，第一反射板111a及第二反射板111b依次贴合，在进行沉积工作时，基座112处于高温状态，通过在内壁110b上设置多层反射板可及时隔绝辐射热，防止热量向外散失。其中，第一反射板111a及第二反射板111b呈圆形设置在内壁110b上。第一反射板111a及第二反射板111b可由整体保温材料组成或由多块保温材料组成。本实施例在内壁110b上设置两层反射板，在一些实施例中可设置3层或4层或更多或更少层反射板。
请参阅图10-11，在本实施例中，在生长腔体110的内壁110b上设置多个卡箍132，该卡箍132用于固定第一反射板111a及第二反射板111b。其中，该卡箍132包括多个限位条1321，相邻两个限位条1321形成一卡槽1322，该卡箍132中一端的限位条1321设置在内壁110b上，然后将第一反射板111a及第二反射板111b设置在相应的卡槽1322内。在本实施例中，第一反射板111a及第二反射板111b设置在相邻的卡槽1322，在一些实施例中，第一反射板111a及第二反射板111b可间隔设置在相应的卡槽1322内。第一反射板111a及第二反射板111b的两端分别包括一弯折部(未显示)，第一反射板111a的两端的弯折部突出于卡槽1322，因此第一反射板111a成圆形设置在内壁110b上。在本实施例中，在内壁110b上设有 例如六个卡箍132，卡箍132均匀设置在内壁110b上。在本实施例中，在外壁110a，内壁110b，第一反射板111a及第二反射板111b相同的位置上设有相同大小的通孔130，该通孔130的位置高于基座111，在外壁110a及内壁110b的通孔130上设置有耐高温透明材料。由此工作人员可从生长腔体110的外部了解生长腔体110内的生长情况。在内壁110b上还设有一挡片131。
请参阅图12，在该生长腔体110的外壁110a还设有一冷却装置140，该冷却装置140用于吸收散失到外壁110a上的热量，防止外壁110a由于高温出现变形的情况。在本实施例中，该冷却装置140例如为围绕在外壁110a上的水管，该水管的一端为进水口，该水管的另一端为出水口，通过将该水管形成循环的水路，有效吸收了外壁110a上的温度。
请参阅图1及图13-14，在本实施例中，该生长腔体110上包括至少一个进气口，该进气口连接外部气源124，外部气源124通过该进气口向该生长腔体110内送入气体。在生长腔体110上至少包括一个抽气口，该抽气口连接真空泵125，真空泵125通过该抽气口对该生长腔体110进行抽真空处理。在一些实施例中，该生长腔体110上至少包括两个进气口，例如包括第一进气口119a及第二进气口119b，第一进气口119a及第二进气口119b分别设置在生长腔体110的相对两侧上，第一进气口119a及第二进气口119b相互对称，通过第一进气口119a及第二进气口119b可向生长腔体110内输入气体。在本实施例中，第一进气口119a及第二进气口119b分别连接一个进气管道200，该进气管道200包括外套管210及内套管220，内套管220平行设置在外套管210内，内套管220的一端可以与外套管210的一端连接，形成封闭的环形空腔。该进气管道200的一端连接在进气口上，该进气管道200的另一端可接触生长腔体110的内壁或者进气管道200的另一端与生长腔体110的内壁具有一定的间隙。外套管210上包括多个第一排气孔211，内套管210上包括多个第二排气孔221，多个第一排气孔211分别均匀设置在外套管210上，多个第二排气孔221分别均匀设置在内套管220上，其中，第二排气孔221的尺寸大于或等于第一排气孔211的尺寸，因此第一排气孔211与第二排气孔221可相互错开或部分重叠或重叠。在本实施例中，第一排气孔211的尺寸小于第二排气孔221的尺寸，且第一排气孔211和第二排气孔221相互错开，第一排气孔211及第二排气孔221例如为圆形，长方形，三角形中或其他形狀的一种或其组合。外部气流先进入内套管220内，然后通过内套管220上的第二排气孔221进入到环形空腔中，再由外套管210上的第一排气孔211较均匀地进入到生长腔体110内，这样进入到生长腔体110内的气流的流速可得到较大程度的减缓、且不会紊乱，从而大大减轻了因气流冲击带来的设备及产品的震动，避免出现设备硬伤、产品破损的现象，同时进入生长腔体110内的气流均匀，也可以提高镀膜的均匀性。
请参阅图14，在本实施例中，该进气管道200通过一支管230连接在进气口上，该支管230，该支管230的一端固定在进气口上，该支管230的另一端连接在外套管210内，在生长腔体110的外壁上还设置一排气管240，排气管240与生长腔体110的外壁保持密封状态，该排气管240设置在进气口上，排气管240还连接一外部气源250，通过该外部气源250通过排气管240向支管230内输送气体，当气体进入到内套管220后，通过内套管220上的多个第二排气孔221进入到外套管210内，然后通过外套管210上的多个第一排气孔211进入到生长腔体110内，这样进入到生长腔体110内的气流的流速可得到较大程度的减缓、且不会紊乱，从而大大减轻了因气流冲击带来的设备及产品的震动，避免出现设备硬伤、产品破损的现象，同时进入生长腔体110内的气流均匀，也可以提高镀膜的均匀性。在一些实施例中，还可在支管230或排气管240上设置一气流调节器，该气流调节器可用于调整进气管道200内的气体流速。
请参阅图15，在一些实施例中，内套管220底部与外套管210的底部之间具有一定的间隙，该间隙例如2-3mm。在内套管220的底部上设置有多个第二排气孔221，在外套管210的底部上设置有多个第一排气孔211，同时第二排气孔221的直径大于第一排气孔211的直径，因此第一排气孔211的相对密度大于第二排气孔221的相对密度，同时第一排气孔211与第二排气孔221相互错开或重叠或部分重叠。在本实施例中，在进气管道200的一端上设有多个通孔，可进一步提高气流进入生长腔体110的均匀性。
请参阅图16，在一些实施例中，在生长腔体110的侧壁上设置多个进气口，例如分别为第一进气口119a，第二进气口119b，第三进气口119c及第四进气口119d。所述四个进气口分别连接一进气管道200，通过该四个进气口向该生长腔体110输入气体，由此可提高气体在生长腔体110内的均匀性，从而能够提高镀膜的均匀性。
请参阅图17，在一些实施例中，在生长腔体110的侧壁上设置有两个进气口，分别为第一进气口119a及第二进气口119b。第一进气口119a及第二进气口119b相互错开。在第一进气口119a及第二进气口119b分别接入一进气管道200，该进气管道200上包括多个排风孔201，以便气体进入生长腔体110后变得更加均匀。第一进气口119a及第二进气口119b连接的进气管道200的直径可相同或不同，以便调节气体的流速。
请参阅图18，在一些实施例中，在生长腔体110的侧壁上设有一进气口119a，在第一进气口119a接入一进气管道200，在进气管道200上包括多个排风孔201，多个排风孔201的直径可相同或不同，以便调节气体的流速。
请参阅图19，在一些实施例中，在生长腔体110的顶部设置多个进气口，分别为第一进气口119a及第二进气口119b，在第一进气口119a及第二进气口119b分别接入一进气管道 200，进气管道200位于靶材112的上方，该进气管道200上包括多个排风孔201，以便气体进入生长腔体110后变得更加均匀，提高靶材112的溅射均匀性和靶材112的利用率，以提高镀膜的均匀性。第一进气口119a及第二进气口119b连接的进气管道200的直径可相同或不同，以便调节气体的流速。
请参阅图20，在一实施例中，还提出一种半导体设备300，该半导体设备300包括一传送腔体310，过渡腔体320，清洗腔体330，预热腔体340及多个生长腔体350。该传送腔体310可包括基板装卸机械手臂311，可操作基板装卸机械手臂311，用于过渡腔体320与生长腔体350之间传送基板。在一些实施例中，该半导体设备还包括一制造界面313，在制造界面313内包括卡匣及基板装卸机械手臂(未示出)，卡匣含有需要进行处理的基板，基板装卸机械手臂可包含基板规划系统，以将卡匣内的基板装载至过渡腔体320内。
请参阅图21，该过渡腔体320连接传送腔体310，其中该过渡腔体320位于制造界面313与传送腔体310之间。过渡腔体320在制造界面313与传送腔体310之间提供真空界面。该过渡腔体320可包括一壳体320a，该壳体320a例如为密封的圆柱体，同时在该壳体320a的侧壁上设有抽气口及排气口。该过渡腔体320内设有一冷却板322，冷却板322通过多个支架321固定在壳体320a的底部。通过该冷却板322可对基板进行冷却处理。在本实施例中，该冷却板322可例如为圆柱形或矩形或其他形状，该冷却板322可例如通过四个支架321固定在壳体320a内。
请参阅图22，该冷却板322可为圆柱形，该冷却板322上包括多个内螺纹孔322a，例如包括四个内螺纹孔322a。在支架321的两端设有相应的外螺纹，由此可将支架321的一端设置在该内螺纹孔322a内。
请参阅图23，该支架321的另一端通过底座3211固定在壳体320a内，该底座3211包括多个第一螺纹孔3211a及一个第二螺纹孔3211b，其中，第二螺纹孔3211b位于底座3211的中心位置上，多个第一螺纹孔3211a均匀设置在第二螺纹孔3211b的四周。该支架321的另一端设置在第二螺纹孔3211b内，多个第一螺纹孔3211a用于放置多个螺母，由此可将底座3211固定在壳体320a内。在本实施例中，在底座3211上包括六个第一螺纹孔3211a，在一些实施例中，在底座3211上可设置四个或其他多个第一螺纹孔3211a。
请再参阅图21，在该壳体320a内设置至少一载台325，例如设置两个载台，例如为第一载台325及第二载台328，第一载台325及第二载台328固定在支撑板323上，第一载台325位于第二载台328上。该支撑板323包括一主杆及两个侧板，两个侧板分别设置在主杆的两端，该第一载台325和第二载台328设置在两个侧板之间。该支撑板323还连接一控制杆324，具体地，该控制杆324连接在支撑板323的主杆上，且该控制杆324的一端还位于壳体320a 外，该控制杆324可带动支撑板114上升和/或下降。在本实施例中，该控制杆324连接一驱动单元(未显示)，该驱动单元用于控制该控制杆324上升和/或下降。该控制杆324连接一驱动单元(未显示)，该驱动单元用于控制该控制杆324上升和/或下降。当驱动单元控制控制杆324下降时，第二载台328可接触冷却板322。
请参阅图24，第一载台325及第二载台328上可放置至少一个托盘，托盘用于放置基板，例如以第一载台325为例，该第一载台325上可放置至少一个托盘3251，例如放置两个或三个或更多个托盘3251。
请再参阅图21，该过渡腔体320还可包括一抽气口，该抽气口连接真空泵327，通过该真空泵327对过渡腔体320进行抽真空。本实施例通过多个步骤实现抽真空处理，例如先使用干泵(Dry Pump)将该过渡腔体320抽至1×10 -2Pa，然后在使用涡轮高真空泵(Turbo Molecular Pump)将该过渡腔体320抽至1×10 -4Pa或小于1×10 -4Pa，当该过渡腔体320以进入到真空状态后，控制杆324带动第一载台325及第二载台328沿着预设路径移动，例如控制杆324带动向上移动。本实施例中，该过渡腔体320连接至传送腔体，传送腔体内的基板装卸机械手臂将基板从过渡腔体320内传送至传送腔体，然后在由基板装卸机械手臂将该基板传输至其他腔体，例如预热腔体，清洗腔体或生长腔体，在生长腔体内，可在基板的表面上形成薄膜。当该基板完成镀膜工作后，传送腔体内的基板装卸机械手臂将该基板传输至过渡腔体320内的第二载台328上，然后控制杆324带动该第一载台325及第二载台328沿着与预设路径相反的方向移动，例如向下移动，将该第二载台328接触到冷却板322，通过该冷却板322对第二载台328及第二载台328上的基板进行冷却。同时在该壳体320a的一侧上还包括一排气口，该排气口连接一气源326，当对过渡腔体320进行破真空处理，首先通过控制杆324带动该第二载台328远离冷却板322，使得第二载台328与冷却板322之间具有预设的间距，该预设的间距例如为5-10mm，然后通过气源326通过排气口向过渡腔体320内通入氮气或氩气，对该过渡腔体320进行破真空处理，从而避免基板在冷却的同时，由于氮气的通入使得基板上产生裂纹。当该过渡腔体320完成破真空后，可将该基板取出，进行保存分析。
请再参阅图20，清洗腔体330连接传送腔体310，清洗腔体330位于传送腔体310的侧壁上，当基板进入过渡腔体320时，传送腔体310内的基板装卸机械手臂311随后将基板从过渡腔体320传送至清洗腔体330中以进行清洗。
请参阅图25，在该清洗腔体330内设置一基板支撑组件331，该基板支撑组件331设置在清洗腔体330的底部，且该基板支撑组件331未接触清洗腔体330。该基板支撑组件331包括台座电极3311及静电卡盘3312，静电卡盘3312设置在台座电极3311上，静电卡盘3312 用于放置基板，该静电卡盘3312上可至少放置一个基板，在一些实施例中，可在静电卡盘3312上设置多个基板，同时对多个基板进行清洗工作，从而提高工作效率。
请再参阅图25，该基板支撑组件331还连接一升降旋转机构334，具体地，该升降旋转机构334连接在台座电极3311上，通过该升降旋转机构334可实现基板支撑组件331的升降或旋转，间接实现基板的升降或旋转。当基板支撑组件331旋转上升或下降时，基板与电极332的距离发生变化，以调整台座电极3311与电极332之间的电场强度，使得等离子体能够更好的清洗基板。
请参阅图26，该升降旋转机构334包括带动台座电极3311上升或下降的升降机构以及带动台座电极3311旋转的旋转机构。其中，该升降机构包括升降电机3341及导向杆3342。其中，导向杆3341的一端设置在清洗腔体330内，且与台座电极3311连接，导向杆3342与台座电极3311之间通过密封圈3343进行密封。在本实施例中，升降电机3341的输出轴连接导向杆3342，由此可通过升降电机3341带动台座电极3311上升或下降。在本实施例中，该旋转机构包括旋转电机3344，蜗杆3345及蜗轮3346。其中，旋转电机3344的输出轴连接蜗杆3345，蜗杆3345连接蜗轮3346，该蜗轮3346固定在导向杆3342上，蜗轮3346和蜗杆3345啮合传动，旋转电机3344例如为步进电机，旋转电机3344步进一次，台座电极3311旋转一个托持位，导向杆3342上固定有托持旋转机构的托架。
请再参阅图25，该清洗腔体330内还包括一电极332，该电极332相对设置在基板支撑组件331的上方，该电极332未接触清洗腔体330的顶部，在一些实施例中，电极332与基板支撑组件331的距离可在2-25cm，例如在10-20cm，又例如在16-18cm。该电极332同时还连接一升降旋转机构333，该升降旋转机构333的与升降旋转机构334的结构一致，本实施例不在对该升降旋转机构333进行阐述。当电极332进行旋转上升或下降时，电极332与基板之间的距离发生变化，以调节电极332与基板之间的电场强度，使得等离子体能够均匀的清洗基板。当电极332与基板支撑组件331同时发生旋转时，电极332的旋转速度与基板支撑组件331的旋转速度可相同或存在一定的速度差，以使得等离子体均匀的清洗基板。
请再参阅图25，基板支撑组件331还连接至少一个射频偏压电源338，具体地，该射频偏压电源338连接台座电极3311上。该射频偏压电源338的射频频率可以是高频、中频或低频。例如，高频可以是13.56MHZ的射频偏压源；中频可以是2MHZ的射频偏压源，低频可以是几300-500KHZ的射频偏压源。其中，利用高频射频可以进行硅刻蚀；利用中频或者低频射频可以进行电介质的刻蚀，因此，可以在台座电极3311上同时连接不同频率的射频偏压电源338以实现同时刻蚀硅和电介质。在本实施例中，该电极332还连接至少一射频电源337，该射频电源337的射频频率例如为13.56MHZ。该射频电源337和射频偏压电源338均 由同步脉冲来驱动，能够同时开关，降低清洗腔体330内的电子温度，并且同步脉冲对于基板密集区域的清洗(刻蚀深度)具有良好的控制。
请再参阅图25，清洗腔体330还包括一进气口，该进气口靠近电极332，该进气口连接气体源335，通过气体源335向清洗腔体330内输送气体，该气体为用于清洗应用的前驱物气体，例如包括含氯气体、含氟气体、含碘气体、含溴气体、含氮气体和/或其它适合的反应性元素。当启动射频电源337和/或射频偏压电源338时，以在基板表面附件产生等离子体。在一个实施例中，向设置在基板支撑组件331中的台座电极3311施加约-5伏特～-1000伏特的偏压达约1秒至15分钟之久，基板设置在基板支撑组件331上。输送至清洗腔体330的处理区域的功率的频率可从约10千赫兹至100兆赫兹之间变化，并且功率水平可处于约1千瓦特与10千瓦特之间。该清洗腔体330还可包括一抽气口，该抽气口靠近基板支撑组件331，该抽气口连接一真空泵336，该真空泵336用于抽取清洗腔体330内的气体，使得清洗腔体330的压强进入预定的本底真空范围，预定本底真空范围例如为10 -5-10 -3Pa，向清洗腔体330混合通入用于清洗应用的前驱物气体，调整清洗腔体330的抽气速度，使得清洗腔体330的压强进入预定的工作压强范围，预定工作压强范围例如为1Pa-20Pa。
请参阅图27，在另一实施例中，提出另一种清洗腔体，包括反应腔200，下电极201，衬套(bushing)203，线圈组件204以及射频偏压源206。该反应腔200具有一反应空间，在该反应空间中可以容置产生的等离子及其他部件。在反应腔200的的腔壁可以是石英窗口205。下电极201可设置于反应腔200的底部，但不与反应腔200底部接触。该下电极201用于支撑待刻蚀的基板202，且下电极201为导电板，比如，可以是铁板等，但并不限于此。进一步地，下电极201可以与一温度控制器(未予以图示)相连接，该温度控制器控制下电极201的温度在0-100℃范围内，通过下电极201可以间接控制基板202达到工艺所需的温度。
请参阅图27及28，衬套203设置于反应腔200的顶部中心区域，即衬套203位于反应腔200上腔壁之上，不与上腔壁接触。衬套203可以是圆柱形或其他形状。另外，衬套203为导电板，比如，可以是铁板等，但并不限于此。进一步地，衬套203为可旋转型衬套，其旋转轴与反应腔200的上壁垂直，当然，也可以有一定角度的偏转。衬套203与线圈组件204之间的位置不是固定连接，其相对位置在刻蚀过程中通过衬套203的旋转发生变化，这样将会使得基板202上各个位置的刻蚀速率(清洗速率)更加均衡。
请参阅图27，该衬套203还与射频电源(图中未显示)相连接，该射频电源的频率例如是13.56MHZ。下电极201与至少一个射频偏压源206相连接，图27中只示意了一个射频偏压源206。该射频偏压源206的射频频率可以是高频、中频或低频。例如，高频可以是13.56MHZ的射频偏压源；中频可以是2MHZ的射频偏压源，低频可以是400-600KHZ的射 频偏压源。
请再参阅图20，该预热腔体340连接传送腔体310，预热腔体340位于传送腔体310的侧壁上，当基板在预热腔体340内完成必要的半导体工艺后，传送腔体310内的基板装卸机械手臂311将基板传送至预热腔体340内，对该基板进行预热。
请参阅图29，该预热腔体340包括一壳体340a，在该壳体340a的底部设有一支架341，该支架341可例如为空心结构，然后将导线放置在支架341的内部结构中，将导线连接在加热器342上。在本实施例中，该支架341可例如为耐高温材料。
请参阅图29-30，在预热腔体340内设置一个加热器342，该加热器342固定在支架341上，该加热器342包括一底盘3421及加热线圈3424，该底盘3421包括多个限位条3422，多个限位条3422呈扇形分部在底盘3421上，相邻两个限位条3422之间设置有间隔腔体，该间隔腔体可利于漆包线散热。多个限位条3422及底盘3421可一体成型。在多个限位条3422上还设置有多个挡板3423，多个挡板3423呈扇形分布在多个限位条上，形成同心圆结构。
请参阅图31，该加热线圈3424的横截面为圆形，且挡板3423的高度大于该加热线圈3424的高度。
请参阅图32，该托盘343上靠近基板344的一面上还设有多个测量点，然后将多个测量点连接一测温装置，该测温装置可设置在预热腔体340内或者设置在该预热腔体340的外侧，通过该测温装置可实时测出基板344上的温度，从而可控制基板344的表面温度及其热均匀性。
请再参阅图29，在该预热腔体340的底部还可设有一抽气口，该抽气口连接真空泵345，通过该真空泵345对预热腔体340进行抽真空处理，以获得真空状态的预热腔体340。在预热腔体340内设置一个加热器342，需要说明的是，还可以在预热腔体340的侧壁上设置多个加热器342，还可以在预热腔体340的顶部上设置多个加热器，以保证预热腔体340整体温度的均匀性。
请再参阅图20，在该传送腔体310的侧壁上设置多个生长腔体350，当基板在预热腔体340内完成相应的工艺后，传送腔体310内的基板装卸机械手臂311将基板传送至生长腔体350内进行作业，由于在生长腔体350内形成均匀的弧形磁场，由此可在基板的表面形成均匀的溅射离子，从而在基板上形成均匀的薄膜。
请参阅图33，本实施例还提出一种半导体设备的使用方法，包括：S1：将所述基板放置在所述托盘上；
S2：进行抽真空处理，所述载台进行上升移动，以将所述基板运送至所述生长腔体内，以在所述基板上形成薄膜；
S3：进行破真空处理，所述载台与所述冷却板之间具有预设的间距。
请参阅图34，在一实施例中，对基板上的薄膜(例如氮化铝镀膜)进行分析，从图中可以看出，当相对温度小于0.1时，A1区表现为疏松纤维状微晶，在该结构为倒锥状纤维，同时晶界存在大量间隙，薄膜强度差。当相对温度在0.1-0.3时，A2区表现为致密纤维状微晶。当相对温度在0.3-0.5时，A3区表现为柱状晶特征，在该区域内各个晶粒分别生长获得均匀柱状晶，柱状晶晶体内缺陷密度低，晶界致密度高，呈现出晶体学平面特征。当相对温度大于0.5时，A4区表现为粗大的等轴晶，等轴晶内缺陷密度很低，薄膜结晶非常完整，强度较高。由此，当相对温度较低时，即0-0.3时，溅射离子在入射到基板表面后，未能发生充分的表面扩散，就被后续溅射离子不断覆盖，由此形成相互平行生长的较致密纤维组织，纤维间被相对较疏松的边界所包围，纤维组织边界致密度低，结合强度低，薄弱而易于开裂，且在断面形貌上表现出明显的束状纤维特征。当相对稳定较高时，即0.3-0.7时，溅射离子在入射到基板表面后，能发生充分的表面扩散，溅射离子的迁移距离增加，微细纤维组织由于表面扩散形成柱状晶，柱状晶在经过体扩散及晶界移动形成粗大的等轴晶，晶界间的缺陷减少。因此，本公开的半导体设备在均匀高温下沉积镀膜，可成膜速度快，薄膜(例如氮化铝)的晶格排列呈现柱状晶方向生长，成膜的结晶性好，成膜均匀性也得到提高。其中，相对温度为基板温度与薄膜熔化温度的比值，如果基板温度较低，则相对温度较低，如果基板温度较高，则相对温度较高。
请参阅图35，本实施例对在基板400上形成的氮化铝薄膜401进行分析，从图中可以看出，该氮化铝薄膜401为柱状晶晶体结构，氮化铝薄膜401内部致密度高，缺陷密度少，因此，通过该半导体设备形成的氮化铝薄膜质量高。
请参阅图36，图中显示为两种不同成膜条件下形成的氮化铝薄膜的摇摆曲线，然后通过摇摆曲线来研究氮化铝薄膜(002)晶面的位错密度。需要说明的是，两次成膜条件的差别仅在于对基板的前处理。从图36中可以看出，C1曲线的半峰宽为227弧角，C2曲线的半峰宽为259弧角，由此得出未对基板进行前处理获得的氮化铝薄膜的生长速度快，位错密度大，对基板进行前处理获得氮化铝薄膜的生长速度慢，位错密度小。因此在对基板进行前处理后，在相同条件下形成的氮化铝薄膜的质量得到提高。
然不限于上述举例说明的氮化铝薄膜，利用本申请的设备或制成方法也可应用与其他该质量薄膜，例如金属薄膜、半导体薄膜、绝缘薄膜、化合物薄膜或其他材料的薄膜。再者，在本申请中所形成高质量薄膜可应用于各种半导体结构、电子原件或电子装置中，例如开关元件、功率元件、射频元件、发光二极管、微型发光二极管、显示面板、手机、手表、笔记本电脑、投载式装置、充电装置、充电桩、虚拟现实(VR)装置、扩充现实(AR)装置、 可携式电子装置、游戏机或其他电子装置。
请参阅图37，当利用本公开的半导体设备来制造一半导体外延结构时，所述半导体外延结构可包括基板1000、氮化铝层1001、第一氮化铝镓层1002、第二氮化铝镓层1003以及氮化镓层1004。其中，氮化铝层1001形成于基板1000上，第一氮化铝镓层形成于氮化铝层1001上，第二氮化铝镓层1003形成于第一氮化铝镓层1002上，氮化镓层1004形成于第二氮化铝镓层1003上，且第一氮化铝镓层1002的铝含量可高于第二氮化铝镓层1003的铝含量。基板1000可以是硅基材料的基板，例如硅(Si)或碳化硅(SiC)。在其他实施例中，基板1000也可以蓝宝石((Al2O3)、砷化镓(GaAs)、铝酸锂(LiAlO2)、氮化镓(GaN)或其他半导体基板材料。
请参阅图38，在一些实施例中，硅基板上表面可设置多个微凹部1000a，微凹部1000a的截面是倒三角形或其他形状，在其他实施例中，微凹部1000a的截面包括椭圆形或多边形。微凹部1000a将基板1000分割成若干介质柱，所述介质柱的横截面包括三角形、椭圆形或其他多边形，介质柱的横截面积自上而下一致，或者自下而上逐渐减小。所述倒三角形的微凹部1000a具有较大口径和较大深度来释放堆积应力。
请再参阅图37及38，在一些实施例中，氮化铝层1001可填充于微凹部1000a内。在基板1000与第一氮化铝镓层1002之间设置氮化铝层1001，可以防止基板1000中的硅与第一氮化铝镓层1002中的镓反应。
请再参阅图37，在不同实施例中，可利用半导体设备100，在基板1000表面溅射一层氮化铝薄膜，以形成氮化铝层1001。当形成氮化铝层1001时，基板1000的温度控制在例如800-1000℃之间，通过控制溅射速率、基底温度、溅射厚度等参数，氮化铝层1001的厚度可例如为0.01-1.6μm。在形成氮化铝层1001后，可对形成的外延结构进行高温退火处理，以提高氮化铝层1001的质量。其中，高温退火处理的条件例如为：退火温度为例如1100-1200℃，退火气体为H 2+NH 3。
请再参阅图37，第一氮化铝镓层1002的铝含量可高于第二氮化铝镓层1003的铝含量。例如，在氮化铝镓层中，铝的含量降低是呈梯度降低，导致晶格参数增加，从而提高所述半导体外延结构的质量。
请再参阅图37，在例如硅基板1000上形成氮化铝层1001，氮化铝与硅之间晶格失配可达到19％，氮化铝层1001的位错密度非常高。氮化铝镓层中铝含量降低的相对直向梯度，导致晶格参数增加，从而在生长过程中在随后的层中施加压应力。此时，氮化铝层1001存在高位错密度问题，可通过第一氮化铝镓层1002和第二氮化铝镓层1003的设计来进行改善，提高缓冲层的质量。
请再参阅图37，第一氮化铝镓层1002和第二氮化铝镓层1003可利用半导体设备100或化学气相沉积法制备而成，其中为了调控翘曲和表面平整度，第一氮化铝镓层1002或第二氮化铝镓层1003的厚度可以为例如600-1200nm。其中第一氮化铝镓层(Al xGa 1-xN。)1002的X值大于第二氮化铝镓层(Al YGa 1-YN。)1003中Y的值。
请再参阅图37，所述半导体外延结构还包括氮化镓层1004，氮化镓层1004设置于第二氮化铝镓层1003上，其中高阻值的氮化镓层1004可以提高器件的耐压性。为了获得高阻值的氮化镓材料，氮化镓层1004可以包括多层结构，其至少包括第一氮化镓层、第二氮化镓层以及第三氮化镓层。其中，第一氮化镓层可在高压高温环境下生长，例如生长温度1000-1050℃，反应室压力为400-500torr，生长速率为1-1.5um/h，生长厚度为300-500nm；第二氮化镓层可在中压低温环境下生长，例如生长温度900-1000℃，反应室压力为200-250torr，生长速率2.5-3.5um/h，生长厚度为1-4um；第三氮化镓层可在低压高温环境下生长，例如生长温度1000-1050℃，反应室压力为100-200torr，生长速率0.5-1um/h，生长厚度为300-500nm。
因此，在一些实施例中，通过第一氮化铝镓层1002和第二氮化铝镓层1003内铝含量的设置，提高所述半导体外延结构的质量。
请参阅图39，在一些实施例中，半导体外延结构可包括基板1100、第一氮化铝层1101、第一氮化镓层1102、第二氮化铝层1103和第二氮化镓层1104。其中，第一氮化铝层1101形成于基板1100上，第一氮化镓层1102形成于第一氮化铝层1101上，第二氮化铝层形1103成于第一氮化镓层1102上，第二氮化镓层1104形成于第二氮化铝层1103上。基板1100的材料可以为硅(Si)、碳化硅(SiC)、蓝宝石((Al2O3)、砷化镓(GaAs)、铝酸锂(LiAlO2)等半导体基板材料，在本实施例中，基板1100例如为硅(Si)基材料，例如硅(Si)或碳化硅(SiC)。
请再参阅图39，形成氮化铝层1101及/或1103的方法包括：例如利用本公开的半导体设备100，在基板表面上形成氮化铝薄膜。
请再参阅图39，形成氮化镓层1102及/或1104的方法包括：通过化学气相沉积法或者金属有机物化学气相沉积法在氮化铝层上生长氮化镓。首先，在生长氮化镓设备的反应室中，向反应室通入例如氦气、氩气、氮气和氢气的一种或多种，然后将反应室的温度升高至预设温度，其中，预设温度为氮化镓层的生长温度，在此条件下生长预设厚度的第一氮化镓层1102及/或第二氮化镓层1104。
请再参阅图39，通过使用多个间隔的氮化铝夹层，可以改进错位进而提高半导体外延结构的质量。在其他实施例中，可以根据氮化铝夹层的质量，进一步在第一氮化镓层1102或第二氮化镓层1104内部间隔设置多个氮化铝夹层，例如可以是第三氮化镓层和第四氮化镓层分 别设置在第一氮化镓层1102和第二氮化镓层1104内部。
请参阅图40，在另一实施例中，第一氮化铝层1101与第一氮化镓层1102之间可以包括第一氮化铝镓层1105和第二氮化铝镓层1106。第一氮化铝镓层1105设置于第一氮化铝层1101上，第二氮化铝镓层1106设置在第一氮化铝镓层1105上，第一氮化镓层1102设置在第二氮铝镓层1106上。其中，第一氮化铝镓层1105的铝含量高于第二氮化铝镓层1106的铝含量。在氮化铝镓层中，铝的含量降低的相对直向梯度，导致晶格参数增加。
请参阅图41，在不同实施例中，当利用本公开的半导体设备及半导体外延结构来形成发光二极管结构时。具体地，所述发光二极管结构可包括半导体外延结构，第一半导体层1107、发光层1108、第二半导体层1109、第一电极1111和第二电极1112，第一半导体层1107位于第二氮化镓层1104上，发光层1108位于第一半导体层1107上，第二半导体层1109位于发光层1108上，第二半导体层1109上还设置一透明导电层1110，在第二半导体层1109的一侧设置有一依次穿过透明导电层1110、第二半导体层1109和发光层1108至第一半导体层1107的凹部，所述凹部与第一半导体层1107接触。第一电极1111形成于透明导电层1110上，第二电极1112形成于所述凹部内的第一半导体层1107上。
请再参阅图41，在一些实施例中，所述半导体外延结构可包括：基板1100、第一氮化铝层1101、第一氮化铝镓层1105、第二氮化铝镓层1106、第一氮化镓层1102、第二氮化铝层1103和第二氮化镓层1104。第一氮化铝层1101形成于基板1100上，第一氮化铝镓层1105形成于第一氮化铝层1101上，第二氮化铝镓层1106形成于第一氮化铝镓层1105上，第一氮化镓层1102形成于第二氮化铝镓层1106上，第二氮化铝层1103形成于第一氮化镓层1102上，第二氮化镓层1104形成于第二氮化铝层1103上。
请再参阅图41，在不同实施例中，在所述半导体外延结构上可设置有第一半导体层1107、发光层1108和第二半导体层1109。第一半导体层1107可以是掺有第一杂质的N型半导体层，或者是掺有第二杂质的P型半导体层，相对应的第二半导体层1109可以是掺有第二杂质的P型半导体层，或者是掺有第一杂质的N型半导体层。第一杂质例如为施主杂质，第二杂质例如为受主杂质，根据所使用的半导体材料，第一杂质和第二杂质可以为不同的元素，在本实施例中，第一半导体层1107可以为氮化镓半层，第一杂质可以为硅(Si)元素，第二杂质可以为镁(Mg)元素。在其他实施例中，第一半导体层1107和第二半导体层1109可以是氮化物化合物，例如第一半导体层1107为N型掺杂氮化镓，第二半导体层1109为P型掺杂氮化镓。在其他实施例中，第一半导体层1107和第二半导体层1109还可以是其他合适的透明材料形成。
请再参阅图41，在不同实施例中，发光层1108是本征半导体层或低掺杂半导体层，发 光层1108掺杂浓度较相邻的同种掺杂类型的半导体层的更低，同时发光层1108可以是量子阱发光层。例如可以选用铟氮化镓(InGaN)。在不同实施例中，发光层可例如为发出不同光色波段的量子阱，发光层的材料可选铟氮化镓(InGaN)、硒化锌(ZnSe)、铟氮化镓/氮化镓(InGaN/GaN)、铟氮化镓/氮化镓(InGaN/GaN)、磷化镓(GaP)、铝磷化镓(AlGaP)、铝砷化镓(AlGaAs)、磷砷化镓(GaAsP)、磷化镓(GaP)等材料中的一种或多种。
请再参阅图41，所述发光二极管结构还包括一透明导电层1110，其设置在第二半导体1109上，位于第一电极1111与第二半导体结构1109之间。透明导电层1110可以使第二半导体层1109与第一电极1111之间形成良好的欧姆接触，透明导电层1110的材制可以为铟锡氧化物(indium tin oxide，简称ITO)、铟锌氧化物(indium zinc oxide，简称IZO)、氧化锌(zinc oxide，简称ZnO)、铟锡锌氧化物(indium tin zinc oxide，简称ITZO)、铝锡氧化物(aluminum tin oxide，简称ATO)、铝锌氧化物(aluminum zinc oxide，简称AZO)或其他适当的透明导电材质。
请参再阅图41，所述发光二极管结构还包括一个凹部，该凹部是位于透明导电层1110、第二半导体层1109、发光层1108的一侧。透明导电层1110上设置有第一电极1111，在所述凹部内设置有第二电极1112，第一电极1111和第二电极1112的材料可以是不透明的导电材料，不透明的导电材料可以包括钛(Ti)、铂(Pt)、金(Au)、铬(Cr)等金属材料，不透明的导电材料还可以铝(Al)、银(Ag)等高反射材料，从而第一电极1111和第二电极1112为高反射电极，在发光层1108发光时，减少电极对光的吸收，提高发光亮度。在本实施例中，可以通过蒸镀和/或溅射技术，分别在透明导电层1110和第一半导体层1107上形成第一电极1111和第二电极1112。
请参阅图42，在另一实施例中，当利用本公开的半导体设备来制造半导体外延结构时，半导体外延结构可包括基板1200、氮化铝层1201、超晶格结构1202和氮化镓层1203，超晶格结构1202包括多个氮化铝夹层和多个氮化铝镓夹层。其中，氮化铝层1201形成于基板1200上，超晶格结构1202形成于氮化铝层1201上，氮化镓层1203形成于超晶格结构1202上。
请再参阅图42，例如，可利用本公开的半导体设备100来形成氮化铝层1201。在氮化铝层1201上设置一超晶格结构1202，超晶格结构1202可由具有不同带隙的两种不同的半导体材料制成，所述两种不同的半导体材料相互交替生长形成周期性结构，在本实施例中，所述两种不同的半导体材料例如为氮化铝和氮化铝镓，超晶格结构1202包括多个氮化铝夹层和多个氮化铝镓夹层，氮化铝夹层和氮化铝镓夹层在氮化铝层上周期性生长。可以按照氮化铝夹层、氮化铝镓夹层、氮化铝夹层、氮化铝镓夹层周期性生长。在其他实施例中，所述两种不同的半导体材料可以例如是氮化铝和氮化镓，超晶格结构1202包括氮化铝夹层以及氮化镓夹 层。
请再参阅图42，所述氮化铝夹层以及所述氮化铝镓夹层的厚度可为纳米级尺寸，生长周期为例如15-20个。所述氮化铝层的厚度为例如4nm，所述氮化铝镓层的厚度为例如20nm。在其他实施例中，所述氮化铝层的厚度为例如4nm，所述氮化镓夹层的厚度为例如20nm。这种超晶格结构1202具有很好的垂直泄露和击穿特性，例如可适用于功率器件。
请再参阅图42，生成超晶格结构1202中的所述氮化铝夹层以及所述氮化铝镓夹层的方法包括：通过沉积工艺在氮化铝层上依次形成所述氮化铝夹层和所述氮化铝镓夹层，后重复对两个夹层相互交替沉积，在生长方向上形成周期性结构。在单个周期内生长所述氮化铝夹层，所述氮化铝夹层的生长厚度可以为例如4nm，所述氮化铝镓夹层的生长厚度为例如20nm。
请再参阅图42，在超晶格结构1202上可设置有一氮化镓层1203。生长氮化镓层1203的生长条件例如是：生长温度为例如950-1000℃，在本实施例中，生长温度为例如980℃。
请再参阅图42，III-V族氮化物材料(诸如GaN)可在合适的基板1200上作为单晶(外延)层生长，其中氮化镓层1203有不同于基板1200的热膨胀系数，因此，当加工之后冷却时，氮化镓层1203由于较厚的基板1200对它们所产生的约束而具有碎裂的倾向。氮化镓层1203的碎裂会限制了它们的最终应用。本申请中提供的氮化铝层1201以及超晶格结构1202能够调节热失配，防止在基板1200加热和后续冷却器件易发生晶圆变形以及氮化镓层1203碎裂。
请参阅图43，在不同实施例中，当利用本公开的半导体设备及外延结构来制造半导体器件时，半导体器件可包括例如上述半导体外延结构、其源极1204、漏极1205及栅极1206。源极1204与漏极1205位于氮化镓层1023上，且分别位于氮化镓层1203的两侧，栅极1206位于源极1204与漏极1205之间，栅极1026可插入氮化镓层，且与超晶格结构1202具有一预设距离。
请再参阅图43，在一些实施例中，所述外延结构包括基板1200、氮化铝层1201、超晶格结构1202以及氮化镓层1203，氮化铝层1201位于基板1200上，超晶格结构1202设置在氮化铝层1201上，氮化镓层1203设置在超晶格结构1202上。其中，所述外延结构中超晶格结构1202中的铝含量可较低于氮化铝层1201中的铝含量，如此，这种外延结构具有很好的垂直泄露和击穿特性，其所形成的半导体器件(例如半导体功率器件)也具有很好的垂直泄露和击穿特性。
请参阅图44，在不同实施例中，当利用本公开的半导体设备来制造半导体外延结构时，所述半导体外延结构包可第一氮化镓层1207以及第二氮化镓层1208。其中，第二氮化镓层1208形成于第一氮化镓层1207上，第一氮化镓层1207的晶格结构(例如为多晶结构或单晶结 构)可不同于第二氮化镓层1208的晶格结构(例如为非晶结构)。
请参阅图44，所述半导体外延结构的生长方法包括：在基板1200上形成氮化铝层1201，其中，基板1200可以为硅(Si)基材料，例如硅(Si)或碳化硅(SiC)。形成氮化铝层1201的方法包括：例如利用本公开的半导体设备，在基板1200表面形成一层氮化铝薄膜，通过控制溅射速率、基底温度、溅射厚度等参数控制保证基板1200表面铺满氮化铝材料，获得一定厚度的氮化铝层1201。在形成氮化铝层1201后，对氮化铝层1201进行高温退火处理以提高氮化铝层1201的质量。
请参阅图44，所述半导体外延结构的第一氮化镓层1207与第二氮化镓层1208可分别使用不同的制程方法或不同制程设备来形成。例如，当形成第一氮化镓层1207时，可利用本公开的半导体设备，并通过物理气相沉积法在氮化铝层1201上形成第一氮化铝层1201。例如，当形成第二氮化镓层1208时，可利用金属有机化合物化学气相沉淀的方法，在第一氮化镓层1207上第二氮化镓层1208。
请参阅图45，在一些实施例中，可将第一氮化镓层1207与第二氮化镓层1208从基板1200上剥离，而得到氮化镓外延结构。具体地，可以通过蚀刻或研磨生长基板1200与氮化铝层1201，将所述外延结构(1207、1208)与基板1200分离。其中，获得的所述氮化镓外延结构包括第一氮化镓层1207和氮化镓层1208。在不同实施例中，上述氮化镓外延结构可应用于垂直导通型的半导体器件。例如，可形成电极及其他半导体层(未显示)于第一氮化镓层1207和氮化镓层1208的上、下两侧，因而形成垂直导通型的半导体器件。
请参阅图46，当利用本公开的半导体设备及外延结构来制造发光二极管结构时，发光二极管结构至少包括：含碳基板1300、低温氮化铝层1301、高温氮化镓缓冲层1302、第一半导体层1303、发光层1304、第二半导体层1305、N型电极1306和P型电极1307。其中，低温氮化铝层1301形成于含碳基板1300上，高温氮化镓缓冲层1302形成于低温氮化铝层1301上，第一半导体层1303行成于高温氮化镓缓冲层1302上，发光层1304形成于第一半导体层1303上，第二半导体层1305形成于发光层1304上，在第二半导体层的一侧开设有一穿过第二半导体层1305、发光层1304至第一半导体层1303的凹部，所述凹部与第一半导体层1303接触，N型电极1306形成于所述凹部内的第一半导体层1303上，P型电极形成于第二半导体层1305上。
请参阅图46，在一些实施例中，可利用具有一含碳层的硅基(silicon-based)基板作为发光二极管结构的基板，以改善发光二极管结构装置的品质、性能和可靠度。其中，含碳基板1300中的含碳层可以避免或降低基板的硅原子和发光二极管结构的金属原子混合(inter-mixing)，因而改善第三族氮化物晶体的品质。品质改善的上述第三族氮化物晶体可以改善发光二极管 结构装置的性能和可靠度。含碳层沿着含碳基板1300的表面设置且延伸进入基板的深度约小于20μm。在不同实施例中，除了碳原子，可选择性将例如硅、锗或类似原子的其他原子导入基板内。
具体地，在含碳基板1300上生长外延结构之前，可对含碳基板1300进行清洗以去除含碳基板1300表面的天然氧化物。所述清洗过程包括：首先，在例如为1100℃下，在氢气环境下对含碳基板1300进行一定时间的原位热清洗，例如为10～20分钟，清洗液可以为H2SO4:H2O2(3:1)溶液，可去除微粒和有机污染物；再用2％氢氟酸(HF)清洗以及去离子水清洗以移除金属污染物；最后可在N2条件下烘干。
请参阅图46，发光二极管低温氮化铝层1301厚度例如为5～30nm。氮化铝层1301的形成过程具体可以包括：例如利用本公开的半导体设备100，在含碳基板1300表面形成一层氮化铝薄膜，含碳基板1300的温度控制在例如为600～1200℃，通过控制溅射速率、基底温度、溅射厚度等参数控制保证含碳基板1300表面上，铺满氮化铝材料，以形成高质量的低温氮化铝层1301。
请参阅图46，在低温氮化铝层1301上可形成高温氮化镓缓冲层1302，高温氮化镓缓冲层1302包括第一高温氮化镓缓冲层1302a和第二高温氮化镓缓冲层1302b。其过程例如包括两个阶段：
第一阶段：将温度提高到一预设温度，例如为1050～1100℃，在低V/III比下采用低温化学气相沉积法例如等离子增强化学气相沉积法(PECVD)，生长一定厚度的非故意掺杂氮化镓层，为第一高温氮化镓缓冲层1302a，第一高温氮化镓缓冲层1302a厚度例如为200～400nm；
第二阶段：在第一阶段的温度下，例如为1050～1100℃，在高V/III比下采用低温化学气相沉积法例如等离子增强化学气相沉积法(PECVD)，生长一定厚度的非故意掺杂氮化镓层，为第二高温氮化镓缓冲层1302b，第二高温氮化镓缓冲层1302b的厚度例如为0.1～0.5mm。
请参阅图46，在高温氮化镓缓冲层1302上可形成第一半导体层1303，第一半导体层1303为硅掺杂N型氮化镓层，其中所述硅掺杂的材料例如可以使用硅烷(SiH4)。第一半导体层1303形成过程包括：在与形成高温氮化镓缓冲层1302的相同温度，在高V/III比下采用低温化学气相沉积法，例如等离子增强化学气相沉积法(PECVD)，生长一定厚度的硅掺杂N型氮化镓层为第一半导体层1303。在本实施例中，第一半导体层1303的厚度可以为例如2mm，同时在高V/III比下能够获得平坦光滑的第一半导体层1303。
请参阅图46，在第一半导体层1303上可形成发光层1304，在不同实施例中，发光层1304为周期性阱层与势垒层，发光层1304按照阱层、势垒层周期性生长。阱层的材料例如为In0.15Ga0.85N，势垒层的材料例如为In0.02Ga0.98N。发光层1304的形成过程可例如包括：单个 生长周期内先生长阱层，生长温度为例如700～800℃，阱层的厚度可以是例如3～5nm，然后提高生长温度至800～900℃，在此条件下生长势垒层，势垒层的厚度可以是例如9～15nm。在本实施例中，生长周期例如为五个。通过生长周期性的阱层与势垒层获得发光层1304，在生长发光层1304的过程中，为了提高铟的掺入率，采用氮气作为载气。
请再参阅图46，在发光层1304上可形成第二半导体层1305，第二半导体层1305为P掺杂的P型氮化镓层。在一些实施例中，所述P掺杂材料具体可以是双环戊二烯基镁(CP2Mg)。第二半导体层1305的形成过程例如包括：在生长完发光层1304后，将衬底温度提高到例如1000℃，在发光层1304上沉积一定厚度的掺镁P型氮化镓层。在不同实施例中，第二半导体层1305的厚度可以为例如200～400nm。
请再参阅图46，在一些实施例中，所述发光二极管结构还包括N型电极1306和P型电极1307。在制作N型电极1306以及P型电极1307之前还可激活掺镁P型氮化镓层，即第二半导体层1305。所述激活过程例如包括：在氮气环境下，将所制备的所述发光二极管结构在例如730℃下退火一定时长，例如为30min，以激活第二半导体层1305，同时在一定的激光波长下，例如为600～700nm的激光波长下，通过反射测量对生长进行原位监测。
请再参阅图46，在一些实施例中，所述发光二极管结构还包括N型电极1306以及P型电极1307，N型电极1306形成于所述硅掺杂N型氮化镓层上，即形成于第一半导体层1303上。P型电极1307形成于所述P型氮化镓层上，即形成于第二半导体层1305上。其中N型电极1306和P型电极1307的形成过程例如包括：退火后，采用电感耦合等离子体刻蚀对上述结构表面进行部分刻蚀，直至暴露第一半导体层1303并继续刻蚀部分第一半导体层1303形成凹部，在所述凹部上沉积Ni/Au触点随后蒸发，形成N型电极1306。在暴露的第二半导体层1305上沉积Ti/Al/Ni/Au触头作为P型电极1307。
然不限于此，在一些实施例中，可移除基板1300、低温氮化铝层1301、高温氮化镓缓冲层1302，以暴露第一半导体层1303，而不需刻蚀部分第一半导体层1303形成凹部。接着，形成N型电极1306于第一半导体层1303上，因而形成了垂直导通型的发光二极管结构。
请参阅图46，通过本公开提供的一种发光二极管结构，可通过低温氮化铝层1301及高温氮化镓缓冲层1302，能够获得较无裂纹，表面形貌光滑的高质量发光二极管结构。
请参阅图47至图51，在一些实施例中，当应用本公开的半导体外延结构来制造微型发光二极管(Micro-LED)时，所述微发光二极管结构的制造方法可包括以下步骤：提供一生长基板500；形成一缓冲层501于生长基板上，形成第一半导体层502于缓冲层501上，形成发光层503于第一半导体层上，形成第二半导体层504与发光层503上；将第一半导体层502、发光层503及第二半导体层504区分成多个发光二极管结构505。生长基板500可以是各种 适当的生长基板，例如生长基板的材料可以为硅(Si)、碳化硅(SiC)、蓝宝石((Al2O3)、砷化镓(GaAs)、铝酸锂(LiAlO2)等半导体基板材料，在本实施例中，生长基板500例如为硅(Si)基材料，例如硅(Si)或碳化硅(SiC)。
请参阅图47，在不同实施例中，当在基板500上形成缓冲层501时，例如可以利用本公开的半导体设备100，并通过物理气相沉积(PVD)工艺可在生长基板500上形成高质量的缓冲层501，缓冲层501的材料可以为氮化铝(AlN)或氮化镓(GaN)等形成的低温成核层。缓冲层501可用于减轻生长基板与第一半导体层之间的晶格不匹配，以降低晶格失配引起的晶格缺陷，降低错位密度，并提高微发光二极管的质量。
请再参阅图47，在缓冲层501上可形成第一半导体层502和在发光层503上形成第二半导体层504的过程中，第一半导体层502可以是掺有第一杂质的N型半导体层，或者是掺有第二杂质的P型半导体层，相对应的第二半导体层504可以是掺有第二杂质的P型半导体层，或者是掺有第一杂质的N型半导体层。在第一半导体层502上可形成发光层503，发光层503可以例如是本征半导体层或低掺杂半导体层(其掺杂浓度较相邻的同种掺杂类型的半导体层的更低)，或者可以为由量子阱形成的发光层。在不同实施例中，发光层503例如是量子阱发光层。例如可以选用铟氮化镓(InGaN)。在一些实施例中，发光层503可以发出蓝光波段，蓝光波段发光层的材料可选铟氮化镓(InGaN)、硒化锌(ZnSe)、铟氮化镓/氮化镓(InGaN/GaN)等材料中的一种或多种。然不限于此，在不同实施例中，发光层503也可以为为发出绿光或红光波段的发光层材料。
请参阅图48至51，在将第一半导体层502、发光层503及第二半导体层504区分成多个发光二极管结构505的过程中。例如可通过蚀刻、激光划槽或其他方法将第一半导体层502、发光层503及第二半导体层504区分成多个发光二极管结构，每一所述发光二极管包括部分的第一半导体层502、发光层503和第二半导体层504。
请参阅图48至51，在一实施例中，当分成多个发光二极管结构505时，具体地，在形成第二半导体层504后的结构上开设凹部或凹槽，用以将第一半导体层502、发光层503及第二半导体层504区分成多个发光二极管结构。之后，可在分离后的第一半导体层502上形成第一电极505，在分离后的第二半导体层504上形成第二电极506。之后，在分离后的第二半导体层502上形成一钝化层507。之后，可移除(例如蚀刻)生长基板500和缓冲层501，以形成多个分离的发光二极管结构(例如是微型发光二极管结构或微型发光二极管芯片)。
请参阅图48，当分成多个发光二极管结构时，具体地，在第二半导体504上形成凹部，所述凹部可包括第一凹部与第二凹部，第一凹部是从第二半导体层504形成至生长基板500， 所述第二凹部从第二半导体层504延伸至第一半导体层502，所述第一凹部和所述第二凹部可以通过蚀刻或激光划槽形成。在第二半导体504上形成凹部时，具体地，在第二半导体层504上形成一层光刻胶，采用光刻工艺溶解光刻胶，得到设定图形的光刻胶图形，在光刻胶的保护下，本实施例采用例如感应耦合等离子体蚀刻工艺在第二半导体层504上开设从第二半导体层504至生长基板500的所述第一凹部，其中所述第一凹部穿过第二半导体层504、发光层503、第一半导体层502、缓冲层501到达生长基板500。再进行第二次蚀刻，通过同样的方法在所述第一凹部的一侧蚀刻出第一凹部，所述第一凹部穿过第二半导体层504和发光层503，与第一半导体层502接触，其中所述第一凹部与第二凹部连接形成台阶状。
请参阅图49，当在第一半导体层502上形成第一电极505，且在第二半导体层504上形成第二电极506时，具体地，可通过蒸镀和/或溅射技术在每个暴露的第一半导体层502上形成第一电极505，在第二半导体层上504形成第二电极506，第一电极505可位于所述第二凹部内。其中，第一电极505和第二电极506的材料可以是不透明的导电材料，不透明的导电材料可以包括钛(Ti)、铂(Pt)、金(Au)、铬(Cr)等金属材料，不透明的导电材料还可以铝(Al)、银(Ag)等高反射材料，从而第一电极505和第二电极506为高反射电极，在发光层503进行发光时，减少电极对光的吸收，提高发光亮度。在其他实施例中，也可以通过保护气流在第一半导体层502和第二半导体层504上回流焊形成锡球。
请参阅图50，当在第二半导体层502上形成一钝化层507时，具体地，首先在第二半导体层504表面形成一层钝化层507，然后在钝化层507上可形成一图案化光阻层，根据图案化光阻层对钝化层进行刻蚀，形成图案化的钝化层507，然后去除图案化光阻层并清洗干净。在本实施例中，钝化层507还位于第一电极505及第二电极506的附近。在本实施例中，钝化层507的材料例如包括氧化硅或者氧化铝，对所述微发光二极管结构进行保护，避免反向漏电等问题，提高二极体结构的可靠性，钝化层507的材料可以选用为氧化硅，便于腐蚀开孔，在一些实施例中，可通过缓冲氧化硅刻蚀液或干法刻蚀钝化层507。
请参阅图51，当移除生长基板500和缓冲层501时，具体地，可运用例如蚀刻技术蚀刻生长基板500和缓冲层501，以得到多个微发光二极管结构，所述蚀刻技术包括干法蚀刻和湿法蚀刻，在湿法蚀刻中需要用到蚀刻剂，所述蚀刻剂例如可以是硝酸、氢氟酸、过氧化物、碱、乙二胺邻苯二酚、胺没食子酸盐(aminegallate)、TMAH、肼等。
然不限于此，在一些实施例中，可移除生长基板500和缓冲层501之后，再形成第一电极505于第一半导体层502暴露出的底面上，因而形成了垂直导通型的发光二极管结构。
请参阅图47至图51，通过本实施例提供的一种微型发光二极管结构及其制造方法，可以同时获得多个微型发光二极管结构，提高获得所述微型发光二极管的制造效率。
请参阅图52至图58，在另一实施例中，当将第一半导体层502、发光层503及第二半导体层504区分成多个发光二极管结构505时，具体地，蚀刻生长基板500和缓冲层501，形成多个第一通道；使用导体材料对第一通道进行填充；蚀刻生长基板500、缓冲层501、第一半导体层502、导电层503，形成多个第二通道；使用导体材料对第二通道进行填充；在第一通道的导体材料上形成第一锡球508、在第二通道的导体材料上形成第二锡球509；在第二半导体层504上形成钝化层；在第二半导体层504上开设凹部，将第一半导体层502、发光层503及第二半导体层504区分成多个发光二极管结构，所述凹部穿过钝化层507、第二半导体层504、发光层503、第一半导体层502、缓冲层501和生长基板500，将整体结构区分为多个微发光二极管结构。
请再参阅图53，当使用导体材料对第一通道进行填充时，具体地，可将导体材料填充入第一通道中，例如可以利用真空下的气相沉积法、膜、糊料、液体涂覆、流延或它们的组合。例如，穿过第一通道在第一半导体层502上沉积反射金属层，随后使用导体材料来填充通道并形成接触。如上所述，导体材料可包含导电金属和金属氧化物，例如Al、Au、Cu、Ag、Pt等。
请再参阅图54，当蚀刻生长基板500、缓冲层501、第一半导体层502、导电层503，以形成多个第二通道时，具体地，通过蚀刻技术蚀刻生长基板500、缓冲层501、第一半导体层502、导电层503，所述蚀刻技术包括干法蚀刻和湿法蚀刻。所述第二通道可以是任意所需的形状，所述第一通道穿过生长基板500、缓冲层501、第一半导体层502、导电层503到达第二半导体层504。
请再参阅图55，当使用半导体材料对第二通道进行填充时，具体地，将导体材料填充入第二通道中，可以包括任选地处于真空下的气相沉积法、膜、糊料、液体涂覆、流延或它们的组合。例如，穿过第二通道在第二半导体层504上沉积反射金属层，随后使用导体材料来填充通道并形成接触。
请再参阅图56，当在第一通道的导体材料上形成第一锡球508、且在第二通道的导体材料上形成第二锡球509时，具体地，通过保护气流在与第一通道的导体材料上回流焊形成第一锡球508，在与第二通道的导体材料上形成第二锡球509，且第一锡球508和第二锡球509可以在同一水平面设置。然不于此，除了锡球，也可在电极上形成其他电性连接件，例如引脚。
请再参阅图57，当在第二半导体层504上形成钝化层时，钝化层507的材料例如可以包括氧化硅或者氧化铝，可对二极体结构进行保护，避免反向漏电等问题，提高二极体结构的可靠性。钝化层的材料可选用氧化硅，便于腐蚀开孔，可通过缓冲氧化硅刻蚀液或干法刻蚀 钝化层。在一些实施例中，如图57所示，可通过钝化层507、封装体或封装胶，将多个微型发光二极管结构整合成微发光二极管芯片。其中，微发光二极管芯片的多个微发光二极管结构可具有相同光色(例如蓝光)或不同光色。
请再请参阅图57至图58，当在第二半导体层504上开设凹部，将第一半导体层502、发光层503及第二半导体层504区分成多个发光二极管结构时，具体地，在第二半导体上开设一个凹部，所述凹部贯穿钝化层507、第二半导体层504、发光层503、第一半导体层502、缓冲层501和生长基板500，开设工艺可以采用蚀刻或激光划槽。其中，所述凹部穿过第二半导体层504、发光层503、第一半导体层502、达缓冲层501和生长基板500，获得多个微发光二极管结构。
请参阅图59至图68，在又一实施例中，当将第一半导体层502、发光层503及第二半导体层504区分成多个发光二极管结构505时，具体地，在第二半导体层504上生长第二电极506；在第二电极506的一侧蚀刻出第一凹部510，第一凹部510穿过第二半导体层504、发光层503、第一半导体层502以及部分缓冲层501；在第一凹部510内填充绝缘层511，绝缘层511填充满第一凹部510及部分第二半导体层504，且绝缘层511与第二电极506侧面连接；在靠近第一凹部510的一侧形成第二凹部512，第二凹部512穿过第二半导体层504、发光层503、第一半导体层502以及部分缓冲层501；在第二凹部512填充导电材料，所述导电材料充满第二凹部512及部分绝缘层511，与第二电极506相对于发光层503的一侧连接，形成第二电极延长结构513；在第二半导体层504上生长一钝化层507；蚀刻生长基板500及缓冲层501；在第一半导体层502上形成第一电极505；在第一电极505上形成第一锡球508，在第二电极延长结构上形成第二锡球507；将整体结构区分为多个微型发光二极管结构。
请参阅图59，当在第二半导体层504上生长第二电极506时，具体地，可通过蒸镀和/或溅射技术在第二半导体层504上形成多个第二电极506，相邻的第二电极506之间具有一定的预设距离。
请参阅图60，当在第二电极506的一侧蚀刻出第一凹部510时，具体地，可在第二半导体层504上形成设定图形的光刻胶图形，在光刻胶的保护下，采用例如干蚀刻或湿蚀刻工艺在第二半导体层504上开设第一凹部510，第一凹部510穿过第一凹部510穿过第二半导体层504、发光层503、第一半导体层502以及部分缓冲层501。
请参阅图61，当在第一凹部510内填充绝缘层511时，具体地，使用绝缘材料对第一凹部510进行填充，该绝缘材料与第二电极506的侧面连接，形成绝缘层511。所述绝缘材料例如包括SiOx、SiNx和SiON、或其他无机绝缘材料。
请参阅图62，当在靠近第一凹部510的一侧形成第二凹部512时，具体地，在第二半导 体层504上形成设定图形的光刻胶图形，在光刻胶的保护下，采用例如干蚀刻或湿蚀刻工艺在第二半导体层504上开设第二凹部512，第二凹部512穿过第二半导体层504、发光层503、第一半导体层502以及部分缓冲层501，第二凹部512的深度与第一凹部510可以相同或不同。
请参阅图63，当在第二凹部512填充导电材料，形成第二电极延长结构513时，具体地，使用导电材料对第二凹部512进行填充，该导电材料填充满第二凹部512，且覆盖绝缘层511，并于第二电极506相对于第二半导体504的一侧连接，形成第二电极延长结构513。所述导电材料例如可以是导电金属或者合金。
请参阅图64，当在第二半导体层504上生长一钝化层507时，具体地，在第二半导体层504上形成一钝化层507，钝化层507可覆盖第二电极延长结构513以及第二半导体层504。其中，钝化层507例如可以是氧化硅等材料。然不限于此，在一些实施例中，钝化层507可作为保护层或封装体，而形成在第二半导体层504及第二电极506上。
请参阅图65，当移除(例如蚀刻)生长基板500及缓冲层501时，具体地，运用例如蚀刻技术蚀刻生长基板500和缓冲层501，所述蚀刻技术包括干法蚀刻和湿法蚀刻。通过蚀刻生长基板500和缓冲层501，暴露出第一半导体层502以及部分绝缘层511以及第二电极延长结构513。
请参阅图66，当在第一半导体层502上形成第一电极505时，具体地，通过蒸镀和/或溅射技术在第一半导体层502上形成多个第一电极505，第一电极505的长度例如等于绝缘层511延伸至缓冲层501的厚度。
请参阅图67，当在第一电极505上形成第一锡球508，且在第二电极延长结构513上形成第二锡球507时，具体地，可通过保护气流在第一电极505上回流焊形成第一锡球508，在与第二电极延长结构513上形成第二锡球509，且第一锡球508和第二锡球509可以在同一水平面设置。然不于此，除了锡球，也可在电极上形成其他电性连接件，例如引脚。
请参阅图68，将整体结构区分(分离)为多个微型发光二极管结构时，具体地，可开设一凹部，所述凹部穿过第一半导体层502、发光层503以及第二半导体层505到达钝化层507，因而获得多个微型发光二极管结构。在一些实施例中，如图68所示，可通过钝化层507、封装体或封装胶，将多个微型发光二极管结构整合成微发光二极管芯片。其中，微发光二极管芯片的多个微发光二极管结构可具有相同光色(例如蓝光)或不同光色。
请参阅图69至图76，在一些实施例中，当应用本公开的半导体设备及微发光二极管芯片来制造微发光二极管面板，所述微发光二极管芯片面板可包括：电路基板700，衬底层701、 多个微发光二极管芯片703，多个电性连接件702以及平坦化层704、光阻隔层705、红色波长转换层706、绿色波长转换层707、透明光阻707a、保护层708和保护基板709。衬底层701设置在电路基板700上，多个微发光二极管芯片703设置在衬底层701上，多个电性连接件702设置在衬底层701以及多个微发光二极管芯片703之间，平坦化层704设置在多个微发光二极管芯片703上，光阻隔层705、红色波长转换层706、绿色波长转换层707设置在平坦化层704上，保护层708设置在光阻隔层705、红色波长转换层706、绿色波长转换层707上及其间隙处，保护基板709设置在保护层708上。
请参阅图69，电路基板700可以是例如TFT驱动电路基板。在电路基板700上可设置一衬底层701，衬底层701可以是聚酰亚胺(PI)材料形成的衬底层，聚酰亚胺(PI)材料的耐热性保证了在制程高温(>400℃)中显示面板不受破坏，聚酰亚胺(PI)材料的低热膨胀系数特性保证了高解析度(>300ppi)以及在面板制程所需的制程对位精度。最后利用聚酰亚胺(PI)材料对紫外光的强吸收特性，使用紫外波段激光透过玻璃辐照聚酰亚胺(PI)材料可以使之剥离。
请参阅图70至图71，电路基板700靠近衬底层的一侧表面还设置驱动电路，所述驱动电路部分设置在电路基板700上，部分设置在衬底层701上。通过所述驱动电路的作用为点亮与之电性连接的微发光二极管芯片703，其中多个微发光二极管芯片703可具有相同或不同光色，例如是多个发出蓝光、红光或绿光的微发光二极管结构。通过驱动电路控制每个微发光二极管芯片703的开关。在不改变电流大小的情况下，通过控制微发光二极管芯片703的点亮数量可以改变微发光二极管面板的亮度。
请参阅图71，多个微发光二极管芯片703可在电路基板700上呈阵列设置，每个微发光二极管芯片703之间等距离间隔，相邻微发光二极管芯片703的间距小于微发光二极管芯片703的长度或宽度，使微发光二极管芯片构成的显示装置具有较高的解析度。微发光二极管芯片703的宽度例如是小于等于10微米，则相邻微发光二极管芯片703小于等于10微米。在其他实施例中，微发光二极管芯片703的宽度例如是小于等于5微米，则相邻微发光二极管芯片703小于等于5微米。
请参阅图70至图72，在衬底层701和多个微发光二极管芯片703之间还包括多个电性连接件702，通过多个电性连接件702，将衬底层701上的驱动电路与微发光二极管芯片703连接。所述驱动电路在衬底层701远离电路基板700的一侧设置有电性连接点，微发光二极管芯片703靠近衬底层701的一侧具有电极，电性连接件702可以将所述电性连接点与所述电极连接。电性连接件702可以是金属连接件，例如为铟/锡连接件。
请参阅图72，在多个微发光二极管芯片703之间以及其上方设置平坦化层704，平坦化 层704可以包括聚合物类材料，所述聚合物类材料可以是透明的，例如可以包括硅基树脂、丙烯酸类树脂、环氧类树脂、PI、聚乙烯等。通过曝光和显影工艺在微发光二极管芯片703之间以及其上部形成平坦化层704。
请参阅图72，在另一些实施例中，平坦化层704还包括第一绝缘层和第二绝缘层(未显示)，其中，第一绝缘层设置在平坦化层704靠近多个微发光二极管芯片703的一侧，第二绝缘层设置在远离多个微发光二极管芯片703的一侧。在形成平坦化层的一些工艺中，例如清洗工艺，外部杂质(例如，湿气)可能会损坏微发光二极管芯片703。通过在平坦化层下方设置第一绝缘层，在平坦化层704上方设置第二绝缘层，可以防止在形成平坦化层704期间和之后防止湿气渗透或使湿气渗透最小化。第一绝缘层和第二绝缘层包括SiOx、SiNx和SiON等无机绝缘材料。第一绝缘层和第二绝缘层可以包括彼此相同的材料或彼此不同的材料。第二绝缘层可以具有大于第一绝缘层的厚度。在不同实施例中，第二绝缘层的厚度可以等于或小于第一绝缘层的厚度。
请再参阅图72，一个微发光二极管芯片703中包括多个微发光微二极管，在形成微发光二极管面板的过程中，可以降低巨量转移的次数，减少误差损失，提高生产制造中的良率。
请参阅图73，在平坦化层704上设置光阻隔层705，其中，光阻隔层705包括多个光阻隔层块，发光二极管芯片703位于相邻光阻隔层块的空隙处，微发光二极管芯片703发出的光穿过所述空隙。在本实施例中，光阻隔层705的形成方法包括：在平坦化层704上形成光阻隔层材质层；采用一次构图工艺对光阻隔层材质层进行处理得到光阻隔层图案，即多个光阻隔层块，其中，所述光阻隔层块位于微发光二极管芯片703之间；采用涂覆、磁控溅射或等离子增强化学气相沉淀法等方法，在光阻隔层材质层上形成光刻胶层；对光刻胶层进行曝光和显影得到光刻胶图案；通过光刻胶图案对光阻隔层材质层进行蚀刻，并剥离光刻胶图案，得到图案化的光阻隔层705，即多个光阻隔层块构成的光阻隔层。
在一些施例中，在形成光阻隔层705后，可以采用等离子氟化工艺对光阻隔层705的表面进行氟化处理。采用等离子氟化工艺对光阻隔层705的表面进行氟化处理，从而降低所得光阻隔层705的表面张力。
请参阅图74，当微发光二极管芯片703中的微发光二极管是发出蓝光时，所述微发光二极管面板还包括红色波长转换层706、绿色波长转换层707和透明光阻707a，用以将微发光二极管的发光转换成红光或绿光，因而可形成全彩色。红色波长转换层706和绿色波长转换层707分别设置在光阻隔层705之间，且可包覆光阻隔层705边缘处，可防止光学漏光。在其他实施例中，还包括蓝色波长转换层，可设置在光阻隔层705空隙处，且包覆光阻隔层705边缘处。
请参阅图74，形成红色波长转换层706的步骤可包括：在具有光阻隔层705的平坦化层704上形成红色色阻膜；在形成有红色色阻膜的绝缘层上涂覆光刻胶，形成光刻胶层；从光刻胶层远离绝缘层的一侧采用掩膜版对光刻胶层进行曝光；对曝光后的光刻胶层进行显影；刻蚀并剥离光刻胶层得到图案化的红色波长转换层706。
在一些施例中，形成红色色阻膜的过程可以包括：用刮胶板将红色色阻材料均匀刮满整个绝缘层；旋涂，将涂有红色色阻材料的绝缘层采用真空吸附的方式设置在旋涂机上，中央滴液并控制旋涂机高速旋转，在绝缘层上形成一定厚度的红色色阻膜；预烘，使红色色阻膜中的溶剂挥发，增强红色色阻膜与绝缘层的黏性。
请参阅图74，重复上述获得红色波长转换层706的方法得到图案化的绿色波长转换层707。红色波长转换层706和绿色波长转换层707间隔设置，通过红色波长转换层706、绿色波长转换层707和光阻隔层705还可防止光的反射。
请参阅图75，在形成所述微发光二极管芯片的过程中，还包括在光阻隔层705、红色波长转换层706、绿色波长转换层707和透明光阻707a上设置保护层708，保护层708位于光阻隔层705、红色波长转换层706、绿色波长转换层707和透明光阻707a的上方。保护层708的材料可以为透明的树脂材料，在本实施例中，所述保护层708的材料可以为丙酸酯聚合物。
请参阅图76，发光二极管在形成一种微发光二极管面板的过程中，还包括在保护层708上设置一保护基板709，保护基板709与保护层708键合形成密闭空腔。
请参阅图77至83，本公开还提供另一微发光二极管面板及其形成过程。在本实施例中，电路基板800靠近衬底层的一侧表面还设置驱动电路，所述驱动电路部分设置在电路基板800上，部分设置在衬底层801上。通过所述驱动电路的作用可以点亮与之电性连接的微发光二极管芯片803。在不改变电流大小的情况下，通过控制微发光二极管芯片803的点亮数量可以改变微发光二极管面板的亮度。
请参阅图77，在衬底层801和多个微发光二极管芯片803之间还包括多个电性连接件802，通过多个电性连接件802，将衬底层801上的驱动电路与微发光二极管芯片703连接。所述驱动电路在衬底层801远离电路基板800的一侧设置有电性连接点，微发光二极管芯片803靠近衬底层801的一侧具有电极，电性连接件802可以将所述电性连接点与所述电极连接。电性连接件802可以是金属连接件，例如为铟/锡连接件或锡球。
请参阅图78，在多个微发光二极管芯片803之间以及其上方设置平坦化层804，通过曝光和显影工艺在微发光二极管芯片803之间以及其上部形成平坦化层804。
请参阅图78，在一些实施例中，平坦化层804可以包括光学层，光学层可以改善从微发光二极管结构发射的光的发光效率或是见减小色差，将发散的光线收拢以较小的发散角度射 出。光学层可以包括具有凹透镜或凸透镜形状的层并且可以包括具有不同折射率的多个层。
请参阅图79，提供一透光基板809，在透光基板809上设置光阻隔层805，其中，光阻隔层805包括多个光阻隔层块，在一些实施例中，光阻隔层805的形成方法包括：在透光基板809上形成光阻隔层材质层；采用一次构图工艺对光阻隔层材质层进行处理得到光阻隔层图案，即多个光阻隔层块，其中，每个所述光阻隔层块之间具有间隙。
请参阅图80，当微发光二极管芯片803中的微发光二极管是发出蓝光时，一种微发光二极管面板还包括红色波长转换层806、绿色波长转换层807和透明光阻807a，红色波长转换层806、绿色波长转换层807、透明光阻807a分别设置在光阻隔层805空隙处，且包覆光阻隔层805边缘处，可以防止光学漏光，且红色波长转换层806、绿色波长转换层807间隔设置。
请参阅图80，形成红色波长转换层806的步骤包括：在具有光阻隔层的透光基板808上形成红色色阻膜；在形成有红色色阻膜的绝缘层上涂覆光刻胶，形成光刻胶层；从光刻胶层远离绝缘层的一侧采用掩膜版对光刻胶层进行曝光；对曝光后的光刻胶层进行显影；刻蚀并剥离光刻胶层得到图案化的红色波长转换层806。
请参阅图80，重复上述获得红色波长转换层806的方法得到图案化的绿色波长转换层807。红色波长转换层806、绿色波长转换层807间隔设置，通过红色波长转换层806、绿色波长转换层807和光阻隔层805可以防止光的反射。
请参阅图81，在形成一种微发光二极管芯片的过程中，还包括形成一保护层808，保护层808位于光阻隔层805、红色波长转换层806、绿色波长转换层807和透明光阻807a的上方。保护层808的材料可以为透明的树脂材料，在本实施例中，保护层808的材料可以为丙酸酯聚合物，可以通过使用溅射或者蒸镀的方式沉积保护层808。
请参阅图82，在形成一种微发光二极管芯片的过程中，还包括在保护层808上形成一透明导电层809，透明导电层809的材质可以为但不仅限于为铟锡氧化物、铟锌氧化物等，可以通过使用溅射或者蒸镀的方式沉积透明导电层809。
请参阅图83，将透光基板808以及其上包括的结构，包括光阻隔层805、红色波长转换层806、绿色波长转换层805、保护层808和透明导电层809与电路基板800以及上的微发光二极管结构801以及偏向层802键合，形成为所述微发光二极管芯片。
请参阅图84，当利用本公开的半导体设备及微型二极体芯片制备微发光二极管面板，所述微发光二极管面板可包括电路基板、多个微发光二极管芯片903以及波长转换层906。所述电路基板可以为膜晶体管阵列基板，薄膜晶体管阵列基板具有多个薄膜晶体管(Thin Film Transistor，TFT)。所述电路基板包括基底900与电路层901，电路层901一般设置在基底 900上部。基底900可以为玻璃基板、蓝宝石基板等，基底900具有固定性且表面平整。电路层901包括驱动电路以及多个开关元件。基板900包括显示区域与非显示区域，非显区域上包括驱动电路，显示区域上包括多个微发光二极管芯片903。
请再参阅图84，在电路基板上设置多个微发光二极管芯片903，微发光二极管芯片903与电路基板上的电路层901电性连接，电路基板上的驱动电路可以驱动多个微发光二极管芯片903发光。多个微发光二极管芯片903设置在电路基板上可构成一个像素结构，电路基板上包括多个像素结构，多个像素结构在电路基板的显示区域以阵列方式排列。
请参阅图84，电路层901上还设置多个接合触头902，多个微发光二极管芯片903具体设置在多个接合触头902上，具体来说，微发光二极管芯片903上设置有电极，多个所述电极电性连接于多个接合触头902。通过接合触头902多个发光二极管芯片与电路基板电性连接。电路基板上的驱动电路可以点亮与之连接的微发光二极管芯片903。在本实施例中，接合触头902可以是金属接合触头902，例如为铟/锡接合触头902。在其他实施例中，接合触头902可以包括苯并环丁烯(BCB)。
请参阅图84，微光二极体芯片903内部包括多个微发光二极管结构903a，多个微发光二极管结构903a以阵列形式设置在微发光二极管芯片903内。相邻的微发光二极管结构903a之间的距离小于微发光二极管结构903a的宽度，微发光二极管结构903a的宽度例如是5微米，则相邻的微发光二极管结构903a之间的距离小于5微米。
请参阅图84，在微发光二极管芯片903上方设置光阻隔层905，光阻隔层905位于相邻微发光二极管结构903a的间隙处。光阻隔层905在电路基板上的正投影与微发光二极管结构903a在电路基板上的正投影不重叠。光阻隔层905具有反射性、散射性或吸光的特性，在相邻的微发光二极管结构903a之间设置光阻隔层905可以避免微发光二极管结构903a发出的光互相干扰，并减少漏光的问题。
请参阅图84，在微发光二极管芯片903上方设置波长转换层，多个波长转换层906设置于多个微发光二极管结构903a的正上方，且位于电路基板相对于微发光二极管芯片903的另一侧。波长转换层位于相邻的光阻隔层905之间，且波长转换层的正投影重叠于微发光二极管结构903a在电路基板上的正投影。在一些实施例中，波长转换层906包覆部分光阻隔层905，可减少漏光。
请参阅图84，至少形成一波长转换层906于多个微发光二极管芯片903上，用于制作波长转换层906的材料包括磷光体和量子点等。波长转换层906例如可以包括第一波长转换层906a、第二波长转换层906b、第三波长转换层906c。微发光二极管结构903a例如都是发出蓝光的微发光二极管结构903a，第一波长转换层906a例如可以是红光波长转换层906，第二 波长转换层906b可以是绿光波长转换层、第三波长转换层906c可以是由散射材料、波长转换结构组成的波长转换层906，但是不改变微发光二极管结构903a的出光。通过第一波长转换层906a可以呈现红光，通过第二波长转换层906b可以呈现绿光，通过第三波长转换层906c呈现蓝光，通过第一波长转换层906a、第二波长转换层906b、第三波长转换层906c使像素结构呈现全彩显示的效果。在其他实施例中，波长转换层906还可以包括蓝光波长转换层906。多个波长转换层906具有相同的厚度，可使光转换质量最佳且具有一致的出光效率。
请参阅图84，在一些实施例中，微发光二极管芯片903例如是发出红光的微发光二极管芯片903，第一波长转换层906a可以是绿光波长转换层，第二波长转换层906b可以是蓝光波长转换层。在其他实施例中，微发光二极管芯片903例如是发出绿光的微发光二极管芯片903，第一波长转换层906a可以是红光波长转换层，第二波长转换层906b可以是蓝光波长转换层。在其他实施例中，微发光二极管芯片903例如是发出紫外光的微发光二极管芯片903，第一波长转换层906a可以是红光波长转换层，第二波长转换层906b可以是绿光波长转换层，第三波长转换层906c可以是蓝光波长转换层。
值得说明的是，上述波长转换层可以是由不同颜色的光阻材料或量子点材料所形成，且上述波长转换层可以形成于微发光二极管芯片上或个别微发光二极管上，用以转换微发光二极管所发出的光波长，亦即转换微发光二极管所发出的光色。
请参阅图84，微发光显示面板包括保护层904，其设置在相邻像素之间与光阻隔层905、波长转换层906上方，保护层904可以避免微发光二极管面板产生水气或氧化的问题。微发光显示面板包括在保护层904上设置一保护基板907，保护基板907与保护层904键合形成密闭空腔。
值得说明的是，上述光阻隔层是设置于微发光二极管芯片或微发光二极管之间，用以阻隔不同光色。在一些实施例中，上述光阻隔层可例如是白色光阻层或高反光型阻隔层，用以反射微发光二极管所发出的光。再者，上述白色或高反光型的光阻隔层可例如是锥型，以向上反射微发光二极管所发出的光，提高出光效率。
请参阅图85，本公开还提供一种电子装置，所述电子装置包括微发光二极管面板910以及电子装置本体911，微发光二极管面板910与电子装置本体911连接，其中微发光二极管面板910包括电路基板、多个微发光二极管芯片903、至少一波长转换层906。电子装置本体911包括控制器911a、存储器911b、电源911c。其中，电源911c可以将市电(220V交流电)转换为控制器911a和存储器911b所需要的直流电，同时为微发光二极管面板910提供电源。存储器911b与电源911c连接，用于存储电子装置工作的相关数据，控制器911a与电源911c连接，同时与存储器911b连接，电源911c用于为控制器911a供电，控制器所述执行存储器 911b内的程序控制所述电子装置。其中，电子装置可例如是显示面板、手机、手表、笔记本电脑、投载式装置、充电装置、充电桩、虚拟现实(VR)装置、扩充现实(AR)装置、可携式电子装置、游戏机或其他电子装置。
请参阅图86，当应用本公开的半导体外延结构来制造半导体器件时，所述半导体器件包括基板1400、缓冲层1401、第一半导体层1402、第二半导体层1403、源极1404、漏极1405以及栅极1406。其中，缓冲层1401设置于基板上，第一半导体层1402设置于缓冲层1401上，第二半导体层1403设置于第一半导体层1402上，源极1404形成于第二半导体层1403上，漏极1405形成于第二半导体层1403上，栅极1406形成于第二半导体层1403上，且位于源极1404和漏极1405之间。基板1400可是各种适当的生长基板1400，基板1400的材料可以为硅(Si)、碳化硅(SiC)、蓝宝石((Al2O3)、砷化镓(GaAs)、铝酸锂(LiAlO2)等半导体基板1400材料，在一些实施例中，基板1400例如为硅(Si)基材料，例如硅(Si)或碳化硅(SiC)等硅基材料。
请再参阅图86，缓冲层1401设置在基板1400和第一半导体层1402之间，可以缓和基板1400与第一半导体层1401之间晶格不匹配情况。第一半导体层1402的材料例如可以为含铟的氮化镓层。为缓和晶格不匹配的情况，缓冲层1401例如为氮化镓层，所述氮化镓层的厚度可以设置例如为5～10nm。同时在基板1400与第一半导体层1402之间设置的缓冲层1401有利于后续外延结构的的生长，提高所述半导体器件的质量。
请再参阅图86，第一半导体层1402的材料例如为含铟的氮化镓层(InGaN)。使用含铟的氮化镓层作为第一半导体层1402，可以降低所述半导体器件的噪声系数，且当第一半导体层1402含铟时，电子亲和力增加，为所述半导体器件提供高漏电流以及更高的截止频率。第一半导体层1402的厚度可以设置为例如70～80nm。然不限于此，在其他实施例中，第一半导体层1402也可以是氮化镓层。
请再参阅图86，所述半导体器件包括第二半导体层1403，第二半导体层1403位于第一半导体层1402上。在本实施例中，第二半导体层1403的材料可为含铟的氮化铝层(InAlN)，第二半导体层1403的厚度为可以为例如15～25nm。所述含铟的氮化铝层中，较高的铝含量具有较高的载流子密度，使所述半导体器件具有较高的漏电流和跨导，同时获得了较低的最小噪声系数。第二半导体层1403采用含铟的氮化铝层，可以改善与缓冲层1401之间晶格失配。在本实施例中，可以利用铟熔点低的原理，在高温下易扩散获得获得InAlN。第二半导体层1403的方法包括：周期性生长第一AlN层、第一InN层和第二AlN层获得所述第二半导体层1403，在生长第二半导体的过程中，通过控制生长温度以及第一AlN层、第一InN层和第二AlN层的厚度调节第二半导体层1403中铟的含量。第二半导体层1403利用铟的熔点 低，高温下易扩散的原理获得InAlN为第二半导体层1403，第二半导体层1403可以有效降低所述半导体器件的暗电流，从而降低所述半导体器件的噪声电流，提高信噪比，提高所述所述半导体器件的质量。
请再参阅图86，所述半导体器件包括源极1404、漏极1405以及栅极1406，源极1404、漏极1405以及栅极1406均设置在第二半导体层1403上，且栅极1406位于源极1404与漏极1405之间。所述半导体器件的一侧设置有第一凹部和第二凹部，第一凹部内设置源极1404，第二凹部内设置漏极1405。其中所述第一凹部位于所述半导体器件的一侧，在第二半导体层1403上蚀刻第一凹部，所述第一凹部的深度小于第二半导体层1403的厚度，即所述第一凹部的底部距离第二半导体层1403底部具有一定的预设距离，即第一预设距离；所述第二凹部设置在第二半导体层1403上，且位于所述第一凹部的相对侧，在第二半导体层1403上蚀刻第二凹部，所述第二凹部的深度小于第二半导体层1403的厚度，即所述第二凹部的底部与第二半导体层1403底部具有一定的预设距离，即第二预设距离。在本实施例中所述第一预设距离与第二预设距离相等。
请参阅图86，源极1404设置在第一凹部内且高于所述第一凹部，漏极1405设置在第二凹部内且高于第二凹部，栅极1406设置在第二半导体层1403上，栅极1406位于源极1404与漏极1405之间，且更靠近源极1404的一侧。在不同实施例中，栅极1406可呈“T”字型，以改善噪声。
请参阅图86，栅极1406与第二半导体层1403之间还包括一氧化层1407，氧化层1407可包括ITO、ZnO、RuOx、TiOx或IrOx中的至少一种。在本实施例中，氧化层1407为二氧化钛层(TiO2)。与其它氧化物相比，通过设置二氧化钛层为氧化层1407可改进所述半导体器件的电流以及截止频率。同时氧化层1407可以减小栅极1406与第二半导体层1403之间的接触电阻，进而改善所述半导体器件的噪声，使其在最大有效电流情况下噪声更小。
请参阅图86，在一些实施例中，源极1404与第二半导体层1403接触的一侧包括第一N型重掺杂区1409，第一N型重掺杂区1409位于所述第一沟槽内，且第一N型重掺杂区1409的高度高于第二半导体层1403，保证第一N型重掺杂区1409与第二半导体层1403完全接触。漏极1405与二半导体层1403接触的一侧包括第二N型重掺杂区1408，第二N型重掺杂区1408位于所述第二沟槽内，且第二N型重掺杂区1408的高度高于第二半导体层1403，保证，第二N型重掺杂区1408与第二半导体层1403完全接触。第一N型重掺杂区1409和第二N型重掺杂区1408都是高掺杂区域，与第二半导体层1043之间形成良好的欧姆接触。
请参阅图87，当应用本公开的半导体器件来射频模组时，所述射频模组包括所述半导体器件。所述射频模组主要包括射频(radio frequency，RF)切换器件1411、射频(radio frequency， RF)有源器件1414、射频(radio frequency，RF)无源器件1412和控制器件1413。其中射频(radio frequency，RF)有源器件1414可以是本申请中的所述半导体器件，射频(radio frequency，RF)无源器件1412可以是电容器、电阻器和电感器等无源器件。其中，射频(radio frequency，RF)切换器件1411、射频(radio frequency，RF)有源器件1414、射频(radio frequency，RF)无源器件1412和控制器件1413均形成于半导体衬底1410上。
请参阅图88，在不同实施例中，当利用本公开提供的半导体设备及外延结构制造半导体器件时，所述半导体器件包括基板1400、缓冲层1501、第一半导体层1502、第二半导体层1504、源极1506、漏极1505、栅极1507以及第一半导体台状部1509。缓冲层1501设置在基板1400上，第一半导体层1502设置在缓冲层1501上，第二半导体层1504设置在第一半导体层1502上，源极1506、漏极1505形成于第二半导体层1504上，且位于相对的两侧，第一半导体台状部1509形成于第二半导体层1504上，且位于源极1506和漏极1505之间，栅极1507形成于第一半导体台状部1509上，其中栅极1507的长度或宽度是大于第一半导体台状部1509的长度或宽度。
基板1400的材料可以为硅(Si)、碳化硅(SiC)、蓝宝石((Al2O3)、砷化镓(GaAs)、铝酸锂(LiAlO2)等半导体基板1400材料，在一些实施例中，基板1400例如为硅(Si)基材料，例如硅(Si)或碳化硅(SiC)等硅基材料。第一半导体层1502行位于缓冲层1501上，且第一半导体层1502位于缓冲层1501与第二半导体层1504之间。在一些实施例中，第一半导体层1502例如为氮化镓层，第一半导体层1502的厚度可以设置为例如200～300nm。第二半导体层1504位于第一半导体层1502上，在本实施例中，第二半导体层1504例如为氮化铝镓层(AlGaN)，所述氮化铝镓层的厚度可以是例如10～15nm。
请再参阅图88，在一实施例中，第一半导体层1502为氮化镓层(GaN)，第二半导体层1504为氮化铝镓层(AlGaN)，氮化镓层与氮化铝镓层可构成异质型半导体结构，所述半导体结构为一种增强型半导体结构。依靠第一半导体层1502(氮化镓层)和第二半导体层1504(氮化铝镓层)较强的自发和压电极化效应，在第一半导体层1502和第二半导体层1504异质结构中诱导出一层二维电子气1503。
请再参阅图88，所述半结构还包括一图案化的钝化层1510，钝化层1510设置在第二半导体层1504上。钝化层1510的形成过程包括：首先在第二半导体层1504上形成一钝化层1510，然后在钝化层1510上形成一图案化光阻层，然后根据图案化光阻层对钝化层1510进行刻蚀，形成图案化的钝化层1510，然后去除图案化光阻层并清洗干净。钝化层1510的材料可以选用氧化硅或是氧化铝，可以对所述半导体器件进行保护，避免反向漏电的问题，提高芯片的可靠性。在一些实施例中，钝化层1510可选用材料SiO2，便于腐蚀开孔，在蚀刻 时可通过缓冲氧化硅刻蚀液或干法刻蚀去除部分钝化层1510。
请参阅图88，在一实施例中，在钝化层1510上蚀刻出两个开口，第一开口和第二开口，同时在钝化层1510蚀刻出一凹部。所述凹部位于在钝化层1510的中间，且穿过钝化层1510与第二半导体层1504接触。第一开口与第二开口分别位于所述凹部的两侧，且第一开口与第二开口相对设置，第一开口与第二开口均穿过钝化层1510与第二半导体层1504接触。在本实施例中，在第一开口内设置源极1506，在第二开口内设置漏极1505，源极1506与漏极1505的高度均小于钝化层1510的厚度。
请参阅图88，所述半导体器件还包括栅极1507，栅极1507设置在源极1506与漏极1505之间，位于所述凹部内，且设置在第一半导体台状部1509上。在本实施例中，第一半导体台状部1509位于第二半导体层1504上，且设置在所述凹部内，第一半导体台状部1509的高度大于所述凹部的深度，第一半导体台状部1509与所述凹部侧壁具有一定的预设距离，第一半导体台状部1509的材料例如为P型氮化镓(P-GaN)。在埋入式P型GaN在没有被活化的情况下，未金属化的半导体结构结构在反向偏压下显示出高漏电流，而经过活化后，可以抑制电流的高漏。所述活化的的过程例如为：在干燥空气氛围中在725℃下退火30分钟来进行活化。
请参阅图88，栅极1507设置在第一半导体台状部1509上，且栅极1507的长度或宽度大于第一半导体台状部1509的长度或是宽度。栅极1507设置在在第一半导体台状部1509上与第二半导体层1504上，栅极1507填满第一半导体台状部1509与所述凹侧壁之间的沟道。栅极1507的截面呈倒置的“凹”字状扣在第一半导体台状部1509上，栅极1507的长度或宽度大于第一半导体台状部1509的长度或是宽度。在栅极1507的长度或宽度比第一半导体台状部1509的长度或是宽度大的情况下，更加容易开启沟道的二维电子气，从而产生更高的漏电流，第一半导体台状部1509与所述凹部侧壁之间的栅极1507具有更好的栅极控制、更好的跨导和更低的栅漏电流，从而提高所述半导体器件的性能。
请参阅图88，栅极1507与第一半导体台状部1509之间还包括一氧化层1508，氧化层1508设置在栅极1507与第一半导体台状部1509之间，通过设置氧化层1508降低栅极漏电流。在本实施例中，氧化层1508例如为氧化铝层。通过将氧化层1508设置为氧化铝层，可以增加氧化层的电容容量、正向电流密度以及跨导，有利于开通沟道的二维电子气，改善所述半导体器件的质量。
请参阅图89，当应用本公开的半导体器件来射频模组时，所述射频模组包括所述半导体器件。所述射频模组主要包括射频(radio frequency，RF)切换器件1511、射频(radio frequency，RF)有源器件1514、射频(radio frequency，RF)无源器件1512和控制器件1513。其中射 频(radio frequency，RF)有源器件1514可以是本申请中的所述半导体器件，射频(radio frequency，RF)无源器件1512可以是电容器、电阻器和电感器等无源器件。其中，射频(radio frequency，RF)切换器件1511、射频(radio frequency，RF)有源器件1514、射频(radio frequency，RF)无源器件1512和控制器件1513均形成于半导体衬底1515上。
请参阅图88，在不同实施例中，当利用本公开提供的半导体设备及外延结构制造半导体器件时，所述半导体器件包括基板1400、缓冲层1601、第一半导体层1603、第二半导体层1604、第三半导体层1602以及源极1607、漏极1608和栅极1609。其中，缓冲层1601形成于基板1400上，第一半导体层1603形成于缓冲层1601上，第二半导体层1604形成于第一半导体层1603上，第三半导体层1602形成于第一半导体层1603与缓冲层1601之间。源极1607形成于第一半导体层1603的一侧，并由第二半导体层1604延伸至缓冲层1601，漏极1608形成于第一半导体层1603的另一侧，并由第二半导体层1604延伸至缓冲层1601，栅极1609形成于第二半导体层1604上，并位于源极1607与漏极1608之间。
请参阅图90，所述半导体器件包括一基板1400，基板1400一般可以是各种适当的生长基板1400，基板1400的材料可以为硅(Si)、碳化硅(SiC)、蓝宝石((Al2O3)、砷化镓(GaAs)、铝酸锂(LiAlO2)等半导体基板材料，在本实施例中，基板1400例如为硅(Si)基材料，例如硅(Si)或碳化硅(SiC)等硅基材料。
请参阅图90，所述半导体器件包括缓冲层1601，缓冲层1601设置在基板1400上，缓冲层1601设置在基板1400与半导体层之间，可缓和基板1400与所述半导体层之间晶格不匹配的情况，缓冲层1601的材料一般根据基板1400的材料以及基板1400上半导体材料决定。在本实施例中，缓冲层1601可以是氮化镓铝层，所述氮化镓铝的层的厚度设置在例如为115～125埃之间，例如为120埃。同时在基板1400上生长缓冲层1601有利于其上设置的外延结构的生长，提高所述半导体器件的质量。
请参阅图90，所述半导体器件包括第三半导体层1602，第三半导体层1602设位于缓冲层1601上方。在本实施例中，第三半导体层1602包括第三施主层1602a和第三间隔层1602b，第三施主层1602a为氮化镓铝层，第三施主层1602a设置在缓冲层1601上，第三施主层1602a的厚度设置在例如48～52埃之间，例如为50埃。第三施主层1602a的离子掺杂浓度例如为1×10 24m -3～2×10 24m -3。第三间隔层1602b设置在第三施主层1602a与第一半导体层1603之间，第三间隔层1602b为氮化镓铝层，第三间隔层1602b的厚度与第三施主层1602a的厚度设置相同，例如为50埃。
请参阅图90，所述半导体器件包括第一半导体层1603，第一半导体层1603上设置在第三半导体层1602上。在本实施例中，第一半导体层1603例如为氮化镓层，第一半导体层1603 的厚度设置例如为195-205埃之间，例如为200埃。氮化镓是第三代宽禁带半导体材料，具有大禁带宽度(3.4eV)、高电子饱和速率、高击穿电场、较高的热导率、耐腐蚀和抗辐射性能，而且氮化镓层能够与但氮化镓铝层形成AlGaN/GaN异质结，进而形成高浓度、高迁移率的二维电子气，以便于制作半导体器件器件。
请参阅图90，所述半导体器件包括第二半导体层1604，第二半导体层1604形成于第一半导体层1603上。在本实施例中，第二半导体层1604包括第二施主层1604a和第二间隔层1604b，第二施主层1604a设置在第一半导体层1603上，第二施主层1604a也是氮化镓铝层，第二施主层1604a的厚度与第三施主层1602a相同设置，例如设置为50埃。第二施主层1604a的离子掺杂浓度与第三施主层的离子掺杂浓度相同，例如为1×10 24m -3～2×10 24m -3。第二间隔层1604b设置在第一半导体层1603和第二施主层1604a之间，第二间隔层1604b也为氮化镓铝层，其厚度与第二间隔层1604b相同设置，例如为50埃。
请参阅图90，所述半导体器件包括两个二维电子气层，第一二维电子气层1610和第二二维电子气层1611。第一二维电子气层1610形成于第一半导体层1603与第三半导体层1602之间，第二二维电子气层1611形成于第一半导体层1603与第二半导体层1604之间。两个二维电子气层使所述半导体器件具有更高的耐压性，也更有利于开通沟道的二维电子气。
请参阅图90，所述半导体器件包括阻挡层1605，阻挡层1605设置在第二半导体层1604上。在本实施例中，阻挡层1605为氮化镓铝层，阻挡层1606的厚度设置在115-125埃之间，例如为120埃。
请参阅图90，所述半导体器件还包括一氮化镓盖层1606，氮化镓盖层1606位于阻挡层上方，在本实施例中，氮化镓盖层1606的厚度设置在例如95-105埃之间，例如为100埃。
请参阅图90，所述半导体器件结构包括源极1607、漏极1608和栅极1609。源极1607设置在第一半导体的一侧，且源极1607由第二半导体层1604延伸至缓冲层1601，漏极1608设置第一半导体层1603的另一侧，且漏极1608由第二半导体层1604延伸至缓冲层1601。栅极1609设置在源极1607与漏极1608之间，且栅极1609设置在第二半导体层1604上。
请参阅图90，在本实施例中，源极1607依次穿过第二半导体层1604、第一半导体层1603和第三半导体层1602到达缓冲层1601，漏极1608也依次穿过第二半导体层1604、第一半导体层1603和第三半导体层1602到达缓冲层1601，源极1607与漏极1608均与第一二维电子层1610和第二二维电子层1611层欧姆连接。更加容易开通沟道的二维电子气。栅极1609设置在第二半导体层1604上，栅极1609的截面宽度小于源极1607和漏极1608的宽度。
请参阅图91，当应用本公开的半导体器件来射频模组时，所述射频模组包括所述半导体器件。所述射频模组主要包括射频(radio frequency，RF)切换器件1615、射频(radio frequency， RF)有源器件1618、射频(radio frequency，RF)无源器件1616和控制器件1617。其中射频(radio frequency，RF)有源器件1618可以是本申请中的所述半导体器件，射频(radio frequency，RF)无源器件1616可以是电容器、电阻器和电感器等无源器件。其中，射频(radio frequency，RF)切换器件1615、射频(radio frequency，RF)有源器件1618、射频(radio frequency，RF)无源器件1616和控制器件1617均形成于半导体衬底1619上。
请参阅图92，在不同实施例中，当利用本公开提供的半导体设备及外延结构制造半导体器件时，所述半导体器件包括基板1400、缓冲层1701、第一半导体层1702、第二半导体层1704，以及第二半导体层1704上的源极1705、漏极1707和栅极1706。缓冲层1701设置在基板1400上，第一半导体层1702设置在缓冲层1701上，第二半导体层1704设置在第一半导体层1702上。源极1705和漏极1707形成于所述第二半导体层1704上，且源极1705与漏极1707位于相对的两侧，栅极1706位于源极1705与漏极1707之间，其中，第一半导体层1702与第二半导体层1704之间形成一二维电子气层1702。
请参阅图92，基板1400的材料可以为硅(Si)、碳化硅(SiC)、蓝宝石((Al2O3)、砷化镓(GaAs)、铝酸锂(LiAlO2)等材料。利用本公开提供的半导体设备，利用物理气相沉积的方法在基板1400上形成一缓冲层1701，缓冲层1701设置在基板1400与半导体层之间，可缓和基板1400与所述半导体层之间晶格不匹配的情况，同时在基板1400上生长缓冲层1701有利于其上设置的外延结构的生长，提高所述半导体器件的质量。缓冲层1701的材料根据基板1400的材料以及基板1400上半导体材料决定。缓冲层1701例如可以是氮化镓缓层，且所述氮化镓缓冲层1701具有较大的厚度，所述氮化铝缓冲层1701的厚度可以设置为例如大于60nm。
请参阅图92，第一半导体层1702设置在缓冲层1701上，其中第一半导体层1702为非故意掺杂的氮化镓层。第二半导体层1704设置在第一半导体层1702上，第二半导体层1704为氮化铝镓层。所述氮化镓层与所述氮化铝镓之间具有较强的自发和压电极化效应，在第一半导体层1702和第二半导体层1704之间诱导出二维电子气层1702，使形成的半导体器件具有较好的垂直泄露和击穿特性。
请参阅图92，第二半导体层1704上包括源极1705、漏极1707和栅极1706，源极1705形成与第二半导体层1704的一侧，漏极1707位于相对于源极1705的一侧，栅极1706设置在源极1705与漏极1707之间。
请参阅图93，当应用本公开的半导体器件来射频模组时，所述射频模组包括所述半导体器件。所述射频模组主要包括射频(radio frequency，RF)切换器件1715、射频(radio frequency，RF)有源器件1718、射频(radio frequency，RF)无源器件1716和控制器件1717。其中射 频(radio frequency，RF)有源器件1718可以是本申请中的所述半导体器件，射频(radio frequency，RF)无源器件1716可以是电容器、电阻器和电感器等无源器件。其中，射频(radio frequency，RF)切换器件1715、射频(radio frequency，RF)有源器件1718、射频(radio frequency，RF)无源器件1716和控制器件1717均形成于半导体衬底1719上。
综上所述，本申请提出一种半导体设备，能够提高镀膜的均匀性。利用本申请的设备或制成方法也可应用于其他该质量薄膜或外延结构，例如金属薄膜、半导体薄膜、绝缘薄膜、化合物薄膜或其他材料的薄膜。再者，在本申请中所形成高质量薄膜及外延结构可应用于各种半导体结构、电子原件或电子装置中，例如开关元件、功率元件、射频元件、发光二极管、微型发光二极管、显示面板、手机、手表、笔记本电脑、投载式装置、充电装置、充电桩、虚拟现实(VR)装置、扩充现实(AR)装置、可携式电子装置、游戏机或其他电子装置。
以上描述仅为本申请的较佳实施例以及对所运用技术原理的说明，本领域技术人员应当理解，本申请中所涉及的公开范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离所述公开构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案，例如上述特征与本申请中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。
除说明书所述的技术特征外，其余技术特征为本领域技术人员的已知技术，为突出本公开的创新特点，其余技术特征在此不再赘述。

Claims (14)

  1. 一种半导体外延结构，包括：
    基板；
    氮化铝层，形成于所述基板上；以及
    至少一氮化镓层，形成于所述氮化铝层上。
  2. 根据权利要求1所述的半导体外延结构，还包括:
    第一氮化铝镓层，形成于所述氮化铝层上；
    第二氮化铝镓层，形成于所述第一氮化铝镓层上。
  3. 根据权利要求2所述的半导体外延结构，其中所述第一氮化铝镓层(Al xGa 1-xN)的X值大于所述第二氮化铝镓层(Al YGa 1-YN)中Y的值。
  4. 根据权利要求1所述的半导体外延结构，其中所述氮化镓层包括第一氮化镓层、第二氮化镓层以及第三氮化镓层。
  5. 根据权利要求2所述的半导体外延结构，其特征在于：所述第一氮化铝镓层或第二氮化铝镓层的厚度为600-1200纳米。
  6. 根据权利要求1所述的半导体外延结构，还包括:超晶格结构，形成于所述氮化铝层上，其中所述超晶格结构包括多个氮化铝夹层及多个氮化铝镓夹层。
  7. 根据权利要求6所述的半导体外延结构，其中所述氮化铝夹层的厚度为4-10nm。
  8. 根据权利要求6所述的半导体外延结构，其中所述氮化铝镓夹层的厚度为10-30nm。
  9. 一种半导体器件，包括：根据权利要求1所述的半导体外延结构。
  10. 一种电子装置，包括：根据权利要求9所述的半导体器件。
  11. 一种发光二极管结构，包括：根据权利要求1所述的半导体外延结构。
  12. 一种微型发光二极管芯片，其特征在于，包括：根据权利要求11所述的发光二极管结构。
  13. 一种微发光二极管面板，其特征在于，包括：根据权利要求11所述的发光二极管结构。
  14. 一种半导体外延结构的制造方法，包括：
    提供一基板；
    形成氮化铝层于所述基板上；
    形成至少一氮化镓层于所述氮化铝层上。
PCT/CN2020/116501 2019-09-20 2020-09-21 一种半导体外延结构及其应用与制造方法 WO2021052498A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/698,013 US20220223759A1 (en) 2019-09-20 2022-03-18 Semiconductor epitaxial structure and application and manufacturing methods thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910895152.5 2019-09-20
CN201910895152.5A CN110643962A (zh) 2019-09-20 2019-09-20 一种半导体设备

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/698,013 Continuation US20220223759A1 (en) 2019-09-20 2022-03-18 Semiconductor epitaxial structure and application and manufacturing methods thereof

Publications (1)

Publication Number Publication Date
WO2021052498A1 true WO2021052498A1 (zh) 2021-03-25

Family

ID=69010998

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/116501 WO2021052498A1 (zh) 2019-09-20 2020-09-21 一种半导体外延结构及其应用与制造方法

Country Status (3)

Country Link
US (1) US20220223759A1 (zh)
CN (1) CN110643962A (zh)
WO (1) WO2021052498A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110643934A (zh) * 2019-09-20 2020-01-03 深圳市晶相技术有限公司 一种半导体设备
WO2021052497A1 (zh) * 2019-09-20 2021-03-25 深圳市晶相技术有限公司 一种半导体设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007005984A1 (en) * 2005-07-05 2007-01-11 Kansas State University Research Foundation Light emitting diode with mg doped superlattice
CN101079463A (zh) * 2006-05-23 2007-11-28 Lg.菲利浦Lcd株式会社 发光二极管芯片及其制造方法以及包括其的液晶显示器件
CN102714162A (zh) * 2009-11-04 2012-10-03 同和电子科技有限公司 第iii族氮化物外延层压基板
CN103199164A (zh) * 2013-04-07 2013-07-10 中国科学院半导体研究所 一种具有dbr高反射结构的紫外发光二极管及其制备方法
CN103258844A (zh) * 2012-02-17 2013-08-21 台积固态照明股份有限公司 在硅衬底上生长高品质的iii-v族化合物层的方法
CN108110098A (zh) * 2017-10-25 2018-06-01 华灿光电（浙江）有限公司 一种氮化镓基发光二极管外延片及其制造方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2236500Y (zh) * 1995-05-19 1996-10-02 四川大学 半圆柱磁控溅射阴极
JP4680352B2 (ja) * 1999-07-06 2011-05-11 アプライド マテリアルズ インコーポレイテッド スパッタリング装置および成膜方法
JP4680353B2 (ja) * 1999-07-06 2011-05-11 アプライド マテリアルズ インコーポレイテッド スパッタリング装置および成膜方法
US6440282B1 (en) * 1999-07-06 2002-08-27 Applied Materials, Inc. Sputtering reactor and method of using an unbalanced magnetron
US20060105114A1 (en) * 2004-11-16 2006-05-18 White John M Multi-layer high quality gate dielectric for low-temperature poly-silicon TFTs
CN101988189B (zh) * 2009-08-07 2012-10-10 鸿富锦精密工业（深圳）有限公司 磁控溅射靶及采用该磁控溅射靶的磁控溅射装置
JP5706102B2 (ja) * 2010-05-07 2015-04-22 ローム株式会社 窒化物半導体素子
CN102400107A (zh) * 2010-09-13 2012-04-04 北京北方微电子基地设备工艺研究中心有限责任公司 磁控溅射源及磁控溅射设备
CN102534529B (zh) * 2010-12-24 2015-04-15 北京北方微电子基地设备工艺研究中心有限责任公司 磁控溅射源及磁控溅射设备
CN202246871U (zh) * 2011-10-08 2012-05-30 保定天威集团有限公司 一种集成化的多腔室星型结构真空镀膜设备
CN104093878B (zh) * 2012-01-30 2016-05-11 日立金属株式会社 磁控溅射用磁场产生装置
CN104112640B (zh) * 2013-04-16 2016-12-28 北京北方微电子基地设备工艺研究中心有限责任公司 一种磁控溅射设备及磁控溅射方法
CN103396008A (zh) * 2013-08-02 2013-11-20 蚌埠雷诺真空技术有限公司 磁控溅射真空室均匀进气装置
US11008651B2 (en) * 2016-04-11 2021-05-18 Spts Technologies Limited DC magnetron sputtering
CN108690961A (zh) * 2017-04-06 2018-10-23 北京北方华创微电子装备有限公司 磁控溅射组件、磁控溅射腔室及磁控溅射设备
CN207121636U (zh) * 2017-05-25 2018-03-20 北京滨松光子技术股份有限公司 一种结构紧凑的磁控溅射镀膜装置
EP3496131B1 (en) * 2017-12-05 2023-06-21 IMEC vzw Method for forming a semiconductor structure and a semiconductor structure manufactured thereof
CN211199388U (zh) * 2019-09-20 2020-08-07 深圳市晶相技术有限公司 一种半导体设备

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007005984A1 (en) * 2005-07-05 2007-01-11 Kansas State University Research Foundation Light emitting diode with mg doped superlattice
CN101079463A (zh) * 2006-05-23 2007-11-28 Lg.菲利浦Lcd株式会社 发光二极管芯片及其制造方法以及包括其的液晶显示器件
CN102714162A (zh) * 2009-11-04 2012-10-03 同和电子科技有限公司 第iii族氮化物外延层压基板
CN103258844A (zh) * 2012-02-17 2013-08-21 台积固态照明股份有限公司 在硅衬底上生长高品质的iii-v族化合物层的方法
CN103199164A (zh) * 2013-04-07 2013-07-10 中国科学院半导体研究所 一种具有dbr高反射结构的紫外发光二极管及其制备方法
CN108110098A (zh) * 2017-10-25 2018-06-01 华灿光电（浙江）有限公司 一种氮化镓基发光二极管外延片及其制造方法

Also Published As

Publication number Publication date
US20220223759A1 (en) 2022-07-14
CN110643962A (zh) 2020-01-03

Similar Documents

Publication Publication Date Title
CN112768571B (zh) 一种微型发光二极管结构的制造方法
US20070246700A1 (en) Light Emitting Device and Method of Manufacturing the Same
JP5097532B2 (ja) 化合物半導体発光素子の製造方法
WO2016192434A1 (zh) 一种利用化学腐蚀的方法剥离生长衬底的方法
JP5117596B2 (ja) 半導体発光素子、ウェーハ、および窒化物半導体結晶層の製造方法
US20220223759A1 (en) Semiconductor epitaxial structure and application and manufacturing methods thereof
KR101878742B1 (ko) 그래핀층 상에 ＧａＮ 층을 성장시키는 방법 및 상기 그래핀층 상의 ＧａＮ을 이용한 발광소자
KR20100055187A (ko) 산화갈륨기판 제조방법, 발광소자 및 발광소자 제조방법
CN104362240A (zh) 一种LED芯片的Al2O3/SiON钝化层结构及其生长方法
TW200300616A (en) Light emitting device and its manufacturing method
TWI823150B (zh) 半導體結構及其應用
WO2024120154A1 (zh) 紫外发光二极管及其制造方法
CN213327795U (zh) 一种半导体外延结构及其应用
TWI821665B (zh) 微型發光二極體特徵之預清洗及封裝
KR20110050212A (ko) 질화물 반도체 발광소자 및 그 제조방법
JP5449415B2 (ja) 半導体発光素子
CN210429860U (zh) 一种具有高稳定性电流阻挡层的led芯片
KR101072199B1 (ko) 발광소자 및 그 제조방법
CN105261691A (zh) 发光二极管倒装芯片的制备方法及发光二极管倒装芯片
KR101450268B1 (ko) 반도체 소자의 제조 방법 및 이를 이용하여 제조된 반도체 소자
KR101153484B1 (ko) 수직형 발광소자 제조방법
JP2012244152A (ja) 半導体発光素子

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20865783

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20865783

Country of ref document: EP

Kind code of ref document: A1