WO2021047120A1 - 一种fpga异构加速卡集群中的资源调度方法、设备及介质 - Google Patents

一种fpga异构加速卡集群中的资源调度方法、设备及介质 Download PDF

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Publication number
WO2021047120A1
WO2021047120A1 PCT/CN2019/130032 CN2019130032W WO2021047120A1 WO 2021047120 A1 WO2021047120 A1 WO 2021047120A1 CN 2019130032 W CN2019130032 W CN 2019130032W WO 2021047120 A1 WO2021047120 A1 WO 2021047120A1
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card
storage
storage resources
fpga heterogeneous
heterogeneous accelerator
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PCT/CN2019/130032
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English (en)
French (fr)
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葛海亮
刘钧锴
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苏州浪潮智能科技有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/781—On-chip cache; Off-chip memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

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  • the present invention relates to the field of FPGA, and more specifically, to a resource scheduling method, equipment and readable medium in an FPGA heterogeneous accelerator card cluster.
  • FPGA heterogeneous accelerator cards have been widely used in server data centers.
  • FPGA accelerator cards often have storage resources (including but not limited to DDR, etc.).
  • storage resources including but not limited to DDR, etc.
  • FPGA heterogeneous accelerator cards are connected to the system, how to schedule and use these storage Resources become the key to the problem.
  • Most of the existing technologies are limited to the card's FPGA logic calling the card's storage resources. The problem is that when the card's storage resources called by the card's FPGA logic are in short supply, the hardware can only be replaced. In this way, the cost increases and the development cycle becomes longer.
  • the card resources called by the FPGA logic of the card are abundant, the card-side storage resources are idle and wasted in the entire system.
  • the purpose of the embodiments of the present invention is to propose a resource scheduling method, equipment and medium in an FPGA heterogeneous accelerator card cluster, which can fully call the entire FPGA heterogeneous accelerator card cluster by sending a storage resource request to the main card.
  • Storage resources to prevent the storage resources of a single FPGA heterogeneous accelerator card from being strained or idle.
  • one aspect of the embodiments of the present invention provides a resource scheduling method in an FPGA heterogeneous accelerator card cluster, which includes the following steps: receiving a request for storage information, and determining whether the storage resources of the card are exhausted; When the storage resources are exhausted, send a storage resource request to the main card in the FPGA heterogeneous accelerator card cluster; and accept the storage resources of other FPGA heterogeneous accelerator cards allocated by the main card, and store the storage information in the storage resources allocated by the main card .
  • the storage resources of the card include: storage resources inside the FPGA heterogeneous accelerator card, storage resources on the same board as the FPGA heterogeneous accelerator card, and storage reserved for the FPGA heterogeneous accelerator card on the server side. Resources.
  • judging whether the storage resources of the card are exhausted includes: judging whether the delay time requirement for storing information is less than a threshold; and in response to the delay time requirement for storing information being less than the threshold, judging the storage resources inside the FPGA heterogeneous accelerator card Is it exhausted?
  • the method further includes: in response to exhaustion of storage resources inside the FPGA heterogeneous accelerator card, judging whether the storage resources of the same board as the FPGA heterogeneous accelerator card are exhausted.
  • the method further includes: in response to exhaustion of storage resources on the same board as the FPGA heterogeneous accelerator card, judging whether the storage resources reserved for the FPGA heterogeneous accelerator card on the server side are exhausted.
  • it further includes: in response to the delay requirement of storing information not being lower than the threshold, judging whether the storage resources of the same board as the FPGA heterogeneous accelerator card are exhausted.
  • the method further includes: in response to exhaustion of storage resources on the same board as the FPGA heterogeneous accelerator card, judging whether the storage resources reserved for the FPGA heterogeneous accelerator card on the server side are exhausted.
  • the method further includes: determining whether the usage of the storage resource has changed; and in response to the usage of the storage resource, updating the storage resource record information of the card and sending it to the main card.
  • a computer device including: at least one processor; and a memory.
  • the memory stores computer instructions that can run on the processor, and the instructions are executed by the processor to implement the following steps: Receive storage information requests, and determine whether the storage resources of the card are exhausted; in response to exhaustion of storage resources, send storage resource requests to the main card in the FPGA heterogeneous accelerator card cluster; and accept other FPGA heterogeneous allocations from the main card Accelerate the storage resources of the card and store the storage information in the storage resources allocated by the main card.
  • a computer-readable storage medium stores a computer program that implements the steps of the above method when executed by a processor.
  • the present invention has the following beneficial technical effects: by sending a storage resource request to the main card, the storage resources of the entire FPGA heterogeneous accelerator card cluster are fully invoked, and the storage resources of a single FPGA heterogeneous accelerator card are prevented from being tight or idle.
  • FIG. 1 is a schematic diagram of an embodiment of a resource scheduling method in an FPGA heterogeneous accelerator card cluster provided by the present invention
  • FIG. 2 is a schematic diagram of the structure of the FPGA heterogeneous accelerator card provided by the present invention.
  • Fig. 3 is a flowchart of an embodiment of a resource scheduling method in an FPGA heterogeneous accelerator card cluster provided by the present invention.
  • Fig. 1 shows a schematic diagram of an embodiment of a resource scheduling method in an FPGA heterogeneous accelerator card cluster provided by the present invention.
  • the embodiment of the present invention includes the following steps:
  • the storage resources of the FPGA heterogeneous accelerator card include: storage resources inside the FPGA heterogeneous accelerator card, storage resources on the same board as the FPGA heterogeneous accelerator card, and server-side reserved for FPGA heterogeneous The storage resources of the accelerator card.
  • storage resources inside the FPGA heterogeneous accelerator card storage resources inside the FPGA heterogeneous accelerator card
  • storage resources on the same board as the FPGA heterogeneous accelerator card and server-side reserved for FPGA heterogeneous The storage resources of the accelerator card.
  • server-side reserved for FPGA heterogeneous The storage resources of the accelerator card In a single FPGA heterogeneous accelerator card, there are three types of storage resources.
  • the storage resources inside the FPGA heterogeneous accelerator card can be the high-performance storage unit inside the FPGA heterogeneous accelerator card, including but not limited to HBM (High Bandwidth Memory), etc.;
  • the storage resources on the same board as the FPGA heterogeneous accelerator card for example, can be storage resources outside the FPGA, including but not limited to DDR (Double Data Rate, dual Multi-rate synchronous dynamic random access memory), etc.;
  • FIG. 2 shows a schematic diagram of the structure of the FPGA heterogeneous accelerator card provided by the present invention.
  • multiple FPGA heterogeneous accelerator cards are inserted on the server side through PCIE DMA (Peripheral Component Interconnect Express Direct Memory Access, direct access to high-speed peripherals interconnect memory) or OpenCapi (open standard interface for high-performance acceleration), etc. Interconnection mechanism communication.
  • FPGA heterogeneous accelerator cards are connected through a network, and communicate through interconnection mechanisms such as MAC or RDMA (Remote Direct Memory Access).
  • the specified method includes but is not limited to the form of a hardware DIP switch.
  • the board with the DIP switch set to 1 is used as the main card.
  • the main card is responsible for scheduling and scheduling the resources of the entire system. Use, the remaining boards are named as secondary cards.
  • Each board uses a fixed physical mac address as the identification of identification, which is called board identification.
  • the specific process can be as follows:
  • each board updates the memory resource record information of the card.
  • the secondary card sends the storage resource record information of the card to the main card. After the main card receives it, it updates the storage resource record information used to record the entire system.
  • a single FPGA heterogeneous acceleration card receives the request for storing information and judges whether the storage resources corresponding to the FPGA heterogeneous acceleration card are exhausted.
  • judging whether the storage resources of the card is exhausted includes: judging that the delay time requirement for storing information is less than a threshold; and in response to the delay time requirement for storing information being less than the threshold, judging whether the storage resources inside the FPGA heterogeneous accelerator card are Exhausted. In response to the exhaustion of the internal storage resources of the FPGA heterogeneous accelerator card, it is determined whether the storage resources of the same board as the FPGA heterogeneous accelerator card are exhausted. In response to the exhaustion of storage resources on the same board as the FPGA heterogeneous accelerator card, it is determined whether the storage resources reserved for the FPGA heterogeneous accelerator card on the server side are exhausted.
  • the requirement for the delay time of stored information to be less than the threshold indicates that the stored information needs low latency, and the delay of the storage resources inside the FPGA heterogeneous accelerator card is the lowest. Therefore, the storage information is stored in the storage resources inside the FPGA heterogeneous accelerator card first.
  • it further includes: in response to the delay requirement of storing information not being lower than the threshold, judging whether the storage resources of the same board as the FPGA heterogeneous accelerator card are exhausted. In response to the exhaustion of storage resources on the same board as the FPGA heterogeneous accelerator card, it is determined whether the storage resources reserved for the FPGA heterogeneous accelerator card on the server side are exhausted.
  • the delay requirement of the stored information is not lower than the threshold, indicating that the stored information does not have high requirements for delay.
  • the stored information can be stored in the storage resource on the same board as the FPGA heterogeneous accelerator card, so that the FPGA heterogeneous acceleration can be accelerated
  • the internal storage resources of the card are reserved for storage information that requires high latency.
  • the method further includes: determining whether the usage of the storage resource has changed; and in response to the usage of the storage resource, updating the storage resource record information of the card and sending it to the main card.
  • the main card allocates an idle storage resource to the card according to the storage record information, and the priority use level of the storage resource can be the same as that of the card.
  • the secondary card confirms the use of idle storage resources allocated by the main card, and updates the system storage resource records.
  • Fig. 3 shows a flowchart of an embodiment of a resource scheduling method in an FPGA heterogeneous accelerator card cluster provided by the present invention.
  • FIG. 3 starting from box 101, then proceeding to box 102 to receive a request for storing information; then proceeding to box 103 to determine whether the storage resources of the card are exhausted, if not, proceed to the end of box 107, if yes , Proceed to block 104 to send a storage resource request to the main card in the FPGA heterogeneous accelerator card cluster; after sending the resource request, proceed to block 105, and the main card allocates the storage resources of the card according to the usage of the existing storage resources; Then proceed to block 106, accept the storage resources of other FPGA heterogeneous accelerator cards allocated by the main card, and store the storage information in the storage resources allocated by the main card, and then proceed to block 107 to end.
  • the second aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory, where computer instructions that can run on the processor are stored in the memory, and the instructions are executed by the processor.
  • a computer device including: at least one processor; and a memory, where computer instructions that can run on the processor are stored in the memory, and the instructions are executed by the processor.
  • S1 receive a request for storage information, and determine whether the storage resources of the card are exhausted
  • S2 in response to exhaustion of storage resources, send a storage resource request to the main card in the FPGA heterogeneous accelerator card cluster
  • S3 Accept the storage resources of other FPGA heterogeneous accelerator cards allocated by the main card, and store the storage information in the storage resources allocated by the main card.
  • the storage resources of the card include: storage resources inside the FPGA heterogeneous accelerator card, storage resources on the same board as the FPGA heterogeneous accelerator card, and storage reserved for the FPGA heterogeneous accelerator card on the server side. Resources.
  • judging whether the storage resources of the card are exhausted includes: judging whether the delay requirement of storing information is lower than a threshold; and in response to the delay requirement of storing information being less than the threshold, judging the storage resources inside the FPGA heterogeneous accelerator card Is it exhausted?
  • the method further includes: in response to exhaustion of storage resources inside the FPGA heterogeneous accelerator card, judging whether the storage resources of the same board as the FPGA heterogeneous accelerator card are exhausted.
  • the method further includes: in response to exhaustion of storage resources on the same board as the FPGA heterogeneous accelerator card, judging whether the storage resources reserved for the FPGA heterogeneous accelerator card on the server side are exhausted.
  • it further includes: in response to the delay requirement of storing information not being lower than the threshold, judging whether the storage resources of the same board as the FPGA heterogeneous accelerator card are exhausted.
  • the method further includes: in response to exhaustion of storage resources on the same board as the FPGA heterogeneous accelerator card, judging whether the storage resources reserved for the FPGA heterogeneous accelerator card on the server side are exhausted.
  • the method further includes: determining whether the usage of the storage resource has changed; and in response to the usage of the storage resource, updating the storage resource record information of the card and sending it to the main card.
  • the present invention also provides a computer-readable storage medium, and the computer-readable storage medium stores a computer program that executes the above method when executed by a processor.
  • the program of the resource scheduling method in the FPGA heterogeneous accelerator card cluster can be Stored in a computer readable storage medium, when the program is executed, it may include the processes of the above-mentioned method embodiments.
  • the storage medium of the program can be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.
  • the foregoing computer program embodiment can achieve the same or similar effects as any of the foregoing corresponding method embodiments.
  • the method disclosed according to the embodiment of the present invention may also be implemented as a computer program executed by a processor, and the computer program may be stored in a computer-readable storage medium.
  • the computer program executes the above-mentioned functions defined in the method disclosed in the embodiment of the present invention.
  • the above method steps and system units can also be implemented using a controller and a computer-readable storage medium for storing a computer program that enables the controller to implement the above steps or unit functions.
  • non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory Memory.
  • Volatile memory can include random access memory (RAM), which can act as external cache memory.
  • RAM can be obtained in many forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchronous link DRAM (SLDRAM) and direct Rambus RAM (DRRAM).
  • DRAM synchronous RAM
  • DRAM dynamic RAM
  • SDRAM synchronous DRAM
  • DDR SDRAM double data rate SDRAM
  • ESDRAM enhanced SDRAM
  • SLDRAM Synchronous link DRAM
  • DRRAM direct Rambus RAM
  • the storage devices of the disclosed aspects are intended to include, but are not limited to, these and other suitable types of memory.
  • DSP digital signal processors
  • ASIC application-specific integrated circuits
  • FPGA Field Programmable Gate Array
  • a general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
  • the processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP, and/or any other such configuration.
  • the steps of the method or algorithm described in combination with the disclosure herein may be directly included in hardware, a software module executed by a processor, or a combination of the two.
  • the software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor such that the processor can read information from or write information to the storage medium.
  • the storage medium may be integrated with the processor.
  • the processor and the storage medium may reside in the ASIC.
  • the ASIC can reside in the user terminal.
  • the processor and the storage medium may reside as discrete components in the user terminal.
  • functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored as one or more instructions or codes on a computer-readable medium or transmitted through the computer-readable medium.
  • Computer-readable media include computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another location.
  • a storage medium may be any available medium that can be accessed by a general-purpose or special-purpose computer.
  • the computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or may be used for carrying or storing instructions in the form of Or any other medium that can be accessed by a general-purpose or special-purpose computer or general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium.
  • coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave to send software from a website, server, or other remote source
  • coaxial cable Cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are all included in the definition of media.
  • magnetic disks and optical disks include compact disks (CD), laser disks, optical disks, digital versatile disks (DVD), floppy disks, and Blu-ray disks. Disks usually reproduce data magnetically, while optical disks use lasers to optically reproduce data. . Combinations of the above content should also be included in the scope of computer-readable media.
  • the program can be stored in a computer-readable storage medium.
  • the storage medium can be a read-only memory, a magnetic disk or an optical disk, etc.

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Abstract

一种FPGA异构加速卡集群中的资源调度方法，包括以下步骤：接收存储信息的请求，并判断本卡的存储资源是否用尽；响应于存储资源用尽，向FPGA异构加速卡集群中的主卡发送存储资源请求；以及接受所述主卡分配的其他FPGA异构加速卡的存储资源，并将所述存储信息存储到所述主卡分配的存储资源中。本发明还公开了一种计算机设备和可读存储介质。本发明提出的FPGA异构加速卡集群中的资源调度方法、设备及介质可以充分调用整个FPGA异构加速卡集群的存储资源，防止单个FPGA异构加速卡的存储资源紧张或闲置。

Description

一种FPGA异构加速卡集群中的资源调度方法、设备及介质
本申请要求于2019年9月12日提交中国专利局、申请号为201910864468.8、发明名称为“一种FPGA异构加速卡集群中的资源调度方法、设备及介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及FPGA领域，更具体地，特别是指一种FPGA异构加速卡集群中的资源调度方法、设备及可读介质。
背景技术
近年来，FPGA异构加速卡在服务器数据中心大量使用，FPGA加速卡上往往带有存储资源(包括但不限于DDR等)，当FPGA异构加速卡连接到系统时，如何调度与使用这些存储资源成为问题的关键，现有技术大多是仅限于本卡FPGA逻辑调用本卡的存储资源，存在的问题是，当本卡FPGA逻辑调用的本卡存储资源紧张的时候，只能采取更换硬件的方式，成本增加同时开发周期变长，另外，当本卡FPGA逻辑调用的本卡资源充裕的时候，本卡侧存储资源在整个系统中闲置浪费。
发明内容
有鉴于此，本发明实施例的目的在于提出一种FPGA异构加速卡集群中的资源调度方法、设备及介质，可以通过向主卡发送存储资源请求，充分调用整个FPGA异构加速卡集群的存储资源，防止单个FPGA异构加速卡的存储资源紧张或闲置。
基于上述目的，本发明实施例的一方面提供了一种FPGA异构加速卡集群中的资源调度方法，包括如下步骤：接收存储信息的请求，并判断本卡的存储资源是否用尽；响应于存储资源用尽，向FPGA异构加速卡集群中的主卡发送存储资源请求；以及接受主卡分配的其他FPGA异构加速卡的存储资源，并将存储信息存储到主卡分配的存储资源中。
在一些实施方式中，本卡的存储资源包括：FPGA异构加速卡内部的存储资源、与FPGA异构加速卡处于同一个板卡的存储资源以及服务器端预留给FPGA异构加速卡的存储资源。
在一些实施方式中，判断本卡的存储资源是否用尽包括：判断存储信息的延迟时间要求是否小于阈值；以及响应于存储信息的延迟时间要求小于阈值，判断FPGA异构加速卡内部的存储资源是否用尽。
在一些实施方式中，还包括：响应于FPGA异构加速卡内部的存储资源用尽，判断与FPGA异构加速卡处于同一个板卡的存储资源是否用尽。
在一些实施方式中，还包括：响应于与FPGA异构加速卡处于同一个板卡的存储资源用尽，判断服务器端预留给FPGA异构加速卡的存储资源是否用尽。
在一些实施方式中，还包括：响应于存储信息的延迟要求不低于阈值，判断与FPGA异构加速卡处于同一个板卡的存储资源是否用尽。
在一些实施方式中，还包括：响应于与FPGA异构加速卡处于同一个板卡的存储资源用尽，判断服务器端预留给FPGA异构加速卡的存储资源是否用尽。
在一些实施方式中，还包括：判断存储资源的使用情况是否发生变化；以及响应于存储资源的使用情况发生变化，更新本卡的存储资源记录信息，并发送给主卡。
本发明实施例的另一方面，还提供了一种计算机设备，包括：至少一个处理器；以及存储器，存储器存储有可在处理器上运行的计算机指令，指令由处理器执行以实现如下步骤：接收存储信息的请求，并判断本卡的存储资源是否用尽；响应于存储资源用尽，向FPGA异构加速卡集群中的主卡发送存储资源请求；以及接受主卡分配的其他FPGA异构加速卡的存储资源，并将存储信息存储到主卡分配的存储资源中。
本发明实施例的再一方面，还提供了一种计算机可读存储介质，计算机可读存储介质存储有被处理器执行时实现如上方法步骤的计算机程序。
本发明具有以下有益技术效果：通过向主卡发送存储资源请求，充分调用整个FPGA异构加速卡集群的存储资源，防止单个FPGA异构加速卡 的存储资源紧张或闲置。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的实施例。
图1为本发明提供的FPGA异构加速卡集群中的资源调度方法的实施例的示意图；
图2为本发明提供的FPGA异构加速卡的构造示意图；
图3为本发明提供的FPGA异构加速卡集群中的资源调度方法的实施例的流程图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明实施例进一步详细说明。
需要说明的是，本发明实施例中所有使用“第一”和“第二”的表述均是为了区分两个相同名称非相同的实体或者非相同的参量，可见“第一”“第二”仅为了表述的方便，不应理解为对本发明实施例的限定，后续实施例对此不再一一说明。
基于上述目的，本发明实施例的第一个方面，提出了一种FPGA异构加速卡集群中的资源调度方法的实施例。图1示出的是本发明提供的FPGA异构加速卡集群中的资源调度方法的实施例的示意图。如图1所示，本发明实施例包括如下步骤：
S1、接收存储信息的请求，并判断本卡的存储资源是否用尽；
S2、响应于存储资源用尽，向FPGA异构加速卡集群中的主卡发送存储资源请求；以及
S3、接受主卡分配的其他FPGA异构加速卡的存储资源，并将存储信 息存储到主卡分配的存储资源中。
在某些实施方式中，FPGA异构加速卡的存储资源包括：FPGA异构加速卡内部的存储资源、与FPGA异构加速卡处于同一个板卡的存储资源以及服务器端预留给FPGA异构加速卡的存储资源。在单个的FPGA异构加速卡中，存在的存储资源有以下三类，第一，FPGA异构加速卡内部的存储资源，例如可以是FPGA异构加速卡内部高性能存储单元，包括但不限于HBM(High Bandwidth Memory，高带宽内存)等；第二，与FPGA异构加速卡处于同一个板卡的存储资源，例如可以是FPGA外部的存储资源，包括但不限于DDR(Double Data Rate，双倍速率同步动态随机存储器)等；第三，服务器端HOST MEMORY(主机存储器)预留给FPGA异构加速卡使用的存储资源。
图2示出的是本发明提供的FPGA异构加速卡的构造示意图。如图2所示，多张FPGA异构加速卡插在服务器侧，通过PCIE DMA(Peripheral Component Interconnect ExpressDirect Memory Access，高速外围设备互连内存直接访问)或者OpenCapi(高性能加速的开放标准接口)等互联机制通信。FPGA异构加速卡之间通过网络相连，通过MAC或者RDMA(Remote Direct Memory Access，远程直接数据存取)等互联机制通信。
在系统中指定一个块板卡作为主卡，指定的方式包括但不限于硬件拨码开关的形式，例如将拨码开关拨到1的板卡作为主卡，主卡负责整个系统资源的调度与使用，其余板卡命名为副卡。每块板卡使用固定的物理mac地址作为身份识别的标识，称为板卡标识。具体流程可以如下：
首先，系统上电，硬件复位，FPGA异构系统中，各个板卡更新本卡的存储资源记录信息。副卡将本卡的存储资源记录信息，发送给主卡，主卡收到后，更新用来记录整个系统的存储资源记录信息。当异构加速系统在异构加速过程中，产生需要存储的信息时，单个FPGA异构加速卡接收存储信息的请求，并判断该FPGA异构加速卡对应的存储资源是否用尽。
在一些实施方式中，判断本卡的存储资源是否用尽包括：判断存储信息的延迟时间要求小于阈值；以及响应于存储信息的延迟时间要求小于阈值，判断FPGA异构加速卡内部的存储资源是否用尽。响应于FPGA异构 加速卡内部的存储资源用尽，判断与FPGA异构加速卡处于同一个板卡的存储资源是否用尽。响应于与FPGA异构加速卡处于同一个板卡的存储资源用尽，判断服务器端预留给FPGA异构加速卡的存储资源是否用尽。存储信息的延迟时间要求小于阈值表明该存储信息需要低延迟，FPGA异构加速卡内部的存储资源的延迟最低，因此，优先将存储信息存储到FPGA异构加速卡内部的存储资源中。
在一些实施方式中，还包括：响应于存储信息的延迟要求不低于阈值，判断与FPGA异构加速卡处于同一个板卡的存储资源是否用尽。响应于与FPGA异构加速卡处于同一个板卡的存储资源用尽，判断服务器端预留给FPGA异构加速卡的存储资源是否用尽。存储信息的延迟要求不低于阈值，表明该存储信息对延迟的要求不高，可以将存储信息优先存储到与FPGA异构加速卡处于同一个板卡的存储资源，这样可以将FPGA异构加速卡内部的存储资源预留给对延迟要求较高的存储信息。
在一些实施方式中，还包括：判断存储资源的使用情况是否发生变化；以及响应于存储资源的使用情况发生变化，更新本卡的存储资源记录信息，并发送给主卡。
如果本卡的存储资源使用完，向主卡申请使用系统闲置存储资源。主卡根据存储记录信息分配给本卡一块闲置的存储资源，存储资源的优先使用级别可以和本卡相同。副卡确认使用主卡分配的闲置存储资源，并且进行系统存储资源记录的更新。
图3示出的是本发明提供的FPGA异构加速卡集群中的资源调度方法的实施例的流程图。如图3所示，从框101开始，接着前进到框102，接收存储信息的请求；接着前进到框103，判断本卡的存储资源是否用尽，如果否，前进到框107结束，如果是，前进到框104，向FPGA异构加速卡集群中的主卡发送存储资源请求；发送资源请求后，接着前进到框105，主卡根据现有存储资源的使用情况分配给本卡存储资源；接着前进到框106，接受主卡分配的其他FPGA异构加速卡的存储资源，并将存储信息存储到主卡分配的存储资源中，然后前进到框107结束。
需要特别指出的是，上述FPGA异构加速卡集群中的资源调度方法的 各个实施例中的各个步骤均可以相互交叉、替换、增加、删减，因此，这些合理的排列组合变换之于FPGA异构加速卡集群中的资源调度方法也应当属于本发明的保护范围，并且不应将本发明的保护范围局限在实施例之上。
基于上述目的，本发明实施例的第二个方面，提出了一种计算机设备，包括：至少一个处理器；以及存储器，存储器存储有可在处理器上运行的计算机指令，指令由处理器执行以实现如下步骤：S1、接收存储信息的请求，并判断本卡的存储资源是否用尽；S2、响应于存储资源用尽，向FPGA异构加速卡集群中的主卡发送存储资源请求；以及S3、接受主卡分配的其他FPGA异构加速卡的存储资源，并将存储信息存储到主卡分配的存储资源中。
在一些实施方式中，本卡的存储资源包括：FPGA异构加速卡内部的存储资源、与FPGA异构加速卡处于同一个板卡的存储资源以及服务器端预留给FPGA异构加速卡的存储资源。
在一些实施方式中，判断本卡的存储资源是否用尽包括：判断存储信息的延迟要求是否低于阈值；以及响应于存储信息的延迟时间要求小于阈值，判断FPGA异构加速卡内部的存储资源是否用尽。
在一些实施方式中，还包括：响应于FPGA异构加速卡内部的存储资源用尽，判断与FPGA异构加速卡处于同一个板卡的存储资源是否用尽。
在一些实施方式中，还包括：响应于与FPGA异构加速卡处于同一个板卡的存储资源用尽，判断服务器端预留给FPGA异构加速卡的存储资源是否用尽。
在一些实施方式中，还包括：响应于存储信息的延迟要求不低于阈值，判断与FPGA异构加速卡处于同一个板卡的存储资源是否用尽。
在一些实施方式中，还包括：响应于与FPGA异构加速卡处于同一个板卡的存储资源用尽，判断服务器端预留给FPGA异构加速卡的存储资源是否用尽。
在一些实施方式中，还包括：判断存储资源的使用情况是否发生变化；以及响应于存储资源的使用情况发生变化，更新本卡的存储资源记录信息， 并发送给主卡。
本发明还提供了一种计算机可读存储介质，计算机可读存储介质存储有被处理器执行时执行如上方法的计算机程序。
最后需要说明的是，本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，可以通过计算机程序来指令相关硬件来完成，FPGA异构加速卡集群中的资源调度方法的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，程序的存储介质可为磁碟、光盘、只读存储记忆体(ROM)或随机存储记忆体(RAM)等。上述计算机程序的实施例，可以达到与之对应的前述任意方法实施例相同或者相类似的效果。
此外，根据本发明实施例公开的方法还可以被实现为由处理器执行的计算机程序，该计算机程序可以存储在计算机可读存储介质中。在该计算机程序被处理器执行时，执行本发明实施例公开的方法中限定的上述功能。
此外，上述方法步骤以及系统单元也可以利用控制器以及用于存储使得控制器实现上述步骤或单元功能的计算机程序的计算机可读存储介质实现。
此外，应该明白的是，本文的计算机可读存储介质(例如，存储器)可以是易失性存储器或非易失性存储器，或者可以包括易失性存储器和非易失性存储器两者。作为例子而非限制性的，非易失性存储器可以包括只读存储器(ROM)、可编程ROM(PROM)、电可编程ROM(EPROM)、电可擦写可编程ROM(EEPROM)或快闪存储器。易失性存储器可以包括随机存取存储器(RAM)，该RAM可以充当外部高速缓存存储器。作为例子而非限制性的，RAM可以以多种形式获得，比如同步RAM(DRAM)、动态RAM(DRAM)、同步DRAM(SDRAM)、双数据速率SDRAM(DDR SDRAM)、增强SDRAM(ESDRAM)、同步链路DRAM(SLDRAM)、以及直接Rambus RAM(DRRAM)。所公开的方面的存储设备意在包括但不限于这些和其它合适类型的存储器。
本领域技术人员还将明白的是，结合这里的公开所描述的各种示例性逻辑块、模块、电路和算法步骤可以被实现为电子硬件、计算机软件或两 者的组合。为了清楚地说明硬件和软件的这种可互换性，已经就各种示意性组件、方块、模块、电路和步骤的功能对其进行了一般性的描述。这种功能是被实现为软件还是被实现为硬件取决于具体应用以及施加给整个系统的设计约束。本领域技术人员可以针对每种具体应用以各种方式来实现的功能，但是这种实现决定不应被解释为导致脱离本发明实施例公开的范围。
结合这里的公开所描述的各种示例性逻辑块、模块和电路可以利用被设计成用于执行这里功能的下列部件来实现或执行：通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现场可编程门阵列(FPGA)或其它可编程逻辑器件、分立门或晶体管逻辑、分立的硬件组件或者这些部件的任何组合。通用处理器可以是微处理器，但是可替换地，处理器可以是任何传统处理器、控制器、微控制器或状态机。处理器也可以被实现为计算设备的组合，例如，DSP和微处理器的组合、多个微处理器、一个或多个微处理器结合DSP和/或任何其它这种配置。
结合这里的公开所描述的方法或算法的步骤可以直接包含在硬件中、由处理器执行的软件模块中或这两者的组合中。软件模块可以驻留在RAM存储器、快闪存储器、ROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬盘、可移动盘、CD-ROM、或本领域已知的任何其它形式的存储介质中。示例性的存储介质被耦合到处理器，使得处理器能够从该存储介质中读取信息或向该存储介质写入信息。在一个替换方案中，存储介质可以与处理器集成在一起。处理器和存储介质可以驻留在ASIC中。ASIC可以驻留在用户终端中。在一个替换方案中，处理器和存储介质可以作为分立组件驻留在用户终端中。
在一个或多个示例性设计中，功能可以在硬件、软件、固件或其任意组合中实现。如果在软件中实现，则可以将功能作为一个或多个指令或代码存储在计算机可读介质上或通过计算机可读介质来传送。计算机可读介质包括计算机存储介质和通信介质，该通信介质包括有助于将计算机程序从一个位置传送到另一个位置的任何介质。存储介质可以是能够被通用或专用计算机访问的任何可用介质。作为例子而非限制性的，该计算机可读 介质可以包括RAM、ROM、EEPROM、CD-ROM或其它光盘存储设备、磁盘存储设备或其它磁性存储设备，或者是可以用于携带或存储形式为指令或数据结构的所需程序代码并且能够被通用或专用计算机或者通用或专用处理器访问的任何其它介质。此外，任何连接都可以适当地称为计算机可读介质。例如，如果使用同轴线缆、光纤线缆、双绞线、数字用户线路(DSL)或诸如红外线、无线电和微波的无线技术来从网站、服务器或其它远程源发送软件，则上述同轴线缆、光纤线缆、双绞线、DSL或诸如红外线、无线电和微波的无线技术均包括在介质的定义。如这里所使用的，磁盘和光盘包括压缩盘(CD)、激光盘、光盘、数字多功能盘(DVD)、软盘、蓝光盘，其中磁盘通常磁性地再现数据，而光盘利用激光光学地再现数据。上述内容的组合也应当包括在计算机可读介质的范围内。
以上是本发明公开的示例性实施例，但是应当注意，在不背离权利要求限定的本发明实施例公开的范围的前提下，可以进行多种改变和修改。根据这里描述的公开实施例的方法权利要求的功能、步骤和/或动作不需以任何特定顺序执行。此外，尽管本发明实施例公开的元素可以以个体形式描述或要求，但除非明确限制为单数，也可以理解为多个。
应当理解的是，在本文中使用的，除非上下文清楚地支持例外情况，单数形式“一个”旨在也包括复数形式。还应当理解的是，在本文中使用的“和/或”是指包括一个或者一个以上相关联地列出的项目的任意和所有可能组合。
上述本发明实施例公开实施例序号仅仅为了描述，不代表实施例的优劣。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
所属领域的普通技术人员应当理解：以上任何实施例的讨论仅为示例性的，并非旨在暗示本发明实施例公开的范围(包括权利要求)被限于这些例子；在本发明实施例的思路下，以上实施例或者不同实施例中的技术 特征之间也可以进行组合，并存在如上的本发明实施例的不同方面的许多其它变化，为了简明它们没有在细节中提供。因此，凡在本发明实施例的精神和原则之内，所做的任何省略、修改、等同替换、改进等，均应包含在本发明实施例的保护范围之内。

Claims (10)

  1. 一种FPGA异构加速卡集群中的资源调度方法，其特征在于，包括：
    接收存储信息的请求，并判断本卡的存储资源是否用尽；
    响应于本卡的存储资源用尽，向FPGA异构加速卡集群中的主卡发送存储资源请求；以及
    接受所述主卡分配的其他FPGA异构加速卡的存储资源，并将所述存储信息存储到所述主卡分配的存储资源中。
  2. 根据权利要求1所述的资源调度方法，其特征在于，本卡的存储资源包括：
    FPGA异构加速卡内部的存储资源、与所述FPGA异构加速卡处于同一个板卡的存储资源以及服务器端预留给所述FPGA异构加速卡的存储资源。
  3. 根据权利要求2所述的资源调度方法，其特征在于，所述判断本卡的存储资源是否用尽包括：
    判断所述存储信息的延迟时间要求是否小于阈值；以及
    响应于所述存储信息的延迟时间要求小于阈值，判断所述FPGA异构加速卡内部的存储资源是否用尽。
  4. 根据权利要求3所述的资源调度方法，其特征在于，还包括：
    响应于所述FPGA异构加速卡内部的存储资源用尽，判断与所述FPGA异构加速卡处于同一个板卡的存储资源是否用尽。
  5. 根据权利要求4所述的资源调度方法，其特征在于，还包括：
    响应于与所述FPGA异构加速卡处于同一个板卡的存储资源用尽，判断服务器端预留给所述FPGA异构加速卡的存储资源是否用尽。
  6. 根据权利要求3所述的资源调度方法，其特征在于，还包括：
    响应于所述存储信息的延迟要求不低于阈值，判断与所述FPGA异构加速卡处于同一个板卡的存储资源是否用尽。
  7. 根据权利要求6所述的资源调度方法，其特征在于，还包括：
    响应于与所述FPGA异构加速卡处于同一个板卡的存储资源用尽，判断服务器端预留给所述FPGA异构加速卡的存储资源是否用尽。
  8. 根据权利要求1所述的资源调度方法，其特征在于，还包括：
    判断存储资源的使用情况是否发生变化；以及
    响应于所述存储资源的使用情况发生变化，更新本卡的存储资源记录信息，并发送给所述主卡。
  9. 一种计算机设备，其特征在于，包括：
    至少一个存储器；以及
    存储器，所述存储器存储有可在所述处理器上运行的计算机指令，所述指令由所述处理器执行时实现如下步骤：
    接收存储信息的请求，并判断本卡的存储资源是否用尽；
    响应于存储资源用尽，向FPGA异构加速卡集群中的主卡发送存储资源请求；以及
    接受所述主卡分配的其他FPGA异构加速卡的存储资源，并将所述存储信息存储到所述主卡分配的存储资源中。
  10. 一种计算机可读存储介质，所述计算机可读存储介质存储有计算机程序，其特征在于，所述计算机程序被处理器执行时实现权利要求1-8任意一项所述方法的步骤。
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