WO2017031637A1 - 一种内存访问方法、装置和系统 - Google Patents

一种内存访问方法、装置和系统 Download PDF

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Publication number
WO2017031637A1
WO2017031637A1 PCT/CN2015/087817 CN2015087817W WO2017031637A1 WO 2017031637 A1 WO2017031637 A1 WO 2017031637A1 CN 2015087817 W CN2015087817 W CN 2015087817W WO 2017031637 A1 WO2017031637 A1 WO 2017031637A1
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Prior art keywords
memory
remote
cache
accessed
memory device
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PCT/CN2015/087817
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English (en)
French (fr)
Inventor
罗达新
李刚
潘顺成
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2015/087817 priority Critical patent/WO2017031637A1/zh
Priority to EP15901909.0A priority patent/EP3321809B1/en
Priority to CN201580001217.7A priority patent/CN107408071A/zh
Publication of WO2017031637A1 publication Critical patent/WO2017031637A1/zh
Priority to US15/899,941 priority patent/US20180173639A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0871—Allocation or management of cache space
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1008—Correctness of operation, e.g. memory ordering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/15—Use in a specific computing environment
    • G06F2212/154—Networked environment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/16—General purpose computing application
    • G06F2212/163—Server or database system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/31—Providing disk cache in a specific location of a storage system
    • G06F2212/313—In storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/608—Details relating to cache mapping

Definitions

  • the present invention relates to the field of computer technologies, and in particular, to a memory access method, apparatus, and system.
  • the system is generally equipped with local memory devices and remote memory devices.
  • a CPU Central Processing Unit
  • a remote memory device is greater than an access rate to a remote memory device.
  • the entire storage space of the local memory device is generally used as a cache of the remote memory device.
  • the memory access method is: when the local memory device includes the memory area to be accessed, the local memory device is accessed; otherwise, the remote memory device is accessed.
  • the above memory access method brings the following problem: the storage space of the local memory device cannot be fully utilized, resulting in poor overall performance of the system.
  • Embodiments of the present invention provide a memory access method, apparatus, and system for rationally utilizing a storage space of a local memory device, thereby improving overall performance of the system.
  • the first aspect provides a memory access method, which is applied to a computer system, where the memory device of the computer system includes a local memory device and a remote memory device; the method includes:
  • the local memory device When the memory area to be accessed is in the local memory, perform an access operation on the to-be-accessed memory area according to the memory access request; wherein the local memory device includes a local memory and a remote cache, and the remote cache Used as a cache for the remote memory device;
  • the remote cache When the memory area to be accessed is in the remote memory device, and the remote cache includes a cache block corresponding to the to-be-accessed memory area, corresponding to the memory area to be accessed according to the memory access request
  • the cache block performs access operations.
  • the method further includes:
  • the memory area to be accessed is in the remote memory device, and the cache buffer does not include the cache block corresponding to the memory area to be accessed, the memory area to be accessed is performed according to the memory access request. Access operation.
  • the method further includes:
  • the memory access request is a memory write request; the method further includes:
  • the remote cache When the to-be-accessed memory area is in the remote memory device, and the remote cache does not include a cache block corresponding to the to-be-accessed memory area, creating a memory area to be accessed in the remote cache Corresponding cache block, and writing data of the memory write request to a cache block corresponding to the to-be-accessed memory area.
  • the method before receiving the memory access request, the method further includes:
  • the determining, by the local memory device, the local memory and the capacity of the remote cache including:
  • a capacity of the remote cache in the local memory device Determining, according to a capacity of the remote memory device and a preset hit ratio, a capacity of the remote cache in the local memory device; wherein a capacity of the remote cache is respectively related to a capacity of the remote memory device and the pre- Set the hit rate into a positive correlation;
  • the remaining portion of the local memory device is taken as the capacity of the local memory.
  • the method further includes:
  • the first threshold is smaller than the second threshold.
  • a memory access device for use in a computer system, the memory device of the computer system includes a local memory device and a remote memory device; and the memory access device includes:
  • a receiving unit configured to receive a memory access request, where the memory access request carries address information of a memory area to be accessed;
  • a determining unit configured to determine, according to the address information, a memory area to be accessed indicated by the address information
  • An access unit configured to perform an access operation on the to-be-accessed memory area according to the memory access request when the to-be-accessed memory area is in the local memory, where the local memory device includes a local memory and a remote cache
  • the remote cache is used as a cache of the remote memory device; when the memory area to be accessed is in the remote memory device, and the remote cache includes a cache block corresponding to the memory area to be accessed, And performing an access operation on the cache block corresponding to the to-be-accessed memory area according to the memory access request.
  • the access unit is further configured to: when the to-be-accessed memory area is in the remote memory device, and the remote cache does not include the When accessing the cache block corresponding to the memory area, the access operation is performed on the to-be-accessed memory area according to the memory access request.
  • the access unit is further configured to:
  • the memory access request is a memory write request
  • the access unit is further configured to: when the memory area to be accessed is in the remote memory device, When a cache block corresponding to the to-be-accessed memory area is not included in the remote cache, a cache block corresponding to the to-be-accessed memory area is created in the remote cache, and data of the memory write request is written and The cache block corresponding to the to-be-accessed memory area.
  • the determining unit is further configured to: Determining the local memory and the remote cache in a memory device Capacity
  • the memory access device further includes: an allocating unit, configured to allocate a memory address for the local memory and the remote memory device.
  • the determining unit when determining the capacity of the local memory and the remote cache in the local memory device, specifically Used for:
  • a capacity of the remote cache in the local memory device Determining, according to a capacity of the remote memory device and a preset hit ratio, a capacity of the remote cache in the local memory device; wherein a capacity of the remote cache is respectively related to a capacity of the remote memory device and the pre- Set the hit rate into a positive correlation;
  • the remaining portion of the local memory device is taken as the capacity of the local memory.
  • the memory access device further includes:
  • a statistical unit configured to count, according to a preset period T, a hit ratio of the remote cache
  • the adjusting unit is configured to dynamically increase the capacity of the remote cache when the hit ratio of the remote cache is less than a preset first threshold; and dynamically decrease when the hit ratio of the remote cache is greater than a preset second threshold The capacity of the remote cache is small; wherein the first threshold is less than the second threshold.
  • the third aspect provides a memory access system, including: a local memory device, a remote memory device, and any of the memory access devices provided in the second aspect; wherein the local memory device includes a local memory and a remote cache.
  • the remote cache is used as a cache for the remote memory device.
  • the above technical solution is to use a part of the local memory device as a remote cache, and another part as a local memory, and when the memory area to be accessed is in the local memory, access the memory area according to the memory access request; in the memory area to be accessed
  • the access operation is performed according to the memory access request to access the cache block corresponding to the memory area.
  • the entire memory space of the local memory is directly used as a remote cache, and the local memory device is accessed when the local memory device includes the memory area to be accessed; otherwise, the access operation operation on the remote memory device is performed. Compared with the scheme, it can effectively improve the utilization of local memory devices.
  • the capacity of the local memory device is greater than the capacity of the cache (ie, remote cache) required by the remote memory device, some of the storage space in the local memory device can be used as a remote cache, and other storage spaces in the local memory device can be used as Local memory, so that by properly setting the capacity of the remote cache, the purpose of effectively utilizing the storage space of the local memory device can be achieved, thereby improving the overall performance of the system.
  • the cache ie, remote cache
  • FIG. 1 is a schematic diagram of a system architecture of an electrical interconnection local memory device and an optical interconnection remote memory device provided by the prior art
  • FIG. 2 is a schematic structural diagram of a system architecture applicable to a technical solution provided by an embodiment of the present invention
  • FIG. 3 is a schematic flowchart of a memory access method according to an embodiment of the present disclosure
  • FIG. 4 is a schematic flowchart diagram of another memory access method according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a memory access device according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of another memory access device according to an embodiment of the present invention.
  • Local memory device refers to a memory device that is directly mounted on the system bus.
  • the connection between the local memory device and the system bus is an electrical connection.
  • the local memory device is on the same printed circuit board as the CPU.
  • a part of the storage space of the local memory device is used as a cache of the remote memory device, that is, for storing data in the remote memory device (ie, remote data), and the part of the storage space is “remote cache”; Another part of the memory device is used to store local data, and the other part of the storage space is "local memory.”
  • Local memory and “remote cache” can be on the same local memory device or on different local memory devices.
  • Remote memory device refers to a memory device that is mounted indirectly on the system bus.
  • the remote memory device is a memory device connected to the system bus by optical interconnection such as optical fiber or optical waveguide.
  • the remote memory device is connected to the system bus through an optical fiber as an example for description.
  • the remote memory device and the CPU are located on different printed circuit boards, and the communication delay between the remote memory device and the CPU is greater than the communication delay between the local memory device and the CPU.
  • FIG. 1 is a schematic diagram of a system architecture of an electrical interconnection local memory device and an optical interconnection remote memory device provided in the prior art.
  • FIG. 1 includes a CPU board and a memory board, wherein the CPU board and the memory board are connected by an optical fiber.
  • the CPU board includes a CPU, a local memory device, a processing module 1 and other common computer hardware modules not shown.
  • the memory board includes remote memory devices, processing modules 2, and other common computer hardware modules not shown.
  • the processing module 1 and the processing module 2 are used to implement conversion between an electrical signal and an optical signal, conversion of a transmission protocol, and the like.
  • FIG. 2 is a schematic structural diagram of a system architecture to which the technical solution provided by the embodiment of the present invention is applied.
  • the local memory device and the remote memory device in FIG. 2 are connected to the same interface through the address management module.
  • the address management module can be integrated with the memory controller or can be set independently; the interface can be an interface integrated with the memory controller or a custom interface.
  • the address management module performs unified management on the local memory device and the remote memory device through the interface (for example, unified addressing, unified debugging, etc.); the CPU accesses the local memory device and the remote memory device through the interface.
  • FIG. 3 is a schematic flowchart diagram of a memory access method according to an embodiment of the present invention.
  • the method shown in FIG. 3 is applied to a computer system.
  • the memory device of the computer system includes a local memory device and a remote memory device, wherein the local memory device includes local memory and a remote cache, and the remote cache is used as a cache of the remote memory device.
  • the method shown in FIG. 3 includes the following steps S301-S303:
  • S301 Receive a memory access request, where the memory access request carries address information of a memory area to be accessed.
  • the execution body of the memory access method provided by the embodiment of the present invention may be the address management module in FIG. 2, and the address management module may be integrated with the memory controller or may be independently set.
  • the "to-access memory address" can be included in local memory or a remote memory device.
  • the address information of the memory area to be accessed may be a virtual address of the memory area to be accessed. It can also be the physical address of the memory area to be accessed; it can also be any other information that can represent the virtual address or physical address of the memory area to be accessed.
  • step S301 can be implemented as follows: the address management module receives a memory access request sent by the CPU, where the memory access request carries the virtual address of the memory area to be accessed. .
  • step S301 can be implemented as follows: the address management module receives the memory access request sent by the memory controller, where the memory access request carries the physical address of the memory area to be accessed.
  • the "memory access request" may specifically be a memory read request or a memory write request.
  • the memory access request may further carry data to be written, that is, data of the memory write request.
  • S302 Determine, according to the address information, a memory area to be accessed indicated by the address information.
  • the physical address of the memory area to be accessed is determined, thereby determining the memory area to be accessed.
  • the address management module can determine whether the physical area to be accessed is the address of the local memory or the address of the remote memory device, thereby determining whether the memory area to be accessed is in the local memory or in the remote memory device.
  • the address management module reads data from the memory area to be accessed; when the memory area to be accessed is in the remote memory device and in the remote cache When the cache block corresponding to the memory area to be accessed is included, the address management module reads data from the cache block corresponding to the memory area to be accessed.
  • the address management module when the memory area to be accessed is in the local memory, the address management module writes the data of the memory write request to the memory area to be accessed; when the memory area to be accessed is in the remote memory device, and
  • the remote cache includes a cache block corresponding to the memory area to be accessed, and the address management module writes the data of the memory write request to the cache block corresponding to the memory area to be accessed; subsequently, the data in the memory area to be accessed is updated to the memory write. Requested data.
  • the memory access method provided by the embodiment of the present invention implements memory access by using a part of the local memory device as a remote cache and another part as a local memory.
  • the entire memory space of the local memory is directly used as a remote cache, thereby realizing the utilization of the local memory device.
  • the capacity of the local memory device is greater than the capacity of the cache (ie, remote cache) required by the remote memory device, some of the storage space in the local memory device can be used as a remote cache, and other storage spaces in the local memory device can be used as Local memory, so that by properly setting the capacity of the remote cache, the purpose of effectively utilizing the storage space of the local memory device can be achieved, thereby improving the overall performance of the system.
  • the method may further include: when the memory area to be accessed is in the remote memory device, and the cache block corresponding to the to-be-accessed memory area is not included in the remote cache, the access is treated according to the memory access request.
  • the memory area is accessed.
  • the address management module accesses the memory area to be accessed. Reading data; if the memory access request is a memory write request, the address management module writes the data of the memory write request into the memory area to be accessed.
  • the method may further include: creating a cache block corresponding to the to-be-accessed memory area in the remote cache; and writing data in the to-be-accessed memory area to the cache block corresponding to the to-be-accessed memory area.
  • the address management module may also create a cache block corresponding to the memory area to be accessed in the remote cache. And write the data of the memory write request to the cache block corresponding to the memory area to be accessed.
  • the method may further include the following steps A)-B):
  • the step A) may specifically include: determining a capacity of the remote cache in the local memory device according to the capacity of the remote memory device and the preset hit ratio; wherein the capacity of the remote cache is positively correlated with the capacity of the remote memory device and the preset hit ratio respectively. Relationship; and the remaining portion of the local memory device is taken as the capacity of the local memory.
  • the preset hit ratio is preset.
  • the specific value of the preset hit ratio and the manner in which the specific value is obtained are not limited.
  • the preset hit ratio may be: the ratio of the capacity of the L1 cache in the CPU cache to the capacity of the L2 cache, or the ratio of the capacity of the L2 cache to the capacity of the L3 cache; or A value determined by the requirements in the specific application scenario, and so on.
  • the capacity of the remote cache the capacity of the remote memory device * the default hit ratio.
  • the step A) may include: determining the remote cache according to the capacity of the remote memory device, the preset hit ratio, and combining one or more of the capacity of the local memory device, the transmission path delay, and the experience value. Capacity.
  • the method may further include: recording an address range of the local memory and an address range of the remote memory device; wherein the “address range” includes a start address and a stop address.
  • the “address range” includes a start address and a stop address.
  • four registers are set in the system, The start address of the local memory, the termination address of the local memory, the start address of the remote memory device, and the termination address of the remote memory device are respectively recorded in the four registers.
  • FIG. 4 is a schematic flowchart diagram of a memory access method according to an embodiment of the present invention. The method shown in FIG. 4 includes the following steps S401-S413:
  • S401 Determine a preset hit ratio, a capacity of a local memory device, and a capacity of a remote memory device.
  • the ratio of the ratio of the capacity of the level 1 cache in the CPU cache to the capacity of the level 2 cache is used as an example.
  • the capacity of the L1 cache, the capacity of the L2 cache, the capacity of the local memory device, and the capacity of the remote memory device are determined when the system is set up.
  • the capacity Cl of the local memory device is 2G
  • the capacity Cr of the remote memory device is 8G.
  • S402 The product of the capacity of the remote memory device and the preset hit ratio is used as the initial capacity of the remote cache.
  • step S403 Determine whether the initial capacity of the remote cache is less than or equal to the capacity of the local memory device. If yes, go to step S404: If no, go to step S405.
  • S404 The initial capacity of the remote cache is used as the capacity of the remote cache, and the capacity of the local memory is determined.
  • the capacity of the remote cache determined after performing step S404 is 1G
  • S405 Use the capacity of the local memory device as the capacity of the remote cache, and determine the capacity of the local memory.
  • the capacity of the local memory device Cl is 8G
  • the capacity of the remote memory device The amount of Cr is 128G
  • the capacity of the remote cache determined after performing step S405 is 8G
  • the capacity of the remote cache may be re-determined.
  • step S405 the entire storage space of the local memory device is used as the remote cache in step S405
  • the present embodiment is based on performing steps S401-S403 and satisfying certain conditions (ie, the determination of step S403).
  • the result is "No"
  • the entire storage space of the local memory device is used as the remote cache; whereas the prior art does not perform any operation, and directly uses the entire storage space of the local memory device as the remote cache. There is an essential difference between the two.
  • S406 Allocating a memory address for the local memory and the remote memory device, and configuring a Memory Address Assigned Table (MAAT); wherein the configured memory address allocation table includes four registers, wherein the four registers are used to record the local memory. The starting address, the ending address of the local memory, the starting address of the remote memory device, and the ending address of the remote memory device.
  • MAAT Memory Address Assigned Table
  • the address of the memory with a total capacity of 9G is [0x0000 00000000, 0x0000 0002 3FFF FFFF]
  • the address of the local memory can be [0x0000 0000 0000, 0x0000 0000 3FFF FFFF]
  • the address of the remote memory device can be [0x0000 0000 4000 0000, 0x0000 0002 3FFF FFFF].
  • S407 Receive a memory access request, where the memory access request carries address information of the memory area to be accessed.
  • S408 Determine, according to the address information, a memory area to be accessed indicated by the address information.
  • step S409 Determine, according to the memory address allocation table, whether the memory area to be accessed is in the local memory or in the remote memory device. If it is in the local memory, step S410 is performed; if it is in the remote memory device, step S411 is performed.
  • step S406 if 0x0000 0000 0000 0000 ⁇ the physical address of the memory area to be accessed ⁇ 0x0000 0000 3FFF FFFF, the memory area to be accessed is in the local memory; if 0x0000 0000 4000 0000 ⁇ the physical address of the memory area to be accessed ⁇ 0x0000 0002 3FFF FFFF, the memory area to be accessed is in the remote memory device.
  • S410 Perform an access operation on the memory area to be accessed according to the memory access request.
  • S411 Determine whether the cache buffer corresponding to the to-be-accessed memory area is included in the remote cache.
  • step S412 is performed; if not, the cache miss is performed, then step S413 is performed.
  • S412 Perform an access operation on the cache block corresponding to the memory area to be accessed according to the memory access request.
  • S413 Perform an access operation on the access memory area according to the memory access request, and create a cache block corresponding to the to-be-accessed memory area in the remote cache, and then write the data in the to-be-accessed memory area to the cache block corresponding to the to-be-accessed memory area.
  • the method further includes: counting a hit ratio of the remote cache according to a preset period T; and dynamically increasing the remote cache when the hit ratio of the remote cache is less than a preset first threshold. Capacity; when the hit ratio of the remote cache is greater than a preset second threshold, dynamically reducing the capacity of the remote cache; wherein the first threshold is less than the second threshold.
  • the "hide cache hit rate” refers to the ratio of the actual number of times the remote cache is accessed to the total number of accesses to the memory in the preset period T.
  • the specific values of the preset period T, the first threshold, and the second threshold, and the manner in which the values are obtained are not limited.
  • the first threshold may be 90% and the second threshold may be 100%; for example, the first threshold may be 80%, the second threshold may be 90%, and the like.
  • the capacity of the remote cache is dynamically adjusted is not limited in the embodiment of the present invention.
  • the capacity of the remote cache may be incrementally increased or decreased according to a certain value.
  • the optional implementation calculates the hit ratio of the remote cache according to the preset period T, and adjusts the capacity of the remote cache when certain conditions are met; thus, the remote cache obtained after the adjustment can be made by one or more adjustments.
  • the hit rate of the remote cache is greater than or equal to the first threshold and less than or equal to the second threshold; since the first threshold and the second threshold are generally determined according to characteristics such as overall system performance, the optional The implementation can improve system performance.
  • FIG. 5 is a schematic structural diagram of a memory access device according to an embodiment of the present invention.
  • the memory access device 5 shown in FIG. 5 is used to execute any of the memory access methods provided above.
  • the memory access device 5 is applied to a computer system.
  • the memory device of the computer system includes a local memory device and a remote memory device.
  • the local memory device includes a local memory and a remote cache, and the remote cache is used as a cache of the remote memory device.
  • the memory access device 5 includes a receiving unit 51, a determining unit 52, and an access unit 53.
  • the receiving unit 51 is configured to receive a memory access request, where the memory access request carries address information of a memory area to be accessed.
  • the determining unit 52 is configured to determine, according to the address information, a memory area to be accessed indicated by the address information.
  • the access unit 53 is configured to perform an access operation on the access memory area according to the memory access request when the memory area to be accessed is in the local memory, wherein the local memory device includes a local memory and a remote cache, and the remote cache is used as a cache of the remote memory device; When the memory area to be accessed is in the remote memory device, and the cache block corresponding to the memory area to be accessed is included in the remote cache, the access operation is performed on the cache block corresponding to the memory area to be accessed according to the memory access request.
  • the access unit 53 is further configured to: when the memory to be accessed When the area is in the remote memory device and the remote cache does not contain the cache block corresponding to the memory area to be accessed, the access operation is performed according to the memory access request.
  • the access unit 53 is further configured to: create a cache block corresponding to the memory area to be accessed in the remote cache, and write data in the memory area to be accessed to the memory to be accessed.
  • the cache block corresponding to the area is further configured to: create a cache block corresponding to the memory area to be accessed in the remote cache, and write data in the memory area to be accessed to the memory to be accessed.
  • the cache block corresponding to the area is further configured to: create a cache block corresponding to the memory area to be accessed in the remote cache, and write data in the memory area to be accessed to the memory to be accessed.
  • the memory access request is a memory write request; the access unit 53 is further configured to: when the memory area to be accessed is in the remote memory device, and the remote cache does not include the memory area corresponding to the to-be-accessed memory area When the block is cached, a cache block corresponding to the memory area to be accessed is created in the remote cache, and the data of the memory write request is written into the cache block corresponding to the memory area to be accessed.
  • the determining unit 52 is further configured to: determine a local memory and a capacity of the remote cache in the local memory device; in this case, as shown in FIG. 6, the memory access device 5 can also The method includes an allocating unit 54 for allocating memory addresses for local memory and remote memory devices.
  • the determining unit 52 when determining the capacity of the local memory and the remote cache in the local memory device, is specifically configured to determine the capacity of the remote cache in the local memory device according to the capacity of the remote memory device and the preset hit ratio; The capacity of the remote cache is positively correlated with the capacity of the remote memory device and the preset hit ratio; the remaining portion of the local memory device is used as the capacity of the local memory.
  • the memory access device 5 may further include: a statistics unit 55 and an adjustment unit 56.
  • the statistics unit 55 is configured to collect the remote cache according to a preset period T.
  • the hit unit is configured to dynamically increase the capacity of the remote cache when the hit ratio of the remote cache is less than a preset first threshold; and dynamically reduce the remote cache when the hit ratio of the remote cache is greater than a preset second threshold. The capacity; wherein the first threshold is less than the second threshold.
  • the memory access device 5 can be integrated with the memory controller or set independently to the memory controller.
  • the phase in the memory access device 5 provided by this embodiment For the explanation of the related content, reference may be made to the method embodiment provided above, and details are not described herein again.
  • the memory access device provided in this embodiment implements memory access by using a part of the local memory device as a remote cache and another part as a local memory.
  • the entire memory space of the local memory is directly used as a remote cache, thereby realizing the utilization of the local memory device.
  • the capacity of the local memory device is greater than the capacity of the cache (ie, remote cache) required by the remote memory device, some of the storage space in the local memory device can be used as a remote cache, and other storage spaces in the local memory device can be used as Local memory, so that by properly setting the capacity of the remote cache, the purpose of effectively utilizing the storage space of the local memory device can be achieved, thereby improving the overall performance of the system.
  • an embodiment of the present invention further provides a memory controller, which includes any of the memory access devices 5 provided above.
  • the embodiment of the present invention further provides a memory access system, including: a local memory device, a remote memory device, and any of the memory access devices 5 provided above; wherein the local memory device includes Local memory and remote cache, which acts as a cache for the remote memory device.
  • the disclosed system, apparatus, and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit. It can be electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may be physically included separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the above-described integrated unit implemented in the form of a software functional unit can be stored in a computer readable storage medium.
  • the software functional units described above are stored in a storage medium and include instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform portions of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a ROM (Read-Only Memory), a RAM (Random Access Memory), a disk or an optical disk, and the like, which can store program codes. .

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Abstract

一种内存访问方法、装置和系统，涉及计算机技术领域，用以合理利用本地内存设备的存储空间，从而提升系统的整体性能。该方法应用于包含本地内存设备和远程内存设备的系统。该方法包括：接收携带待访问内存区域的地址信息的内存访问请求（S301）；确定该地址信息指示的待访问内存区域（S302）；当待访问内存区域在本地内存中时，根据内存访问请求对待访问内存区域进行访问操作；其中，本地内存设备包括本地内存和远程缓存；当待访问内存区域在远程内存设备中、且远程缓存中包含与待访问内存区域对应的缓存块时，根据内存访问请求对该缓存块进行访问操作（S303）。

Description

一种内存访问方法、装置和系统 技术领域
本发明涉及计算机技术领域，尤其涉及一种内存访问方法、装置和系统。
背景技术
在大数据环境中，基于扩充内存容量的考虑，系统一般设置有本地内存设备和远程内存设备。一般地，CPU(Central Processing Unit，中央处理器)对本地内存设备的访问速率大于对远程内存设备的访问速率。基于此，为了提高系统的整体访问效率，一般将本地内存设备的全部存储空间作为远程内存设备的缓存。这样，内存访问方法为：当本地内存设备中包含待访问内存区域时，对本地内存设备进行访问操作；否则，对远程内存设备进行访问操作。
当本地内存设备的容量大于远程内存设备所需的缓存的容量时，上述内存访问方法会带来如下问题：本地内存设备的存储空间不能被充分利用，导致系统的整体性能较差。
发明内容
本发明的实施例提供一种内存访问方法、装置和系统，用以合理利用本地内存设备的存储空间，从而提升系统的整体性能。
为达到上述目的，本发明的实施例采用如下技术方案：
第一方面，提供一种内存访问方法，应用于计算机系统，所述计算机系统的内存设备包含本地内存设备和远程内存设备；所述方法包括：
接收内存访问请求；其中，所述内存访问请求中携带待访问内存区域的地址信息；
根据所述地址信息，确定所述地址信息指示的待访问内存区域；
当所述待访问内存区域在所述本地内存中时，根据所述内存访问请求对所述待访问内存区域进行访问操作；其中，所述本地内存设备包括本地内存和远程缓存，所述远程缓存用作所述远程内存设备的缓存；
当所述待访问内存区域在所述远程内存设备中、且所述远程缓存中包含与所述待访问内存区域对应的缓存块时，根据所述内存访问请求对所述待访问内存区域对应的缓存块进行访问操作。
结合第一方面，在第一种可能的实现方式中，所述方法还包括：
当所述待访问内存区域在所述远程内存设备中、且所述远程缓存中不包含与所述待访问内存区域对应的缓存块时，根据所述内存访问请求对所述待访问内存区域进行访问操作。
结合第一方面的第一种可能的实现方式，在第二种可能的实现方式中，所述方法还包括：
在所述远程缓存中创建与所述待访问内存区域对应的缓存块；
将所述待访问内存区域中的数据写入与所述待访问内存区域对应的缓存块。
结合第一方面，在第三种可能的实现方式中，所述内存访问请求为内存写请求；所述方法还包括：
当所述待访问内存区域在所述远程内存设备中、且所述远程缓存中不包含与所述待访问内存区域对应的缓存块时，在所述远程缓存中创建与所述待访问内存区域对应的缓存块，并将所述内存写请求的数据写入与所述待访问内存区域对应的缓存块。
结合第一方面，第一方面的第一种可能的实现方式至第三种可 能的实现方式任一种，在第四种可能的实现方式中，在接收内存访问请求之前，所述方法还包括：
在所述本地内存设备中确定所述本地内存和所述远程缓存的容量；
为所述本地内存和所述远程内存设备分配内存地址。
结合第一方面的第四种可能的实现方式，在第五种可能的实现方式中，所述在所述本地内存设备中确定所述本地内存和所述远程缓存的容量，包括：
根据所述远程内存设备的容量和预设命中率，在所述本地内存设备中确定所述远程缓存的容量；其中，所述远程缓存的容量分别与所述远程内存设备的容量和所述预设命中率成正相关关系；
将所述本地内存设备的剩余部分大小作为所述本地内存的容量。
结合第一方面，第一方面的第一种可能的实现方式至第五种可能的实现方式任一种，在第六种可能的实现方式中，所述方法还包括：
按照预设的周期T统计所述远程缓存的命中率；
当所述远程缓存的命中率小于预设的第一阈值时，动态增加所述远程缓存的容量；
当所述远程缓存的命中率大于预设的第二阈值时，动态减小所述远程缓存的容量；
其中，所述第一阈值小于所述第二阈值。
第二方面，提供一种内存访问装置，应用于计算机系统，所述计算机系统的内存设备包含本地内存设备和远程内存设备；所述内存访问装置包括：
接收单元，用于接收内存访问请求；其中，所述内存访问请求中携带待访问内存区域的地址信息；
确定单元，用于根据所述地址信息，确定所述地址信息指示的待访问内存区域；
访问单元，用于当所述待访问内存区域在所述本地内存中时，根据所述内存访问请求对所述待访问内存区域进行访问操作，其中，所述本地内存设备包括本地内存和远程缓存，所述远程缓存用作所述远程内存设备的缓存；当所述待访问内存区域在所述远程内存设备中、且所述远程缓存中包含与所述待访问内存区域对应的缓存块时，根据所述内存访问请求对所述待访问内存区域对应的缓存块进行访问操作。
结合第二方面，在第一种可能的实现方式中，所述访问单元还用于：当所述待访问内存区域在所述远程内存设备中、且所述远程缓存中不包含与所述待访问内存区域对应的缓存块时，根据所述内存访问请求对所述待访问内存区域进行访问操作。
结合第二方面的第一种可能的实现方式，在第二种可能的实现方式中，所述访问单元还用于：
在所述远程缓存中创建与所述待访问内存区域对应的缓存块；
将所述待访问内存区域中的数据写入与所述待访问内存区域对应的缓存块。
结合第二方面，在第三种可能的实现方式中，所述内存访问请求为内存写请求；所述访问单元还用于：当所述待访问内存区域在所述远程内存设备中、且所述远程缓存中不包含与所述待访问内存区域对应的缓存块时，在所述远程缓存中创建与所述待访问内存区域对应的缓存块，并将所述内存写请求的数据写入与所述待访问内存区域对应的缓存块。
结合第二方面，第二方面的第一种可能的实现方式至第三种可能的实现方式任一种，在第四种可能的实现方式中，所述确定单元还用于：在所述本地内存设备中确定所述本地内存和所述远程缓存 的容量；
所述内存访问装置还包括：分配单元，用于为所述本地内存和所述远程内存设备分配内存地址。
结合第二方面的第四种可能的实现方式，在第五种可能的实现方式中，所述确定单元执行在所述本地内存设备中确定所述本地内存和所述远程缓存的容量时，具体用于：
根据所述远程内存设备的容量和预设命中率，在所述本地内存设备中确定所述远程缓存的容量；其中，所述远程缓存的容量分别与所述远程内存设备的容量和所述预设命中率成正相关关系；
将所述本地内存设备的剩余部分大小作为所述本地内存的容量。
结合第二方面，第二方面的第一种可能的实现方式至第五种可能的实现方式任一种，在第六种可能的实现方式中，所述内存访问装置还包括：
统计单元，用于按照预设的周期T统计所述远程缓存的命中率；
调整单元，用于当所述远程缓存的命中率小于预设的第一阈值时，动态增加所述远程缓存的容量；当所述远程缓存的命中率大于预设的第二阈值时，动态减小所述远程缓存的容量；其中，所述第一阈值小于所述第二阈值。
第三方面，提供一种内存访问系统，包括：本地内存设备、远程内存设备，以及上述第二方面提供的任一种内存访问装置；其中，所述本地内存设备包括本地内存和远程缓存，所述远程缓存用作所述远程内存设备的缓存。
上述技术方案，通过将本地内存设备的一部分作为远程缓存，另一部分作为本地内存，并在待访问内存区域在本地内存中时，根据内存访问请求对待访问内存区域进行访问操作；在待访问内存区 域在远程内存设备中、且远程缓存中包含与待访问内存区域对应的缓存块时，根据内存访问请求对待访问内存区域对应的缓存块进行访问操作。与现有技术中直接将本地内存的全部存储空间均作为远程缓存，并在本地内存设备中包含待访问内存区域时，对本地内存设备进行访问操作；否则，对远程内存设备进行访问操作的技术方案相比，能够有效地提高本地内存设备的利用率。例如，当本地内存设备的容量大于远程内存设备所需的缓存(即远程缓存)的容量时，可以将本地内存设备中的部分存储空间作为远程缓存，并将本地内存设备中的其他存储空间作为本地内存，这样通过合理地设置远程缓存的容量，可以达到有效地利用本地内存设备的存储空间的目的，从而提高系统的整体性能。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术提供的一种电互连本地内存设备和光互连远程内存设备的系统架构示意图；
图2为本发明实施例提供的技术方案所适用的一种系统架构的结构示意图；
图3为本发明实施例提供的一种内存访问方法的流程示意图；
图4为本发明实施例提供的另一种内存访问方法的流程示意图；
图5为本发明实施例提供的一种内存访问装置的结构示意图；
图6为本发明实施例提供的另一种内存访问装置的结构示意 图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行示例性地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
首先，对本文中涉及的部分术语进行解释说明：
1)本地内存设备、远程缓存与本地内存
“本地内存设备”是指直接挂载在系统总线上的内存设备。本地内存设备与系统总线之间的连接方式为电连接。一般地，本地内存设备与CPU处于同一块印刷电路板上。
在本发明实施例中，本地内存设备的一部分存储空间用作远程内存设备的缓存，即用于存储远程内存设备中的数据(即远程数据)，该部分存储空间即为“远程缓存”；本地内存设备的另一部分存储空间用于存储本地数据，该另一部分存储空间即为“本地内存”。
“本地内存”和“远程缓存”可以位于同一个本地内存设备上，也可以分别位于不同的本地内存设备上。
2)远程内存设备
“远程内存设备”是指间接挂载在系统总线上的内存设备。优选地，远程内存设备为通过光纤或光波导等光互连方式实现与系统总线连接的内存设备。本发明实施例的附图中均以远程内存设备通过光纤与系统总线连接为例进行说明。一般地，远程内存设备与CPU位于不同的印刷电路板上，而且远程内存设备与CPU之间的通信延时比本地内存设备与CPU之间的通信延时大。
参见图1，为现有技术中提供的一种电互连本地内存设备和光互连远程内存设备的系统架构示意图。图1中包括CPU板(CPU board)和存储板(Memory board)，其中，CPU板与存储板之间通过光纤连接。CPU板中包括CPU、本地内存设备、处理模块1和其他未示出的常见的计算机硬件模块。存储板中包括远程内存设备、处理模块2和其他未示出的常见的计算机硬件模块。处理模块1和处理模块2用于实现电信号与光信号之间的转换、传输协议的转换等。
参见图2，为本发明实施例提供的技术方案所适用的一种系统架构的结构示意图。与图1相比，图2中的本地内存设备与远程内存设备通过地址管理模块连接在同一接口上。其中，地址管理模块可以与内存控制器集成在一起，也可以独立设置；该接口可以为与内存控制器集成在一起的接口或为自定义接口。在该系统架构中，地址管理模块通过该接口对本地内存设备和远程内存设备进行统一管理(例如，统一编址、统一调试等)；CPU通过该接口访问本地内存设备和远程内存设备。
参见图3，为本发明实施例提供的一种内存访问方法的流程示意图。图3所示的方法应用于计算机系统，计算机系统的内存设备包含本地内存设备和远程内存设备，其中，本地内存设备包括本地内存和远程缓存，远程缓存用作远程内存设备的缓存。图3所示的方法包括以下步骤S301-S303：
S301：接收内存访问请求；其中，该内存访问请求中携带待访问内存区域的地址信息。
本发明实施例提供的内存访问方法的执行主体可以为图2中的地址管理模块，该地址管理模块可以与内存控制器集成在一起，也可以独立设置。
“待访问内存地址”可以包含在本地内存或远程内存设备中。“待访问内存区域的地址信息”可以为待访问内存区域的虚拟地址， 也可以为待访问内存区域的物理地址；还可以为其他任一能够表示待访问内存区域的虚拟地址或物理地址的信息。
举例而言，当地址管理模块与内存控制器集成在一起或独立设置时，步骤S301可以实现为：地址管理模块接收CPU发送的内存访问请求，该内存访问请求中携带待访问内存区域的虚拟地址。当地址管理模块与内存控制器独立设置时，步骤S301可以实现为；地址管理模块接收内存控制器发送的内存访问请求，该内存访问请求中携带待访问内存区域的物理地址。
“内存访问请求”具体可以为内存读请求或内存写请求。当内存访问请求为内存写请求时，该内存访问请求中还可以携带待写入数据，即内存写请求的数据。
S302：根据该地址信息，确定该地址信息指示的待访问内存区域。
举例而言，根据该地址信息，确定待访问内存区域的物理地址，从而确定待访问内存区域。
S303：当待访问内存区域在本地内存中时，根据内存访问请求对待访问内存区域进行访问操作；当待访问内存区域在远程内存设备中、且远程缓存中包含与待访问内存区域对应的缓存块时，根据内存访问请求对待访问内存区域对应的缓存块进行访问操作。
举例而言，地址管理模块可以通过判断待访问内存区域的物理地址是本地内存的地址还是远程内存设备的地址，从而确定待访问内存区域在本地内存中还是在远程内存设备中。
假设内存访问请求为内存读请求，那么：当待访问内存区域在本地内存中时，地址管理模块从待访问内存区域中读取数据；当待访问内存区域在远程内存设备中、且远程缓存中包含与待访问内存区域对应的缓存块时，地址管理模块从待访问内存区域对应的缓存块中读取数据。
假设内存访问请求为内存写请求，那么：当待访问内存区域在本地内存中时，地址管理模块将内存写请求的数据写入待访问内存区域；当待访问内存区域在远程内存设备中、且远程缓存中包含与待访问内存区域对应的缓存块，则地址管理模块将内存写请求的数据写入待访问内存区域对应的缓存块；后续，可以将待访问内存区域中的数据更新为内存写请求的数据。
本发明实施例提供的内存访问方法，通过将本地内存设备的一部分作为远程缓存，另一部分作为本地内存，从而实现内存访问。与现有技术中直接将本地内存的全部存储空间作为远程缓存，从而实现内存访问的技术方案相比，能够有效地提高本地内存设备的利用率。例如，当本地内存设备的容量大于远程内存设备所需的缓存(即远程缓存)的容量时，可以将本地内存设备中的部分存储空间作为远程缓存，并将本地内存设备中的其他存储空间作为本地内存，这样通过合理地设置远程缓存的容量，可以达到有效地利用本地内存设备的存储空间的目的，从而提高系统的整体性能。
在一种可选的实现方式中，该方法还可以包括：当待访问内存区域在远程内存设备中、且远程缓存中不包含与待访问内存区域对应的缓存块时，根据内存访问请求对待访问内存区域进行访问操作。
举例而言，当待访问内存区域在远程内存设备中、且远程缓存中不包含与待访问内存区域对应的缓存块时，若内存访问请求为内存读请求，则地址管理模块从待访问内存区域中读取数据；若内存访问请求为内存写请求，则地址管理模块将内存写请求的数据写入待访问内存区域。
进一步可选的，该方法还可以包括：在远程缓存中创建与待访问内存区域对应的缓存块；并将待访问内存区域中的数据写入与待访问内存区域对应的缓存块。
在另一种可选的实现方式中，如果内存访问请求为内存写请求， 那么，当待访问内存区域在远程内存设备中、且远程缓存中不包含与待访问内存区域对应的缓存块时，地址管理模块还可以在远程缓存中创建与待访问内存区域对应的缓存块，并将内存写请求的数据写入与待访问内存区域对应的缓存块。
在一种可选的实现方式中，在步骤S301之前，该方法还可以包括以下步骤A)-B)：
步骤A)：在本地内存设备中确定本地内存和远程缓存的容量。
步骤B)：为本地内存和远程内存设备分配内存地址(即物理地址)。具体的：为本地内存和远程内存设备统一进行编址。
步骤A)具体可以包括：根据远程内存设备的容量和预设命中率，在本地内存设备中确定远程缓存的容量；其中，远程缓存的容量分别与远程内存设备的容量和预设命中率成正相关关系；并将本地内存设备的剩余部分大小作为本地内存的容量。
其中，“预设命中率”为预先设置好的；本发明实施例对“预设命中率”的具体取值以及该具体取值的获取方式不进行限定。例如，预设命中率可以为：CPU缓存中的一级缓存的容量与二级缓存的容量的比值，或二级缓存的容量与三级缓存的容量的比值等；也可以为：根据经验值和具体应用场景中的需求所确定的一个值等。
一般地，远程内存设备的容量越大，远程缓存的容量就越大；预设命中率越大，远程缓存的容量就越大。优选地，远程缓存的容量＝远程内存设备的容量*预设命中率。
需要说明的是，步骤A)可以包括：根据远程内存设备的容量、预设命中率，并结合本地内存设备的容量、传输通路延时以及经验值等信息中的一种或多种确定远程缓存的容量。
另外需要说明的是，具体实现时，该方法还可以包括：记录本地内存的地址范围和远程内存设备的地址范围；其中，“地址范围”包括起始地址和终止地址。具体的，在系统中设置4个寄存器，然 后在该4个寄存器中分别记录本地内存的起始地址、本地内存的终止地址、远程内存设备的起始地址和远程内存设备的终止地址。
参见图4，为本发明实施例提供的一种内存访问方法的流程示意图。图4所示的方法包括以下步骤S401-S413：
S401：确定预设命中率、本地内存设备的容量和远程内存设备的容量。
本实施例中以预设命中率为CPU缓存中的一级缓存的容量与二级缓存的容量的比值为例进行说明。一般地，一级缓存的容量、二级缓存的容量、本地内存设备的容量和远程内存设备的容量在系统设置好时即已确定。
假设一级缓存的容量L1为32KB，二级缓存的容量L2为256KB，那么，预设命中率α＝L1/L2＝1/8。假设本地内存设备的容量Cl为2G，远程内存设备的容量Cr为8G。
S402：将远程内存设备的容量与预设命中率的乘积作为远程缓存的初始容量。
基于步骤S401中的示例，远程缓存的初始容量＝Cr*α＝1G。
S403：判断远程缓存的初始容量是否小于或等于本地内存设备的容量。若是，则执行步骤S404：若否，则执行步骤S405。
S404：将远程缓存的初始容量作为远程缓存的容量，并确定本地内存的容量。
基于步骤S402中的示例，执行步骤S404后所确定的远程缓存的容量为1G，本地内存的容量为Cl-α*Cr＝1G；该情况下，系统内存的总容量为：Cl+Cr-α*Cr＝9G。
S405：将本地内存设备的容量作为远程缓存的容量，并确定本地内存的容量。
假设α＝1/8，本地内存设备的容量Cl为8G，远程内存设备的容 量Cr为128G，那么，远程缓存的初始容量＝Cr*α＝8G。执行步骤S405后所确定的远程缓存的容量为8G，本地内存的容量为0；该情况下，系统内存的总容量为：Cl+Cr-α*Cr＝128G。
需要说明的是，当本地内存设备的容量、远程内存设备的容量或预设命中率发生变化时，可以重新确定远程缓存的容量。
另外需要说明的是，虽然步骤S405中将本地内存设备的全部存储空间作为了远程缓存；但是，本实施例是在执行步骤S401-S403的基础上，并在满足一定条件(即步骤S403的判断结果为“否“)时，才将本地内存设备的全部存储空间作为远程缓存；而现有技术是在不执行任何操作的情况下，直接将本地内存设备的全部存储空间作为远程缓存。二者存在本质区别。
S406：为本地内存和远程内存设备分配内存地址，并配置内存地址分配表(Memory Address Assigned Table，MAAT)；其中，配置内存地址分配表包括4个寄存器，该4个寄存器分别用于记录本地内存的起始地址、本地内存的终止地址、远程内存设备的起始地址、远程内存设备的终止地址。
假设为总容量为9G的内存分配的地址为[0x0000 0000 00000000，0x0000 0002 3FFF FFFF]，那么，本地内存的地址可以为[0x0000 0000 0000 0000，0x0000 0000 3FFF FFFF]，远程内存设备的地址可以为[0x0000 0000 4000 0000，0x0000 0002 3FFF FFFF]。
S407：接收内存访问请求；其中，内存访问请求中携带待访问内存区域的地址信息。
S408：根据该地址信息，确定该地址信息指示的待访问内存区域。
S409：根据内存地址分配表，判断待访问内存区域在本地内存中还是在远程内存设备中。若在本地内存中，则执行步骤S410；若在远程内存设备中，则执行步骤S411。
基于步骤S406中的示例，若0x0000 0000 0000 0000≤待访问内存区域的物理地址≤0x0000 0000 3FFF FFFF，则待访问内存区域在本地内存中；若0x0000 0000 4000 0000≤待访问内存区域的物理地址≤0x0000 0002 3FFF FFFF，则待访问内存区域在远程内存设备中。
S410：根据内存访问请求对待访问内存区域进行访问操作。
S411：判断远程缓存中是否包含待访问内存区域对应的缓存块。
若是，说明缓存命中，则执行步骤S412；若否，即缓存未命中，则执行步骤S413。
S412：根据内存访问请求对待访问内存区域对应的缓存块进行访问操作。
S413：根据内存访问请求对待访问内存区域进行访问操作，并在远程缓存中创建与待访问内存区域对应的缓存块，然后将待访问内存区域中的数据写入与待访问内存区域对应的缓存块。
在上文提供的任一种内存访问方法中，还可以包括：按照预设的周期T统计远程缓存的命中率；当远程缓存的命中率小于预设的第一阈值时，动态增加远程缓存的容量；当远程缓存的命中率大于预设的第二阈值时，动态减小远程缓存的容量；其中，第一阈值小于第二阈值。
“远程缓存的命中率”是指预设的周期T内实际访问远程缓存的次数与访问内存的总次数的比值。
本发明实施例对“预设的周期T”、“第一阈值”和“第二阈值”的具体取值以及其取值的获取方式不进行限定。例如，第一阈值可以为90％，第二阈值可以为100％；又如，第一阈值可以为80％，第二阈值可以为90％等。
本发明实施例对动态调整远程缓存的容量的方式不进行限定，例如，可以按照某一值递进增加或减少远程缓存的容量。
需要说明的是，由于远程缓存的容量的变化会影响到系统内存的总容量，而在系统运行的过程中，系统内存的总容量一般不变，因此，一般当系统重启时，调整后的远程缓存的容量才开始生效。
该可选的实现方式通过按照预设的周期T统计远程缓存的命中率，并在满足一定条件时调整远程缓存的容量；这样，通过一次或多次调整，能够使得在调整后得到的远程缓存的容量的情况下，使远程缓存的命中率大于等于第一阈值并小于等于第二阈值；由于第一阈值和第二阈值一般是根据系统整体性能较优等特性所确定的，因此，该可选的实现方式能够提高系统性能。
参见图5，为本发明实施例提供的一种内存访问装置的结构示意图。图5所示的内存访问装置5用以执行上文提供的任一种内存访问方法。内存访问装置5应用于计算机系统，计算机系统的内存设备包含本地内存设备和远程内存设备，其中，本地内存设备包括本地内存和远程缓存，远程缓存用作远程内存设备的缓存。内存访问装置5包括：接收单元51、确定单元52和访问单元53。
接收单元51用于接收内存访问请求；其中，所述内存访问请求中携带待访问内存区域的地址信息。
确定单元52用于根据该地址信息，确定该地址信息指示的待访问内存区域。
访问单元53用于当待访问内存区域在本地内存中时，根据内存访问请求对待访问内存区域进行访问操作，其中，本地内存设备包括本地内存和远程缓存，远程缓存用作远程内存设备的缓存；当待访问内存区域在远程内存设备中、且远程缓存中包含与所述待访问内存区域对应的缓存块时，根据所述内存访问请求对所述待访问内存区域对应的缓存块进行访问操作。
在一种可选的实现方式中，访问单元53还用于：当待访问内存 区域在远程内存设备中、且远程缓存中不包含与待访问内存区域对应的缓存块时，根据内存访问请求对待访问内存区域进行访问操作。
示例性的，在该可选的实现方式中，访问单元53还用于：在远程缓存中创建与待访问内存区域对应的缓存块，并将待访问内存区域中的数据写入与待访问内存区域对应的缓存块。
在另一种可选的实现方式中，内存访问请求为内存写请求；访问单元53还用于：当待访问内存区域在远程内存设备中、且远程缓存中不包含与待访问内存区域对应的缓存块时，在远程缓存中创建与待访问内存区域对应的缓存块，并将内存写请求的数据写入与待访问内存区域对应的缓存块。
在另一种可选的实现方式中，确定单元52还用于：在本地内存设备中确定本地内存和所述远程缓存的容量；该情况下，如图6所示，内存访问装置5还可以包括：分配单元54，用于为本地内存和远程内存设备分配内存地址。
示例性的，确定单元52执行在本地内存设备中确定本地内存和远程缓存的容量时，具体用于：根据远程内存设备的容量和预设命中率，在本地内存设备中确定远程缓存的容量；其中，远程缓存的容量分别与远程内存设备的容量和预设命中率成正相关关系；将本地内存设备的剩余部分大小作为本地内存的容量。
在另一种可选的实现方式中，如图6所示，内存访问装置5还可以包括：统计单元55和调整单元56；其中，统计单元55用于按照预设的周期T统计远程缓存的命中率；调整单元56用于当远程缓存的命中率小于预设的第一阈值时，动态增加远程缓存的容量；当远程缓存的命中率大于预设的第二阈值时，动态减小远程缓存的容量；其中，第一阈值小于第二阈值。
需要说明的是，内存访问装置5可以与内存控制器集成在一起，或去内存控制器独立设置。本实施例提供的内存访问装置5中的相 关内容的解释可以参考上文提供的方法实施例，此处不再赘述。
本实施例提供的内存访问装置，通过将本地内存设备的一部分作为远程缓存，另一部分作为本地内存，从而实现内存访问。与现有技术中直接将本地内存的全部存储空间均作为远程缓存，从而实现内存访问的技术方案相比，能够有效地提高本地内存设备的利用率。例如，当本地内存设备的容量大于远程内存设备所需的缓存(即远程缓存)的容量时，可以将本地内存设备中的部分存储空间作为远程缓存，并将本地内存设备中的其他存储空间作为本地内存，这样通过合理地设置远程缓存的容量，可以达到有效地利用本地内存设备的存储空间的目的，从而提高系统的整体性能。
另外，本发明实施例还提供了一种内存控制器，该内存控制器中包括上文提供的任一种内存访问装置5。
另外，本发明实施例还提供了一种内存访问系统，该内存访问系统包括：本地内存设备、远程内存设备，以及上文提供的任一种内存访问装置5；其中，所述本地内存设备包括本地内存和远程缓存，所述远程缓存用作所述远程内存设备的缓存。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接， 可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理包括，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
上述以软件功能单元的形式实现的集成的单元，可以存储在一个计算机可读取存储介质中。上述软件功能单元存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的部分步骤。而前述的存储介质包括：U盘、移动硬盘、ROM(Read-Only Memory，只读存储器)、RAM(Random Access Memory，随机存取存储器)、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (15)

  1. 一种内存访问方法，其特征在于，应用于计算机系统，所述计算机系统的内存设备包含本地内存设备和远程内存设备；所述方法包括：
    接收内存访问请求；其中，所述内存访问请求中携带待访问内存区域的地址信息；
    根据所述地址信息，确定所述地址信息指示的待访问内存区域；
    当所述待访问内存区域在所述本地内存中时，根据所述内存访问请求对所述待访问内存区域进行访问操作；其中，所述本地内存设备包括本地内存和远程缓存，所述远程缓存用作所述远程内存设备的缓存；
    当所述待访问内存区域在所述远程内存设备中、且所述远程缓存中包含与所述待访问内存区域对应的缓存块时，根据所述内存访问请求对所述待访问内存区域对应的缓存块进行访问操作。
  2. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    当所述待访问内存区域在所述远程内存设备中、且所述远程缓存中不包含与所述待访问内存区域对应的缓存块时，根据所述内存访问请求对所述待访问内存区域进行访问操作。
  3. 根据权利要求2所述的方法，其特征在于，所述方法还包括：
    在所述远程缓存中创建与所述待访问内存区域对应的缓存块；
    将所述待访问内存区域中的数据写入与所述待访问内存区域对应的缓存块。
  4. 根据权利要求1所述的方法，其特征在于，所述内存访问请求为内存写请求；所述方法还包括：
    当所述待访问内存区域在所述远程内存设备中、且所述远程缓存中不包含与所述待访问内存区域对应的缓存块时，在所述远程缓存中创建与所述待访问内存区域对应的缓存块，并将所述内存写请求的数 据写入与所述待访问内存区域对应的缓存块。
  5. 根据权利要求1-4任一项所述的方法，其特征在于，在接收内存访问请求之前，所述方法还包括：
    在所述本地内存设备中确定所述本地内存和所述远程缓存的容量；
    为所述本地内存和所述远程内存设备分配内存地址。
  6. 根据权利要求5所述的方法，其特征在于，所述在所述本地内存设备中确定所述本地内存和所述远程缓存的容量，包括：
    根据所述远程内存设备的容量和预设命中率，在所述本地内存设备中确定所述远程缓存的容量；其中，所述远程缓存的容量分别与所述远程内存设备的容量和所述预设命中率成正相关关系；
    将所述本地内存设备的剩余部分大小作为所述本地内存的容量。
  7. 根据权利要求1-6任一项所述的方法，其特征在于，所述方法还包括：
    按照预设的周期T统计所述远程缓存的命中率；
    当所述远程缓存的命中率小于预设的第一阈值时，动态增加所述远程缓存的容量；
    当所述远程缓存的命中率大于预设的第二阈值时，动态减小所述远程缓存的容量；
    其中，所述第一阈值小于所述第二阈值。
  8. 一种内存访问装置，其特征在于，应用于计算机系统，所述计算机系统的内存设备包含本地内存设备和远程内存设备；所述内存访问装置包括：
    接收单元，用于接收内存访问请求；其中，所述内存访问请求中携带待访问内存区域的地址信息；
    确定单元，用于根据所述地址信息，确定所述地址信息指示的待访问内存区域；
    访问单元，用于当所述待访问内存区域在所述本地内存中时，根据所述内存访问请求对所述待访问内存区域进行访问操作，其中，所述本地内存设备包括本地内存和远程缓存，所述远程缓存用作所述远程内存设备的缓存；当所述待访问内存区域在所述远程内存设备中、且所述远程缓存中包含与所述待访问内存区域对应的缓存块时，根据所述内存访问请求对所述待访问内存区域对应的缓存块进行访问操作。
  9. 根据权利要求8所述的内存访问装置，其特征在于，
    所述访问单元还用于：当所述待访问内存区域在所述远程内存设备中、且所述远程缓存中不包含与所述待访问内存区域对应的缓存块时，根据所述内存访问请求对所述待访问内存区域进行访问操作。
  10. 根据权利要求9所述的内存访问装置，其特征在于，所述访问单元还用于：
    在所述远程缓存中创建与所述待访问内存区域对应的缓存块；
    将所述待访问内存区域中的数据写入与所述待访问内存区域对应的缓存块。
  11. 根据权利要求8所述的内存访问装置，其特征在于，所述内存访问请求为内存写请求；
    所述访问单元还用于：当所述待访问内存区域在所述远程内存设备中、且所述远程缓存中不包含与所述待访问内存区域对应的缓存块时，在所述远程缓存中创建与所述待访问内存区域对应的缓存块，并将所述内存写请求的数据写入与所述待访问内存区域对应的缓存块。
  12. 根据权利要求8-11任一项所述的内存访问装置，其特征在于，所述确定单元还用于：在所述本地内存设备中确定所述本地内存和所述远程缓存的容量；
    所述内存访问装置还包括：分配单元，用于为所述本地内存和所述远程内存设备分配内存地址。
  13. 根据权利要求12所述的内存访问装置，其特征在于，所述确定单元执行在所述本地内存设备中确定所述本地内存和所述远程缓存的容量时，具体用于：
    根据所述远程内存设备的容量和预设命中率，在所述本地内存设备中确定所述远程缓存的容量；其中，所述远程缓存的容量分别与所述远程内存设备的容量和所述预设命中率成正相关关系；
    将所述本地内存设备的剩余部分大小作为所述本地内存的容量。
  14. 根据权利要求8-13任一项所述的内存访问装置，其特征在于，还包括：
    统计单元，用于按照预设的周期T统计所述远程缓存的命中率；
    调整单元，用于当所述远程缓存的命中率小于预设的第一阈值时，动态增加所述远程缓存的容量；当所述远程缓存的命中率大于预设的第二阈值时，动态减小所述远程缓存的容量；其中，所述第一阈值小于所述第二阈值。
  15. 一种内存访问系统，其特征在于，包括：本地内存设备、远程内存设备，以及权利要求8-14任一项所述的内存访问装置；其中，所述本地内存设备包括本地内存和远程缓存，所述远程缓存用作所述远程内存设备的缓存。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115168247A (zh) * 2022-09-02 2022-10-11 北京登临科技有限公司 用于并行处理器中动态共享存储空间的方法及相应处理器

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108984323B (zh) * 2018-07-13 2022-04-01 上海联影医疗科技股份有限公司 一种共享存储空间的调度方法及系统
CN112737975B (zh) * 2020-12-25 2023-05-09 珠海西山居数字科技有限公司 缓冲区容量调整方法及装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5778429A (en) * 1994-07-04 1998-07-07 Hitachi, Ltd. Parallel processor system including a cache memory subsystem that has independently addressable local and remote data areas
US5829052A (en) * 1994-12-28 1998-10-27 Intel Corporation Method and apparatus for managing memory accesses in a multiple multiprocessor cluster system
CN101510144A (zh) * 2009-03-24 2009-08-19 中国科学院计算技术研究所 基于分布式虚拟机管理器的分布式cache系统及其工作方法
CN102035881A (zh) * 2010-11-19 2011-04-27 清华大学 一种云端存储系统的数据缓存方法
CN104503707A (zh) * 2014-12-24 2015-04-08 华为技术有限公司 读取数据的方法以及装置

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0777183B1 (en) * 1995-12-01 2002-07-31 Hewlett-Packard Company, A Delaware Corporation Computer cache system
US6523102B1 (en) * 2000-04-14 2003-02-18 Interactive Silicon, Inc. Parallel compression/decompression system and method for implementation of in-memory compressed cache improving storage density and access speed for industry standard memory subsystems and in-line memory modules
US6684298B1 (en) * 2000-11-09 2004-01-27 University Of Rochester Dynamic reconfigurable memory hierarchy
US7096323B1 (en) * 2002-09-27 2006-08-22 Advanced Micro Devices, Inc. Computer system with processor cache that stores remote cache presence information
US7467238B2 (en) * 2004-02-10 2008-12-16 Hitachi, Ltd. Disk controller and storage system
US7266663B2 (en) * 2005-01-13 2007-09-04 International Business Machines Corporation Automatic cache activation and deactivation for power reduction
US7509460B2 (en) * 2006-05-04 2009-03-24 Sun Microsystems, Inc. DRAM remote access cache in local memory in a distributed shared memory system
US7962692B2 (en) * 2006-10-05 2011-06-14 Computer Associates Think, Inc. Method and system for managing performance data
US20080244181A1 (en) * 2007-03-30 2008-10-02 Michael Walz Dynamic run-time cache size management
US20100199036A1 (en) * 2009-02-02 2010-08-05 Atrato, Inc. Systems and methods for block-level management of tiered storage
US8195883B2 (en) * 2010-01-27 2012-06-05 Oracle America, Inc. Resource sharing to reduce implementation costs in a multicore processor
US8635406B2 (en) * 2012-03-08 2014-01-21 Arm Limited Data processing apparatus and method for providing target address information for branch instructions
CN103077125B (zh) * 2012-12-13 2015-09-16 北京锐安科技有限公司 一种高效利用存储空间的自适应自组织塔式缓存方法
GB2511325A (en) * 2013-02-28 2014-09-03 Ibm Cache allocation in a computerized system
CN103902474B (zh) * 2014-04-11 2017-02-08 华中科技大学 一种支持固态盘缓存动态分配的混合存储系统和方法
CN104808967B (zh) * 2015-05-07 2017-07-04 盐城工学院 一种处理器的动态数据预取系统
US10073758B2 (en) * 2015-07-15 2018-09-11 Citrix Systems, Inc. Performance of a wrapped application

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5778429A (en) * 1994-07-04 1998-07-07 Hitachi, Ltd. Parallel processor system including a cache memory subsystem that has independently addressable local and remote data areas
US5829052A (en) * 1994-12-28 1998-10-27 Intel Corporation Method and apparatus for managing memory accesses in a multiple multiprocessor cluster system
CN101510144A (zh) * 2009-03-24 2009-08-19 中国科学院计算技术研究所 基于分布式虚拟机管理器的分布式cache系统及其工作方法
CN102035881A (zh) * 2010-11-19 2011-04-27 清华大学 一种云端存储系统的数据缓存方法
CN104503707A (zh) * 2014-12-24 2015-04-08 华为技术有限公司 读取数据的方法以及装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3321809A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115168247A (zh) * 2022-09-02 2022-10-11 北京登临科技有限公司 用于并行处理器中动态共享存储空间的方法及相应处理器
CN115168247B (zh) * 2022-09-02 2022-12-02 北京登临科技有限公司 用于并行处理器中动态共享存储空间的方法及相应处理器

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