WO2021042706A1 - 一种数字逻辑自动测试装置及方法 - Google Patents

一种数字逻辑自动测试装置及方法 Download PDF

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WO2021042706A1
WO2021042706A1 PCT/CN2020/082071 CN2020082071W WO2021042706A1 WO 2021042706 A1 WO2021042706 A1 WO 2021042706A1 CN 2020082071 W CN2020082071 W CN 2020082071W WO 2021042706 A1 WO2021042706 A1 WO 2021042706A1
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test
data
input
result
output
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PCT/CN2020/082071
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French (fr)
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吴汉明
朱敏
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芯创智（北京）微电子有限公司
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B23/00—Testing or monitoring of control systems or parts thereof
    • G05B23/02—Electric testing or monitoring
    • G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
    • G05B23/0218—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterised by the fault detection method dealing with either existing or incipient faults
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]

Definitions

  • the invention relates to the technical field of chip testing, in particular to a digital logic automatic testing device and method.
  • the existing test equipment can only verify the overall function and performance of the chip, and cannot accurately test the highest operating frequency of the logic of a single part of the chip, which leads to partial and inaccurate test results, which in turn leads to the failure of the chip. The evaluation of functions and performance will be inaccurate.
  • the current integrated circuit testing includes manual testing and automated testing.
  • Automated testing has fast speed, high degree, and comprehensive testing, so it is widely used in mass product testing, but its cost is high, the testing process is complicated, and the debugging cycle is long.
  • the manual test is generally implemented on a customized test board. It is completed by the tester observing the light, sound or instrument reading. The manual test is suitable for small batches, simple, and non-comprehensive rapid tests.
  • the purpose of the present invention is to provide a digital logic automatic test device and method, which can test the function and performance of the logic to be tested in a targeted manner, and accurately measure the highest operating frequency.
  • test device comprising: an input serial register, an input register, a test module, an output register, and an output serial register connected in sequence;
  • the input serial register is used to receive external data scanned in through a standard JTAG interface, and then send it to the input register in parallel;
  • the input register is used to input the received external data into the test module
  • the test module is used to perform a test according to the external data and an externally input start signal based on the work mode in the external data, and after the test is completed, save the test result in the output register, and the work mode includes: Single-step test mode, vector loading mode and self-test mode;
  • the output register is used to input the test result into the output serial register in parallel;
  • the output serial register is used to scan out the received test result through the standard JTAG interface.
  • the input register includes: a control DFF and a data DFF
  • the output register includes: an output DFF
  • the control DFF is used to input control information in the external data into the test module
  • the data DFF is used to input data information in the external data into the test module
  • the output DFF is used to output the test result of the test module to the output serial register.
  • the test module is specifically configured to determine the corresponding working module according to the control information input by the control DFF, and according to the working mode and the data information input by the data DFF And the external input start signal is tested, and after the test is completed, the test result is saved in the output DFF;
  • the start signal is used to determine whether the control information and the data information are valid, and when the control information and the data information are both valid, the test module starts the corresponding working mode.
  • the test module includes: a test controller, and an input vector memory, a result vector memory and a circuit to be tested connected to the test controller;
  • test controller is used for:
  • the working mode is the single-step test mode
  • the data to be tested is read from the input vector memory, the test data is obtained after the logic operation of the circuit to be tested, and the test data is compared with the result vector memory. The read result data is compared, and the test result is obtained and output to the output DFF.
  • the test module further includes: a first data selector, a second data selector, a third data selector, and a fourth data selector connected to the test controller.
  • a selector, the first data selector, the second data selector, the circuit to be tested, the third data selector, and the fourth data selector are connected in sequence;
  • test controller is used for:
  • the data information input by the data DFF is sequentially loaded into the circuit to be tested through the first data selector and the second data selector, and the After the logic operation of the circuit to be tested, the test result is sequentially output to the output DFF through the third data selector and the fourth data selector.
  • the first data selector is connected to the input vector memory and the result vector memory
  • test controller is used for:
  • address analysis is performed on the data information input by the data DFF, and if the vector type in the data information is an input vector, the data information is taken as the address obtained by the analysis.
  • the data to be tested is loaded into the input vector memory via the first data selector, and if the vector type in the data information is the result vector, the data information is used as the result data through the first data according to the parsed address.
  • a data selector is loaded into the result vector memory.
  • the test module further includes: a result comparator, the result comparator and the test controller, the third data selector, and the fourth data The selector is connected to the result vector memory;
  • test controller is used for:
  • the data to be tested read from the input vector memory is loaded into the circuit to be tested through the second data selector, and after the logic operation of the circuit to be tested To obtain test data, input the test data to the result comparator via the third data selector, and the result comparator compares the test data with the result data read from the result vector memory, The test result is obtained and output to the output DFF through the fourth data selector.
  • the input vector register includes: a counter connected to the test controller;
  • test controller is also used for:
  • the counter When it is determined that the working mode is the self-test mode, the counter is turned on, and the data to be tested is read from the input vector memory according to the test address generated by the counter for testing. If the result data read in the result vector memory is the same, the test result is determined to be correct, and the next test is performed according to the new test address generated by the counter until all the data to be tested in the input vector memory are tested. The number of cycles in the control information is used for the next cycle test.
  • test controller is further used for:
  • the self-test DEBUG in the control information is in the on state, when an error occurs in the test process, the result data in the result vector memory is passed through the fourth data The selector outputs to the output DFF.
  • a digital logic automatic test method includes:
  • testing is performed according to the external data and the externally input start signal to obtain the test result.
  • the working modes include: single-step test mode, vector loading mode and self-test mode.
  • the beneficial effect of the present invention is that the device and method provided by the present invention can test the function and performance of the logic to be tested in a targeted manner, and accurately measure the highest operating frequency.
  • the present invention supports automatic test, manual single-step test and test debugging functions, and meets the requirements of cost, speed, degree and comprehensiveness.
  • FIG. 1 is a schematic structural diagram of a digital logic automatic test device provided in an embodiment of the present invention
  • FIG. 2 is a schematic diagram of the structure of a test module provided in an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of the structure of an input vector register and a result vector register provided in an embodiment of the present invention
  • FIG. 4 is a schematic flowchart of a digital logic automatic test method provided in an embodiment of the present invention.
  • the present invention adopts a method of adding redundant test logic, so that the function and performance of the logic to be tested can be tested in a targeted manner, and the highest operating frequency can be measured.
  • the present invention supports automatic test, manual single-step test and test debugging functions, and meets the requirements of cost, speed, degree and comprehensiveness.
  • a digital logic automatic test device the test device includes: an input serial register, an input register, a test module, an output register, and an output serial register connected in sequence;
  • the input serial register is used to receive the external data scanned in through the standard JTAG interface, and then send it to the input register in parallel;
  • the input register is used to input the received external data into the test module
  • the test module is used to test based on the working mode in the external data and according to the external data and the external input start signal. After the test is completed, the test result is saved in the output register.
  • the working modes include: single-step test mode, vector loading mode and self Test mode
  • the output register is used to input and output the test result in parallel to the serial register
  • the output serial register is used to scan out the received test results through the standard JTAG interface.
  • Input registers include: control DFF and data DFF, and output registers include: output DFF;
  • the control DFF is used to input the control information in the external data into the test module
  • Data DFF is used to input data information in external data into the test module
  • the output DFF is used to output the test result of the test module to the output serial register.
  • the test module is specifically used to determine the corresponding working module according to the control information input by the control DFF, and perform the test according to the working mode, the data information input by the data DFF and the external input start signal, and after the test is completed, the test result is saved and output to the DFF;
  • the start signal is used to judge whether the control information and data information are valid. When the control information and data information are both valid, the test module starts the corresponding working mode.
  • the test module includes: the test controller, and the input vector memory, the result vector memory and the circuit to be tested connected to the test controller;
  • the test controller is used to:
  • the data information input by the data DFF is loaded into the circuit under test, and after the logic operation of the circuit under test, the test result is output to the output DFF;
  • the address analysis is performed on the data information input by the data DFF, and the data information is stored in the input vector memory or the result vector memory according to the analysis result and the vector type in the data information;
  • the data to be tested is read from the input vector memory, and the test data is obtained after the logic operation of the circuit to be tested.
  • the test data is compared with the result data read from the result vector memory to obtain the test
  • the result is output to the output DFF.
  • the test module also includes: a first data selector, a second data selector, a third data selector, and a fourth data selector connected to the test controller, the first data selector, the second data selector, and the circuit to be tested , The third data selector and the fourth data selector are connected in sequence;
  • the test controller is used to:
  • the data information input by the data DFF is sequentially loaded into the circuit to be tested through the first data selector and the second data selector. After the logical operation of the circuit to be tested, the test results are sequentially passed through The third data selector and the fourth data selector output to the output DFF.
  • the first data selector is connected to the input vector memory and the result vector memory;
  • the test controller is used to:
  • the address analysis is performed on the data information input by the data DFF. If the vector type in the data information is an input vector, the data information is used as the data to be measured according to the address obtained by the analysis and selected by the first data Load the input vector memory into the input vector memory, and if the vector type in the data information is the result vector, the data information is loaded into the result vector memory via the first data selector as the result data according to the address obtained by the analysis.
  • the test module also includes: a result comparator, which is connected to the test controller, the third data selector, the fourth data selector and the result vector memory;
  • the test controller is used to:
  • the data to be tested read from the input vector memory is loaded into the circuit to be tested through the second data selector, the test data is obtained after the logic operation of the circuit to be tested, and the test data is passed through the third
  • the data selector inputs the result comparator, and the result comparator compares the test data with the result data read from the result vector memory to obtain the test result, which is output to the output DFF via the fourth data selector.
  • the input vector register includes: a counter connected to the test controller;
  • test controller is also used to:
  • the counter When the working mode is determined to be the self-test mode, the counter is turned on, and the test data is read from the input vector memory according to the test address generated by the counter for testing. If the test data is the same as the result data read from the result vector memory, then Make sure that the test result is correct, and perform the next test according to the new test address generated by the counter, until all the data to be tested in the input vector memory are tested, and the next round of cyclic testing is performed according to the number of cycles in the control information.
  • test controller is also used to:
  • the self-test DEBUG in the control information is turned on, when an error occurs in the test process, the result data in the result vector memory is output to the output DFF through the fourth data selector.
  • the digital logic automatic test device provided by the present invention supports automatic test, manual single-step test and test debugging functions, supports clock upscaling to measure the highest operating frequency, and uses memory to store test vectors and result vectors, which can be targeted for testing Find out the function and performance of the logic to be tested, and measure the highest operating frequency.
  • a digital logic automatic test device includes: input serial register, input register, test module, output register, and output serial register.
  • External data passes through standard JTAG interfaces (TMS, TCK, TDI). Wire) control to enter the input serial register, and the external high-frequency clock signal is input into the input register, test module, and output register respectively.
  • TMS JTAG interfaces
  • TCK TCK
  • TDI TDI
  • Wire control to enter the input serial register
  • the external high-frequency clock signal is input into the input register, test module, and output register respectively.
  • TDO line controls the output.
  • the standard JTAG interface includes 4 wires: TMS, TCK, TDI, TDO, which are respectively the mode selection, clock, data input and data output lines.
  • Table 1 is a table of functional test logic and external interface signals. Both i_DATA_TCEN and i_CFG_TCEN have a bit width of 1 bit as the start signal of the test logic (test module in Figure 1).
  • the bit width of i_CfgCtrl is 256 bits, which is the control signal that is externally input to the test logic.
  • the bit width of i_CfgData is 256 bits, which is the data signal that is externally input to the test logic.
  • the bit width of o_RespData is 256 bits. response.
  • a direction of I means input, and a direction of O means output.
  • the present invention uses a memory to store the input vector and the result vector of the circuit to be tested.
  • the input is the control DFF, the data DFF and the start signal, and the output is the output DFF.
  • the start signal is used to control the opening of the logic self-test module;
  • the control DFF bit width is 256 bits, which is used to receive external circuit control signals and transmit them to the test controller to control the logic self-test operation;
  • the data DFF bit width is 256 bits, Used to receive external data; output DFF is used to output test results.
  • Control DFF has a total of 256 bits, each meaning supports user-defined, but must include five domains: reset, test module, work mode, self-test DEBUG mode and cycle times, control DFF trigger interface definition is shown in Table 2.
  • the data DFF has a total of 256 bits, and each meaning supports user-defined, but it must contain four fields: test module, vector type, address and data.
  • the data DFF trigger interface definition is detailed in Table 3.
  • the output DFF has a total of 256 bits, and each meaning supports user-defined, but it must contain four fields: test module, vector type, address and data.
  • the output DFF trigger interface definition is detailed in Table 4.
  • the bit width of the test output indicator signal is 1 bit, including 5 indicator signals, as shown in Table 5.
  • i_DATA_TCEN and i_CFG_TCEN are used as the test logic start signal to determine whether the data signal and the control signal are valid, and if they are both valid, the test module is started.
  • i_test_en, o_test_done, and o_test_fail are used to indicate test enable signal, test completion signal and test error signal, respectively.
  • the direction is I for input, and the direction is O for output.
  • Vector memory includes input vector memory and result vector memory.
  • the input vector memory contains a 4bit counter, which is used to generate the test address.
  • Input/result vector memory write operation corresponds to the vector load working mode. Under the control of the test controller, the input data is written into the storage entry of the corresponding address.
  • Input/result vector memory read operation corresponds to the self-test work mode.
  • the counter generates a test address, and reads the corresponding data from the input vector memory according to the test address. As a result, the vector memory read address is consistent with the input vector memory.
  • the result comparator is responsible for comparing the output result of the circuit under test with the correct result loaded from the result vector memory, and gives information on whether the comparison is correct.
  • the test controller is responsible for analyzing the input 256-bit control data, controlling the correct operation of the entire test process, and at the same time being responsible for the recovery of test results.
  • the test controller first parses the input control signal, and parses out information such as soft reset, test module, working mode, self-test DEBUG, and cycle times (Table 2). Then start the entire test process.
  • test the controller choose to directly pass the data from the data DFF through MUX1, then through MUX2, and enter the circuit under test. After the logic operation of the circuit under test, directly pass through MUX3 without comparing the results. Then pass through MUX4 to output DFF output. Whether the test is correct requires manual judgment based on the output result (the line pointed by the dashed arrow in Figure 2).
  • MUX1, MUX2, MUX3, and MUX4 are all data selectors.
  • test the controller choose to store the data from the data DFF to the vector memory ( Figure 2).
  • the address analysis module will parse out whether the data is an input vector or a result vector according to Table 3, and parse out the storage address of the data in the memory. If the vector type is an input vector, it is stored in the corresponding storage address of the input vector memory. If the vector type is an output vector, it is stored in the corresponding storage address of the result vector memory ( Figure 3). Multiple sets of vectors need to be loaded multiple times.
  • the test controller Before the self-test mode starts, several sets of vectors have been loaded in the input vector memory and the result vector memory. If it is in the self-test mode, the test controller turns on the counter to work ( Figure 2 and Figure 3) to generate the test address, read the input vector from the input vector memory, the vector to be tested ( Figure 3), and the data after the logic operation of the circuit to be tested , And then compare with the result data read from the result vector memory. If the comparison is equal, the test result is correct. This process will be performed on all valid data in the vector memory, and will cycle several times, the number of cycles is configured by controlling the DFF (Table 2).
  • the input register in Figure 1 is the data DFF and control DFF in Figure 2. Sweep the data into the input serial register through the JTAG standard interface, and then send it to the input register in parallel. If it is control information, the data enters the control DFF, if it is data information, the data enters the data DFF.
  • the meanings of control information and data information are shown in Table 2 and Table 3 respectively. After the control information and data information are entered into the input register, the corresponding working mode can be turned on.
  • the data of the selected test data DFF is loaded into the circuit under test through MUX1 and MUX2, and the output of the circuit under test enters the output DFF through MUX3 and MUX4 and then is output.
  • Vector loading When the start signal is valid, the mode is selected as vector loading, and the input vector and result vector are loaded into the corresponding memory shot by shot.
  • Control DFF[253:252] bits indicate the working mode selection (see Table 2 for details). If the working mode is selected as vector loading, the input vector and result vector are loaded respectively to Corresponding memory. Load a set of vectors each time, including the input vector and the result vector. Before the data is loaded into the memory, address analysis is required. According to the signal of the module under test from the test controller, the loaded vector type is judged. The data DFF[252] bit indicates the vector type (see Table 3 for details). If it is an input vector, it is stored in the input vector memory, if it is a result vector, it is stored in the result vector memory.
  • the test controller After starting the test, through the control of the test controller, read the vector to be tested from the memory in turn, load it to the circuit to be tested via MUX2, compare the output data with the stored result to determine whether it is correct, and continue the next vector test until it is correct. All vector tests are completed, and the next round of cyclic testing is performed. If all loop tests of all vectors are completed and the results are still correct, then the o_test_done signal is asserted. If an error occurs when testing a vector, the o_test_done signal is set to be valid, and the o_test_fail signal is set to be valid (Table 5). The number of cycles is specified by the "Number of cycles" field that controls the DFF (Table 2). In the self-test mode, if the DEBUG is turned on and an error occurs in the test process, the result vector will be output to the output DFF through MUX4.
  • test result is saved in the output register and directly connected to the output serial register in parallel. Sweep out the content in the output serial register through the TDO line of the JTAG standard interface.
  • the digital logic automatic test device provided by the present invention supports automatic test, manual single-step test and test debugging functions, supports clock upscaling to measure the highest operating frequency, and uses memory to store test vectors and result vectors, which can be targeted for testing Find out the function and performance of the logic to be tested, and measure the highest operating frequency.
  • test method includes:
  • the working modes include: single-step test mode, vector loading mode and self-test mode;
  • S100 includes:
  • the input serial register receives the external data scanned in through the standard JTAG interface, and then sends it to the input register in parallel;
  • the input register inputs the received external data into the test module
  • S200 includes: the test module is based on the working mode in the external data, and performs the test according to the external data and the external input start signal. After the test is completed, the test result is saved in the output register;
  • S300 includes:
  • the output register inputs and outputs the test result into the serial register in parallel
  • the output serial register scans the received test result through the standard JTAG interface.
  • Input registers include: control DFF and data DFF, and output registers include: output DFF;
  • the control DFF is used to input the control information in the external data into the test module
  • Data DFF is used to input data information in external data into the test module
  • the output DFF is used to output the test result of the test module to the output serial register.
  • the test module is specifically used to determine the corresponding working module according to the control information input by the control DFF, and perform the test according to the working mode, the data information input by the data DFF and the external input start signal, and after the test is completed, the test result is saved and output to the DFF;
  • the start signal is used to judge whether the control information and data information are valid. When the control information and data information are both valid, the test module starts the corresponding working mode;
  • Working modes include: single-step test mode, vector loading mode and self-test mode.
  • the test module includes: the test controller, and the input vector memory, the result vector memory and the circuit to be tested connected to the test controller;
  • S200 includes: test controller,
  • the data information input by the data DFF is loaded into the circuit under test, and after the logic operation of the circuit under test, the test result is output to the output DFF;
  • the address analysis is performed on the data information input by the data DFF, and the data information is stored in the input vector memory or the result vector memory according to the analysis result and the vector type in the data information;
  • the data to be tested is read from the input vector memory, and the test data is obtained after the logic operation of the circuit to be tested.
  • the test data is compared with the result data read from the result vector memory to obtain the test
  • the result is output to the output DFF.
  • the test module also includes: a first data selector, a second data selector, a third data selector, and a fourth data selector connected to the test controller, the first data selector, the second data selector, and the circuit to be tested , The third data selector and the fourth data selector are connected in sequence;
  • S200 includes: test controller,
  • the data information input by the data DFF is sequentially loaded into the circuit to be tested through the first data selector and the second data selector. After the logical operation of the circuit to be tested, the test results are sequentially passed through The third data selector and the fourth data selector output to the output DFF.
  • the first data selector is connected to the input vector memory and the result vector memory;
  • S200 includes: test controller,
  • the address analysis is performed on the data information input by the data DFF. If the vector type in the data information is an input vector, the data information is used as the data to be measured according to the address obtained by the analysis and selected by the first data Load the input vector memory into the input vector memory, and if the vector type in the data information is the result vector, the data information is loaded into the result vector memory via the first data selector as the result data according to the address obtained by the analysis.
  • the test module also includes: a result comparator, which is connected to the test controller, the third data selector, the fourth data selector and the result vector memory;
  • S200 includes: test controller,
  • the data to be tested read from the input vector memory is loaded into the circuit to be tested through the second data selector, the test data is obtained after the logic operation of the circuit to be tested, and the test data is passed through the third
  • the data selector inputs the result comparator, and the result comparator compares the test data with the result data read from the result vector memory to obtain the test result, which is output to the output DFF via the fourth data selector.
  • the input vector register includes: a counter connected to the test controller;
  • S200 includes: test controller,
  • the counter When the working mode is determined to be the self-test mode, the counter is turned on, and the test data is read from the input vector memory according to the test address generated by the counter for testing. If the test data is the same as the result data read from the result vector memory, then Make sure that the test result is correct, and perform the next test according to the new test address generated by the counter, until all the data to be tested in the input vector memory are tested, and the next round of cyclic testing is performed according to the number of cycles in the control information.
  • S200 includes: test controller,
  • the self-test DEBUG in the control information is turned on, when an error occurs in the test process, the result data in the result vector memory is output to the output DFF through the fourth data selector.

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Abstract

一种数字逻辑自动测试装置及方法，测试装置包括：依次连接的输入串行寄存器、输入寄存器、测试模块、输出寄存器和输出串行寄存器；输入串行寄存器用于接收通过标准JTAG接口扫入的外部数据，再并行送入输入寄存器；输入寄存器用于将接收到的外部数据输入测试模块；测试模块用于基于外部数据中的工作模式，根据外部数据和外部输入的启动信号进行测试，测试完成后，将测试结果保存在输出寄存器；输出寄存器用于将测试结果并行输入输出串行寄存器；输出串行寄存器用于将接收到的测试结果通过标准JTAG接口扫出。该方案所提供的装置及方法，可以有针对性的测试出待测逻辑的功能和性能，准确测出最高工作频率。

Description

一种数字逻辑自动测试装置及方法 技术领域
本发明涉及芯片测试技术领域，具体涉及一种数字逻辑自动测试装置及方法。
背景技术
在芯片完成设计，流片返回后，一般需要对芯片进行测试，用以验证芯片上的功能是否正确，以及性能是否达到要求。但是，现有的测试装置往往只能验证芯片整体的功能和性能，并不能对芯片内部的单个部分的逻辑的最高工作频率进行准确测试，从而导致测试结果片面、不准确，进而导致对芯片的功能和性能上的评估也会不准确。
而且，目前集成电路测试，包括手工测试和自动化测试两种。自动化测试速度快、程度高、测试全面，所以在大批量产品测试时获得普遍的应用，但其成本高、测试过程复杂、调试周期长。而手工测试，一般在定制的测试板上实现，通过测试人员观测灯亮、声音或仪器读表完成，手工测试适用于小批量的、简单的、非全面的快速测试。
发明内容
针对现有技术中存在的缺陷，本发明的目的在于提供一种数字逻辑自动测试装置及方法，可以有针对性的测试出待测逻辑的功能和性能，准确测出最高工作频率。
为实现上述目的，本发明采用的技术方案如下：
一种数字逻辑自动测试装置，所述测试装置包括：依次连接的输入串行寄存器、输入寄存器、测试模块、输出寄存器和输出串行寄存器；
所述输入串行寄存器用于接收通过标准JTAG接口扫入的外部数据，再并行送入所述输入寄存器；
所述输入寄存器用于将接收到的所述外部数据输入所述测试模块；
所述测试模块用于基于所述外部数据中的工作模式，根据所述外部数据 和外部输入的启动信号进行测试，测试完成后，将测试结果保存在所述输出寄存器，所述工作模式包括：单步测试模式、向量加载模式和自测试模式；
所述输出寄存器用于将所述测试结果并行输入所述输出串行寄存器；
所述输出串行寄存器用于将接收到的所述测试结果通过所述标准JTAG接口扫出。
进一步，如上所述的一种数字逻辑自动测试装置，所述输入寄存器包括：控制DFF和数据DFF，所述输出寄存器包括：输出DFF；
所述控制DFF用于将所述外部数据中的控制信息输入所述测试模块；
所述数据DFF用于将所述外部数据中的数据信息输入所述测试模块；
所述输出DFF用于将所述测试模块的测试结果输出至所述输出串行寄存器。
进一步，如上所述的一种数字逻辑自动测试装置，所述测试模块具体用于根据所述控制DFF输入的控制信息确定对应的工作模块，根据所述工作模式、所述数据DFF输入的数据信息以及外部输入的启动信号进行测试，测试完成后，将测试结果保存所述输出DFF；
所述启动信号用于判断所述控制信息和所述数据信息是否有效，当所述控制信息和所述数据信息均有效时所述测试模块开启对应的工作模式。
进一步，如上所述的一种数字逻辑自动测试装置，所述测试模块包括：测试控制器，以及与所述测试控制器连接的输入向量存储器、结果向量存储器和待测电路；
所述测试控制器用于：
当确定所述工作模式为单步测试模式时，将所述数据DFF输入的数据信息加载入所述待测电路，经所述待测电路逻辑运算后，将测试结果输出至所述输出DFF；
当确定所述工作模式为向量加载模式时，对所述数据DFF输入的数据信息进行地址解析，根据解析结果和所述数据信息中的向量类型将所述数据信息存储在所述输入向量存储器或所述结果向量存储器中；
当确定所述工作模式为自测试模式时，从所述输入向量存储器读出待测数据，经过所述待测电路逻辑运算后得到测试数据，将所述测试数据与从所述结果向量存储器中读出的结果数据进行比较，得到测试结果输出至所述输出DFF。
进一步，如上所述的一种数字逻辑自动测试装置，所述测试模块还包括：与所述测试控制器连接的第一数据选择器、第二数据选择器、第三数据选择器和第四数据选择器，所述第一数据选择器、所述第二数据选择器、所述待测电路、所述第三数据选择器和所述第四数据选择器依次连接；
所述测试控制器用于：
当确定所述工作模式为单步测试模式时，将所述数据DFF输入的数据信息依次经所述第一数据选择器、所述第二数据选择器加载入所述待测电路，经所述待测电路逻辑运算后，将测试结果依次经所述第三数据选择器、所述第四数据选择器输出至所述输出DFF。
进一步，如上所述的一种数字逻辑自动测试装置，所述第一数据选择器与所述输入向量存储器和所述结果向量存储器连接；
所述测试控制器用于：
当确定所述工作模式为向量加载模式时，对所述数据DFF输入的数据信息进行地址解析，若所述数据信息中的向量类型为输入向量，则根据解析得到的地址将所述数据信息作为待测数据经所述第一数据选择器加载入所述输入向量存储器，若所述数据信息中的向量类型为结果向量，则根据解析得到的地址将所述数据信息作为结果数据经所述第一数据选择器加载入所述结果向量存储器。
进一步，如上所述的一种数字逻辑自动测试装置，所述测试模块还包括：结果比较器，所述结果比较器与所述测试控制器、所述第三数据选择器、所述第四数据选择器和所述结果向量存储器连接；
所述测试控制器用于：
当确定所述工作模式为自测试模式时，将从所述输入向量存储器读出的 待测数据经过所述第二数据选择器加载入所述待测电路，经所述待测电路逻辑运算后得到测试数据，将所述测试数据经所述第三数据选择器输入所述结果比较器，所述结果比较器将所述测试数据与从所述结果向量存储器中读出的结果数据进行比较，得到测试结果，经所述第四数据选择器输出至所述输出DFF。
进一步，如上所述的一种数字逻辑自动测试装置，所述输入向量寄存器包括：与所述测试控制器连接的计数器；
所述测试控制器还用于：
当确定所述工作模式为自测试模式时，开启所述计数器工作，根据所述计数器生成的测试地址从所述输入向量存储器中读出待测数据进行测试，若所述测试数据与从所述结果向量存储器中读出的结果数据相同，则确定测试结果正确，根据所述计数器生成的新的测试地址进行下一个测试，直到所述输入向量存储器中的所有待测数据均测试完成，依据所述控制信息中的循环次数进行下一轮循环测试。
进一步，如上所述的一种数字逻辑自动测试装置，所述测试控制器还用于：
当确定所述工作模式为自测试模式时，若所述控制信息中的自测试DEBUG为开启状态，则当测试过程出现错误时，将所述结果向量存储器中的结果数据经所述第四数据选择器输出至所述输出DFF。
一种数字逻辑自动测试方法，所述测试方法包括：
(1)通过标准JTAG接口扫入外部数据；
(2)基于所述外部数据中的工作模式，根据所述外部数据和外部输入的启动信号进行测试，得到测试结果，所述工作模式包括：单步测试模式、向量加载模式和自测试模式。
(3)通过所述标准JTAG接口扫出所述测试结果。
本发明的有益效果在于：本发明所提供的装置及方法，可以有针对性的 测试出待测逻辑的功能和性能，准确测出最高工作频率。本发明支持自动测试、手动单步测试和测试调试功能，满足了成本、速度、程度和全面等方面的要求。
附图说明
图1为本发明实施例中提供的一种数字逻辑自动测试装置的结构示意图；
图2为本发明实施例中提供的测试模块的结构示意图；
图3为本发明实施例中提供的输入向量寄存器和结果向量寄存器的结构示意图；
图4为本发明实施例中提供的一种数字逻辑自动测试方法的流程示意图。
具体实施方式
下面结合说明书附图与具体实施方式对本发明做进一步的详细说明。
现有技术中，往往只能验证芯片整体的功能和性能，而对其内部某部分逻辑则很难正确测出最高工作频率。
针对上述缺陷，本发明采用一种增加冗余测试逻辑的方法，可以有针对性的测试出待测逻辑的功能和性能，测出最高工作频率。本发明支持自动测试、手动单步测试和测试调试功能，满足了成本、速度、程度和全面等方面的要求。
如图1所示，一种数字逻辑自动测试装置，测试装置包括：依次连接的输入串行寄存器、输入寄存器、测试模块、输出寄存器和输出串行寄存器；
输入串行寄存器用于接收通过标准JTAG接口扫入的外部数据，再并行送入输入寄存器；
输入寄存器用于将接收到的外部数据输入测试模块；
测试模块用于基于外部数据中的工作模式，根据外部数据和外部输入的启动信号进行测试，测试完成后，将测试结果保存在输出寄存器，工作模式 包括：单步测试模式、向量加载模式和自测试模式；
输出寄存器用于将测试结果并行输入输出串行寄存器；
输出串行寄存器用于将接收到的测试结果通过标准JTAG接口扫出。
输入寄存器包括：控制DFF和数据DFF，输出寄存器包括：输出DFF；
控制DFF用于将外部数据中的控制信息输入测试模块；
数据DFF用于将外部数据中的数据信息输入测试模块；
输出DFF用于将测试模块的测试结果输出至输出串行寄存器。
测试模块具体用于根据控制DFF输入的控制信息确定对应的工作模块，根据工作模式、数据DFF输入的数据信息以及外部输入的启动信号进行测试，测试完成后，将测试结果保存输出DFF；
启动信号用于判断控制信息和数据信息是否有效，当控制信息和数据信息均有效时测试模块开启对应的工作模式。
测试模块包括：测试控制器，以及与测试控制器连接的输入向量存储器、结果向量存储器和待测电路；
测试控制器用于：
当确定工作模式为单步测试模式时，将数据DFF输入的数据信息加载入待测电路，经待测电路逻辑运算后，将测试结果输出至输出DFF；
当确定工作模式为向量加载模式时，对数据DFF输入的数据信息进行地址解析，根据解析结果和数据信息中的向量类型将数据信息存储在输入向量存储器或结果向量存储器中；
当确定工作模式为自测试模式时，从输入向量存储器读出待测数据，经过待测电路逻辑运算后得到测试数据，将测试数据与从结果向量存储器中读出的结果数据进行比较，得到测试结果输出至输出DFF。
测试模块还包括：与测试控制器连接的第一数据选择器、第二数据选择器、第三数据选择器和第四数据选择器，第一数据选择器、第二数据选择器、待测电路、第三数据选择器和第四数据选择器依次连接；
测试控制器用于：
当确定工作模式为单步测试模式时，将数据DFF输入的数据信息依次经第一数据选择器、第二数据选择器加载入待测电路，经待测电路逻辑运算后，将测试结果依次经第三数据选择器、第四数据选择器输出至输出DFF。
第一数据选择器与输入向量存储器和结果向量存储器连接；
测试控制器用于：
当确定工作模式为向量加载模式时，对数据DFF输入的数据信息进行地址解析，若数据信息中的向量类型为输入向量，则根据解析得到的地址将数据信息作为待测数据经第一数据选择器加载入输入向量存储器，若数据信息中的向量类型为结果向量，则根据解析得到的地址将数据信息作为结果数据经第一数据选择器加载入结果向量存储器。
测试模块还包括：结果比较器，结果比较器与测试控制器、第三数据选择器、第四数据选择器和结果向量存储器连接；
测试控制器用于：
当确定工作模式为自测试模式时，将从输入向量存储器读出的待测数据经过第二数据选择器加载入待测电路，经待测电路逻辑运算后得到测试数据，将测试数据经第三数据选择器输入结果比较器，结果比较器将测试数据与从结果向量存储器中读出的结果数据进行比较，得到测试结果，经第四数据选择器输出至输出DFF。
输入向量寄存器包括：与测试控制器连接的计数器；
测试控制器还用于：
当确定工作模式为自测试模式时，开启计数器工作，根据计数器生成的测试地址从输入向量存储器中读出待测数据进行测试，若测试数据与从结果向量存储器中读出的结果数据相同，则确定测试结果正确，根据计数器生成的新的测试地址进行下一个测试，直到输入向量存储器中的所有待测数据均测试完成，依据控制信息中的循环次数进行下一轮循环测试。
测试控制器还用于：
当确定工作模式为自测试模式时，若控制信息中的自测试DEBUG为开启状态，则当测试过程出现错误时，将结果向量存储器中的结果数据经第四数据选择器输出至输出DFF。
本发明提出的一种数字逻辑自动测试装置支持自动测试、手动单步测试 和测试调试功能，支持时钟升频以测出最高工作频率，采用存储器保存测试向量和结果向量，可以有针对性的测试出待测逻辑的功能和性能，测出最高工作频率。
实施例一
如图1所示，本发明提供的一种数字逻辑自动测试装置包括：输入串行寄存器、输入寄存器、测试模块、输出寄存器和输出串行寄存器，外部数据经过标准JTAG接口(TMS、TCK、TDI线)控制进入输入串行寄存器，外部的高频时钟信号分别输入输入寄存器、测试模块、输出寄存器，测试完成后，测试结果保存在输出寄存器，并行直连到输出串行寄存器，同样经过标准JTAG接口(TDO线)控制输出。
标准JTAG接口包括4线：TMS、TCK、TDI、TDO，分别为模式选择、时钟、数据输入和数据输出线。
信号 位数 方向 描述
o_RespData 256 O 观测内部逻辑的响应
i_CfgCtrl 256 I 控制信号
i_CfgData 256 I 数据信号
i_CFG_TCEN 1 I 判断控制信号是否ready,可作模块启动信号
i_DATA_TCEN 1 I 判断数据信号是否ready,可作模块启动信号
表1
表1为功能测试逻辑与外部接口信号表，i_DATA_TCEN和i_CFG_TCEN位宽均为1位，作为测试逻辑(图1中测试模块)的启动信号。i_CfgCtrl位宽为256位，是外部输入到测试逻辑的控制信号，i_CfgData位宽为256位，是外部输入到测试逻辑的数据信号，o_RespData位宽为256位，用于观测测试逻辑输出到外部的响应。方向为I表示输入，方向为O表示输出。
测试模块结构：
如图2所示，本发明采用存储器来存储待测电路输入向量和结果向量。 外部接口主要有四个，其中输入为控制DFF、数据DFF和启动信号，输出为输出DFF。启动信号用于控制逻辑自测试模块的开启；控制DFF位宽为256位，用于接收外部电路控制信号，并传输到测试控制器，从而控制逻辑自测试运行；数据DFF位宽为256位，用于接收外部数据；输出DFF用于将测试结果输出。
控制DFF共256位，每位含义支持用户自定义，但必须包含五个域：复位，测试模块，工作模式，自测试DEBUG模式和循环次数，控制DFF触发器接口定义具体如表2。
Figure PCTCN2020082071-appb-000001
表2
数据DFF共256位，每位含义支持用户自定义，但必须包含四个域：测试模块，向量类型，地址和数据，数据DFF触发器接口定义具体如表3。
Figure PCTCN2020082071-appb-000002
表3
输出DFF共256位，每位含义支持用户自定义，但必须包含四个域：测试模块，向量类型，地址和数据，输出DFF触发器接口定义具体如表4。
Figure PCTCN2020082071-appb-000003
表4
测试输出指示信号的位宽为1位，包括5种指示信号，具体如表5。
序号 名称 方向 位宽 说明
1 i_CFG_TCEN I 1 判断控制信号是否ready
2 i_DATA_TCEN I 1 判断数据信号是否ready
3 i_test_en I 1 测试使能信号
4 o_test_done O 1 测试完成信号
5 o_test_fail O 1 测试报错信号
表5
如表5所示，i_DATA_TCEN和i_CFG_TCEN位宽为1，作为测试逻辑启动信号，分别判断数据信号和控制信号是否有效，如果均有效则启动测试模块。i_test_en，o_test_done，o_test_fail分别用于表示测试使能信号、测试完成信号和测试报错信号，方向为I表示输入，方向为O表示输出。
向量存储器：
向量存储器包括输入向量存储器和结果向量存储器。输入向量存储器包含一个4bit计数器，用于生成测试地址。
输入/结果向量存储器写操作：写操作对应向量加载工作模式。在测试控制器控制下，把输入数据写入到对应地址的存储条目。
输入/结果向量存储器读操作：读操作对应自测试工作模式。计数器产生测试地址，根据测试地址从输入向量存储器中读出相应数据。结果向量存储器读地址与输入向量存储器一致。
结果比较器：
结果比较器负责将待测电路输出结果与结果向量存储器加载过来的正确结果进行比较，并给出比较是否正确的信息。
测试控制器：
测试控制器负责对输入的256位控制数据进行解析，控制整个测试流程正确运行，同时负责测试结果回收。测试控制器首先对输入的控制信号进行解析，从中解析出软复位、测试模块、工作模式、自测试DEBUG和循环次数等信息(表2)。然后开启整个测试流程。
对于单步测试模式：测试控制器，选择将数据DFF进来的数据直接穿过MUX1，再穿过MUX2，进入到待测电路，经待测电路逻辑运算后，直接穿过MUX3，不进结果比较器，再穿过MUX4到输出DFF输出。测试是否正确需要人工根据输出结果判断(图2中虚线箭头指向的线路)。MUX1、MUX2、MUX3和MUX4均为数据选择器。
对于向量加载模式：测试控制器，选择将数据DFF进来的数据存储到向量存储器(图2)。地址解析模块会依据表3解析出数据是输入向量还是结果向量，解析出数据在存储器中的存储地址。如果向量类型是输入向量，则存储到输入向量存储器的相应存储地址，如果向量类型是输出向量，则存储到结果向量存储器的相应存储地址(图3)。多组向量需要通过多次加载。
对于自测试模式：自测试模式开始前，已经加载了若干组向量在输入向量存储器和结果向量存储器。如果是自测试模式，那么测试控制器开启计数器工作(图2和图3)生成测试地址，从输入向量存储器读出输入向量即待测向量(图3)，经过待测电路逻辑运算后的数据，再与从结果向量存储器中读出的结果数据进行比较，若比较相等，则测试结果正确。该过程会对向量存储器中所有有效数据进行，并且会循环若干轮次，循环次数通过控制DFF配置(表2)。
下面结合图1-3、表1-5对数据输入过程、测试过程和数据输出过程进行详细描述。
数据输入过程：图1中输入寄存器即为图2中数据DFF和控制DFF。通过JTAG标准接口把数据扫入输入串行寄存器，再并行送到输入寄存器。如果是控制信息则数据进入到控制DFF，如果是数据信息则数据进入到数据DFF。控制信息和数据信息的含义分别见表2和表3，控制信息和数据信息都进到输入寄存器后，就可以开启对应的工作模式。
测试过程：
【单步测试】当启动信号有效，此时已通过JTAG接口对控制DFF和数据DFF都写入了数据，控制DFF[253:252]位表示工作模式选择(详见表2)，如果工作模式选择单步测试，则开始单步测试。
选择测试数据DFF的数据，经过MUX1和MUX2加载到待测电路，待测电路输出经过MUX3和MUX4进入输出DFF然后输出。
【向量加载】当启动信号有效，模式选择为向量加载，逐拍将输入向量和结果向量加载到相应存储器。
通过JTAG接口对控制DFF和数据DFF都写入内容，控制DFF[253:252]位表示工作模式选择(详见表2)，如果工作模式选择为向量加载，即将输入向量和结果向量分别加载到对应的存储器。每次加载一组向量，包括输入向量和结果向量。数据在加载入存储器之前，需要进行地址解析，根据测试控制器传来的待测模块信号，判断所加载的向量类型，数据DFF[252]位表示向量类型(详见表3)。如果是输入向量，则存入输入向量存储器，如果是结果向量，则存入结果向量存储器。
【自测试】当启动信号有效，模式选择为自测试，开启对指定模块的自测试。通过JTAG接口对控制DFF写入内容，控制DFF[253:252]位表示工作模式选择(详见表2)，如果工作模式选择为自测试，则开启自测试模式。
开始测试后，通过测试控制器的控制，依次从存储器读取待测向量，经MUX2加载到待测电路，将输出数据与存储的结果比较，判断是否正确，正确则继续下一个向量测试，直到所有向量测试完成，进行下一轮循环测试。如果完成所有向量的所有循环测试，结果仍然正确，则将o_test_done信号置 为有效。如果在测试某向量时错误，则将o_test_done信号置为有效，将o_test_fail信号置为有效(表5)。循环次数由控制DFF的“循环次数”域指定(表2)。在自测试模式下，如果开启DEBUG，测试过程出错时，则将结果向量通过MUX4输出到输出DFF。
数据输出过程：测试完成后，测试结果保存在输出寄存器中，并行直连到输出串行寄存器。通过JTAG标准接口的TDO线将输出串行寄存器中的内容扫出。
本发明提出的一种数字逻辑自动测试装置支持自动测试、手动单步测试和测试调试功能，支持时钟升频以测出最高工作频率，采用存储器保存测试向量和结果向量，可以有针对性的测试出待测逻辑的功能和性能，测出最高工作频率。
如图4所示，一种数字逻辑自动测试方法，测试方法包括：
S100、通过标准JTAG接口扫入外部数据；
S200、基于外部数据中的工作模式，根据外部数据和外部输入的启动信号进行测试，得到测试结果，工作模式包括：单步测试模式、向量加载模式和自测试模式；
S300、通过标准JTAG接口扫出测试结果。
S100包括：
S101、输入串行寄存器接收通过标准JTAG接口扫入的外部数据，再并行送入输入寄存器；
S102、输入寄存器将接收到的外部数据输入测试模块；
S200包括：测试模块基于外部数据中的工作模式，根据外部数据和外部输入的启动信号进行测试，测试完成后，将测试结果保存在输出寄存器；
S300包括：
S301、输出寄存器将测试结果并行输入输出串行寄存器；
S302、输出串行寄存器将接收到的测试结果通过标准JTAG接口扫出。
输入寄存器包括：控制DFF和数据DFF，输出寄存器包括：输出DFF；
控制DFF用于将外部数据中的控制信息输入测试模块；
数据DFF用于将外部数据中的数据信息输入测试模块；
输出DFF用于将测试模块的测试结果输出至输出串行寄存器。
测试模块具体用于根据控制DFF输入的控制信息确定对应的工作模块，根据工作模式、数据DFF输入的数据信息以及外部输入的启动信号进行测试，测试完成后，将测试结果保存输出DFF；
启动信号用于判断控制信息和数据信息是否有效，当控制信息和数据信息均有效时测试模块开启对应的工作模式；
工作模式包括：单步测试模式、向量加载模式和自测试模式。
测试模块包括：测试控制器，以及与测试控制器连接的输入向量存储器、结果向量存储器和待测电路；
S200包括：测试控制器，
当确定工作模式为单步测试模式时，将数据DFF输入的数据信息加载入待测电路，经待测电路逻辑运算后，将测试结果输出至输出DFF；
当确定工作模式为向量加载模式时，对数据DFF输入的数据信息进行地址解析，根据解析结果和数据信息中的向量类型将数据信息存储在输入向量存储器或结果向量存储器中；
当确定工作模式为自测试模式时，从输入向量存储器读出待测数据，经过待测电路逻辑运算后得到测试数据，将测试数据与从结果向量存储器中读出的结果数据进行比较，得到测试结果输出至输出DFF。
测试模块还包括：与测试控制器连接的第一数据选择器、第二数据选择器、第三数据选择器和第四数据选择器，第一数据选择器、第二数据选择器、待测电路、第三数据选择器和第四数据选择器依次连接；
S200包括：测试控制器，
当确定工作模式为单步测试模式时，将数据DFF输入的数据信息依次经第一数据选择器、第二数据选择器加载入待测电路，经待测电路逻辑运算后，将测试结果依次经第三数据选择器、第四数据选择器输出至输出DFF。
第一数据选择器与输入向量存储器和结果向量存储器连接；
S200包括：测试控制器，
当确定工作模式为向量加载模式时，对数据DFF输入的数据信息进行地址解析，若数据信息中的向量类型为输入向量，则根据解析得到的地址将数据信息作为待测数据经第一数据选择器加载入输入向量存储器，若数据信息中的向量类型为结果向量，则根据解析得到的地址将数据信息作为结果数据经第一数据选择器加载入结果向量存储器。
测试模块还包括：结果比较器，结果比较器与测试控制器、第三数据选择器、第四数据选择器和结果向量存储器连接；
S200包括：测试控制器，
当确定工作模式为自测试模式时，将从输入向量存储器读出的待测数据经过第二数据选择器加载入待测电路，经待测电路逻辑运算后得到测试数据，将测试数据经第三数据选择器输入结果比较器，结果比较器将测试数据与从结果向量存储器中读出的结果数据进行比较，得到测试结果，经第四数据选择器输出至输出DFF。
输入向量寄存器包括：与测试控制器连接的计数器；
S200包括：测试控制器，
当确定工作模式为自测试模式时，开启计数器工作，根据计数器生成的测试地址从输入向量存储器中读出待测数据进行测试，若测试数据与从结果向量存储器中读出的结果数据相同，则确定测试结果正确，根据计数器生成的新的测试地址进行下一个测试，直到输入向量存储器中的所有待测数据均测试完成，依据控制信息中的循环次数进行下一轮循环测试。
S200包括：测试控制器，
当确定工作模式为自测试模式时，若控制信息中的自测试DEBUG为开启状态，则当测试过程出现错误时，将结果向量存储器中的结果数据经第四数据选择器输出至输出DFF。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其同等技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (10)

  1. 一种数字逻辑自动测试装置，其特征在于，所述测试装置包括：依次连接的输入串行寄存器、输入寄存器、测试模块、输出寄存器和输出串行寄存器；
    所述输入串行寄存器用于接收通过标准JTAG接口扫入的外部数据，再并行送入所述输入寄存器；
    所述输入寄存器用于将接收到的所述外部数据输入所述测试模块；
    所述测试模块用于基于所述外部数据中的工作模式，根据所述外部数据和外部输入的启动信号进行测试，测试完成后，将测试结果保存在所述输出寄存器，所述工作模式包括：单步测试模式、向量加载模式和自测试模式；
    所述输出寄存器用于将所述测试结果并行输入所述输出串行寄存器；
    所述输出串行寄存器用于将接收到的所述测试结果通过所述标准JTAG接口扫出。
  2. 根据权利要求1所述的一种数字逻辑自动测试装置，其特征在于，所述输入寄存器包括：控制DFF和数据DFF，所述输出寄存器包括：输出DFF；
    所述控制DFF用于将所述外部数据中的控制信息输入所述测试模块；
    所述数据DFF用于将所述外部数据中的数据信息输入所述测试模块；
    所述输出DFF用于将所述测试模块的测试结果输出至所述输出串行寄存器。
  3. 根据权利要求2所述的一种数字逻辑自动测试装置，其特征在于，所述测试模块具体用于根据所述控制DFF输入的控制信息确定对应的工作模块，根据所述工作模式、所述数据DFF输入的数据信息以及外部输入的启动信号进行测试，测试完成后，将测试结果保存所述输出DFF；
    所述启动信号用于判断所述控制信息和所述数据信息是否有效，当所述控制信息和所述数据信息均有效时所述测试模块开启对应的工作模式。
  4. 根据权利要求3所述的一种数字逻辑自动测试装置，其特征在于，所 述测试模块包括：测试控制器，以及与所述测试控制器连接的输入向量存储器、结果向量存储器和待测电路；
    所述测试控制器用于：
    当确定所述工作模式为单步测试模式时，将所述数据DFF输入的数据信息加载入所述待测电路，经所述待测电路逻辑运算后，将测试结果输出至所述输出DFF；
    当确定所述工作模式为向量加载模式时，对所述数据DFF输入的数据信息进行地址解析，根据解析结果和所述数据信息中的向量类型将所述数据信息存储在所述输入向量存储器或所述结果向量存储器中；
    当确定所述工作模式为自测试模式时，从所述输入向量存储器读出待测数据，经过所述待测电路逻辑运算后得到测试数据，将所述测试数据与从所述结果向量存储器中读出的结果数据进行比较，得到测试结果输出至所述输出DFF。
  5. 根据权利要求4所述的一种数字逻辑自动测试装置，其特征在于，所述测试模块还包括：与所述测试控制器连接的第一数据选择器、第二数据选择器、第三数据选择器和第四数据选择器，所述第一数据选择器、所述第二数据选择器、所述待测电路、所述第三数据选择器和所述第四数据选择器依次连接；
    所述测试控制器用于：
    当确定所述工作模式为单步测试模式时，将所述数据DFF输入的数据信息依次经所述第一数据选择器、所述第二数据选择器加载入所述待测电路，经所述待测电路逻辑运算后，将测试结果依次经所述第三数据选择器、所述第四数据选择器输出至所述输出DFF。
  6. 根据权利要求5所述的一种数字逻辑自动测试装置，其特征在于，所述第一数据选择器与所述输入向量存储器和所述结果向量存储器连接；
    所述测试控制器用于：
    当确定所述工作模式为向量加载模式时，对所述数据DFF输入的数据信息进行地址解析，若所述数据信息中的向量类型为输入向量，则根据解析得 到的地址将所述数据信息作为待测数据经所述第一数据选择器加载入所述输入向量存储器，若所述数据信息中的向量类型为结果向量，则根据解析得到的地址将所述数据信息作为结果数据经所述第一数据选择器加载入所述结果向量存储器。
  7. 根据权利要求5所述的一种数字逻辑自动测试装置，其特征在于，所述测试模块还包括：结果比较器，所述结果比较器与所述测试控制器、所述第三数据选择器、所述第四数据选择器和所述结果向量存储器连接；
    所述测试控制器用于：
    当确定所述工作模式为自测试模式时，将从所述输入向量存储器读出的待测数据经过所述第二数据选择器加载入所述待测电路，经所述待测电路逻辑运算后得到测试数据，将所述测试数据经所述第三数据选择器输入所述结果比较器，所述结果比较器将所述测试数据与从所述结果向量存储器中读出的结果数据进行比较，得到测试结果，经所述第四数据选择器输出至所述输出DFF。
  8. 根据权利要求7所述的一种数字逻辑自动测试装置，其特征在于，所述输入向量寄存器包括：与所述测试控制器连接的计数器；
    所述测试控制器还用于：
    当确定所述工作模式为自测试模式时，开启所述计数器工作，根据所述计数器生成的测试地址从所述输入向量存储器中读出待测数据进行测试，若所述测试数据与从所述结果向量存储器中读出的结果数据相同，则确定测试结果正确，根据所述计数器生成的新的测试地址进行下一个测试，直到所述输入向量存储器中的所有待测数据均测试完成，依据所述控制信息中的循环次数进行下一轮循环测试。
  9. 根据权利要求5至8任一项所述的一种数字逻辑自动测试装置，其特征在于，所述测试控制器还用于：
    当确定所述工作模式为自测试模式时，若所述控制信息中的自测试DEBUG为开启状态，则当测试过程出现错误时，将所述结果向量存储器中的 结果数据经所述第四数据选择器输出至所述输出DFF。
  10. 一种数字逻辑自动测试方法，其特征在于，所述测试方法包括：
    (1)通过标准JTAG接口扫入外部数据；
    (2)基于所述外部数据中的工作模式，根据所述外部数据和外部输入的启动信号进行测试，得到测试结果，所述工作模式包括：单步测试模式、向量加载模式和自测试模式。
    (3)通过所述标准JTAG接口扫出所述测试结果。
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CN110750086B (zh) * 2019-09-02 2020-11-17 芯创智（北京）微电子有限公司 一种数字逻辑自动测试装置及方法
CN111709203B (zh) * 2020-05-09 2023-08-15 芯创智（北京）微电子有限公司 一种面向维护系统星型拓扑结构的fpga优化方法及系统
CN112305411A (zh) * 2020-11-23 2021-02-02 珠海市一微半导体有限公司 一种i2s接口的功能测试电路及测试方法
CN117289114A (zh) * 2023-10-10 2023-12-26 苏州异格技术有限公司 一种逻辑功能测试电路及测试方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1178321A2 (de) * 2000-08-03 2002-02-06 Siemens Aktiengesellschaft Verfahren zum Betreiben eines Logik- und Speicherelemente aufweisenden Bausteins
US20020138157A1 (en) * 2001-03-20 2002-09-26 International Business Machines Corporation Clock controller for AC self-test timing analysis of logic system
WO2003010612A2 (en) * 2001-07-24 2003-02-06 University Of Delhi Multifunction interface device for use, inter alia, in laboratory procedures
CN102401876A (zh) * 2010-09-17 2012-04-04 深圳安博电子有限公司 一种光电集成电路芯片的测试系统和测试方法
CN102540060A (zh) * 2010-12-27 2012-07-04 北京中电华大电子设计有限责任公司 一种数字集成电路芯片测试系统
CN103163451A (zh) * 2013-03-06 2013-06-19 中国人民解放军国防科学技术大学 面向超级计算系统的自选通边界扫描调测试方法及装置
CN108072827A (zh) * 2016-11-18 2018-05-25 瑞士优北罗股份有限公司 有自测试能力的集成电路装置和对集成电路自测试的方法
CN110750086A (zh) * 2019-09-02 2020-02-04 芯创智（北京）微电子有限公司 一种数字逻辑自动测试装置及方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7313740B2 (en) * 2002-07-25 2007-12-25 Inapac Technology, Inc. Internally generating patterns for testing in an integrated circuit device
CN100365584C (zh) * 2003-07-28 2008-01-30 华为技术有限公司 一种边界扫描测试的实现方法及装置
US7395471B2 (en) * 2004-06-17 2008-07-01 Texas Instruments Incorporated Connection of auxiliary circuitry to tap and instruction register controls
US7322000B2 (en) * 2005-04-29 2008-01-22 Freescale Semiconductor, Inc. Methods and apparatus for extending semiconductor chip testing with boundary scan registers
CN105004984A (zh) * 2015-06-25 2015-10-28 深圳市芯海科技有限公司 一种自动化芯片测试方法
CN105572565B (zh) * 2015-12-23 2018-08-24 中国电子科技集团公司第五十八研究所 适用于1553总线协议的内建自测试电路
CN105929818B (zh) * 2016-07-05 2020-03-06 深圳市博巨兴微电子科技有限公司 一种微控制器soc内建io映射测试装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1178321A2 (de) * 2000-08-03 2002-02-06 Siemens Aktiengesellschaft Verfahren zum Betreiben eines Logik- und Speicherelemente aufweisenden Bausteins
US20020138157A1 (en) * 2001-03-20 2002-09-26 International Business Machines Corporation Clock controller for AC self-test timing analysis of logic system
WO2003010612A2 (en) * 2001-07-24 2003-02-06 University Of Delhi Multifunction interface device for use, inter alia, in laboratory procedures
CN102401876A (zh) * 2010-09-17 2012-04-04 深圳安博电子有限公司 一种光电集成电路芯片的测试系统和测试方法
CN102540060A (zh) * 2010-12-27 2012-07-04 北京中电华大电子设计有限责任公司 一种数字集成电路芯片测试系统
CN103163451A (zh) * 2013-03-06 2013-06-19 中国人民解放军国防科学技术大学 面向超级计算系统的自选通边界扫描调测试方法及装置
CN108072827A (zh) * 2016-11-18 2018-05-25 瑞士优北罗股份有限公司 有自测试能力的集成电路装置和对集成电路自测试的方法
CN110750086A (zh) * 2019-09-02 2020-02-04 芯创智（北京）微电子有限公司 一种数字逻辑自动测试装置及方法

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