WO2021042231A1 - 用于像素阵列的信号处理电路和方法以及图像传感器 - Google Patents

用于像素阵列的信号处理电路和方法以及图像传感器 Download PDF

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Publication number
WO2021042231A1
WO2021042231A1 PCT/CN2019/103944 CN2019103944W WO2021042231A1 WO 2021042231 A1 WO2021042231 A1 WO 2021042231A1 CN 2019103944 W CN2019103944 W CN 2019103944W WO 2021042231 A1 WO2021042231 A1 WO 2021042231A1
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signal
circuit
pixel
ramp
coupled
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PCT/CN2019/103944
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English (en)
French (fr)
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徐荣贵
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深圳市汇顶科技股份有限公司
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Priority to CN201980001720.0A priority Critical patent/CN110720212B/zh
Priority to PCT/CN2019/103944 priority patent/WO2021042231A1/zh
Publication of WO2021042231A1 publication Critical patent/WO2021042231A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/63—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array

Definitions

  • the present disclosure relates to pixel signal processing technology, and more particularly to a signal processing circuit and signal processing method for a pixel array, and related image sensors.
  • the pixel array of the image sensor adopting active noise reduction includes active pixels (active pixels) and dark pixels (dark pixels).
  • the image sensor samples the active pixel signal generated by the active pixel and the dark pixel signal generated by the dark pixel, and subtracts the sampling result of the dark pixel from the sampling result of the active pixel signal to reduce the sampling result of the active pixel signal.
  • Noise information since the noise interference received by the pixel array changes with time, and the image sensor samples the dark pixel signal and the active pixel signal at different time points, the noise information carried by the sampling result of the dark pixel signal is different from the active pixel signal. The noise information carried by the signal sampling results is quite different, resulting in limited noise reduction effects.
  • One of the objectives of the present disclosure is to provide a signal processing circuit and a signal processing method for a pixel array, and a related image sensor, to solve the above-mentioned problems.
  • An embodiment of the present disclosure provides a signal processing circuit for a pixel array.
  • the signal processing circuit includes a signal generating circuit, a comparing circuit and a counting circuit.
  • the signal generating circuit is used for generating a second ramp signal according to a first ramp signal and N first pixel signals output by the pixel array, where N is a positive integer, and the second ramp signal includes the Nth Noise information carried by a pixel signal.
  • the comparison circuit is coupled to the signal generation circuit and used for comparing a second pixel signal output by the pixel array with the second ramp signal to generate a comparison signal.
  • the counting circuit is coupled to the comparison circuit for generating the count value of the second pixel signal according to the comparison signal.
  • An embodiment of the present disclosure provides an image sensor.
  • the image sensor includes a pixel array and a signal processing circuit.
  • the pixel array includes a plurality of active pixels and a plurality of dark pixels.
  • the signal processing circuit is coupled to the pixel array and includes a signal generating circuit, a first comparing circuit, a second comparing circuit, a first counting circuit, and a second counting circuit.
  • the signal generating circuit is used for generating a second ramp signal according to a first ramp signal and N dark pixel signals respectively output by N dark pixels in the plurality of dark pixels, where N is a positive integer, and the second ramp signal
  • the ramp signal includes noise information carried by the N dark pixel signals.
  • the first comparison circuit is coupled to at least one active pixel of the plurality of active pixels and the signal generating circuit, and is used to compare an active pixel signal output by the active pixel with the second
  • the ramp signals are compared to generate a first comparison signal.
  • the second comparison circuit is coupled to at least one dark pixel of the N dark pixels and the signal generating circuit, and is used to compare a dark pixel signal output by the dark pixel with the second ramp signal , To generate a second comparison signal.
  • the first counting circuit is coupled to the first comparing circuit, and is configured to generate a count value of the active pixel signal according to the first comparison signal.
  • the second counting circuit is coupled to the second comparison circuit and used for generating the count value of the dark pixel signal according to the second comparison signal.
  • An embodiment of the present disclosure provides a signal processing method for a pixel array.
  • the signal processing method includes: generating a second ramp signal according to a first ramp signal and N first pixel signals output by the pixel array, where N is a positive integer, and the second ramp signal includes the N th Noise information carried by a pixel signal; comparing a second pixel signal output by the pixel array with the second ramp signal to generate a comparison signal; and generating the second pixel signal according to the comparison signal Count value.
  • FIG. 1 is a functional block diagram of an embodiment of the image sensor of the present disclosure.
  • FIG. 2 is a schematic diagram of an embodiment of at least a part of the signal processing circuit shown in FIG. 1.
  • FIG. 3 is a flowchart of an embodiment of the signal processing method of the pixel array of the present disclosure.
  • FIG. 1 is a functional block diagram of an embodiment of the image sensor of the present disclosure.
  • the image sensor 100 may include (but is not limited to) a pixel array 110, a control circuit 120, and a signal processing circuit 130.
  • the pixel array 110 includes a plurality of active pixels (also referred to as active pixels) arranged in M rows and R columns.
  • Source pixel unit or active pixel circuit) P 1,1 -P M,R and multiple dark pixels arranged in M rows and Q columns (also called dark pixel units or dark pixel circuits) P 1,R+1 -P M,R+Q , where M, R and Q are all positive integers greater than 1.
  • a plurality of dark pixels P 1,R+1 -P M,R+Q may be arranged on one side of the pixel array 110 (such as the right side of the plurality of active pixels P 1,1 -P M,R). Side), however, the present disclosure is not limited to this.
  • a plurality of dark pixels P 1,R+1 -PM ,R+Q may be disposed on the other side of the pixel array 110 (such as the left side of the plurality of active pixels P 1,1 -PM ,R).
  • a part of the plurality of dark pixels P 1,R+1 -P M,R+Q may be arranged on one side of the pixel array 110, and the plurality of dark pixels P 1,R+1 -P M,R+Q The other part may be provided on the other side of the pixel array 110.
  • the control circuit 120 is coupled to the pixel array 110 to control operations related to each pixel in the pixel array 110 (such as charge transfer, signal reset, signal amplification and/or readout operations), so that each pixel generates a corresponding pixel signal, such as One of the plurality of active pixel signals APS 1 -APS R or one of the plurality of dark pixel signals DPS 1 -DPS Q.
  • the signal processing circuit 130 is coupled to the pixel array 110 to compensate the active pixel signal output by the one or more active pixels according to the dark pixel signal output by the one or more dark pixels.
  • the signal processing circuit 130 can also sample the pixel signal output by the pixel array 110 according to the ramp signal carrying pixel noise, so as to reduce/eliminate the noise information carried by the pixel signal in real time.
  • the pixel noise can be dark. The noise information carried by the pixel signal, or the noise information carried by the active pixel signal.
  • the signal processing circuit 130 may use a successive approximation register ADC (SAR ADC) or other types of analog-to-digital converters to implement a column-parallel analog-to-digital conversion structure.
  • the signal processing circuit 130 may adopt a pixel-parallel ADC architecture to process pixel signals.
  • the signal processing circuit 130 includes (but is not limited to) a signal generating circuit 132, a plurality of comparison circuits 134 1 -134 R+Q, and a plurality of counting circuits 136 1 -136 R+Q .
  • the signal generating circuit 132 is used for generating a second ramp signal VR2 according to a first ramp signal VR1 and N first pixel signals (N is a positive integer) output by the pixel array 110, wherein the second ramp signal VR2 includes the N first pixel signals. Noise information carried by a pixel signal.
  • the first ramp signal VR1 can be generated by (but not limited to) a ramp generator (not shown in FIG. 1).
  • the N first pixel signals may be each of the N dark pixels included in the pixel array 110 (for example, the N dark pixels in the same row among the plurality of dark pixels P 1, R+1- PM , R+Q). Generated N dark pixel signals.
  • the signal generating circuit 132 may couple the N first pixel signals to the first ramp signal VR1, so that the second ramp signal VR2 includes the noise information carried by the N first pixel signals.
  • the signal generating circuit 132 may perform preprocessing (such as signal coupling or signal averaging) on the N first pixel signals to combine (or couple) the N first pixel signals into a preprocessed signal, And coupling/superimposing the preprocessed signal to the first ramp signal VR1.
  • Each comparison circuit of the plurality of comparison circuits 134 1 -134 R+Q is coupled to the signal generation circuit 132 for comparing a second pixel signal output by the pixel array 110 with the second ramp signal VR2 to generate a Compare signals.
  • the comparator circuit is coupled to each of the active pixels (a plurality of comparator circuits 134 1 -134 R therein) may be referred to as a first comparator circuit, which may be an active pixel signals (a plurality of active pixel One of the signals APS 1 -APS R ) is compared with the second ramp signal VR2 to generate a first comparison signal (one of a plurality of comparison signals CR 1 -CR R ).
  • each comparison circuit (one of a plurality of comparison circuits 134 R+ 1-134 R+Q ) coupled to a dark pixel can be called a second comparison circuit, which can convert the dark pixel signal (a plurality of dark pixels One of the signals DPS 1 -DPS Q ) is compared with the second ramp signal VR2 to generate a second comparison signal (one of a plurality of comparison signals CR R+1 -CR R+Q ).
  • Each of the plurality of counting circuits 136 1 -136 R+Q is coupled to a corresponding comparison circuit for generating a corresponding count value of the second pixel signal according to the corresponding comparison signal (multiple count values CT 1- One of CT R+Q ).
  • each counter circuit (counter circuit wherein one of the plurality 136 1 -136 R) coupled to the first comparator circuit may be referred to as a first counting circuit, which can produce the active according to a corresponding first comparison signal The count value of the pixel signal.
  • each counter circuit (one of the plurality of counter circuits 136 R+ 1-136 R+Q ) coupled to the second comparison circuit can be referred to as a second counter circuit, which can be based on the corresponding second comparison signal Generates the count value of the dark pixel signal.
  • control circuit 120 can control the pixel array 110 to read out pixel signals of multiple pixels located in the same row row by row, as multiple active pixel signals APS 1 -APS R and multiple dark pixel signals DPS 1 -DPS Q .
  • the signal generating circuit 132 may generate a second ramp signal VR2 according to the first ramp signal VR1 and N dark pixel signals in the plurality of dark pixel signals DPS 1 -DPS Q , which may carry noise information of the N dark pixel signals.
  • a plurality of comparator circuits comparing circuit 1341-134 each R may be in an active pixel signal VR2 of the second ramp signal is compared to generate a comparison signal.
  • the comparison circuit 134 1 when the comparison signal CR 1 indicates that the signal level of the second ramp signal VR2 reaches the signal level of the active pixel signal APS 1 , it is generated by the counter circuit 136 1 coupled to the comparison circuit 134 1 .
  • the count value CT 1 can be used as the count result of the active pixel signal APS 1 or the analog-to-digital conversion result.
  • the comparison circuit 134 1 can compare the active pixel signal APS 1 with the second ramp signal VR2.
  • the time-varying noise information included in the active pixel signal APS 1 and the N dark pixel signals is subtracted in real time, which may be referred to as common mode noise.
  • the time-varying noise information in the comparison signal CR 1 can be greatly reduced, so that the counting circuit 136 1 can generate a counting result obtained by subtracting the time-varying noise information from the active pixel signal.
  • each of the plurality of comparison circuits 134 R+ 1-134 R+Q can compare a dark pixel signal with the second ramp signal VR2 to generate a comparison signal.
  • the comparison circuit 134 R+1 as an example, when the comparison signal CR R+1 indicates that the signal level of the second ramp signal VR2 reaches the signal level of the dark pixel signal DPS 1 , the counter is coupled to the comparison circuit 134 R+1 circuit 136 R + 1 generated count value CT R + 1 can be used as the dark pixel signal DPS analog to digital conversion result 1.
  • the comparison circuit 134 R+1 can be real-time The noise information that changes with time in the dark pixel signal DPS 1 is deducted.
  • the time-varying noise information in the comparison signal CR R+1 can be greatly reduced, so that the counting circuit 136 R+1 can generate a counting result obtained by subtracting the time-varying noise information from the dark pixel signal.
  • the multiple comparison circuits 134 1 -134 R can deduct the noise information included in the active pixel signal and the dark pixel signal in real time, therefore, the multiple comparison signals CR 1 -CR R have been deducted in real time. Comparison result of noise information. Multiple count values CT 1 -CT R can be used as the sampling result of active noise reduction without deducting the count value of the dark pixel signal.
  • the signal processing scheme of the present disclosure will be described below in conjunction with the corresponding comparison circuit and counter circuit of the active pixel column and the dark pixel column in the pixel array 110 shown in FIG. 1.
  • the present disclosure is not limited to this. As long as it is a signal processing circuit that can copy/couple at least one pixel signal to the ramp signal to subtract the time-varying noise information in the pixel signal in real time, design-related alternatives are all included in the scope of the present disclosure.
  • FIG. 2 is a schematic diagram of an embodiment of at least a part of the signal processing circuit 130 shown in FIG. 1.
  • the signal processing circuit 230 includes (but is not limited to) a signal generating circuit 232, a plurality of comparison circuits 234X and 234Y, and a plurality of counting circuits 236X and 236Y.
  • the signal generating circuit 232 may be an embodiment of the signal generating circuit 132 shown in FIG. 1.
  • the comparison circuit 234X may be an embodiment of at least one comparison circuit among the comparison circuits 134 1 -134 R shown in FIG. 1.
  • the comparison circuit 234Y may be an embodiment of at least one comparison circuit among the comparison circuits 134 R+ 1-134 R+Q shown in FIG. 1.
  • the counting circuit 236X may be an embodiment of at least one of the counting circuits 136 1 -136 R shown in FIG. 1.
  • the counting circuit 236X may be an embodiment of at least one of the counting circuits 136 R+ 1-136 R+Q shown in FIG. 1.
  • the signal generating circuit 232 includes (but is not limited to) a ramp generator 242, a preprocessing circuit 244, and a signal coupling circuit 246.
  • the ramp generator 242 is used to generate the first ramp signal VR1.
  • the ramp generator 242 can be controlled by the control circuit 120 shown in FIG. 1. In some embodiments, it is also feasible to arrange the ramp generator 242 outside the signal generating circuit 232.
  • the preprocessing circuit 244 is used to combine (or couple) the N first pixel signals output by the pixel array 110 shown in FIG. 1 into a preprocessing signal PPS, where the preprocessing signal PPS may include the N first pixel signals Carry noise information.
  • the N first pixel signals can be implemented by (but not limited to) N dark pixel signals among the plurality of dark pixel signals DPS 1 -DPS Q.
  • the N dark pixel signals may be labeled DPS 1 -DPS N.
  • the pre-processing circuit 244 may copy N dark pixel signals DPS 1 -DPS N to generate a pre-processed signal PPS, where the pre-processed signal PPS may include N dark pixel signals DPS 1- Noise information carried by DPS N.
  • the preprocessing circuit 244 may perform an averaging operation on the respective noise levels of the N dark pixel signals DPS 1 -DPS N to generate the preprocessing signal PPS, where the noise level of the preprocessing signal PPS is based on the N dark pixel signals DPS 1 -DPS N are determined by the average of the respective noise levels. Therefore, the preprocessed signal PPS may include the noise information carried by the N dark pixel signals DPS 1 -DPS N.
  • the preprocessing circuit 244 includes (but is not limited to) N first capacitors C1-CN and a second capacitor Ca.
  • the N first capacitors C1-CN are respectively coupled to the N dark pixel signals DPS 1 -DPS N , wherein each first capacitor is coupled between the corresponding dark pixel signal and the first terminal TC1 of the second capacitor Ca .
  • the second terminal TC2 of the second capacitor Ca can be coupled to a reference terminal TR (such as a ground terminal).
  • the signal coupling circuit 246 is coupled to the ramp generator 242 and the preprocessing circuit 244 for coupling the preprocessing signal PPS to the first ramp signal VR1 to generate the second ramp signal VR2.
  • the signal coupling circuit 246 may couple or superimpose the preprocessing signal PPS to the first ramp signal VR1, so that the second ramp signal VR2 includes N dark pixel signals DPS 1 -DPS N. Noise information.
  • the first input terminal IN61 of the signal coupling circuit 246 is used to receive the first ramp signal VR1, and the second input terminal IN62 of the signal coupling circuit 246 is used to receive the preprocessing signal PPS.
  • the second input terminal IN62 of the signal coupling circuit 246 is coupled to one end of each of the N first capacitors C1-CN and the first terminal TC1 of the second capacitor Ca to receive the preprocessing signal PPS.
  • the output terminal OUT6 of the signal coupling circuit 246 is used to output the second ramp signal VR2.
  • the signal coupling circuit 246 can be implemented by (but not limited to) a gain stage, and can include a first resistor R1, an amplifier 247, and a second resistor R2.
  • the first input terminal IN71 of the amplifier 247 is coupled to the first ramp signal VR1 through the first resistor R1, and the second input terminal IN72 of the amplifier 247 can be used as the second input terminal IN62 of the signal coupling circuit 246.
  • the output terminal OUT7 of the amplifier 247 can be used as the output terminal OUT6 of the signal coupling circuit 246.
  • the second resistor R2 is coupled between the first input terminal IN71 and the output terminal OUT7 of the amplifier 247.
  • the comparison circuit 234X can be implemented by a differential comparator to compare an active pixel signal APSX (one of a plurality of active pixel signals APS 1 -APS R ) with a second ramp signal VR2 to generate A comparison signal CRX.
  • the comparison circuit 234X may be coupled to the active pixel signal APSX through the coupling capacitor CXN to receive the AC signal component of the active pixel signal APSX.
  • the comparison circuit 234X can be coupled to the second ramp signal VR2 through the coupling capacitor CXP to receive the AC signal component of the second ramp signal VR2.
  • the comparison circuit 234Y can be implemented by a differential comparator to compare a dark pixel signal DPSY (one of a plurality of dark pixel signals DPS 1 -DPS Q ) with the second ramp signal VR2 to generate a comparison signal CRY.
  • the comparison circuit 234Y may be coupled to the dark pixel signal DPSY and the second ramp signal VR2 through the coupling capacitor CYN and the coupling capacitor CYP, respectively, to receive the AC signal components of the dark pixel signal DPSY and the second ramp signal VR2.
  • the dark pixel signal DPSY may be one of N dark pixel signals DPS 1 -DPS N.
  • the signal processing circuit 230 may further include a switch 248 coupled between a reference voltage Vref and the second input terminal IN62 of the signal coupling circuit 246.
  • the switch 248 is used to reset the second input terminal IN62 to the reference voltage Vref.
  • the switch 248 can reset the second input terminal IN62 to the reference voltage Vref, thereby resetting the voltage of the output terminal OUT6 of the signal coupling circuit 246.
  • the switch 248 can be turned off, and the signal processing circuit 230 can perform related processing on the active pixel signal APSX and the dark pixel signal DPSY.
  • the preprocessing circuit 244 can generate the preprocessing signal PPS by using the N first capacitors C1-CN and the second capacitor Ca, so that the signal coupling circuit 246 can generate a second ramp carrying noise information of the N dark pixel signals DPS 1 -DPS N Signal VR2.
  • the second ramp signal VR2 can be expressed by the following formula:
  • C[1]-C[N] can respectively represent the capacitance value of N first capacitors C1-CN
  • C[a] can represent the capacitance value of the second capacitor Ca
  • p[1]-p[N] It can respectively represent the signal values of N dark pixel signals DPS 1 -DPS N.
  • the second ramp signal VR2 includes real-time noise information carried by N dark pixel signals DPS 1 -DPS N.
  • the comparison circuit 234X can subtract the time-varying noise information jointly included in the active pixel signal APSX and the N dark pixel signals DPS 1 -DPS N in real time.
  • the signal value p[i] (i is a positive integer less than or equal to N) of a certain dark pixel signal DPS i among the N dark pixel signals DPS 1 -DPS N can be determined by Expression:
  • Vncm can represent the noise level of the noise (such as common mode noise) included in the active pixel signal and the dark pixel signal (which can change dynamically with time), and Vn[i] can represent other noises in the dark pixel signal DPS i The noise level (which can change dynamically over time).
  • the second ramp signal VR2 can be expressed by the following formula:
  • the second ramp signal VR2 can be further expressed as follows:
  • Vn can represent the corresponding effective value of N noise levels Vn[1]-Vn[N]:
  • the comparison circuit 234X can subtract the noise level Vncm of the noise included in the active pixel signal APSX and the dark pixel signal in real time. It is noted that, when the number of pixels used to replicate the noise information dark pixel signals (i.e., N dark pixel number signals DPS 1 -DPS N number signal N) is large enough, the signal component of the second ramp signal VR2 Compared with the signal component (Vncm-VR1), it is negligible, so that the comparison circuit 234X can deduct most (or all) noise information generated by the pixel noise in the active pixel signal APSX.
  • the comparison circuit 234Y can subtract the time-varying noise information jointly included in the dark pixel signal DPSY and the N dark pixel signals DPS 1 -DPS N in real time. For example, when the second ramp signal VR2 reaches the signal level of the dark pixel signal DPSY, the comparison circuit 234Y can subtract the noise level Vncm of the dark pixel signal in real time.
  • the comparing circuit 234Y can deduct the dark pixel because the pixel signal noise DPSY Most (or all) noise information generated. That is, when the second ramp signal VR2 reaches the signal level of the dark pixel signal DPSY, the signal level of the comparison signal CRY may be equal to or substantially equal to zero.
  • the signal processing circuit 230 can deduct the noise information jointly included in the active pixel signal and the dark pixel signal in real time, even if the signal processing circuit 230 samples the active pixel signal APSX and the dark pixel signal at different time points, respectively.
  • the signal DPSY that is, the signal level of the comparison signal CRX and the signal level of the comparison signal CRY are inverted at different points in time
  • the comparison signal CRX and the comparison signal CRY have been deducted (or almost deducted) from the noise information that changes with time.
  • both the count value CTX and the count value CTY have been deducted (or almost deducted) from the noise information that changes with time.
  • the signal processing circuit 230 since the count value CTX generated by the counting circuit 236X has been subtracted (or almost subtracted) from the noise information included in the active pixel signal and the dark pixel signal, the signal processing circuit 230 does not need to combine the count value CTX and the count value CTY. Subtract to perform digital ANC (digital ANC). In other words, the signal processing circuit 230 is a signal processing circuit that can perform analog ANC operations.
  • the N dark pixel signals DPS 1 -DPS N can also be used to eliminate/reduce noise information in other dark pixel signals.
  • the dark pixel signal DPSY coupled to the comparison circuit 234Y may be any one of the dark pixel signals DPS 1 -DPS Q shown in FIG. 1.
  • At least one active pixel signal may also be used to replicate the noise information jointly included in the active pixel signal and the dark pixel signal.
  • the N signals of a plurality of active pixels active pixel APS 1 -APS R signal preprocessing circuit 244 shown in FIG. 1 may be pretreated in order to the N number of active pixel signals into pre The processing signal PPS, where the preprocessing signal PPS may include noise information carried by the N active pixel signals.
  • the preprocessing circuit 244 can adopt other different circuit structures to generate the preprocessing signal PPS carrying pixel noise information.
  • the signal coupling circuit 246 may adopt other different circuit structures to couple/superimpose the pre-processing signal PPS to the first ramp signal VR1.
  • the signal coupling circuit 246 can directly superimpose the preprocessing signal PPS to the first ramp signal VR1.
  • FIG. 3 is a flowchart of an embodiment of the signal processing method of the pixel array of the present disclosure. If the results obtained are substantially the same, the steps do not have to be performed in the order shown in FIG. 3. For example, certain steps can be inserted in it.
  • the signal processing method shown in FIG. 3 will be described below in conjunction with the signal processing circuit 230 shown in FIG. 2. However, it is feasible to apply the signal processing method shown in FIG. 3 to other signal processing circuits (such as the signal processing circuit 130 shown in FIG. 1).
  • the signal processing method shown in Figure 3 can be briefly summarized as follows.
  • Step 302 Generate a second ramp signal according to a first ramp signal and N first pixel signals output by the pixel array, where N is a positive integer, and the second ramp signal includes the N first pixel signals carrying Noise information.
  • the signal generating circuit 232 generates the second ramp signal VR2 according to the first ramp signal VR1 and the N dark pixel signals DPS 1 -DPS N.
  • Step 304 Compare a second pixel signal output by the pixel array with the second ramp signal to generate a comparison signal.
  • the comparison circuit 234X compares the active pixel signal APSX with the second ramp signal VR2 to generate the comparison signal CRX.
  • the comparison circuit 234Y compares the dark pixel signal DPSY with the second ramp signal VR2 to generate a comparison signal CRY.
  • Step 306 Generate a count value of the second pixel signal according to the comparison signal.
  • the counting circuit 236X generates the count value CTX of the active pixel signal APSX according to the comparison signal CRX.
  • the counting circuit 236Y generates the count value CTY of the dark pixel signal DPSY according to the comparison signal CRY.
  • an averaging operation may be performed on the respective noise levels of the N first pixel signals to generate a preprocessed signal, thereby coupling the preprocessed signal to the first ramp Signal to generate the second ramp signal.
  • the preprocessing circuit 244 may use a plurality of first capacitors C1-CN and second capacitors Ca to perform an average operation on the respective noise levels of the N dark pixel signals DPS 1 -DPS N to replicate the N dark pixel signals DPS. 1- DPS N noise information, thereby generating the preprocessed signal PPS.
  • the signal coupling circuit 246 may couple the pre-processing signal PPS to the first ramp signal VR1 to generate the second ramp signal VR2.
  • the second pixel signal used in step 304 may be at least one pixel signal of the N first pixel signals used in step 302.

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Abstract

本公开提供一种用于像素阵列的信号处理电路和信号处理方法以及图像传感器。所述信号处理电路(230)包括信号产生电路(232)、比较电路(234X)以及计数电路(236X)。所述信号产生电路用以根据第一斜坡信号和所述像素阵列输出的N个第一像素信号产生第二斜坡信号，其中N是正整数，所述第二斜坡信号包括所述N个第一像素信号携带的噪声信息。所述比较电路耦接到所述信号产生电路，用以将所述像素阵列输出的第二像素信号与所述第二斜坡信号作比较，以产生比较信号。所述计数电路耦接到所述比较电路，用以根据所述比较信号产生所述第二像素信号的计数值。所述信号处理电路可实时地扣除有源像素信号与暗像素信号共同包括的噪声信息。

Description

用于像素阵列的信号处理电路和方法以及图像传感器 技术领域
本公开涉及像素信号处理技术，尤其涉及一种用于像素阵列的信号处理电路和信号处理方法，及其相关的图像传感器。
背景技术
采用主动降噪(active noise reduction，ANC)的图像传感器的像素阵列包括有源像素(active pixel)和暗像素(dark pixel)。图像传感器分别对有源像素产生的有源像素信号以及暗像素产生的暗像素信号进行采样，并将有源像素信号的采样结果扣除暗像素的采样结果，以减少有源像素信号的采样结果包括的噪声信息。然而，由于像素阵列受到的噪声干扰会随时间变化，且图像传感器分别在不同的时间点采样暗像素信号和有源像素信号，因此，暗像素信号的采样结果所携带的噪声信息与有源像素信号的采样结果所携带的噪声信息有相当的差异，造成降噪的效果有限。
因此，需要一种创新的信号处理方案，其可有效降低像素信号包括的噪声信息。
发明内容
本公开的目的之一在于提供一种用于像素阵列的信号处理电路和信号处理方法，及其相关的图像传感器，来解决上述问题。
本公开的一实施例提供了一种用于像素阵列的信号处理电路。所述信号处理电路包括一信号产生电路、一比较电路以及一计数电路。所述信号产生电路用以根据一第一斜坡信号和所述像素阵列输 出的N个第一像素信号产生一第二斜坡信号，其中N是正整数，所述第二斜坡信号包括所述N个第一像素信号携带的噪声信息。所述比较电路耦接到所述信号产生电路，用以将所述像素阵列输出的一第二像素信号与所述第二斜坡信号作比较，以产生一比较信号。所述计数电路耦接到所述比较电路，用以根据所述比较信号产生所述第二像素信号的计数值。
本公开的一实施例提供了一种图像传感器。所述图像传感器包括一像素阵列以及一信号处理电路。所述像素阵列包括多个有源像素和多个暗像素。所述信号处理电路耦接到所述像素阵列，并包括一信号产生电路、一第一比较电路、一第二比较电路、一第一计数电路以及一第二计数电路。所述信号产生电路用以根据一第一斜坡信号和所述多个暗像素中的N个暗像素分别输出的N个暗像素信号产生一第二斜坡信号，其中N是正整数，所述第二斜坡信号包括所述N个暗像素信号携带的噪声信息。所述第一比较电路耦接到所述多个有源像素中的至少一个有源像素和所述信号产生电路，用以将所述有源像素输出的一有源像素信号与所述第二斜坡信号作比较，以产生一第一比较信号。所述第二比较电路耦接到所述N个暗像素中的至少一个暗像素和所述信号产生电路，用以将所述暗像素输出的一暗像素信号与所述第二斜坡信号作比较，以产生一第二比较信号。所述第一计数电路耦接到所述第一比较电路，用以根据所述第一比较信号产生所述有源像素信号的计数值。所述第二计数电路耦接到所述第二比较电路，用以根据所述第二比较信号产生所述暗像素信号的计数值。
本公开的一实施例提供了一种像素阵列的信号处理方法。所述信号处理方法包括：根据一第一斜坡信号和所述像素阵列输出的N个第一像素信号产生一第二斜坡信号，其中N是正整数，所述第二斜坡信号包括所述N个第一像素信号携带的噪声信息；将所述像素阵列输出的一第二像素信号与所述第二斜坡信号作比较，以产生一比较信号；以及根据所述比较信号产生所述第二像素信号的计数值。
附图说明
图1是本公开的图像传感器的一实施例的功能方框示意图。
图2是图1所示的信号处理电路的至少一部分的一实施例的示意图。
图3是本公开的像素阵列的信号处理方法的一实施例的流程图。
其中，附图标记说明如下：
100                                 图像传感器
110                                 像素阵列
120                                 控制电路
130                                 信号处理电路
120                                 控制电路
130、230                            信号处理电路
132、232                            信号产生电路
134 1-134 R+Q、234X、234Y              比较电路
136 1-136 R+Q、236X、236Y              计数电路
242                                 斜坡产生器
244                                 预处理电路
246                                 信号耦合电路
247                                 放大器
248                                 开关
302、304、306                       步骤
P 1,1-P M,R                            有源像素
P 1,R+1-P M,R+Q                         暗像素
CXP、CXN、CYP、CYN                  耦合电容
C1-CN                               第一电容
Ca                                  第二电容
TC1                                 第一端
TC2                               第二端
TR                                参考端
IN61、IN71                        第一输入端
IN62、IN72                        第二输入端
OUT6、OUT7                        输出端
R1                                第一电阻
R2                                第二电阻
VR1                               第一斜坡信号
VR2                               第二斜坡信号
APS 1-APS R、APSX                   有源像素信号
DPS 1-DPS Q、DPSY                   暗像素信号
CR 1-CR R+Q、CRX、CRY               比较信号
CT 1-CT R+Q、CTX、CTY               计数值
具体实施方式
在说明书及之前的权利要求书当中使用了某些词汇来指称特定的组件。本领域的技术人员应可理解，制造商可能会用不同的名词来称呼同样的组件。本说明书及之前的权利要求书并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的基准。在通篇说明书及之前的权利要求书当中所提及的“包括”为一开放式的用语，故应解释成“包括但不限定于”。此外，“耦接”一词在此包括任何直接和间接的电连接手段。因此，若文中描述一第一装置耦接于一第二装置，则代表所述第一装置可直接电连接于所述第二装置，或通过其它装置或连接手段间接地电连接到所述第二装置。
图1是本公开的图像传感器的一实施例的功能方框示意图。图像传感器100可包括(但不限于)一像素阵列110、一控制电路120以及一信号处理电路130，其中像素阵列110包括排列成M行与R列的多个有源像素(亦可称作有源像素单元或有源像素电路) P 1,1-P M,R以及排列成M行与Q列的多个暗像素(亦可称作暗像素单元或暗像素电路)P 1,R+1-P M,R+Q，其中M、R和Q均为大于1的正整数。在此实施例中，多个暗像素P 1,R+1-P M,R+Q可设置在像素阵列110的一侧(诸如多个有源像素P 1,1-P M,R的右侧)，然而，本公开并不以此为限。例如，多个暗像素P 1,R+1-P M,R+Q可设置在像素阵列110的另一侧(诸如多个有源像素P 1,1-P M,R的左侧)。又例如，多个暗像素P 1,R+1-P M,R+Q的一部分可设置在像素阵列110的一侧，多个暗像素P 1,R+1-P M,R+Q的另一部分可设置在像素阵列110的另一侧。
控制电路120耦接到像素阵列110，用以控制像素阵列110中各像素相关的操作(例如电荷转移、信号复位、信号放大和/或读出操作)，使各像素产生相应的像素信号，诸如多个有源像素信号APS 1-APS R其中的一个或多个暗像素信号DPS 1-DPS Q其中的一个。
信号处理电路130耦接到像素阵列110，用以根据一个或多个暗像素输出的暗像素信号，来补偿一个或多个有源像素所输出的有源像素信号。在此实施例中，信号处理电路130还可根据携带有像素噪声的斜坡信号来采样像素阵列110输出的像素信号，以实时地减少/消除像素信号所携带的噪声信息，其中像素噪声可以是暗像素信号所携带的噪声信息，或有源像素信号所携带的噪声信息。
出于说明的目的，以下基于采用列并行单斜率模数转换结构(column-parallel single slope analog-to-digital converter architecture，column-parallel SS ADC architecture)的信号处理电路130来说明本公开的信号处理方案。然而，本公开并不以此为限。举例来说，在某些实施例中，信号处理电路130可利用逐次逼近式模数转换器(successive approximation register ADC，SAR ADC)或其他类型的模数转换器来实施列并行模数转换结构。又例如，信号处理电路130可采用像素并行模数转换结构(pixel-parallel ADC architecture)来处理像素信号。
在此实施例中，信号处理电路130包括(但不限于)一信号产 生电路132、多个比较电路134 1-134 R+Q以及多个计数电路136 1-136 R+Q。信号产生电路132用以根据一第一斜坡信号VR1和像素阵列110输出的N个第一像素信号(N是正整数)产生一第二斜坡信号VR2，其中第二斜坡信号VR2包括所述N个第一像素信号携带的噪声信息。第一斜坡信号VR1可由(但不限于)一斜坡产生器(ramp generator)(图1未示)产生。所述N个第一像素信号可以是像素阵列110包括的N个暗像素(例如，多个暗像素P 1,R+1-P M,R+Q中位于同一行的N个暗像素)各自产生的N个暗像素信号。
举例来说，信号产生电路132可将所述N个第一像素信号耦合至第一斜坡信号VR1，使第二斜坡信号VR2包括所述N个第一像素信号携带的噪声信息。又例如，信号产生电路132可对所述N个第一像素信号进行预处理(诸如信号耦合或信号平均)，以将所述N个第一像素信号合并(或耦合)为一预处理信号，以及将所述预处理信号耦合/叠加至第一斜坡信号VR1。
多个比较电路134 1-134 R+Q的每个比较电路均耦接到信号产生电路132，用以将像素阵列110输出的一第二像素信号与第二斜坡信号VR2作比较，以产生一比较信号。举例来说，耦接于有源像素的每个比较电路(多个比较电路134 1-134 R其中的一个)可称作第一比较电路，其可将有源像素信号(多个有源像素信号APS 1-APS R其中的一个)与第二斜坡信号VR2作比较，以产生第一比较信号(多个比较信号CR 1-CR R其中的一个)。又例如，耦接于暗像素的每个比较电路(多个比较电路134 R+1-134 R+Q其中的一个)可称作第二比较电路，其可将暗像素信号(多个暗像素信号DPS 1-DPS Q其中的一个)与第二斜坡信号VR2作比较，以产生第二比较信号(多个比较信号CR R+1-CR R+Q其中的一个)。
多个计数电路136 1-136 R+Q的每个计数电路耦接到相应的比较电路，用以根据相应的比较信号产生相应的第二像素信号的一计数值(多个计数值CT 1-CT R+Q其中的一个)。举例来说，耦接于第一比较电路的每个计数电路(多个计数电路136 1-136 R其中的一个)可称作第 一计数电路，其可根据相应的第一比较信号产生有源像素信号的计数值。又例如，耦接于第二比较电路的每个计数电路(多个计数电路136 R+1-136 R+Q其中的一个)可称作第二计数电路，其可根据相应的第二比较信号产生暗像素信号的计数值。
于操作中，控制电路120可控制像素阵列110逐行读出位于同一行的多个像素的像素信号，作为多个有源像素信号APS 1-APS R和多个暗像素信号DPS 1-DPS Q。信号产生电路132可根据第一斜坡信号VR1和多个暗像素信号DPS 1-DPS Q中的N个暗像素信号产生第二斜坡信号VR2，其可携带所述N个暗像素信号的噪声信息。多个比较电路134 1-134 R中的每个比较电路可将一有源像素信号与第二斜坡信号VR2作比较，以产生一比较信号。以比较电路134 1为例，当比较信号CR 1指示出第二斜坡信号VR2的信号电平达到有源像素信号APS 1的信号电平时，耦接于比较电路134 1的计数电路136 1所产生的计数值CT 1可作为有源像素信号APS 1的计数结果或模数转换结果。
值得注意的是，由于第二斜坡信号VR2包括了所述N个暗像素信号携带的实时噪声信息，因此，通过将有源像素信号APS 1与第二斜坡信号VR2作比较，比较电路134 1可实时地扣除有源像素信号APS 1与所述N个暗像素信号共同包括的随时间变化的噪声信息，其可称作共模噪声(common mode noise)。也就是说，比较信号CR 1中随时间变化的噪声信息可大幅减少，使计数电路136 1可产生将有源像素信号扣除随时间变化的噪声信息之后所得到的计数结果。
此外，多个比较电路134 R+1-134 R+Q中的每个比较电路可将一暗像素信号与第二斜坡信号VR2作比较，以产生一比较信号。以比较电路134 R+1为例，当比较信号CR R+1指示出第二斜坡信号VR2的信号电平达到暗像素信号DPS 1的信号电平时，耦接于比较电路134 R+1的计数电路136 R+1所产生的计数值CT R+1可作为暗像素信号DPS 1的模数转换结果。相似地，由于第二斜坡信号VR2包括了所述N个暗像素信号携带的实时噪声信息，因此，通过将暗像素信号DPS 1与第二斜坡信号VR2作比较，比较电路134 R+1可实时地扣除暗像素信号DPS 1 中随时间变化的噪声信息。比较信号CR R+1中随时间变化的噪声信息可大幅减少，使计数电路136 R+1可产生将暗像素信号扣除随时间变化的噪声信息之后所得到的计数结果。
再者，由于多个比较电路134 1-134 R均可实时地扣除有源像素信号中与暗像素信号共同包括的噪声信息，因此，多个比较信号CR 1-CR R均是已实时地扣除噪声信息的比较结果。多个计数值CT 1-CT R可无需扣除暗像素信号的计数值，即可作为主动降噪的采样结果。
为方便理解，下文搭配图1所示的像素阵列110中有源像素列和暗像素列各自相应的比较电路和计数电路来说明本公开的信号处理方案。然而，本公开并不以此为限。只要是可将至少一像素信号复制/耦合至斜坡信号以实时地扣除像素信号中随时间变化的噪声信息的信号处理电路，设计上相关的替代方案均包括在本公开的范围内。
请参阅图2。图2是图1所示的信号处理电路130的至少一部分的一实施例的示意图。信号处理电路230包括(但不限于)一信号产生电路232、多个比较电路234X和234Y，以及多个计数电路236X和236Y。信号产生电路232可以是图1所示的信号产生电路132的一实施方式。比较电路234X可以是图1所示的比较电路134 1-134 R中至少一比较电路的一实施方式。比较电路234Y可以是图1所示的比较电路134 R+1-134 R+Q中至少一比较电路的一实施方式。计数电路236X可以是图1所示的计数电路136 1-136 R中至少一计数电路的一实施方式。计数电路236X可以是图1所示的计数电路136 R+1-136 R+Q中至少一计数电路的一实施方式。
信号产生电路232包括(但不限于)一斜坡产生器242、一预处理电路244以及一信号耦合电路246。斜坡产生器242用以产生第一斜坡信号VR1。斜坡产生器242可由图1所示的控制电路120所控制。在某些实施例中，将斜坡产生器242设置在信号产生电路232的外部也是可行的。
预处理电路244用以将图1所示的像素阵列110输出的N个第 一像素信号合并为(或耦合)一预处理信号PPS，其中预处理信号PPS可包括所述N个第一像素信号携带的噪声信息。在此实施例中，所述N个第一像素信号可由(但不限于)多个暗像素信号DPS 1-DPS Q其中的N个暗像素信号来实施。出于说明的目的，所述N个暗像素信号可标记为DPS 1-DPS N。
举例来说(但本公开不限于此)，预处理电路244可复制N个暗像素信号DPS 1-DPS N以产生预处理信号PPS，其中预处理信号PPS可包括N个暗像素信号DPS 1-DPS N携带的噪声信息。又例如，预处理电路244可对N个暗像素信号DPS 1-DPS N各自的噪声电平执行平均操作以产生预处理信号PPS，其中预处理信号PPS的噪声电平是根据N个暗像素信号DPS 1-DPS N各自的噪声电平的平均来决定。因此，预处理信号PPS可包括N个暗像素信号DPS 1-DPS N携带的噪声信息。
在此实施例中，预处理电路244包括(但不限于)N个第一电容C1-CN以及一第二电容Ca。N个第一电容C1-CN分别耦接到N个暗像素信号DPS 1-DPS N，其中每个第一电容均耦接于相应的暗像素信号与第二电容Ca的第一端TC1之间。第二电容Ca的第二端TC2可耦接到一参考端TR(诸如接地端)。
信号耦合电路246耦接到斜坡产生器242和预处理电路244，用以将预处理信号PPS耦合到第一斜坡信号VR1以产生第二斜坡信号VR2。举例来说(但本公开不限于此)，信号耦合电路246可将预处理信号PPS耦合或叠加至第一斜坡信号VR1，使第二斜坡信号VR2包括N个暗像素信号DPS 1-DPS N携带的噪声信息。信号耦合电路246的第一输入端IN61用以接收第一斜坡信号VR1，信号耦合电路246的第二输入端IN62用以接收预处理信号PPS。在此实施例中，信号耦合电路246的第二输入端IN62耦接到N个第一电容C1-CN各自的一端以及第二电容Ca的第一端TC1，以接收预处理信号PPS。此外，信号耦合电路246的输出端OUT6用以输出第二斜坡信号VR2。
信号耦合电路246可由(但不限于)一增益级(gain stage)来实施，并可包括一第一电阻R1、一放大器247以及一第二电阻R2。 放大器247的第一输入端IN71通过第一电阻R1耦接到第一斜坡信号VR1，放大器247的第二输入端IN72可作为信号耦合电路246的第二输入端IN62。放大器247的输出端OUT7可作为信号耦合电路246的输出端OUT6。此外，第二电阻R2耦接于放大器247的第一输入端IN71与输出端OUT7之间。
比较电路234X可由差分比较器(differential comparator)来实施，用以将一有源像素信号APSX(多个有源像素信号APS 1-APS R其中的一个)与第二斜坡信号VR2作比较，以产生一比较信号CRX。在此实施例中，比较电路234X可通过耦合电容CXN耦接到有源像素信号APSX，以接收有源像素信号APSX的交流信号成分。此外，比较电路234X可通过耦合电容CXP耦接到第二斜坡信号VR2，以接收第二斜坡信号VR2的交流信号成分。
相似地，比较电路234Y可由差分比较器来实施，用以将一暗像素信号DPSY(多个暗像素信号DPS 1-DPS Q其中的一个)与第二斜坡信号VR2作比较，以产生一比较信号CRY。比较电路234Y可分别通过耦合电容CYN和耦合电容CYP耦接到暗像素信号DPSY和第二斜坡信号VR2，以接收暗像素信号DPSY和第二斜坡信号VR2的交流信号成分。在此实施例中，暗像素信号DPSY可以是N个暗像素信号DPS 1-DPS N其中的一个。
在此实施例中，信号处理电路230还可包括一开关248，其耦接于一参考电压Vref与信号耦合电路246的第二输入端IN62之间。开关248用以将第二输入端IN62复位到参考电压Vref。
于操作中，开关248可将第二输入端IN62复位到参考电压Vref，从而复位信号耦合电路246的输出端OUT6的电压。接下来，开关248可断开，以及信号处理电路230可对有源像素信号APSX和暗像素信号DPSY进行相关处理。预处理电路244可利用N个第一电容C1-CN和第二电容Ca产生预处理信号PPS，使信号耦合电路246可产生携带N个暗像素信号DPS 1-DPS N的噪声信息的第二斜坡信号VR2。第二斜坡信号VR2可由下式表示：
Figure PCTCN2019103944-appb-000001
，其中C[1]-C[N]可分别代表N个第一电容C1-CN的电容值，C[a]可代表第二电容Ca的电容值，以及p[1]-p[N]可分别代表N个暗像素信号DPS 1-DPS N的信号值。值得注意的是，第二斜坡信号VR2包括了N个暗像素信号DPS 1-DPS N携带的实时噪声信息。
通过将有源像素信号APSX与第二斜坡信号VR2作比较，比较电路234X可实时地扣除有源像素信号APSX与N个暗像素信号DPS 1-DPS N共同包括的随时间变化的噪声信息。举例来说(但本公开不限于此)，N个暗像素信号DPS 1-DPS N中某一暗像素信号DPS i的信号值p[i](i是小于或等于N的正整数)可由下式表示：
p[i]＝Vncm+Vn[i]
其中Vncm可代表有源像素信号和暗像素信号共同包括的噪声(诸如共模噪声)的噪声电平(其可随时间动态变化)，Vn[i]可代表暗像素信号DPS i中的其他噪声的噪声电平(其可随时间动态变化)。
在N个第一电容C1-CN中的每个第一电容具有相同的电容值，以及第二电容Ca的电容值C[a]等于N个第一电容C1-CN的电容值总和的情形下，第二斜坡信号VR2可由下式表示：
Figure PCTCN2019103944-appb-000002
在第一电阻R1和第二电阻R2由具有相同的电阻值的电阻来实施的情形下，第二斜坡信号VR2可进一步表示如下：
Figure PCTCN2019103944-appb-000003
其中Vn可代表N个噪声电平Vn[1]-Vn[N]相应的有效值：
Figure PCTCN2019103944-appb-000004
因此，当第二斜坡信号VR2到达有源像素信号APSX的信号电平时，比较电路234X可实时地扣除有源像素信号APSX与暗像素信号共同包括的噪声的噪声电平Vncm。值得注意的是，当用来复制暗像素信号的噪声信息的像素个数(即，N个暗像素信号DPS 1-DPS N的信号个数N)够多时，第二斜坡信号VR2的信号成分
Figure PCTCN2019103944-appb-000005
相对于信号成分(Vncm-VR1)来说是可忽略的，使比较电路234X可以扣除有源像素信号APSX中因为像素噪声而产生的大部分(或全部)的噪声信息。
相似地，通过将暗像素信号DPSY与第二斜坡信号VR2作比较，比较电路234Y可实时地扣除暗像素信号DPSY与N个暗像素信号DPS 1-DPS N共同包括的随时间变化的噪声信息。例如，当第二斜坡信号VR2到达暗像素信号DPSY的信号电平时，比较电路234Y可实时地扣除暗像素信号的噪声电平Vncm。当用来复制暗像素信号的噪声信息的像素个数(即，N个暗像素信号DPS 1-DPS N的信号个数N)够多时，比较电路234Y可以扣除暗像素信号DPSY中因为像素噪声而产生的大部分(或全部)的噪声信息。也就是说，当第二斜坡信号VR2到达暗像素信号DPSY的信号电平时，比较信号CRY的信号电平可等于或大致等于零。
值得注意的是，由于信号处理电路230可实时地扣除有源像素信号与暗像素信号共同包括的噪声信息，因此，即使信号处理电路230分别在不同的时间点采样有源像素信号APSX和暗像素信号DPSY(即，比较信号CRX的信号电平和比较信号CRY的信号电平在不同的时间点翻转)，比较信号CRX和比较信号CRY均已扣除(或几乎扣除)随时间变化的噪声信息。也就是说，计数值CTX和计数值CTY均已扣除(或几乎扣除)随时间变化的噪声信息。
再者，由于计数电路236X所产生的计数值CTX已扣除(或几乎扣除)有源像素信号与暗像素信号共同包括的噪声信息，因此，信号处理电路230可无需将计数值CTX和计数值CTY相减以执行数字主动降噪操作(digital ANC)。也就是说，信号处理电路230是可执行模拟主动降噪操作(analog ANC)的信号处理电路。
以上所述是出于说明的目的，并非用来限制本公开的范围。在某些实施例中，N个暗像素信号DPS 1-DPS N也可以用来消除/降低其他暗像素信号中的噪声信息。例如，比较电路234Y所耦接的暗像素信号DPSY可以是图1所示的多个暗像素信号DPS 1-DPS Q中的任一个暗像素信号。
在某些实施例中，也可以利用至少一有源像素信号来复制有源像素信号和暗像素信号共同包括的噪声信息。例如，预处理电路244可对图1所示的多个有源像素信号APS 1-APS R中的N个有源像素信号进行预处理，以将所述的N个有源像素信号合并为预处理信号PPS，其中预处理信号PPS可包括所述N个有源像素信号携带的噪声信息。
在某些实施例中，预处理电路244可采用其他不同的电路结构来产生携带像素噪声信息的预处理信号PPS。在某些实施例中，信号耦合电路246可采用其他不同的电路结构来将预处理信号PPS耦合/叠加至第一斜坡信号VR1。此外，在某些实施例中，信号耦合电路246可直接将预处理信号PPS叠加至第一斜坡信号VR1。以上所述的替代方案均包括在本公开的范围内。
图3是本公开的像素阵列的信号处理方法的一实施例的流程图。假若所得到的结果实质上大致相同，则步骤不一定要按照图3所示的顺序来进行。举例来说，某些步骤可安插于其中。为了方便说明，以下搭配图2所示的信号处理电路230来说明图3所示的信号处理方法。然而，将图3所示的信号处理方法应用于采用其他信号处理电路(诸如图1所示的信号处理电路130)均是可行的。图3所示的信号处理方法可简单归纳如下。
步骤302：根据一第一斜坡信号和所述像素阵列输出的N个第 一像素信号产生一第二斜坡信号，其中N是正整数，所述第二斜坡信号包括所述N个第一像素信号携带的噪声信息。例如，信号产生电路232根据第一斜坡信号VR1和N个暗像素信号DPS 1-DPS N产生第二斜坡信号VR2。
步骤304：将所述像素阵列输出的一第二像素信号与所述第二斜坡信号作比较，以产生一比较信号。例如，比较电路234X将有源像素信号APSX与第二斜坡信号VR2作比较，以产生比较信号CRX。又例如，比较电路234Y将暗像素信号DPSY与第二斜坡信号VR2作比较，以产生比较信号CRY。
步骤306：根据所述比较信号产生所述第二像素信号的计数值。例如，计数电路236X根据比较信号CRX产生有源像素信号APSX的计数值CTX。又例如，计数电路236Y根据比较信号CRY产生暗像素信号DPSY的计数值CTY。
在某些实施例中，于步骤302，可对所述N个第一像素信号各自的噪声电平执行平均操作以产生一预处理信号，从而将所述预处理信号耦合到所述第一斜坡信号以产生所述第二斜坡信号。例如，预处理电路244可采用多个第一电容C1-CN和第二电容Ca来对N个暗像素信号DPS 1-DPS N各自的噪声电平执行平均操作，以复制N个暗像素信号DPS 1-DPS N的噪声信息，从而产生预处理信号PPS。信号耦合电路246可将预处理信号PPS耦合至第一斜坡信号VR1以产生第二斜坡信号VR2。此外，在某些实施例中，步骤304所采用的所述第二像素信号可以是步骤302所采用的所述N个第一像素信号其中的至少一个像素信号。
由于本领域的技术人员通过阅读图1和图2相关的段落说明之后，应可了解图3所示的信号处理方法中每个步骤的细节，因此进一步的说明在此便不再赘述。
以上所述仅为本公开的实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包括在本公开的保护范围之内。

Claims (23)

  1. 一种用于像素阵列的信号处理电路，其特征在于，包括：
    信号产生电路，用以根据第一斜坡信号和所述像素阵列输出的N个第一像素信号产生第二斜坡信号，其中N是正整数，所述第二斜坡信号包括所述N个第一像素信号携带的噪声信息；
    比较电路，耦接到所述信号产生电路，用以将所述像素阵列输出的第二像素信号与所述第二斜坡信号作比较，以产生比较信号；以及
    计数电路，耦接到所述比较电路，用以根据所述比较信号产生所述第二像素信号的计数值。
  2. 如权利要求1所述的信号处理电路，其特征在于，所述第二像素信号是所述N个第一像素信号其中的至少一个像素信号。
  3. 如权利要求1所述的信号处理电路，其特征在于，所述N个第一像素信号是所述像素阵列包括的N个暗像素各自产生的N个暗像素信号。
  4. 如权利要求1所述的信号处理电路，其特征在于，所述第二像素信号是所述像素阵列包括的暗像素所产生的暗像素信号或所述像素阵列包括的有源像素所产生的有源像素信号。
  5. 如权利要求1-4中任一项所述的信号处理电路，其特征在于，所述信号产生电路包括：
    预处理电路，用以将所述N个第一像素信号合并为预处理信号，所述预处理信号包括所述N个第一像素信号携带的噪声信息；以及
    信号耦合电路，耦接到所述预处理电路，用以将所述预处理信号耦合到所述第一斜坡信号以产生所述第二斜坡信号，其中所述信号耦合电路的第一输入端用以接收所述第一斜坡信号，所述信号耦合电路的第二输入端用以接收所述预处理信号，以及所述信号耦合电路的输出端用以输出所述第二斜坡信号。
  6. 如权利要求5所述的信号处理电路，其特征在于，所述预处理电路用以对所述N个第一像素信号各自的噪声电平执行平均操作以产生所述预处理信号，其中所述预处理信号的噪声电平是根据所述N个第一像素信号各自的噪声电平的平均来决定。
  7. 如权利要求5所述的信号处理电路，其特征在于，所述预处理电路包括：
    N个第一电容，分别耦接到所述N个第一像素信号，其中每个第一电容均耦接于相应的第一像素信号与所述信号耦合电路的第二输入端之间；以及
    第二电容，耦接于参考端与所述信号耦合电路的第二输入端之间。
  8. 如权利要求7所述的信号处理电路，其特征在于，所述N个第一电容中每个第一电容具有相同的电容值，以及所述第二电容的电容值等于所述N个第一电容的电容值总和。
  9. 如权利要求5所述的信号处理电路，其特征在于，所述信号耦合电路包括：
    第一电阻；
    放大器，其中所述放大器的第一输入端通过所述第一电阻耦接到所述第一斜坡信号，所述放大器的第二输入端作为所述信号耦合电路的第二输入端，以及所述放大器的输出端作为所述信号耦合电路的输出端；以及
    第二电阻，耦接于所述放大器的第一输入端与所述放大器的输出端之间。
  10. 如权利要求9所述的信号处理电路，其特征在于，所述第一电阻和所述第二电阻具有相同的电阻值。
  11. 如权利要求5所述的信号处理电路，其特征在于，所述信号产生电路还包括：
    开关，耦接于参考电压与所述信号耦合电路的第二输入端之间，用以将所述信号耦合电路的第二输入端复位到所述参考电压。
  12. 一种图像传感器，其特征在于，包括：
    像素阵列，包括多个有源像素和多个暗像素；以及
    信号处理电路，耦接到所述像素阵列，所述信号处理电路包括：
    信号产生电路，用以根据第一斜坡信号和所述多个暗像素中的N个暗像素分别输出的N个暗像素信号产生第二斜坡信号，其中N是正整数，所述第二斜坡信号包括所述N个暗像素信号携带的噪声信息；
    第一比较电路，耦接到所述多个有源像素中的至少一个有源像素和所述信号产生电路，用以将所述有源像素输出的有源像素信号与所述第二斜坡信号作比较，以产生第一 比较信号；
    第二比较电路，耦接到所述N个暗像素中的至少一个暗像素和所述信号产生电路，用以将所述暗像素输出的暗像素信号与所述第二斜坡信号作比较，以产生第二比较信号；
    第一计数电路，耦接到所述第一比较电路，用以根据所述第一比较信号产生所述有源像素信号的计数值；以及
    第二计数电路，耦接到所述第二比较电路，用以根据所述第二比较信号产生所述暗像素信号的计数值。
  13. 如权利要求12所述的图像传感器，其特征在于，所述信号产生电路包括：
    预处理电路，用以将所述N个暗像素信号合并为预处理信号，所述预处理信号包括所述N个暗像素信号携带的噪声信息；以及
    信号耦合电路，耦接到所述预处理电路，用以将所述预处理信号耦合到所述第一斜坡信号以产生所述第二斜坡信号，其中所述信号耦合电路的第一输入端用以接收所述第一斜坡信号，所述信号耦合电路的第二输入端用以接收所述预处理信号，以及所述信号耦合电路的输出端用以输出所述第二斜坡信号。
  14. 如权利要求13所述的图像传感器，其特征在于，所述预处理电路包括：
    N个第一电容，分别耦接到所述N个暗像素信号，其中每个第一电容均耦接于相应的暗像素信号与所述信号耦合电路的第二输入端之间；以及
    第二电容，耦接于参考端与所述信号耦合电路的第二输入端之 间。
  15. 如权利要求13或14所述的图像传感器，其特征在于，所述信号耦合电路包括：
    第一电阻；
    放大器，其中所述放大器的第一输入端通过所述第一电阻耦接到所述第一斜坡信号，所述放大器的第二输入端作为所述信号耦合电路的第二输入端，以及所述放大器的输出端作为所述信号耦合电路的输出端；以及
    第二电阻，耦接于所述放大器的第一输入端与所述放大器的输出端之间。
  16. 如权利要求13或14所述的图像传感器，其特征在于，所述信号产生电路还包括：
    开关，耦接于参考电压与所述信号耦合电路的第二输入端之间，用以将所述信号耦合电路的第二输入端复位到所述参考电压。
  17. 一种像素阵列的信号处理方法，包括：
    根据第一斜坡信号和所述像素阵列输出的N个第一像素信号产生第二斜坡信号，其中N是正整数，所述第二斜坡信号包括所述N个第一像素信号携带的噪声信息；
    将所述像素阵列输出的第二像素信号与所述第二斜坡信号作比较，以产生比较信号；以及
    根据所述比较信号产生所述第二像素信号的计数值。
  18. 如权利要求17所述的信号处理方法，其特征在于，所述第二像素信号是所述N个第一像素信号其中的至少一个像素信号。
  19. 如权利要求17所述的信号处理方法，其特征在于，所述N个第一像素信号是所述像素阵列包括的N个暗像素各自产生的N个暗像素信号。
  20. 如权利要求17至19中任一项所述的信号处理方法，其特征在于，根据所述第一斜坡信号和所述N个第一像素信号产生所述第二斜坡信号的步骤包括：
    将所述N个第一像素信号合并为预处理信号，所述预处理信号包括所述N个第一像素信号携带的噪声信息；以及
    将所述预处理信号耦合到所述第一斜坡信号以产生所述第二斜坡信号。
  21. 如权利要求20所述的信号处理方法，其特征在于，将所述N个第一像素信号合并为所述预处理信号的步骤包括：
    对所述N个第一像素信号各自的噪声电平执行平均操作以产生所述预处理信号，其中所述预处理信号的噪声电平是根据所述N个第一像素信号各自的噪声电平的平均来决定。
  22. 如权利要求20所述的信号处理方法，其特征在于，将所述预处理信号耦合到所述第一斜坡信号以产生所述第二斜坡信号的步骤包括：
    将所述第一斜坡信号和所述预处理信号分别输入到放大器的第一输入端和第二输入端，以在所述放大器的输出端产生所述 第二斜坡信号。
  23. 如权利要求22所述的信号处理方法，其特征在于，还包括：
    在所述预处理信号输入到所述放大器的第二输入端之前，将所述放大器的第二输入端复位到参考电压。
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