WO2021037081A1 - 像素电路及其驱动方法、阵列基板、显示面板以及电子设备 - Google Patents

像素电路及其驱动方法、阵列基板、显示面板以及电子设备 Download PDF

Info

Publication number
WO2021037081A1
WO2021037081A1 PCT/CN2020/111486 CN2020111486W WO2021037081A1 WO 2021037081 A1 WO2021037081 A1 WO 2021037081A1 CN 2020111486 W CN2020111486 W CN 2020111486W WO 2021037081 A1 WO2021037081 A1 WO 2021037081A1
Authority
WO
WIPO (PCT)
Prior art keywords
unit
sensing
signal
driving
control
Prior art date
Application number
PCT/CN2020/111486
Other languages
English (en)
French (fr)
Inventor
冯雪欢
李永谦
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/420,054 priority Critical patent/US11495153B2/en
Publication of WO2021037081A1 publication Critical patent/WO2021037081A1/zh
Priority to US17/944,523 priority patent/US11688316B2/en

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • the present disclosure relates to the field of display technology, for example, to a pixel circuit and a driving method thereof, an array substrate, a display panel, and an electronic device.
  • the pixel circuit In the display field, such as OLED (Organic Light-Emitting Diode, organic light emitting diode) display, the pixel circuit usually adopts 3T1C structure, and the pixel circuit is driven by GOA (Gate Driver On Array, array substrate row drive) circuit, GOA circuit It is an effective means to reduce panel defects and reduce costs.
  • OLED Organic Light-Emitting Diode, organic light emitting diode
  • GOA Gate Driver On Array, array substrate row drive
  • a pixel circuit in one aspect, includes a first driving line, a second driving line, a data line, and a sensing line; a first pixel sub-circuit, the first pixel sub-circuit includes a first writing unit, a first sensing unit, and a first A driving unit, the first writing unit is connected to the data line, the first sensing unit is connected to the sensing line, and the first driving unit is connected to a first light-emitting unit to drive the first The light-emitting unit emits light; a second pixel sub-circuit, the second pixel sub-circuit includes a second writing unit, a second sensing unit and a second driving unit, the second writing unit is connected to the data line, so The second sensing unit is connected to the sensing line, and the second driving unit is connected to the second light-emitting unit to drive the second light-emitting unit to emit light; wherein, the first pixel sub-circuit and the second The pixel sub-circuits are respectively located
  • the first end of the first writing unit is connected to the data line, and the control end of the first writing unit is connected to the first driving line; the first sensing unit The first end of the first drive unit is connected to the sensing line, the control end of the first sensing unit is connected to the second drive line; the control end of the first drive unit is connected to the first write unit The two ends are connected, the first end of the first driving unit is connected to a first power source, the second end of the first driving unit is connected to the second end of the first sensing unit, and the first driving unit The second end of the second writing unit is also connected to the first light-emitting unit; the first end of the second writing unit is connected to the data line, and the control end of the second writing unit is connected to the second drive line The first end of the second sensing unit is connected to the sensing line, the control end of the second sensing unit is connected to the first driving line; the control end of the second driving unit is connected to the The second end of the second drive unit is connected, the first end of the second drive
  • the first writing unit includes a first writing transistor, and the first terminal, the second terminal, and the control terminal of the first writing transistor are respectively configured as A first terminal, a second terminal, and a control terminal;
  • the second writing unit includes a second writing transistor, and the first terminal, the second terminal, and the control terminal of the second writing transistor are respectively configured as the first The first end, the second end and the control end of the writing unit.
  • the first sensing unit includes a first sensing transistor, and the first terminal, the second terminal, and the control terminal of the first sensing transistor are respectively configured as A first terminal, a second terminal, and a control terminal;
  • the second sensing unit includes a second sensing transistor, and the first terminal, the second terminal, and the control terminal of the second sensing transistor are respectively configured as the first terminal The first end, the second end and the control end of the second sensing unit.
  • the first driving unit includes a first driving transistor and a first storage capacitor, and the first terminal, the second terminal, and the control terminal of the first driving transistor are respectively configured as the first driving unit The first end, the second end and the control end of the first storage capacitor, one end of the first storage capacitor is connected to the control end of the first driving transistor, and the other end of the first storage capacitor is connected to the second end of the first driving transistor.
  • the two ends are connected; one end of the first light-emitting unit is connected to the second end of the first drive transistor, and the other end of the first light-emitting unit is connected to a second power supply;
  • the second drive unit includes a second drive A transistor and a second storage capacitor, the first terminal, the second terminal and the control terminal of the second driving transistor are respectively configured as the first terminal, the second terminal and the control terminal of the second driving unit, the second One end of the storage capacitor is connected to the control end of the second drive transistor, and the other end of the second storage capacitor is connected to the second end of the second drive transistor; one end of the second light-emitting unit is connected to the first end of the second drive transistor.
  • the second ends of the two driving transistors are connected, and the other end of the second light-emitting unit is connected to the second power source.
  • the first driving line and the second driving line are configured to be respectively connected to the output terminals of the gate driving units in two adjacent rows of the gate driving circuit.
  • an array substrate is provided, and the array substrate includes the pixel circuit as described in any of the above embodiments.
  • the first pixel sub-circuit and the second pixel sub-circuit in the pixel circuit are respectively located in two adjacent rows of the pixel array.
  • a display panel in another aspect, includes the array substrate as described in any of the above embodiments.
  • an electronic device in yet another aspect, includes the display panel as described in any of the foregoing embodiments.
  • a method for driving a pixel circuit for driving the pixel circuit according to any one of the above embodiments.
  • the working mode of the pixel circuit includes a display mode, and in the display mode, the method includes At least one first period, the first period includes first to fourth stages; in the first stage of the display mode, the first drive line transmits a first turn-on signal; the first writing unit is in the Turn on under the control of the first turn-on signal to pre-charge the control terminal of the first drive unit; in the second stage of the display mode, the first drive line transmits the first turn-on signal, so The second drive line transmits a second turn-on signal; the first writing unit is turned on under the control of the first turn-on signal to write the first data voltage of the data line into the first drive unit The control terminal; the second writing unit is turned on under the control of the second turn-on signal to precharge the control terminal of the second driving unit; in the third stage of the display mode, the first A driving line transmits a first closing signal, and the second driving line
  • the working mode of the pixel circuit includes a sensing mode.
  • the method includes at least one second cycle, and the second cycle includes a data write-back phase;
  • the first drive line transmits the first turn-on signal
  • the second drive line transmits the second turn-on signal;
  • the first writing unit and the second sensing unit It is turned on under the control of the first turn-on signal, the first sensing unit and the second writing unit are turned on under the control of the second turn-on signal, and the data voltage output by the data line is written simultaneously
  • the control terminal of the first driving unit and the control terminal of the second driving unit, and the reference voltage output by the sensing line is written to the first node and the second node at the same time; wherein, the first driving unit and the second node
  • the first light-emitting unit is connected to the first node, and the second driving unit and the second light-emitting unit are both connected to the second node.
  • the second cycle before the data write-back phase of the sensing mode, the second cycle further includes a first data write phase, a first charging phase, and a first sampling phase;
  • the first drive line transmits the first turn-on signal
  • the second drive line transmits the second turn-on signal;
  • the first writing unit is turned on under the control of the first turn-on signal, and the The first sensing unit is turned on under the control of the second turn-on signal, the data voltage output by the data line is written into the control terminal of the first driving unit, and the reference voltage output by the sensing line is written into the control terminal of the first driving unit.
  • the second cycle before the data write-back phase of the sensing mode and after the first sampling phase, the second cycle further includes a second data write phase, a second charging phase, and a second Sampling stage:
  • the first drive line transmits the first turn-on signal
  • the second drive line transmits the second turn-on signal
  • the second writing unit is in the first
  • the second sensing unit is turned on under the control of the second turn-on signal
  • the second sensing unit is turned on under the control of the first turn-on signal
  • the data voltage output by the data line is written into the control terminal of the second driving unit, and the The reference voltage output by the sensing line is written into the second node
  • the second driving line transmits the second off signal
  • the first driving line transmits the first on signal
  • the second writing unit is turned off under the control of the second turn-off signal
  • the second sensing unit is turned on under the control of the first turn-on signal
  • the first power source is passed through the second driving unit
  • the second node is charged so
  • the first data voltage is also compensated according to the cross voltage of the first light-emitting unit.
  • the second data voltage is further compensated according to the cross voltage of the second light-emitting unit.
  • FIG. 1 is a circuit schematic diagram of a gate driving circuit corresponding to a pixel circuit according to some embodiments
  • Fig. 2 is a block diagram of a pixel circuit according to some embodiments.
  • FIG. 3 is a schematic circuit diagram of a gate driving circuit corresponding to another pixel circuit according to some embodiments.
  • FIG. 4 is a circuit schematic diagram of a pixel circuit according to some embodiments.
  • FIG. 5 is a timing diagram of a pixel circuit according to some embodiments.
  • FIG. 6 is a timing diagram of another pixel circuit according to some embodiments.
  • FIG. 7 is a block diagram of an array substrate according to some embodiments.
  • FIG. 8 is a block diagram of a display panel according to some embodiments.
  • Fig. 9 is a structural diagram of an electronic device according to some embodiments.
  • FIG. 10 is a flowchart of a driving method of a pixel circuit according to some embodiments.
  • FIG. 11 is a flowchart of another method for driving a pixel circuit according to some embodiments.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • exemplary embodiments are described herein with reference to cross-sectional views and/or plan views as idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Therefore, variations in the shape with respect to the drawings due to, for example, manufacturing technology and/or tolerances are conceivable. Therefore, the exemplary embodiments should not be construed as being limited to the shape of the area shown herein, but include shape deviations due to, for example, manufacturing.
  • an etched area shown as a rectangle will generally have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the area of the device, and are not intended to limit the scope of the exemplary embodiments.
  • the pixel circuit adopts the 3T1C structure and requires two gate drive lines.
  • the corresponding GOA circuit needs to have two output terminals OUTA' and OUTB' (that is, OUTA' is connected to a gate
  • OUTB' is connected to another gate drive line)
  • the structure is more complicated.
  • some embodiments of the present disclosure provide a pixel circuit and a driving method thereof, an array substrate, a display panel, and an electronic device.
  • the pixel circuit, a driving method thereof, and an array substrate in some embodiments of the present disclosure are described below with reference to the accompanying drawings. Display panel and electronic equipment.
  • FIG. 2 is a schematic block diagram of a pixel circuit 100 according to some embodiments of the present disclosure.
  • the pixel circuit 100 of some embodiments of the present disclosure includes: a first driving line 10, a second driving line 20, a data line 30, a sensing line 40, a first pixel sub-circuit 50, and a second pixel sub-circuit 60.
  • the first pixel sub-circuit 50 and the second pixel sub-circuit 60 are respectively located in two adjacent rows of the pixel array, and the pixel array includes a plurality of pixel sub-circuits arranged in an array.
  • the plurality of pixel sub-circuits include both the first pixel sub-circuit 50 and the second pixel sub-circuit 60.
  • the pixel array has N rows and M columns.
  • the pixel array of N rows and M columns includes N/2 ⁇ M pixel circuits 100 in the embodiment of FIG. 2 or FIG. 4. That is to say, a pixel circuit 100 can be provided in two adjacent rows and in the same column in the pixel array, that is, in each column of the pixel array, the 2i-1th row and the 2ith row can be those of the embodiment in FIG. 2 or FIG. 4
  • i 1, 2, ..., N/2, and N is an even number.
  • the first pixel sub-circuit 50 may be located in the odd-numbered row of the pixel array, that is, the 2i-1th row, and the second pixel sub-circuit 60 may be located in the even-numbered row of the pixel array, that is, the 2i-th row; or, it may be the first pixel sub-circuit.
  • the circuit 50 is located in the even-numbered row of the pixel array, that is, the 2i-th row, and the second pixel sub-circuit 60 is located in the odd-numbered row of the pixel array, that is, the 2i-1th row.
  • the first pixel sub-circuit 50 includes a first writing unit 51, a first sensing unit 52, and a first driving unit 53, the first writing unit 51 is connected to the data line 30, and the first sensing unit 52 is connected to the sensing line 40 Connected, the first driving unit 53 is connected to the first light-emitting unit 70 to drive the first light-emitting unit 70 to emit light.
  • the second pixel sub-circuit 60 includes a second writing unit 61, a second sensing unit 62, and a second driving unit 63.
  • the second writing unit 61 is connected to the data line 30, and the second sensing unit 62 is connected to the sensing line 40.
  • the second driving unit 63 is connected to the second light-emitting unit 80 to drive the second light-emitting unit 80 to emit light.
  • first writing unit 51 and the second sensing unit 62 are both connected to the first driving line 10 to be turned on or off at the same time under the control of the first driving line 10; the second writing unit 61 and the first sensing The units 52 are all connected to the second driving line 20 to be turned on or off at the same time under the control of the second driving line 20.
  • the first driving line 10 and the second driving line 20 are respectively connected to the output terminals of the gate driving units in two adjacent rows of the gate driving circuit.
  • the first pixel sub-circuit 50 is located in the first pixel row, then the first driving line 10 is connected to the output terminal of the gate driving unit of the first row of the gate driving circuit; the second pixel sub-circuit 60 is located in the second pixel row , Then, the second driving line 20 is connected to the output terminal of the second row of gate driving units of the gate driving circuit.
  • the pixel circuit 100 in some of the above-mentioned embodiments of the present disclosure uses two rows as a basic unit, by combining the first writing unit 51 in the first pixel sub-circuit 50 and the second sensor in the second pixel sub-circuit 60
  • the sensing unit 62 is connected to a driving line (such as the first driving line 10), and the second writing unit 61 in the second pixel sub-circuit 60 and the first sensing unit 52 in the first pixel sub-circuit 50 are connected to each other.
  • the other driving line such as the first driving line 20
  • the two pixel sub-circuits in each pixel circuit 100 that is, the first pixel sub-circuit 50 and the second pixel sub-circuit 60
  • the two gate output terminals of the driving circuit that is, the gate driving circuit corresponding to the pixel circuit 100 needs only one gate output terminal per row.
  • the gate driving unit shown in FIG. 3 has one output terminal OUTA Obviously, compared with the gate driving circuit shown in FIG. 1, the number of output terminals is reduced by one, so that the frame of the display panel can be reduced.
  • the first end of the first writing unit 51 is connected to the data line 30, and the control end of the first writing unit 51 is connected to the first driving line 10.
  • the first end of the first sensing unit 52 is connected to the sensing line 40, and the control end of the first sensing unit 52 is connected to the second driving line 20.
  • the control end of the first drive unit 53 is connected to the second end of the first writing unit 51, the first end of the first drive unit 53 is connected to the first power source ELVDD, and the second end of the first drive unit 53 is connected to the first sensor.
  • the second end of the measuring unit 52 is connected, and the second end of the first driving unit 53 is also connected to the first light-emitting unit 70.
  • the first end of the second writing unit 61 is connected to the data line 30, and the control end of the second writing unit 61 is connected to the second driving line 20.
  • the first end of the second sensing unit 62 is connected to the sensing line 40, and the control end of the second sensing unit 62 is connected to the first driving line 10.
  • the control end of the second drive unit 63 is connected to the second end of the second writing unit 61, the first end of the second drive unit 63 is connected to the first power source ELVDD, and the second end of the second drive unit 63 is connected to the second sensor.
  • the second end of the measuring unit 62 is connected, and the second end of the second driving unit 63 is also connected to the second light-emitting unit 80.
  • the first writing unit 51 includes a first writing transistor T11, and the first end of the first writing transistor T11 is configured as the first end of the first writing unit 51.
  • the second terminal of the writing transistor T11 is configured as the second terminal of the first writing unit 51, and the control terminal of the first writing transistor T11 is configured as the control terminal of the first writing unit 51. That is, the first end of the first write transistor T11 is connected to the data line 30, the control end of the first write transistor T11 is connected to the first drive line 10, and the second end of the first write transistor T11 is connected to the first drive line 10.
  • the control end of the unit 53 is connected.
  • the second writing unit 61 includes a second writing transistor T21, a first end of the second writing transistor T21 is configured as the first end of the second writing unit 61, and a second end of the second writing transistor T21 is configured It is the second terminal of the second writing unit 61, and the control terminal of the second writing transistor T21 is configured as the control terminal of the second writing unit 61. That is, the first end of the second write transistor T21 is connected to the data line 30, the control end of the second write transistor T21 is connected to the second drive line 20, and the second end of the second write transistor T21 is connected to the second drive line 20. The control end of the unit 63 is connected.
  • the first sensing unit 52 includes a first sensing transistor T12, and the first end of the first sensing transistor T12 is configured as the first end of the first sensing unit 52.
  • the second terminal of the sensing transistor T12 is configured as the second terminal of the first sensing unit 52, and the control terminal of the first sensing transistor T12 is configured as the control terminal of the first sensing unit 52. That is, the first end of the first sensing transistor T12 is connected to the sensing line 40, the second end of the first sensing transistor T12 is connected to the second end of the first driving unit 53, and the control of the first sensing transistor T12 The terminal is connected to the second driving line 20.
  • the second sensing unit 62 includes a second sensing transistor T22, the first terminal of the second sensing transistor T22 is configured as the first terminal of the second sensing unit 62, and the second terminal of the second sensing transistor T22 is configured It is the second terminal of the second sensing unit 62, and the control terminal of the second sensing transistor T22 is configured as the control terminal of the second sensing unit 62. That is, the first end of the second sensing transistor T22 is connected to the sensing line 40, the second end of the second sensing transistor T22 is connected to the second end of the second driving unit 63, and the control of the second sensing transistor T22 is The terminal is connected to the first driving line 10.
  • the first driving unit 53 includes a first driving transistor T13 and a first storage capacitor C1, and the first end of the first driving transistor T13 is configured as the first end of the first driving unit 53,
  • the second terminal of the first driving transistor T13 is configured as the second terminal of the first driving unit 53, and the control terminal of the first driving transistor T13 is configured as the control terminal of the first driving unit 53.
  • the first end of the first driving transistor T13 is connected to the first power source ELVDD
  • the second end of the first driving transistor T13 is connected to one end of the first light-emitting unit 70
  • the other end of the first light-emitting unit 70 is connected to the second power source.
  • ELVSS is connected, the control end of the first drive transistor T13 is connected to the first writing unit 51, one end of the first storage capacitor C1 is connected to the control end of the first drive transistor T13, and the other end of the first storage capacitor C1 is connected to the first drive The second end of the transistor T13 is connected.
  • the second driving unit 63 includes a second driving transistor T23 and a second storage capacitor C2.
  • the first end of the second driving transistor T23 is configured as the first end of the second driving unit 63, and the second end of the second driving transistor T23 is It is configured as the second terminal of the second driving unit 63, and the control terminal of the second driving transistor T23 is configured as the control terminal of the second driving unit 63.
  • the first end of the second driving transistor T23 is connected to the first power source ELVDD
  • the second end of the second driving transistor T23 is connected to one end of the second light-emitting unit 80
  • the other end of the second light-emitting unit 80 is connected to the second power source.
  • ELVSS is connected, the control end of the second drive transistor T23 is connected to the second writing unit 61, one end of the second storage capacitor C2 is connected to the control end of the second drive transistor T23, and the other end of the second storage capacitor C2 is connected to the second drive The second end of the transistor T23 is connected.
  • the first driving transistor T13 is connected to the first light-emitting unit 70 to form a first node s1
  • the second driving transistor T23 is connected to the second light-emitting unit 80 to form a second node s2.
  • the working mode of the pixel circuit of some embodiments of the present disclosure includes a display mode and a sensing mode.
  • the first writing transistor T11 and the second sensing transistor T22 must be transistors of the same type, and the second writing transistor T21 and the first sensing transistor T12 must be transistors of the same type.
  • the first writing transistor T11 and the second sensing transistor T22 may be NPN transistors, and when the output signal of the first driving line 10 is at a high level, the first writing transistor T11 and the second sensing transistor T22 is turned on; alternatively, the first writing transistor T11 and the second sensing transistor T22 can also be PNP transistors, and when the output signal of the first driving line 10 is low, the first writing transistor T11 and the second The sensing transistor T22 is turned on.
  • the second writing transistor T21 and the first sensing transistor T12 may be NPN type transistors.
  • the second writing transistor T21 and the first sensing transistor T12 may be PNP type transistors, then when the output signal of the second driving line 20 is low, the second writing transistor T21 and the first sensing transistor The transistor T12 is turned on.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • thin film transistors are used as examples for description.
  • each of the above-mentioned transistors is the gate of the transistor, the first terminal is one of the source and drain of the transistor, and the second terminal is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain of the transistor can be structurally indistinguishable. That is to say, the first end and the second end of the transistor in each embodiment of the present disclosure There can be no difference in structure between the two ends.
  • the transistor is an NPN transistor
  • the first end of the transistor may be the source and the second end may be the drain
  • the second end of the transistor may be One end may be the drain, and the second end may be the source.
  • an NPN MOSFET or an IGBT transistor is taken as an example for description. It should be noted that the embodiments of the present disclosure include but are not limited to this.
  • one or more transistors in the circuit provided by the embodiments of the present disclosure can also be PNP transistors, and only the poles of the selected type of transistors can be connected with reference to the poles of the corresponding transistors in some embodiments of the present disclosure. , And make the corresponding voltage terminal provide the corresponding high voltage or low voltage.
  • FIG. 5 is a timing diagram when the working mode is the display mode, where G1 is the output signal of the first driving line 10, and G2 is the output signal of the second driving line 20.
  • FIG. 6 is a timing diagram when the working mode is the sensing mode, where G1 is the output signal of the first drive line 10, G2 is the output signal of the second drive line 20, DATA is the data voltage signal output by the data line 30, SENSE It is the voltage signal on the sensing line 40.
  • the reference voltage VREF is a low-level voltage, wherein, in the display mode, the first switch K1 is turned on.
  • the first drive line 10 transmits a first turn-on signal, that is, a high-level signal, and the first write transistor T11 is turned on to control the first drive transistor T13
  • the terminal, namely point g1 is precharged, that is, the first storage capacitor C1 is precharged.
  • the first drive line 10 transmits a first turn-on signal, that is, a high-level signal
  • the second drive line 20 transmits a second turn-on signal, that is, a high-level signal
  • the first write transistor T11 continues to conduct.
  • the first data voltage can also be compensated according to the cross voltage of the first light-emitting unit 70.
  • the voltage across the first light-emitting unit 70 is the voltage difference between the two ends of the first light-emitting unit 70.
  • the first drive line 10 transmits a first off signal, that is, a low level signal
  • the second drive line 20 transmits a second on signal, that is, a high level signal.
  • the first write transistor T11 is in the first
  • the control terminal of the first driving transistor T13 is turned off under the control of the shutdown signal.
  • the potential of the control terminal of the first driving transistor T13 is maintained by the first storage capacitor C1. At this time, due to the existence of the first storage capacitor C1, the control terminal of the first driving transistor T13 is different from the second terminal.
  • the voltage Vgs between time remains unchanged, but because the first sensing transistor T12 is turned on under the control of the second turn-on signal, the sensing line 40 provides a low-level signal to the first node s1, and the first light-emitting unit 70 does not emit light. .
  • the second sensing transistor T22 is turned off under the control of the first off signal, and the second writing transistor T21 is turned on under the control of the second on signal to transfer the second data voltage of the data line 30 (to obtain the compensation data).
  • the compensated second data voltage is written into the control terminal of the second driving transistor T23, that is, point g2.
  • the second data voltage can also be compensated according to the cross voltage of the second light-emitting unit 80.
  • the voltage across the second light-emitting unit 80 is the voltage difference between the two ends of the second light-emitting unit 80.
  • the first drive line 10 transmits a first off signal, that is, a low-level signal
  • the second drive line 20 transmits a second off signal, that is, a low-level signal.
  • the first write transistor T11 is in the first
  • the first sensing transistor T12 is turned off under the control of the turn-off signal
  • the first sensing transistor T12 is turned off under the control of the second turn-off signal.
  • the potential of the control terminal of the first driving transistor T13 is maintained at a high potential through the first storage capacitor C1.
  • a driving transistor T13 is turned on, and the voltage at the first node s1 rises.
  • the voltage at the control terminal of the first driving transistor T13 ie the point g1, also bootstraps, and the first driving transistor T13 drives The first light emitting unit 70 emits light.
  • the second write transistor T21 is turned off under the control of the second turn-off signal, and the second sensing transistor T22 is turned off under the control of the first turn-off signal.
  • the potential of the control terminal of the second drive transistor T23 passes through The second storage capacitor C2 is maintained at a high potential, the second drive transistor T23 is turned on, and the voltage at the second node s2 rises. Due to the action of the second storage capacitor C2, the control terminal of the second drive transistor T23 is the voltage at point g2 Also bootstrapped, the second driving transistor T23 drives the second light-emitting unit 80 to emit light.
  • the first drive line 10 transmits a first turn-on signal, that is, a high-level signal
  • the second drive line 20 transmits a second turn-on signal, that is, a high-level signal.
  • the first write transistor T11 is turned on under the control of the first turn-on signal
  • the first sensing transistor T12 is turned on under the control of the second turn-on signal
  • the data voltage Vdata output by the data line 30 is the high-level voltage
  • the control terminal of the first driving transistor T13 is written into the point g1, and the reference voltage VREF output by the sensing line 40, that is, the low-level voltage is written into the first node s1.
  • the external circuit can be controlled by The first switch K1 in 90 is closed, and the reference voltage VREF is written into the sensing line 40, so that the reference voltage VREF output by the sensing line 40, that is, the low-level voltage, is written into the first sensing line through the turned-on first sensing transistor T12. Node s1.
  • the external circuit 90 may be provided in the driver chip to improve circuit integration. In some other embodiments of the present disclosure, the external circuit 90 may also be provided on the display panel.
  • the first drive line 10 transmits a first off signal, that is, a low level signal
  • the second drive line 20 transmits a second on signal, that is, a high level signal
  • the first write transistor T11 is turned off under the control of the first turn-off signal
  • the first sensing transistor T12 is turned on under the control of the second turn-on signal
  • the control terminal of the first driving transistor T13 that is, the potential at point g1 is maintained by the first storage capacitor C1 High potential
  • the first driving transistor T13 is turned on, and the current flowing through the first driving transistor T13 charges the first node s1, that is, the first storage capacitor C1, so that the potential of the sensing line 40 changes with the potential of the first node s1 .
  • the first drive line 10 transmits a first off signal, that is, a low level signal
  • the second drive line 20 transmits a second on signal, that is, a high level signal
  • the first write transistor T11 is turned off under the control of the first turn-off signal.
  • the potential of the first node s1 is Vdata-Vth, where Vth is the threshold voltage of the first driving transistor T13
  • the first sensing transistor T12 is in the second turn-on signal. It is turned on under control, so that the potential of the sensing line 40 can be read through the external circuit 90, and then the threshold voltage of the first driving transistor T13 can be sensed. For example, as shown in FIG.
  • the second circuit in the external circuit 90 can be controlled.
  • the switch K2 is closed, so that the sample-and-hold S/H can sample and hold the voltage at the first node s1 through the turned-on first sensing transistor T12, and then the analog-to-digital converter ADC according to the output of the sample-and-hold S/H
  • the signal senses the threshold voltage of the first driving transistor T13.
  • the first drive line 10 transmits a first turn-on signal, that is, a high-level signal
  • the second drive line 20 transmits a second turn-on signal, that is, a high-level signal
  • the transistor T21 is turned on under the control of the second turn-on signal
  • the second sensing transistor T22 is turned on under the control of the first turn-on signal
  • the data voltage Vdata transmitted by the data line 30 is written into the second driving transistor T23.
  • the reference voltage VREF output by the sensing line 40 that is, the low-level voltage is written into the second node s2.
  • the first switch K1 in the external circuit 90 can be controlled. Closed, the reference voltage VREF is written into the sensing line 40, so that the reference voltage VREF output by the sensing line 40, that is, the low-level voltage, is written into the second node s2 through the turned-on second sensing transistor T22.
  • the second drive line 20 transmits a second off signal, that is, a low level signal
  • the first drive line 10 transmits a first on signal, that is, a high level signal
  • the second write transistor T21 is turned off under the control of the second turn-off signal
  • the second sensing transistor T22 is turned on under the control of the first turn-on signal
  • the control terminal of the second driving transistor T23 that is, the potential at point g2 is maintained by the second storage capacitor C2 High potential
  • the second driving transistor T23 is turned on, and the current flowing through the second driving transistor T23 charges the second node s2, that is, the second storage capacitor C2, so that the potential of the sensing line 40 changes with the potential of the second node s2 .
  • the second drive line 20 transmits a second off signal, that is, a low level signal
  • the first drive line 10 transmits a first on signal, that is, a high level signal
  • the second write transistor T21 is turned off under the control of the second turn-off signal.
  • the potential of the second node s2 is Vdata-Vth', where Vth' is the threshold voltage of the second driving transistor T23, and the second sensing transistor T22 is turned on in the first
  • the signal is turned on under the control of the signal, so that the potential of the sensing line 40 can be read by the external circuit 90, and then the threshold voltage of the second driving transistor T23 can be sensed. For example, as shown in FIG.
  • the external circuit 90 can be controlled
  • the second switch K2 is closed, so that the sample-and-hold S/H can sample and hold the voltage at the second node s2 through the turned-on second sensing transistor T22, and then the analog-to-digital converter ADC can sample and hold the voltage at the second node s2 according to the sample-and-hold S/H.
  • the output signal senses the threshold voltage of the second driving transistor T23.
  • the first drive line 10 transmits a first turn-on signal, that is, a high-level signal
  • the second drive line 20 transmits a second turn-on signal, that is, a high-level signal
  • the first write transistor T11 and the second sense transistor T22 are turned on under the control of the first turn-on signal
  • the first sense transistor T12 and the second write transistor T21 are turned on under the control of the second turn-on signal
  • the data voltage output by 30, that is, the high-level voltage is simultaneously written into the control terminal of the first driving transistor T13, namely point g1, and the control terminal of the second driving transistor T23, namely point g2, and the reference voltage VREF output by the sensing line 40 is the low voltage.
  • the flat voltage is written into the first node s1 and the second node s2 at the same time. For example, as shown in FIG.
  • the reference voltage VREF can be written into the sensing line 40 by controlling the first switch K1 in the external circuit 90 to be closed.
  • the reference voltage VREF output by the sensing line 40 that is, the low-level voltage, is written into the first node s1 and the second node s2 through the turned-on first sensing transistor T12 and the second sensing transistor T22, wherein the first driving transistor
  • the second end of T13 and one end of the first light emitting unit 70 are connected to the first node s1
  • the second end of the second driving transistor T23 and one end of the second light emitting unit 80 are connected to the second node s2.
  • the first pixel sub-circuit 50 and the second pixel sub-circuit 60 perform data write-back at the same time, that is, the first write in the first pixel sub-circuit 50
  • the transistor T11 and the second sensing transistor T22 in the second pixel sub-circuit 60 are turned on simultaneously, and the second writing transistor T21 in the second pixel sub-circuit 60 and the first sensing transistor T12 in the first pixel sub-circuit 50 are simultaneously turned on.
  • the first write transistor T11 and the second write transistor T21 are turned on at the same time to write the same data voltage to the control terminal of the first drive transistor T13 and the control terminal of the second drive transistor T23, respectively.
  • the sensing transistor T12 and the second sensing transistor T22 are turned on at the same time to write the same reference voltage to the first node s1 and the second node s2, respectively.
  • the data voltages transmitted on the data line 30 are not the same, that is, the data voltages used in the sensing mode cannot be applied to display mode.
  • the data voltage transmitted on the data line 30 can be changed during the data write-back stage T4' of the sensing mode, so that after the sensing mode ends, the data line 30
  • the above data voltage is adjusted to be applicable to the display mode of the pixel circuit 100.
  • the pixel circuit proposed according to some embodiments of the present disclosure includes a first driving line 10, a second driving line 20, a data line 30, a sensing line 40, a first pixel sub-circuit 50 and a second pixel sub-circuit 60
  • the first pixel sub-circuit 50 includes a first writing unit 51, a first sensing unit 52, and a first driving unit 53
  • the first writing unit 51 is connected to the data line 30, and the first sensing unit 52 is connected to the sensing line 40
  • the first driving unit 53 is connected to the first light-emitting unit 70 to drive the first light-emitting unit 70 to emit light
  • the second pixel sub-circuit 60 includes a second writing unit 61, a second sensing unit 62 and a second driving unit 63
  • the second writing unit 61 is connected to the data line 30, the second sensing unit 62 is connected to the sensing line 40, and the second driving unit 63 is connected to the second light-emitting unit 80 to drive the second light-emitting unit 80
  • the writing unit 51 and the second sensing unit 62 are connected to the first drive line 10 to be turned on or off simultaneously under the control of the first drive line 10, and the second writing unit 61 and the first sensing unit 52 are connected to the second drive
  • the line 20 can be turned on or off at the same time under the control of the second driving line 20. Therefore, in the pixel circuit 100 of some embodiments of the present disclosure, the first writing unit 51 in the first pixel sub-circuit 50 and the second sensing unit 62 in the second pixel sub-circuit 60 are connected to one driving line.
  • the second writing unit 61 in the second pixel sub-circuit 60 and the first sensing unit 52 in the first pixel sub-circuit 50 are connected to another driving line, so that two pixel sub-circuits in each pixel circuit 100
  • the circuit (that is, the first pixel sub-circuit 50 and the second pixel sub-circuit 60) only needs to be connected to the two gate output terminals of the two rows of gate driving circuits. That is to say, each of the gate driving circuits corresponding to the pixel circuit 100 Only one gate output terminal is required for the row, so that the number of output terminals of the gate driving circuit can be reduced, thereby reducing the frame of the display panel.
  • some embodiments of the present disclosure also provide an array substrate 200.
  • the array substrate 200 includes the pixel circuit 100 described in any of the above-mentioned embodiments.
  • the first pixel sub-circuit 50 and the second pixel sub-circuit 60 in the pixel circuit 100 are respectively located in two adjacent rows of the pixel array 201, and the pixel array 201 includes arrays arranged in an array. Multiple pixel sub-circuits.
  • the pixel array 201 has N rows and M columns. Then, the pixel array 201 of N rows and M columns includes N/2 ⁇ M pixel circuits 100 in the embodiment of FIG. 2 or FIG. 4. That is, in the pixel array 201, two adjacent rows and a pixel circuit 100 are arranged in the same column, that is, in each column of the pixel array 201, the 2i-1th row and the 2ith row can be determined by the embodiment shown in FIG. 2 or FIG. 4
  • the first pixel sub-circuit 50 in the pixel circuit 100 is located in the odd-numbered rows of the pixel array 201, and the second pixel sub-circuit 60 in the pixel circuit 100 is located in the even-numbered rows of the pixel array 201 (as shown in FIG. 7).
  • the first pixel sub-circuit 50 in the pixel circuit 100 may also be located in the even-numbered rows of the pixel array 201, and the second pixel sub-circuit 60 in the pixel circuit 100 is located in the odd-numbered rows of the pixel array 201.
  • FIG. 8 is a schematic block diagram of a display panel 300 according to some embodiments of the present disclosure. As shown in FIG. 8, the display panel 300 includes the array substrate 200 described in any of the above-mentioned embodiments.
  • the first writing unit 51 in the first pixel sub-circuit 50 and the second sensing unit 62 in the second pixel sub-circuit 60 are connected through the array substrate 200 provided On one driving line, the second writing unit 61 in the second pixel sub-circuit 60 and the first sensing unit 52 in the first pixel sub-circuit 50 are connected to another driving line, so that each pixel circuit 100
  • the two pixel sub-circuits (that is, the first pixel sub-circuit 50 and the second pixel sub-circuit 60) only need to be connected to the two gate output terminals of the two rows of gate driving circuits, that is to say, the pixel circuit 100 corresponds to Each row of the gate driving circuit only needs one gate output terminal, so that the number of output terminals of the gate driving circuit can be reduced, thereby reducing the frame of the display panel 300.
  • some embodiments of the present disclosure also provide an electronic device 400 including the foregoing display panel 300.
  • the electronic device 400 may be a display device, and the display device may be, for example, a TV, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, a navigator, or any other component with a display function.
  • the display device may be, for example, a TV, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, a navigator, or any other component with a display function.
  • the first writing unit 51 in the first pixel sub-circuit 50 and the second sensing unit 62 in the second pixel sub-circuit 60 are connected through the display panel 300 provided On one driving line, the second writing unit 61 in the second pixel sub-circuit 60 and the first sensing unit 52 in the first pixel sub-circuit 50 are connected to another driving line, so that each pixel circuit 100
  • the two pixel sub-circuits (that is, the first pixel sub-circuit 50 and the second pixel sub-circuit 60) only need to be connected to the two gate output terminals of the two rows of gate driving circuits, that is to say, the pixel circuit 100 corresponds to Each row of the gate driving circuit only needs one gate output terminal, so that the number of output terminals of the gate driving circuit can be reduced, thereby reducing the frame of the electronic device 400.
  • FIG. 10 is a schematic flowchart of a driving method of a pixel circuit according to some embodiments of the present disclosure. As shown in FIG. 10, the driving method of a pixel circuit of some embodiments of the present disclosure includes the following steps:
  • the first drive line transmits a first turn-on signal, and the first writing unit is turned on under the control of the first turn-on signal to precharge the control terminal of the first drive unit.
  • the first drive line transmits a first turn-on signal
  • the second drive line transmits a second turn-on signal
  • the first writing unit is turned on under the control of the first turn-on signal to turn on the data line
  • the first data voltage is written into the control terminal of the first driving unit
  • the second writing unit is turned on under the control of the second turn-on signal to precharge the control terminal of the second driving unit.
  • the first data voltage is also compensated according to the cross voltage of the first light-emitting unit.
  • the first drive line transmits a first off signal
  • the second drive line transmits a second on signal
  • the first writing unit is closed under the control of the first off signal to maintain the first drive
  • the potential of the control terminal of the unit, and the second writing unit is turned on under the control of the second turn-on signal to write the second data voltage of the data line into the control terminal of the second driving unit.
  • the second data voltage is also compensated according to the cross voltage of the second light-emitting unit.
  • the first driving line transmits a first closing signal
  • the second driving line transmits a second closing signal
  • the first writing unit is closed under the control of the first closing signal
  • the first sensing The unit is turned off under the control of the second turn-off signal, so that the first driving unit drives the first light-emitting unit to emit light
  • the second writing unit is turned off under the control of the second turn-off signal
  • the second sensing unit is turned off by the first turn-off signal. Turn off under the control of, so that the second driving unit drives the second light-emitting unit to emit light.
  • the working mode of the pixel circuit includes a sensing mode.
  • the driving method includes at least one second period, and the second period includes a data write-back phase.
  • the driving method of the pixel circuit of some embodiments of the present disclosure includes the following steps:
  • the first drive line transmits the first turn-on signal
  • the second drive line transmits the second turn-on signal.
  • the first write unit and the second sensing unit are controlled by the first turn-on signal.
  • the first sensing unit and the second writing unit are turned on under the control of the second turn-on signal
  • the data voltage output by the data line is written into the control terminal of the first driving unit and the control terminal of the second driving unit at the same time
  • the sensing The reference voltage output by the measuring line is written into the first node and the second node at the same time.
  • first driving unit and the first light-emitting unit are both connected to the first node
  • second driving unit and the second light-emitting unit are both connected to the second node
  • the second cycle before the data write-back phase of the sensing mode, the second cycle further includes a first data write phase, a first charging phase, and a first sampling phase.
  • the driving method of the pixel circuit of some embodiments of the present disclosure further includes the following steps:
  • the first drive line transmits a first turn-on signal
  • the second drive line transmits a second turn-on signal
  • the first writing unit is turned on under the control of the first turn-on signal
  • the first sensing unit Turning on under the control of the second turn-on signal
  • the data voltage output by the data line is written into the control terminal of the first driving unit
  • the reference voltage output by the sensing line is written into the first node.
  • the first drive line transmits a first turn-off signal
  • the second drive line transmits a second turn-on signal
  • the first writing unit is turned off under the control of the first turn-off signal
  • the first sensing unit is Turning on under the control of the second turn-on signal
  • the first power source charges the first node through the first driving unit, so that the potential of the sensing line changes with the potential of the first node.
  • the first drive line transmits a first turn-off signal
  • the second drive line transmits a second turn-on signal
  • the first writing unit is turned off under the control of the first turn-off signal
  • the first sensing unit is It is turned on under the control of the second turn-on signal
  • the potential of the sensing line is read by an external circuit to sense the threshold voltage of the first driving unit.
  • the second cycle before the data write-back phase of the sensing mode, after the first sampling phase, the second cycle further includes a second data writing phase, a second charging phase, and a second sampling phase.
  • the driving method of the pixel circuit of some embodiments of the present disclosure further includes the following steps:
  • the first drive line transmits the first turn-on signal
  • the second drive line transmits the second turn-on signal
  • the second writing unit is turned on under the control of the second turn-on signal
  • the second sensing unit Turning on under the control of the first turn-on signal
  • the data voltage output by the data line is written into the control terminal of the second driving unit
  • the reference voltage output by the sensing line is written into the second node.
  • the second drive line transmits a second turn-off signal
  • the first drive line transmits a first turn-on signal
  • the second writing unit is turned off under the control of the second turn-off signal
  • the second sensing unit is It is turned on under the control of the first turn-on signal
  • the first power source charges the second node through the second driving unit, so that the potential of the sensing line changes with the potential of the second node.
  • the second drive line transmits a second turn-off signal
  • the first drive line transmits a first turn-on signal
  • the second writing circuit is turned off under the control of the second turn-off signal
  • the second sensing unit is It is turned on under the control of the first turn-on signal
  • the potential of the sensing line is read by an external circuit to sense the threshold voltage of the second driving unit.
  • the first driving line 10 transmits the first turn-on signal
  • the first writing unit 51 is controlled by the first driving line 10
  • the first driving line 10 transmits the first turn-on signal
  • the second drive line 20 transmits the second turn-on signal
  • the first write The input unit 51 is turned on under the control of the first turn-on signal to write the first data voltage of the data line 30 into the control terminal of the first driving unit 53
  • the second write unit 61 is turned on under the control of the second turn-on signal
  • the first driving line 10 transmits the first off signal
  • the second driving line 20 transmits the second on signal
  • the first writing unit 51 It is turned off under the control of the first turn-off signal to maintain the potential of the control terminal of the first
  • the first writing unit 51 in the first pixel sub-circuit 50 and the second sensing unit 62 in the second pixel sub-circuit 60 are connected to one driving line.
  • the second writing unit 61 in the second pixel sub-circuit 60 and the first sensing unit 52 in the first pixel sub-circuit 52 are connected to another drive line, so that two pixels in each pixel circuit 100
  • the sub-circuits (that is, the first pixel sub-circuit 50 and the second pixel sub-circuit 60) only need to connect the two gate output terminals of the two rows of gate driving circuits, that is, the gate driving circuit corresponding to the pixel circuit 100 Only one gate output terminal is required for each row, so that the number of output terminals of the gate driving circuit can be reduced, thereby reducing the frame of the display panel.

Abstract

一种像素电路，包括第一驱动线、第二驱动线、数据线和感测线；第一像素子电路，第一像素子电路包括第一写入单元、第一感测单元和第一驱动单元，第一写入单元与数据线相连，第一感测单元与感测线相连，第一驱动单元与第一发光单元相连以驱动第一发光单元发光；第二像素子电路，第二像素子电路包括第二写入单元、第二感测单元和第二驱动单元，第二写入单元与数据线相连，第二感测单元与感测线相连，第二驱动单元与第二发光单元相连以驱动第二发光单元发光；第一写入单元和第二感测单元均与第一驱动线相连，以在第一驱动线的控制下同时开启或关闭，第二写入单元和第一感测单元均与第二驱动线相连，以在第二驱动线的控制下同时开启或关闭。

Description

像素电路及其驱动方法、阵列基板、显示面板以及电子设备
本申请要求于2019年08月27日提交的、申请号为201910799367.7的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，例如涉及一种像素电路及其驱动方法、阵列基板、显示面板以及电子设备。
背景技术
在显示领域中，例如OLED(Organic Light-Emitting Diode，有机发光二极管)显示中，像素电路通常采用3T1C结构，并且像素电路通过GOA(Gate Driver On Array，阵列基板行驱动)电路进行驱动，GOA电路是减少panel不良和降低成本的一种有效手段。
发明内容
一方面，提供一种像素电路。所述像素电路包括第一驱动线、第二驱动线、数据线和感测线；第一像素子电路，所述第一像素子电路包括第一写入单元、第一感测单元和第一驱动单元，所述第一写入单元与所述数据线相连，所述第一感测单元与所述感测线相连，所述第一驱动单元与第一发光单元相连以驱动所述第一发光单元发光；第二像素子电路，所述第二像素子电路包括第二写入单元、第二感测单元和第二驱动单元，所述第二写入单元与所述数据线相连，所述第二感测单元与所述感测线相连，所述第二驱动单元与第二发光单元相连以驱动所述第二发光单元发光；其中，所述第一像素子电路和所述第二像素子电路分别位于像素阵列的相邻两行，所述像素阵列包括阵列排布的多个像素子电路；所述第一写入单元和所述第二感测单元均与所述第一驱动线相连，以在所述第一驱动线的控制下同时开启或关闭，所述第二写入单元和所述第一感测单元均与所述第二驱动线相连，以在所述第二驱动线的控制下同时开启或关闭。
在一些实施例中，所述第一写入单元的第一端与所述数据线相连，所述第一写入单元的控制端与所述第一驱动线相连；所述第一感测单元的第一端与所述感测线相连，所述第一感测单元的控制端与所述第二驱动线相连；所述第一驱动单元的控制端与所述第一写入单元的第二端相连，所述第一驱动单元的第一端与第一电源相连，所述第一驱动单元的第二端与所述第一感测单元的第二端相连，所述第一驱动单元的第二端还与所述第一发光单元相连；所述第二写入单元的第一端与所述数据线相连，所述第二写入单元的控制端 与所述第二驱动线相连；所述第二感测单元的第一端与所述感测线相连，所述第二感测单元的控制端与所述第一驱动线相连；所述第二驱动单元的控制端与所述第二写入单元的第二端相连，所述第二驱动单元的第一端与所述第一电源相连，所述第二驱动单元的第二端与所述第二感测单元的第二端相连，所述第二驱动单元的第二端还与所述第二发光单元相连。
在一些实施例中，所述第一写入单元包括第一写入晶体管，所述第一写入晶体管的第一端、第二端和控制端分别被配置为所述第一写入单元的第一端、第二端和控制端；所述第二写入单元包括第二写入晶体管，所述第二写入晶体管的第一端、第二端和控制端分别被配置为所述第二写入单元的第一端、第二端和控制端。
在一些实施例中，所述第一感测单元包括第一感测晶体管，所述第一感测晶体管的第一端、第二端和控制端分别被配置为所述第一感测单元的第一端、第二端和控制端；所述第二感测单元包括第二感测晶体管，所述第二感测晶体管的第一端、第二端和控制端分别被配置为所述第二感测单元的第一端、第二端和控制端。
在一些实施例中，所述第一驱动单元包括第一驱动晶体管和第一存储电容，所述第一驱动晶体管的第一端、第二端和控制端分别被配置为所述第一驱动单元的第一端、第二端和控制端，所述第一存储电容的一端与所述第一驱动晶体管的控制端相连，所述第一存储电容的另一端与所述第一驱动晶体管的第二端相连；所述第一发光单元的一端与所述第一驱动晶体管的第二端相连，所述第一发光单元的另一端与第二电源相连；所述第二驱动单元包括第二驱动晶体管和第二存储电容，所述第二驱动晶体管的第一端、第二端和控制端分别被配置为所述第二驱动单元的第一端、第二端和控制端，所述第二存储电容的一端与所述第二驱动晶体管的控制端相连，所述第二存储电容的另一端与所述第二驱动晶体管的第二端相连；所述第二发光单元的一端与所述第二驱动晶体管的第二端相连，所述第二发光单元的另一端与所述第二电源相连。
在一些实施例中，所述第一驱动线和所述第二驱动线被配置为分别与栅极驱动电路中相邻两行的栅极驱动单元的输出端相连。
另一方面，提供一种阵列基板，所述阵列基板包括：如上述任一实施例所述的像素电路。
在一些实施例中，所述像素电路中的第一像素子电路和第二像素子电路分别位于像素阵列的相邻两行。
再一方面，提供一种显示面板，所述显示面板包括：如上述任一实施例所述的阵列基板。
又一方面，提供一种电子设备，所述电子设备包括：如上述任一实施例所述的显示面板。
又一方面，提供一种像素电路的驱动方法，用于驱动如上述任一实施例所述的像素电路，所述像素电路的工作模式包括显示模式，在所述显示模式下，所述方法包括至少一个第一周期，所述第一周期包括第一～第四阶段；在所述显示模式的第一阶段，所述第一驱动线传输第一开启信号；所述第一写入单元在所述第一开启信号的控制下开启，以对所述第一驱动单元的控制端进行预充电；在所述显示模式的第二阶段，所述第一驱动线传输所述第一开启信号，所述第二驱动线传输第二开启信号；所述第一写入单元在所述第一开启信号的控制下开启，以将所述数据线的第一数据电压写入所述第一驱动单元的控制端；所述第二写入单元在所述第二开启信号的控制下开启，以对所述第二驱动单元的控制端进行预充电；在所述显示模式的第三阶段，所述第一驱动线传输第一关闭信号，所述第二驱动线传输所述第二开启信号；所述第一写入单元在所述第一关闭信号的控制下关闭，以维持所述第一驱动单元的控制端的电位；所述第二写入单元在所述第二开启信号的控制下开启，以将所述数据线的第二数据电压写入所述第二驱动单元的控制端；在所述显示模式的第四阶段，所述第一驱动线传输所述第一关闭信号，所述第二驱动线传输第二关闭信号；所述第一写入单元在所述第一关闭信号的控制下关闭，且所述第一感测单元在所述第二关闭信号的控制下关闭，以使所述第一驱动单元驱动所述第一发光单元发光；所述第二写入单元在所述第二关闭信号的控制下关闭，且所述第二感测单元在所述第一关闭信号的控制下关闭，以使所述第二驱动单元驱动所述第二发光单元发光。
在一些实施例中，所述像素电路的工作模式包括感测模式，在所述感测模式下，所述方法包括至少一个第二周期，所述第二周期包括数据写回阶段；在所述感测模式的数据写回阶段，所述第一驱动线传输所述第一开启信号，所述第二驱动线传输第二开启信号；所述第一写入单元和所述第二感测单元在所述第一开启信号的控制下开启，所述第一感测单元和所述第二写入单元在所述第二开启信号的控制下开启，所述数据线输出的数据电压同时写入所述第一驱动单元的控制端和所述第二驱动单元控制端，且所述感测线输出的参考电压同时写入第一节点和第二节点；其中，所述第一驱动单元和所述第一发光单元均与所述第一节点相连，所述第二驱动单元和所述第二发光单元 均与所述第二节点相连。
在一些实施例中，在所述感测模式的数据写回阶段之前，所述第二周期还包括第一数据写入阶段、第一充电阶段和第一采样阶段；在所述第一数据写入阶段，所述第一驱动线传输所述第一开启信号，所述第二驱动线传输第二开启信号；所述第一写入单元在所述第一开启信号的控制下开启，所述第一感测单元在所述第二开启信号的控制下开启，所述数据线输出的数据电压写入所述第一驱动单元的控制端，且所述感测线输出的参考电压写入所述第一节点；在所述第一充电阶段，所述第一驱动线传输所述第一关闭信号，且所述第二驱动线传输第二开启信号；所述第一写入单元在所述第一关闭信号的控制下关闭，所述第一感测单元在所述第二开启信号的控制下开启，第一电源通过所述第一驱动单元对所述第一节点充电，以使所述感测线的电位随所述第一节点的电位变化；在所述第一采样阶段，所述第一驱动线传输所述第一关闭信号，且所述第二驱动线传输第二开启信号；所述第一写入单元在所述第一关闭信号的控制下关闭，所述第一感测单元在所述第二开启信号的控制下开启，通过外部电路读取所述感测线的电位以感测所述第一驱动单元的阈值电压。
在一些实施例中，在所述感测模式的数据写回阶段之前，且在所述第一采样阶段之后，所述第二周期还包括第二数据写入阶段、第二充电阶段和第二采样阶段：在所述第二数据写入阶段，所述第一驱动线传输所述第一开启信号，所述第二驱动线传输第二开启信号；所述第二写入单元在所述第二开启信号的控制下开启，所述第二感测单元在所述第一开启信号的控制下开启，所述数据线输出的数据电压写入所述第二驱动单元的控制端，且所述感测线输出的参考电压写入所述第二节点；在所述第二充电阶段，所述第二驱动线传输所述第二关闭信号，且所述第一驱动线传输第一开启信号；所述第二写入单元在所述第二关闭信号的控制下关闭，所述第二感测单元在所述第一开启信号的控制下开启，所述第一电源通过所述第二驱动单元对所述第二节点充电，以使所述感测线的电位随所述第二节点的电位变化；在所述第二采样阶段，所述第二驱动线传输所述第二关闭信号，且所述第一驱动线传输第一开启信号，所述第二写入电路在所述第二关闭信号的控制下关闭，所述第二感测单元在所述第一开启信号的控制下开启，通过所述外部电路读取所述感测线的电位以感测所述第二驱动单元的阈值电压。
在一些实施例中，在所述显示模式的第二阶段，还根据所述第一发光单元的跨压对所述第一数据电压进行补偿。
在一些实施例中，在所述显示模式的第三阶段，还根据所述第二发光单元的跨压对所述第二数据电压进行补偿。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的一种像素电路对应的栅极驱动电路的电路原理图；
图2为根据一些实施例的一种像素电路的方框图；
图3为根据一些实施例的另一种像素电路对应的栅极驱动电路的电路原理图；
图4为根据一些实施例的一种像素电路的电路原理图；
图5为根据一些实施例的一种像素电路的时序图；
图6为根据一些实施例的另一种像素电路的时序图；
图7为根据一些实施例的一种阵列基板的方框图；
图8为根据一些实施例的一种显示面板的方框图；
图9为根据一些实施例的一种电子设备的结构图；
图10为根据一些实施例的一种像素电路的驱动方法的流程图；
图11为根据一些实施例的另一种像素电路的驱动方法的流程图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)” 或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
下面详细描述本公开的一些实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本公开，而不能理解为对本公开的限制。
在一些示例中，像素电路采用3T1C结构，需要两条栅极驱动线，此时，如图1所示，对应的GOA电路需要有两个输出端OUTA'和OUTB'(即OUTA' 连接一条栅极驱动线，OUTB'连接另一条栅极驱动线)，结构比较复杂。
基于此，本公开一些实施例提供了一种像素电路及其驱动方法、阵列基板，显示面板以及电子设备，下面参考附图描述本公开一些实施例中的像素电路及其驱动方法、阵列基板，显示面板以及电子设备。
图2为根据本公开一些实施例的一种像素电路100的方框示意图。如图2所示，本公开一些实施例的像素电路100包括：第一驱动线10、第二驱动线20、数据线30、感测线40、第一像素子电路50和第二像素子电路60。其中，第一像素子电路50和第二像素子电路60分别位于像素阵列的相邻两行，该像素阵列包括阵列排布的多个像素子电路。
可以理解，该多个像素子电路中既包括第一像素子电路50，也包括第二像素子电路60。举例而言，像素阵列具有N行M列，那么，N行M列的像素阵列包括N/2×M个图2或图4实施例的像素电路100。也就是说，像素阵列中相邻两行且处于同一列处可以设置一个像素电路100，即在像素阵列的每一列，第2i-1行和第2i行可以为图2或图4实施例的像素电路100，i＝1、2、…、N/2，N为偶数。此时，可以是第一像素子电路50位于像素阵列的奇数行即第2i-1行，第二像素子电路60位于像素阵列的偶数行即第2i行；或者，也可以是第一像素子电路50位于像素阵列的偶数行即第2i行，第二像素子电路60位于像素阵列的奇数行即第2i-1行。
第一像素子电路50包括第一写入单元51、第一感测单元52和第一驱动单元53，第一写入单元51与数据线30相连，第一感测单元52与感测线40相连，第一驱动单元53与第一发光单元70相连以驱动第一发光单元70发光。
第二像素子电路60包括第二写入单元61、第二感测单元62和第二驱动单元63，第二写入单元61与数据线30相连，第二感测单元62与感测线40相连，第二驱动单元63与第二发光单元80相连以驱动第二发光单元80发光。
其中，第一写入单元51和第二感测单元62均与第一驱动线10相连，以在第一驱动线10的控制下同时开启或关闭；第二写入单元61和第一感测单元52均与第二驱动线20相连，以在第二驱动线20的控制下同时开启或关闭。
根据本公开的一些实施例，第一驱动线10和第二驱动线20分别与栅极驱动电路中相邻两行的栅极驱动单元的输出端相连。例如，第一像素子电路50位于第一像素行，那么，第一驱动线10与栅极驱动电路的第一行栅极驱动单元的输出端相连；第二像素子电路60位于第二像素行，那么，第二驱动线20与栅极驱动电路的第二行栅极驱动单元的输出端相连。
由此，本公开上述一些实施例的像素电路100是以两行作为一个基本单 元，通过将第一像素子电路50中的第一写入单元51与第二像素子电路60中的第二感测单元62连接在一条驱动线(如第一驱动线10)上，将第二像素子电路60中的第二写入单元61与第一像素子电路50中的第一感测单元52连接在另一条驱动线(如第一驱动线20)上，即每个像素电路100中的两个像素子电路(即第一像素子电路50和第二像素子电路60)只需要连接两行栅极驱动电路的两个栅极输出端，也就是说，上述像素电路100所对应的栅极驱动电路每行只需要一个栅极输出端，如图3示出的栅极驱动单元具有一个输出端OUTA，显然，与图1所示的栅极驱动电路相比，输出端的个数减少了一个，从而可减小显示面板的边框。
下面结合图4详细描述本公开一些实施例的像素电路100的具体电路结构。
在一些实施例中，如图4所示，第一写入单元51的第一端与数据线30相连，第一写入单元51的控制端与第一驱动线10相连。
第一感测单元52的第一端与感测线40相连，第一感测单元52的控制端与第二驱动线20相连。
第一驱动单元53的控制端与第一写入单元51的第二端相连，第一驱动单元53的第一端与第一电源ELVDD相连，第一驱动单元53的第二端与第一感测单元52的第二端相连，第一驱动单元53的第二端还与第一发光单元70相连。
第二写入单元61的第一端与数据线30相连，第二写入单元61的控制端与第二驱动线20相连。
第二感测单元62的第一端与感测线40相连，第二感测单元62的控制端与第一驱动线10相连。
第二驱动单元63的控制端与第二写入单元61的第二端相连，第二驱动单元63的第一端与第一电源ELVDD相连，第二驱动单元63的第二端与第二感测单元62的第二端相连，第二驱动单元63的第二端还与第二发光单元80相连。
示例性的，如图4所示，第一写入单元51包括第一写入晶体管T11，第一写入晶体管T11的第一端被配置为第一写入单元51的第一端，第一写入晶体管T11的第二端被配置为第一写入单元51的第二端，第一写入晶体管T11的控制端被配置为第一写入单元51的控制端。也即，第一写入晶体管T11的第一端与数据线30相连，第一写入晶体管T11的控制端与第一驱动线10相连，第一写入晶体管T11的第二端与第一驱动单元53的控制端相连。
第二写入单元61包括第二写入晶体管T21，第二写入晶体管T21的第一端被配置为第二写入单元61的第一端，第二写入晶体管T21的第二端被配置为第二写入单元61的第二端，第二写入晶体管T21的控制端被配置为第二写入单元61的控制端。也即，第二写入晶体管T21的第一端与数据线30相连，第二写入晶体管T21的控制端与第二驱动线20相连，第二写入晶体管T21的第二端与第二驱动单元63的控制端相连。
示例性的，如图4所示，第一感测单元52包括第一感测晶体管T12，第一感测晶体管T12的第一端被配置为第一感测单元52的第一端，第一感测晶体管T12的第二端被配置为第一感测单元52的第二端，第一感测晶体管T12的控制端被配置为第一感测单元52的控制端。也即，第一感测晶体管T12的第一端与感测线40相连，第一感测晶体管T12的第二端与第一驱动单元53的第二端相连，第一感测晶体管T12的控制端与第二驱动线20相连。
第二感测单元62包括第二感测晶体管T22，第二感测晶体管T22的第一端被配置为第二感测单元62的第一端，第二感测晶体管T22的第二端被配置为第二感测单元62的第二端，第二感测晶体管T22的控制端被配置为第二感测单元62的控制端。也即，第二感测晶体管T22的第一端与感测线40相连，第二感测晶体管T22的第二端与第二驱动单元63的第二端相连，第二感测晶体管T22的控制端与第一驱动线10相连。
示例性的，如图4所示，第一驱动单元53包括第一驱动晶体管T13和第一存储电容C1，第一驱动晶体管T13的第一端被配置为第一驱动单元53的第一端，第一驱动晶体管T13的第二端被配置为第一驱动单元53的第二端，第一驱动晶体管T13的控制端被配置为第一驱动单元53的控制端。此时，第一驱动晶体管T13的第一端与第一电源ELVDD相连，第一驱动晶体管T13的第二端与第一发光单元70的一端相连，第一发光单元70的另一端与第二电源ELVSS相连，第一驱动晶体管T13的控制端与第一写入单元51相连，第一存储电容C1的一端与第一驱动晶体管T13的控制端相连，第一存储电容C1的另一端与第一驱动晶体管T13的第二端相连。
第二驱动单元63包括第二驱动晶体管T23和第二存储电容C2，第二驱动晶体管T23的第一端被配置为第二驱动单元63的第一端，第二驱动晶体管T23的第二端被配置为第二驱动单元63的第二端，第二驱动晶体管T23的控制端被配置为第二驱动单元63的控制端。此时，第二驱动晶体管T23的第一端与第一电源ELVDD相连，第二驱动晶体管T23的第二端与第二发光单元80的一端相连，第二发光单元80的另一端与第二电源ELVSS相连，第二驱 动晶体管T23的控制端与第二写入单元61相连，第二存储电容C2的一端与第二驱动晶体管T23的控制端相连，第二存储电容C2的另一端与第二驱动晶体管T23的第二端相连。
其中，第一驱动晶体管T13与第一发光单元70相连接以形成第一节点s1，第二驱动晶体管T23与第二发光单元80相连接以形成第二节点s2。
下面结合图5-6的时序图对图4实施例的像素电路的工作原理进行说明。
本公开一些实施例的像素电路的工作模式包括显示模式和感测模式。
需要说明的是，第一写入晶体管T11和第二感测晶体管T22必须为同类型的晶体管，第二写入晶体管T21和第一感测晶体管T12必须为同类型的晶体管。举例而言，第一写入晶体管T11和第二感测晶体管T22可为NPN型晶体管，则在第一驱动线10的输出信号为高电平时，第一写入晶体管T11和第二感测晶体管T22导通；或者，第一写入晶体管T11和第二感测晶体管T22也可为PNP型晶体管，则在第一驱动线10的输出信号为低电平时，第一写入晶体管T11和第二感测晶体管T22导通。同样的，第二写入晶体管T21和第一感测晶体管T12可为NPN型晶体管，则在第二驱动线20的输出信号为高电平时，第二写入晶体管T21和第一感测晶体管T12导通；或者，第二写入晶体管T21和第一感测晶体管T12可为PNP型晶体管，则在第二驱动线20的输出信号为低电平时，第二写入晶体管T21和第一感测晶体管T12导通。
本公开各实施例中所采用的晶体管可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。
此外，上述各晶体管的控制端为晶体管的栅极，第一端为晶体管的源极和漏极中一者，第二端为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开各实施例中的晶体管的第一端和第二端在结构上可以是没有区别的。示例性的，在晶体管为NPN型晶体管的情况下，晶体管的第一端可以为源极，第二端可以为漏极；又示例性的，在晶体管为PNP型晶体管的情况下，晶体管的第一端可以为漏极，第二端可以为源极。
本公开一些实施例以NPN型MOSFET或IGBT晶体管为例进行说明。需要说明的是，本公开的实施例包括但不限于此。例如，本公开的实施例提供的电路中的一个或多个晶体管也可以采用PNP型晶体管，只需将选定类型的晶体管的各极参照本公开一些实施例中的相应晶体管的各极相应连接，并且使相应的电压端提供对应的高电压或低电压即可。
图5为工作模式为显示模式时的时序图，其中，G1为第一驱动线10的 输出信号，G2为第二驱动线20的输出信号。图6为工作模式为感测模式时的时序图，其中，G1为第一驱动线10的输出信号，G2为第二驱动线20的输出信号，DATA为数据线30输出的数据电压信号，SENSE为感测线40上的电压信号。参考电压VREF为低电平电压，其中，在显示模式下，第一开关K1导通。
结合图5的实施例，在显示模式的第一阶段T1，第一驱动线10传输第一开启信号即高电平信号，第一写入晶体管T11导通，以对第一驱动晶体管T13的控制端即g1点进行预充电，也即对第一存储电容C1进行预充电。
在显示模式的第二阶段T2，第一驱动线10传输第一开启信号即高电平信号，第二驱动线20传输第二开启信号即高电平信号，第一写入晶体管T11继续导通，以将数据线30的第一数据电压(获取补偿数据后则写入补偿后的第一数据电压)写入第一驱动晶体管T13的控制端即g1点，第二写入晶体管T21在第二开启信号的控制下导通，以对第二驱动晶体管T23的控制端即g2点进行预充电，也即对第二存储电容C2进行预充电。另外，在此阶段还可以根据第一发光单元70的跨压对第一数据电压进行补偿。其中，第一发光单元70的跨压即为第一发光单元70两端的电压差。
在显示模式的第三阶段T3，第一驱动线10传输第一关闭信号即低电平信号，第二驱动线20传输第二开启信号即高电平信号，第一写入晶体管T11在第一关闭信号的控制下关断，第一驱动晶体管T13的控制端的电位通过第一存储电容C1维持，此时，由于第一存储电容C1的存在，第一驱动晶体管T13的控制端与第二端之间的电压Vgs保持不变，但由于第一感测晶体管T12在第二开启信号的控制下导通，感测线40将低电平信号提供至第一节点s1，第一发光单元70未发光。同时，第二感测晶体管T22在第一关闭信号的控制下关断，第二写入晶体管T21在第二开启信号的控制下导通，以将数据线30的第二数据电压(获取补偿数据后则写入补偿后的第二数据电压)写入第二驱动晶体管T23的控制端即g2点。另外，在此阶段还可以根据第二发光单元80的跨压对第二数据电压进行补偿。其中，第二发光单元80的跨压即为第二发光单元80两端的电压差。
在显示模式的第四阶段T4，第一驱动线10传输第一关闭信号即低电平信号，第二驱动线20传输第二关闭信号即低电平信号，第一写入晶体管T11在第一关闭信号的控制下关断，且第一感测晶体管T12在第二关闭信号的控制下关断，此时，第一驱动晶体管T13的控制端的电位通过第一存储电容C1维持在高电位，第一驱动晶体管T13导通，第一节点s1处的电压抬升，由于第 一存储电容C1的作用，第一驱动晶体管T13的控制端即g1点处的电压也自举抬升，第一驱动晶体管T13驱动第一发光单元70发光。并且，第二写入晶体管T21在第二关闭信号的控制下关断，且第二感测晶体管T22在第一关闭信号的控制下关断，此时，第二驱动晶体管T23的控制端的电位通过第二存储电容C2维持在高电位，第二驱动晶体管T23导通，第二节点s2处的电压抬升，由于第二存储电容C2的作用，第二驱动晶体管T23的控制端即g2点处的电压也自举抬升，第二驱动晶体管T23驱动第二发光单元80发光。
结合图6的实施例，在感测模式的第一数据写入阶段T1'，第一驱动线10传输第一开启信号即高电平信号，第二驱动线20传输第二开启信号即高电平信号，第一写入晶体管T11在第一开启信号的控制下导通，第一感测晶体管T12在第二开启信号的控制下导通，数据线30输出的数据电压Vdata即高电平电压写入第一驱动晶体管T13的控制端即g1点，且感测线40输出的参考电压VREF即低电平电压写入第一节点s1，示例地，如图4所示，可通过控制外部电路90中的第一开关K1闭合，将参考电压VREF写入感测线40，从而通过导通的第一感测晶体管T12将感测线40输出的参考电压VREF即低电平电压写入第一节点s1。
其中，在本公开的一些实施例中，外部电路90可以设置在驱动芯片中，以提高电路的集成度，在本公开的其他一些实施例中，外部电路90也可以设置在显示面板上。
在感测模式的第一充电阶段T2'，第一驱动线10传输第一关闭信号即低电平信号，且第二驱动线20传输第二开启信号即高电平信号，第一写入晶体管T11在第一关闭信号的控制下关断，第一感测晶体管T12在第二开启信号的控制下导通，第一驱动晶体管T13的控制端即g1点的电位通过第一存储电容C1保持在高电位，第一驱动晶体管T13导通，流过第一驱动晶体管T13的电流对第一节点s1也即第一存储电容C1充电，以使感测线40的电位随第一节点s1的电位变化。
在感测模式的第一采样阶段T3'，第一驱动线10传输第一关闭信号即低电平信号，且第二驱动线20传输第二开启信号即高电平信号，第一写入晶体管T11在第一关闭信号的控制下关断，此时，第一节点s1的电位为Vdata-Vth，其中Vth为第一驱动晶体管T13的阈值电压，第一感测晶体管T12在第二开启信号的控制下导通，从而通过外部电路90可读取感测线40的电位，进而感测第一驱动晶体管T13的阈值电压，示例地，如图2所示，可控制外部电路90中的第二开关K2闭合，从而采样保持器S/H可通过导通的第一感测晶 体管T12对第一节点s1处的电压进行采样并且保持，进而模数转换器ADC根据采样保持器S/H的输出信号感测第一驱动晶体管T13的阈值电压。
在感测模式的第二数据写入阶段T11'，第一驱动线10传输第一开启信号即高电平信号，第二驱动线20传输第二开启信号即高电平信号，第二写入晶体管T21在第二开启信号的控制下导通，第二感测晶体管T22在第一开启信号的控制下导通，数据线30传输的数据电压Vdata即高电平电压写入第二驱动晶体管T23的控制端即g2点，且感测线40输出的参考电压VREF即低电平电压写入第二节点s2，示例地，如图4所示，可通过控制外部电路90中的第一开关K1闭合，将参考电压VREF写入感测线40，从而通过导通的第二感测晶体管T22将感测线40输出的参考电压VREF即低电平电压写入第二节点s2。
在感测模式的第二充电阶段T22'，第二驱动线20传输第二关闭信号即低电平信号，且第一驱动线10传输第一开启信号即高电平信号，第二写入晶体管T21在第二关闭信号的控制下关断，第二感测晶体管T22在第一开启信号的控制下导通，第二驱动晶体管T23的控制端即g2点的电位通过第二存储电容C2保持在高电位，第二驱动晶体管T23导通，流过第二驱动晶体管T23的电流对第二节点s2也即第二存储电容C2充电，以使感测线40的电位随第二节点s2的电位变化。
在感测模式的第二采样阶段T33'，第二驱动线20传输第二关闭信号即低电平信号，且第一驱动线10传输第一开启信号即高电平信号，第二写入晶体管T21在第二关闭信号的控制下关断，此时，第二节点s2的电位为Vdata-Vth'，其中Vth'为第二驱动晶体管T23的阈值电压，第二感测晶体管T22在第一开启信号的控制下导通，从而通过外部电路90可读取感测线40的电位，进而感测第二驱动晶体管T23的阈值电压，示例地，如图2所示，可控制外部电路90中的第二开关K2闭合，从而采样保持器S/H可通过导通的第二感测晶体管T22对第二节点s2处的电压进行采样并且保持，进而模数转换器ADC根据采样保持器S/H的输出信号感测第二驱动晶体管T23的阈值电压。
如图6所示，在感测模式的数据写回阶段T4'，第一驱动线10传输第一开启信号即高电平信号，第二驱动线20传输第二开启信号即高电平信号，第一写入晶体管T11和第二感测晶体管T22在第一开启信号的控制下导通，第一感测晶体管T12和第二写入晶体管T21在第二开启信号的控制下导通，数据线30输出的数据电压即高电平电压同时写入第一驱动晶体管T13的控制端即g1点和第二驱动晶体管T23的控制端即g2点，且感测线40输出的参考电 压VREF即低电平电压同时写入第一节点s1和第二节点s2，示例地，如图4所示，可通过控制外部电路90中的第一开关K1闭合，将参考电压VREF写入感测线40，从而通过导通的第一感测晶体管T12和第二感测晶体管T22将感测线40输出的参考电压VREF即低电平电压写入第一节点s1和第二节点s2，其中，第一驱动晶体管T13的第二端和第一发光单元70的一端与第一节点s1相连，第二驱动晶体管T23的第二端和第二发光单元80的一端与第二节点s2相连。
可理解，在感测模式的数据写回阶段T4'，第一像素子电路50和第二像素子电路60同时进行数据写回，也就是说，第一像素子电路50中的第一写入晶体管T11和第二像素子电路60中的第二感测晶体管T22同时打开，第二像素子电路60中的第二写入晶体管T21和第一像素子电路50中的第一感测晶体管T12同时打开，并且，第一写入晶体管T11和第二写入晶体管T21同时打开，以分别向第一驱动晶体管T13的控制端和第二驱动晶体管T23的控制端写入相同的数据电压，第一感测晶体管T12和第二感测晶体管T22同时打开，以分别向第一节点s1和第二节点s2写入相同的参考电压。
由于在像素电路100的两种工作模式(即显示模式和感测模式)下，数据线30上传输的数据电压并不相同，也即感测模式下所使用的数据电压并不能够应用于显示模式。通过在感测模式的最后设置数据写回阶段T4'，使得数据线30上传输的数据电压能够在感测模式的数据写回阶段T4'发生变化，从而使得感测模式结束后，数据线30上的数据电压被调整至可应用于像素电路100的显示模式中。
综上，根据本公开一些实施例提出的像素电路，包括第一驱动线10、第二驱动线20、数据线30、感测线40、第一像素子电路50和第二像素子电路60，第一像素子电路50包括第一写入单元51、第一感测单元52和第一驱动单元53，第一写入单元51与数据线30相连，第一感测单元52与感测线40相连，第一驱动单元53与第一发光单元70相连以驱动第一发光单元70发光，第二像素子电路60包括第二写入单元61、第二感测单元62和第二驱动单元63，第二写入单元61与数据线30相连，第二感测单元62与感测线40相连，第二驱动单元63与第二发光单元80相连以驱动第二发光单元80发光，其中，第一写入单元51与第二感测单元62连接第一驱动线10，以在第一驱动线10的控制下同时开启或关闭，第二写入单元61与第一感测单元52连接第二驱动线20，以在第二驱动线20的控制下同时开启或关闭。由此，本公开一些实施例的像素电路100，通过将第一像素子电路50中的第一写入单元51与第二 像素子电路60中的第二感测单元62连接在一条驱动线上，第二像素子电路60中的第二写入单元61与第一像素子电路50中的第一感测单元52连接在另一条驱动线上，使得每个像素电路100中的两个像素子电路(即第一像素子电路50和第二像素子电路60)只需要连接两行栅极驱动电路的两个栅极输出端，也就是说，上述像素电路100所对应的栅极驱动电路每行只需要一个栅极输出端，从而，可减少栅极驱动电路输出端的个数，进而减小显示面板的边框。
基于上述实施例的像素电路100，本公开一些实施例还提出一种阵列基板200。如图7所示，该阵列基板200包括上述任一实施例所述的像素电路100。
示例性的，如图7所示，所述像素电路100中的第一像素子电路50和第二像素子电路60分别位于像素阵列201的相邻两行，该像素阵列201包括阵列排布的多个像素子电路。
举例而言，像素阵列201具有N行M列，那么，N行M列的像素阵列201包括N/2×M个图2或图4实施例的像素电路100。也就是说，像素阵列201中相邻两行且处于同一列处设置一个像素电路100，即在像素阵列201的每一列，第2i-1行和第2i行可以由图2或图4实施例的像素电路100构造，i＝1、2、…、N/2，N为偶数。
在一些示例中，像素电路100中的第一像素子电路50位于像素阵列201的奇数行，像素电路100中的第二像素子电路60位于像素阵列201的偶数行(如图7所示)。
在另一些示例中，像素电路100中的第一像素子电路50还可以位于像素阵列201的偶数行，像素电路100中的第二像素子电路60位于像素阵列201的奇数行。
图8为根据本公开一些实施例的显示面板300的一种方框示意图，如图8所示，显示面板300包括上述任一实施例所述的阵列基板200。
根据本公开一些实施例提出的显示面板300，通过设置的阵列基板200，将第一像素子电路50中的第一写入单元51与第二像素子电路60中的第二感测单元62连接在一条驱动线上，第二像素子电路60中的第二写入单元61与第一像素子电路50中的第一感测单元52连接在另一条驱动线上，使得每个像素电路100中的两个像素子电路(即第一像素子电路50和第二像素子电路60)只需要连接两行栅极驱动电路的两个栅极输出端，也就是说，上述像素电路100所对应的栅极驱动电路每行只需要一个栅极输出端，从而，可减少栅极驱动电路输出端的个数，进而减小显示面板300的边框。
基于上述实施例的显示面板300，如图9所示，本公开一些实施例还提出一种电子设备400，包括前述的显示面板300。
其中，电子设备400可以为显示装置，显示装置例如可以是电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等任何具有显示功能的部件。
根据本公开一些实施例提出的电子设备400，通过设置的显示面板300，将第一像素子电路50中的第一写入单元51与第二像素子电路60中的第二感测单元62连接在一条驱动线上，第二像素子电路60中的第二写入单元61与第一像素子电路50中的第一感测单元52连接在另一条驱动线上，使得每个像素电路100中的两个像素子电路(即第一像素子电路50和第二像素子电路60)只需要连接两行栅极驱动电路的两个栅极输出端，也就是说，上述像素电路100所对应的栅极驱动电路每行只需要一个栅极输出端，从而，可减少栅极驱动电路输出端的个数，进而减小电子设备400的边框。
基于上述实施例的像素电路100，本公开一些实施例还提出一种像素电路的驱动方法，用于驱动前述的像素电路100，像素电路100的工作模式包括显示模式，在显示模式下，该驱动方法包括至少一个第一周期，该第一周期包括第一～第四阶段。图10为根据本公开一些实施例的像素电路的一种驱动方法的流程示意图，如图10所示，本公开一些实施例的像素电路的驱动方法包括以下步骤：
S1，在显示模式的第一阶段，第一驱动线传输第一开启信号，第一写入单元在第一开启信号的控制下开启，以对第一驱动单元的控制端进行预充电。
S2，在显示模式的第二阶段，第一驱动线传输第一开启信号，第二驱动线传输第二开启信号，第一写入单元在第一开启信号的控制下开启，以将数据线的第一数据电压写入第一驱动单元的控制端，第二写入单元在第二开启信号的控制下开启，以对第二驱动单元的控制端进行预充电。
在本公开的一些实施例中，在显示模式的第二阶段，还根据第一发光单元的跨压对第一数据电压进行补偿。
S3，在显示模式的第三阶段，第一驱动线传输第一关闭信号，第二驱动线传输第二开启信号，第一写入单元在第一关闭信号的控制下关闭，以维持第一驱动单元的控制端的电位，且第二写入单元在第二开启信号的控制下开启，以将数据线的第二数据电压写入第二驱动单元的控制端。
在本公开的一些实施例中，在显示模式的第三阶段，还根据第二发光单元的跨压对第二数据电压进行补偿。
S4，在显示模式的第四阶段，第一驱动线传输第一关闭信号，第二驱动线传输第二关闭信号，第一写入单元在第一关闭信号的控制下关闭，且第一感测单元在第二关闭信号的控制下关闭，以使第一驱动单元驱动第一发光单元发光，第二写入单元在第二关闭信号的控制下关闭，且第二感测单元在第一关闭信号的控制下关闭，以使第二驱动单元驱动第二发光单元发光。
根据本公开的一些实施例，像素电路的工作模式包括感测模式，在感测模式下，该驱动方法包括至少一个第二周期，第二周期包括数据写回阶段。如图11所示，本公开一些实施例的像素电路的驱动方法包括以下步骤：
S16，在感测模式的数据写回阶段，第一驱动线传输第一开启信号，第二驱动线传输第二开启信号，第一写入单元和第二感测单元在第一开启信号的控制下开启，第一感测单元和第二写入单元在第二开启信号的控制下开启，数据线输出的数据电压同时写入第一驱动单元的控制端和第二驱动单元控制端，且感测线输出的参考电压同时写入第一节点和第二节点。
其中，第一驱动单元和第一发光单元均与第一节点相连，第二驱动单元和第二发光单元均与第二节点相连。
在本公开一些实施例中，在感测模式的数据写回阶段之前，第二周期还包括第一数据写入阶段、第一充电阶段和第一采样阶段。如图11所示，本公开一些实施例的像素电路的驱动方法还包括以下步骤：
S10，在第一数据写入阶段，第一驱动线传输第一开启信号，第二驱动线传输第二开启信号，第一写入单元在第一开启信号的控制下开启，第一感测单元在第二开启信号的控制下开启，数据线输出的数据电压写入第一驱动单元的控制端，且感测线输出的参考电压写入第一节点。
S11，在第一充电阶段，第一驱动线传输第一关闭信号，且第二驱动线传输第二开启信号，第一写入单元在第一关闭信号的控制下关闭，第一感测单元在第二开启信号的控制下开启，第一电源通过第一驱动单元对第一节点充电，以使感测线的电位随第一节点的电位变化。
S12，在第一采样阶段，第一驱动线传输第一关闭信号，且第二驱动线传输第二开启信号，第一写入单元在第一关闭信号的控制下关闭，第一感测单元在第二开启信号的控制下开启，通过外部电路读取感测线的电位以感测第一驱动单元的阈值电压。
在本公开的一些实施例中，在感测模式的数据写回阶段之前，在第一采样阶段之后，第二周期还包括第二数据写入阶段、第二充电阶段和第二采样阶段。如图11所示，本公开一些实施例的像素电路的驱动方法还包括以下步 骤：
S13，在第二数据写入阶段，第一驱动线传输第一开启信号，第二驱动线传输第二开启信号，第二写入单元在第二开启信号的控制下开启，第二感测单元在第一开启信号的控制下开启，数据线输出的数据电压写入第二驱动单元的控制端，且感测线输出的参考电压写入第二节点。
S14，在第二充电阶段，第二驱动线传输第二关闭信号，且第一驱动线传输第一开启信号，第二写入单元在第二关闭信号的控制下关闭，第二感测单元在第一开启信号的控制下开启，第一电源通过第二驱动单元对第二节点充电，以使感测线的电位随第二节点的电位变化。
S15，在第二采样阶段，第二驱动线传输第二关闭信号，且第一驱动线传输第一开启信号，第二写入电路在第二关闭信号的控制下关闭，第二感测单元在第一开启信号的控制下开启，通过外部电路读取感测线的电位以感测第二驱动单元的阈值电压。
需要说明的是，前述对像素电路实施例的解释说明也适用于本公开实施例的像素电路的驱动方法，此处不再赘述。
综上，根据本公开实施例提出的像素电路100的驱动方法，在显示模式的第一阶段，第一驱动线10传输第一开启信号，第一写入单元51在第一驱动线10的控制下开启，以对第一驱动单元53的控制端进行预充电；在显示模式的第二阶段，第一驱动线10传输第一开启信号，第二驱动线20传输第二开启信号，第一写入单元51在第一开启信号的控制下开启，以将数据线30的第一数据电压写入第一驱动单元53的控制端，第二写入单元61在第二开启信号的控制下开启，以对第二驱动单元63的控制端进行预充电；在显示模式的第三阶段，第一驱动线10传输第一关闭信号，第二驱动线20传输第二开启信号，第一写入单元51在第一关闭信号的控制下关闭，以维持第一驱动单元53的控制端的电位，且第二写入单元61在第二开启信号的控制下开启，以将数据线30的第二数据电压写入第二驱动单元63的控制端；在显示模式的第四阶段，第一驱动线10传输第一关闭信号，第二驱动线20传输第二关闭信号，第一写入单元51在第一关闭信号的控制下关闭，且第一感测单元52在第二关闭信号的控制下关闭，以使第一驱动单元53驱动第一发光单元70发光，第二写入单元61在第二关闭信号的控制下关闭，且第二感测单元62在第一关闭信号的控制下关闭，以使第二驱动单元63驱动第二发光单元80发光。由此，本公开一些实施例的像素电路的驱动方法，将第一像素子电路50中的第一写入单元51与第二像素子电路60中的第二感测单元62连接在一 条驱动线上，第二像素子电路60中的第二写入单元61与第一像素子电路52中的第一感测单元52连接在另一条驱动线上，使得每个像素电路100中的两个像素子电路(即第一像素子电路50和第二像素子电路60)只需要连接两行栅极驱动电路的两个栅极输出端，也就是说，上述像素电路100所对应的栅极驱动电路每行只需要一个栅极输出端，从而，可减少栅极驱动电路输出端的个数，进而减小显示面板的边框。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种像素电路，包括：
    第一驱动线、第二驱动线、数据线和感测线；
    第一像素子电路，所述第一像素子电路包括第一写入单元、第一感测单元和第一驱动单元，所述第一写入单元与所述数据线相连，所述第一感测单元与所述感测线相连，所述第一驱动单元与第一发光单元相连以驱动所述第一发光单元发光；
    第二像素子电路，所述第二像素子电路包括第二写入单元、第二感测单元和第二驱动单元，所述第二写入单元与所述数据线相连，所述第二感测单元与所述感测线相连，所述第二驱动单元与第二发光单元相连以驱动所述第二发光单元发光；
    其中，所述第一像素子电路和所述第二像素子电路分别位于像素阵列的相邻两行，所述像素阵列包括阵列排布的多个像素子电路；
    所述第一写入单元和所述第二感测单元均与所述第一驱动线相连，以在所述第一驱动线的控制下同时开启或关闭，所述第二写入单元和所述第一感测单元均与所述第二驱动线相连，以在所述第二驱动线的控制下同时开启或关闭。
  2. 根据权利要求1所述的像素电路，其中，
    所述第一写入单元的第一端与所述数据线相连，所述第一写入单元的控制端与所述第一驱动线相连；
    所述第一感测单元的第一端与所述感测线相连，所述第一感测单元的控制端与所述第二驱动线相连；
    所述第一驱动单元的控制端与所述第一写入单元的第二端相连，所述第一驱动单元的第一端与第一电源相连，所述第一驱动单元的第二端与所述第一感测单元的第二端相连，所述第一驱动单元的第二端还与所述第一发光单元相连；
    所述第二写入单元的第一端与所述数据线相连，所述第二写入单元的控制端与所述第二驱动线相连；
    所述第二感测单元的第一端与所述感测线相连，所述第二感测单元的控制端与所述第一驱动线相连；
    所述第二驱动单元的控制端与所述第二写入单元的第二端相连，所述第二驱动单元的第一端与所述第一电源相连，所述第二驱动单元的第二端与所述第二感测单元的第二端相连，所述第二驱动单元的第二端还与所述第二发光单元相连。
  3. 根据权利要求2所述的像素电路，其中，
    所述第一写入单元包括第一写入晶体管，所述第一写入晶体管的第一端、第二端和控制端分别被配置为所述第一写入单元的第一端、第二端和控制端；
    所述第二写入单元包括第二写入晶体管，所述第二写入晶体管的第一端、第二端和控制端分别被配置为所述第二写入单元的第一端、第二端和控制端。
  4. 根据权利要求2或3所述的像素电路，其中，
    所述第一感测单元包括第一感测晶体管，所述第一感测晶体管的第一端、第二端和控制端分别被配置为所述第一感测单元的第一端、第二端和控制端；
    所述第二感测单元包括第二感测晶体管，所述第二感测晶体管的第一端、第二端和控制端分别被配置为所述第二感测单元的第一端、第二端和控制端。
  5. 根据权利要求2～4中任一项所述的像素电路，其中，
    所述第一驱动单元包括第一驱动晶体管和第一存储电容，所述第一驱动晶体管的第一端、第二端和控制端分别被配置为所述第一驱动单元的第一端、第二端和控制端，所述第一存储电容的一端与所述第一驱动晶体管的控制端相连，所述第一存储电容的另一端与所述第一驱动晶体管的第二端相连；
    所述第一发光单元的一端与所述第一驱动晶体管的第二端相连，所述第一发光单元的另一端与第二电源相连；
    所述第二驱动单元包括第二驱动晶体管和第二存储电容，所述第二驱动晶体管的第一端、第二端和控制端分别被配置为所述第二驱动单元的第一端、第二端和控制端，所述第二存储电容的一端与所述第二驱动晶体管的控制端相连，所述第二存储电容的另一端与所述第二驱动晶体管的第二端相连；
    所述第二发光单元的一端与所述第二驱动晶体管的第二端相连，所述第二发光单元的另一端与所述第二电源相连。
  6. 根据权利要求1～5中任一项所述的像素电路，其中，所述第一驱动线和所述第二驱动线被配置为分别与栅极驱动电路中相邻两行的栅极驱动单元的输出端相连。
  7. 一种阵列基板，包括多个如权利要求1～6中任一项所述的像素电路。
  8. 根据权利要求7所述的阵列基板，其中，所述像素电路中的第一像素子电路和第二像素子电路分别位于像素阵列的相邻两行。
  9. 一种显示面板，包括：
    如权利要求7或8所述的阵列基板。
  10. 一种电子设备，包括：
    如权利要求9所述的显示面板。
  11. 一种像素电路的驱动方法，用于驱动如权利要求1～6中任一项所述的像素电路，所述像素电路的工作模式包括显示模式，在所述显示模式下，所述方法包括至少一个第一周期，所述第一周期包括第一～第四阶段；
    在所述显示模式的第一阶段，所述第一驱动线传输第一开启信号；所述第一写入单元在所述第一开启信号的控制下开启，以对所述第一驱动单元的控制端进行预充电；
    在所述显示模式的第二阶段，所述第一驱动线传输所述第一开启信号，所述第二驱动线传输第二开启信号；所述第一写入单元在所述第一开启信号的控制下开启，以将所述数据线的第一数据电压写入所述第一驱动单元的控制端；所述第二写入单元在所述第二开启信号的控制下开启，以对所述第二驱动单元的控制端进行预充电；
    在所述显示模式的第三阶段，所述第一驱动线传输第一关闭信号，所述第二驱动线传输所述第二开启信号；所述第一写入单元在所述第一关闭信号的控制下关闭，以维持所述第一驱动单元的控制端的电位；所述第二写入单元在所述第二开启信号的控制下开启，以将所述数据线的第二数据电压写入所述第二驱动单元的控制端；
    在所述显示模式的第四阶段，所述第一驱动线传输所述第一关闭信号，所述第二驱动线传输第二关闭信号；所述第一写入单元在所述第一关闭信号的控制下关闭，且所述第一感测单元在所述第二关闭信号的控制下关闭，以使所述第一驱动单元驱动所述第一发光单元发光；所述第二写入单元在所述第二关闭信号的控制下关闭，且所述第二感测单元在所述第一关闭信号的控制下关闭，以使所述第二驱动单元驱动所述第二发光单元发光。
  12. 根据权利要求11所述的像素电路的驱动方法，其中，所述像素电路的工作模式包括感测模式，在所述感测模式下，所述方法包括至少一个第二周期，所述第二周期包括数据写回阶段；
    在所述感测模式的数据写回阶段，所述第一驱动线传输所述第一开启信号，所述第二驱动线传输第二开启信号；所述第一写入单元和所述第二感测单元在所述第一开启信号的控制下开启，所述第一感测单元和所述第二写入单元在所述第二开启信号的控制下开启，所述数据线输出的数据电压同时写入所述第一驱动单元的控制端和所述第二驱动单元控制端，且所述感测线输出的参考电压同时写入第一节点和第二节点；
    其中，所述第一驱动单元和所述第一发光单元均与所述第一节点相连，所述第二驱动单元和所述第二发光单元均与所述第二节点相连。
  13. 根据权利要求12所述的像素电路的驱动方法，其中，在所述感测模式的数据写回阶段之前，所述第二周期还包括第一数据写入阶段、第一充电阶段和第一采样阶段；
    在所述第一数据写入阶段，所述第一驱动线传输所述第一开启信号，所述第二驱动线传输第二开启信号；所述第一写入单元在所述第一开启信号的控制下开启，所述第一感测单元在所述第二开启信号的控制下开启，所述数据线输出的数据电压写入所述第一驱动单元的控制端，且所述感测线输出的参考电压写入所述第一节点；
    在所述第一充电阶段，所述第一驱动线传输所述第一关闭信号，且所述第二驱动线传输第二开启信号；所述第一写入单元在所述第一关闭信号的控制下关闭，所述第一感测单元在所述第二开启信号的控制下开启，第一电源通过所述第一驱动单元对所述第一节点充电，以使所述感测线的电位随所述第一节点的电位变化；
    在所述第一采样阶段，所述第一驱动线传输所述第一关闭信号，且所述第二驱动线传输第二开启信号；所述第一写入单元在所述第一关闭信号的控制下关闭，所述第一感测单元在所述第二开启信号的控制下开启，通过外部电路读取所述感测线的电位以感测所述第一驱动单元的阈值电压。
  14. 根据权利要求13所述的像素电路的驱动方法，其中，在所述感测模式的数据写回阶段之前，且在所述第一采样阶段之后，所述第二周期还包括第二数据写入阶段、第二充电阶段和第二采样阶段：在所述第二数据写入阶段，所述第一驱动线传输所述第一开启信号，所述第二驱动线传输第二开启信号；所述第二写入单元在所述第二开启信号的控制下开启，所述第二感测单元在所述第一开启信号的控制下开启，所述数据线输出的数据电压写入所述第二驱动单元的控制端，且所述感测线输出的参考电压写入所述第二节点；
    在所述第二充电阶段，所述第二驱动线传输所述第二关闭信号，且所述第一驱动线传输第一开启信号；所述第二写入单元在所述第二关闭信号的控制下关闭，所述第二感测单元在所述第一开启信号的控制下开启，所述第一电源通过所述第二驱动单元对所述第二节点充电，以使所述感测线的电位随所述第二节点的电位变化；
    在所述第二采样阶段，所述第二驱动线传输所述第二关闭信号，且所述第一驱动线传输第一开启信号，所述第二写入电路在所述第二关闭信号的控制下关闭，所述第二感测单元在所述第一开启信号的控制下开启，通过所述外部电路读取所述感测线的电位以感测所述第二驱动单元的阈值电压。
  15. 根据权利要求11～14中任一项所述的像素电路的驱动方法，其中，在所述显示模式的第二阶段，还根据所述第一发光单元的跨压对所述第一数据电压进行补偿。
  16. 根据权利要求11～15中任一项所述的像素电路的驱动方法，其中，在所述显示模式的第三阶段，还根据所述第二发光单元的跨压对所述第二数据电压进行补偿。
PCT/CN2020/111486 2019-08-27 2020-08-26 像素电路及其驱动方法、阵列基板、显示面板以及电子设备 WO2021037081A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US17/420,054 US11495153B2 (en) 2019-08-27 2020-08-26 Pixel circuit and driving method therefor, array substrate, display panel, and electronic device
US17/944,523 US11688316B2 (en) 2019-08-27 2022-09-14 Pixel circuit and driving method therefor, array substrate, display panel, and electronic device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910799367.7 2019-08-27
CN201910799367.7A CN110491337B (zh) 2019-08-27 2019-08-27 像素电路及其驱动方法、显示面板以及电子设备

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US17/420,054 A-371-Of-International US11495153B2 (en) 2019-08-27 2020-08-26 Pixel circuit and driving method therefor, array substrate, display panel, and electronic device
US17/944,523 Continuation US11688316B2 (en) 2019-08-27 2022-09-14 Pixel circuit and driving method therefor, array substrate, display panel, and electronic device

Publications (1)

Publication Number Publication Date
WO2021037081A1 true WO2021037081A1 (zh) 2021-03-04

Family

ID=68553668

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/111486 WO2021037081A1 (zh) 2019-08-27 2020-08-26 像素电路及其驱动方法、阵列基板、显示面板以及电子设备

Country Status (3)

Country Link
US (2) US11495153B2 (zh)
CN (1) CN110491337B (zh)
WO (1) WO2021037081A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110491337B (zh) * 2019-08-27 2021-02-05 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板以及电子设备
CN111261101A (zh) 2020-02-28 2020-06-09 合肥京东方卓印科技有限公司 像素电路及其驱动方法、显示面板
CN113327556A (zh) * 2021-06-25 2021-08-31 合肥京东方卓印科技有限公司 像素电路及其驱动方法、显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020140364A1 (en) * 2000-12-21 2002-10-03 Semiconductor Energy Laboratory Co., Ltd. Light emitting device, driving method thereof and electric equipment using the light emitting device
CN101449311A (zh) * 2006-02-10 2009-06-03 伊格尼斯创新有限公司 用于发光装置显示器的方法和系统
CN104732920A (zh) * 2013-12-24 2015-06-24 乐金显示有限公司 有机发光显示装置
CN109523954A (zh) * 2018-12-24 2019-03-26 合肥鑫晟光电科技有限公司 像素单元、显示面板、驱动方法以及补偿控制方法
CN109935212A (zh) * 2019-02-28 2019-06-25 合肥京东方卓印科技有限公司 显示面板、显示装置及驱动方法
CN110491337A (zh) * 2019-08-27 2019-11-22 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板以及电子设备

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007090287A1 (en) 2006-02-10 2007-08-16 Ignis Innovation Inc. Method and system for light emitting device displays
CN103050080B (zh) * 2011-10-11 2015-08-12 上海天马微电子有限公司 有机发光显示器的像素电路及其驱动方法
KR101528148B1 (ko) * 2012-07-19 2015-06-12 엘지디스플레이 주식회사 화소 전류 측정을 위한 유기 발광 다이오드 표시 장치 및 그의 화소 전류 측정 방법
KR101993747B1 (ko) * 2013-04-02 2019-07-02 삼성디스플레이 주식회사 유기전계발광 표시장치 및 그의 구동방법
KR102021970B1 (ko) * 2013-05-30 2019-09-17 엘지디스플레이 주식회사 발광다이오드 표시장치
CN103413521B (zh) * 2013-07-31 2015-06-10 京东方科技集团股份有限公司 有机发光二极管像素电路及其驱动方法、显示装置
KR101688923B1 (ko) * 2013-11-14 2016-12-23 엘지디스플레이 주식회사 유기발광표시장치 및 그 구동방법
KR102084444B1 (ko) * 2013-12-31 2020-03-04 엘지디스플레이 주식회사 유기발광다이오드 표시장치
KR102431961B1 (ko) * 2015-12-02 2022-08-12 엘지디스플레이 주식회사 유기발광 표시장치 및 그 구동방법
KR102460556B1 (ko) * 2015-12-31 2022-10-31 엘지디스플레이 주식회사 유기발광표시패널, 유기발광표시장치 및 그 구동방법
KR102515629B1 (ko) * 2016-06-30 2023-03-29 엘지디스플레이 주식회사 유기발광 표시장치
KR102482575B1 (ko) * 2017-10-31 2022-12-28 엘지디스플레이 주식회사 유기 발광 표시 장치
CN109166527B (zh) 2018-10-24 2020-07-24 合肥京东方卓印科技有限公司 显示面板、显示装置及驱动方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020140364A1 (en) * 2000-12-21 2002-10-03 Semiconductor Energy Laboratory Co., Ltd. Light emitting device, driving method thereof and electric equipment using the light emitting device
CN101449311A (zh) * 2006-02-10 2009-06-03 伊格尼斯创新有限公司 用于发光装置显示器的方法和系统
CN104732920A (zh) * 2013-12-24 2015-06-24 乐金显示有限公司 有机发光显示装置
CN109523954A (zh) * 2018-12-24 2019-03-26 合肥鑫晟光电科技有限公司 像素单元、显示面板、驱动方法以及补偿控制方法
CN109935212A (zh) * 2019-02-28 2019-06-25 合肥京东方卓印科技有限公司 显示面板、显示装置及驱动方法
CN110491337A (zh) * 2019-08-27 2019-11-22 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板以及电子设备

Also Published As

Publication number Publication date
US20230052249A1 (en) 2023-02-16
US11495153B2 (en) 2022-11-08
US20220084448A1 (en) 2022-03-17
US11688316B2 (en) 2023-06-27
CN110491337B (zh) 2021-02-05
CN110491337A (zh) 2019-11-22

Similar Documents

Publication Publication Date Title
US10726786B2 (en) Pixel compensation circuit, method for driving the same, display panel, and display device
WO2021037081A1 (zh) 像素电路及其驱动方法、阵列基板、显示面板以及电子设备
CN107424555B (zh) 一种像素电路、驱动方法及显示器
US20190259785A1 (en) Pixel circuit of active-matrix light-emitting diode comprising oxide semiconductor transistor and silicon semiconductor transistor and display panel having the same
TWI573117B (zh) 主動式有機發光二極體顯示器的像素電路
EP3156994B1 (en) Pixel driver circuit, driving method, array substrate, and display device
US11132951B2 (en) Pixel circuit, pixel driving method and display device
WO2016095477A1 (zh) 像素驱动电路、像素驱动方法和显示装置
US9293085B2 (en) Pixel circuit which corrects variations in threshold voltage for a driving transistor and driving method thereof
WO2016173124A1 (zh) 像素电路、其驱动方法及相关装置
WO2017054408A1 (zh) 像素驱动电路、显示面板及其驱动方法和显示装置
WO2016011714A1 (zh) 像素电路、像素电路的驱动方法和显示装置
US9870735B2 (en) Display device including double-gate transistors with reduced deterioration
WO2016101504A1 (zh) 一种像素电路、有机电致发光显示面板及显示装置
WO2016011711A1 (zh) 像素电路、像素电路的驱动方法和显示装置
WO2017117940A1 (zh) 像素驱动电路、像素驱动方法、显示面板和显示装置
US9514676B2 (en) Pixel circuit and driving method thereof and display apparatus
US20150053947A1 (en) Light emitting diode pixel unit circuit and display panel
WO2016086626A1 (zh) 一种像素驱动电路、像素驱动方法和显示装置
WO2019109673A1 (zh) 像素电路及其驱动方法、显示面板和显示设备
WO2019223648A1 (zh) 显示面板的驱动方法和显示装置
WO2016155161A1 (zh) Oeld像素电路、显示装置及控制方法
US8847934B2 (en) Displaying apparatus
US20160225313A1 (en) Light emitting diode pixel unit circuit and display panel
CN109949739B (zh) 一种像素电路、驱动方法及显示器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20857055

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20857055

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20857055

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 06.10.2022)

122 Ep: pct application non-entry in european phase

Ref document number: 20857055

Country of ref document: EP

Kind code of ref document: A1