WO2021036836A1 - 接口时序校准方法及装置 - Google Patents

接口时序校准方法及装置 Download PDF

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Publication number
WO2021036836A1
WO2021036836A1 PCT/CN2020/109392 CN2020109392W WO2021036836A1 WO 2021036836 A1 WO2021036836 A1 WO 2021036836A1 CN 2020109392 W CN2020109392 W CN 2020109392W WO 2021036836 A1 WO2021036836 A1 WO 2021036836A1
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data packet
application layer
clock
physical layer
clock signal
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PCT/CN2020/109392
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English (en)
French (fr)
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张西锋
段琪
王卓
邓海东
孙顺清
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晶晨半导体(上海)股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0004—Parallel ports, e.g. centronics

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  • the present invention relates to the field of communication technology, in particular to an interface timing calibration method and device.
  • Chips are greatly affected by chip manufacturing deviations, and large deviations are likely to occur between chip interface data and clock timing. Chips generally use fixed timing parameters, and the effective window margin is relatively small, resulting in product yield. Poor problem.
  • An interface timing calibration method applied to an interface coupled to an application layer and a physical layer, the physical layer adopts a loopback mode, and includes the following steps:
  • the application layer sends a data packet to the physical layer, the application layer receives the data packet sent by the physical layer, and judges the data packet according to the data packet received by the application layer.
  • the validity of the clock signal
  • the effective range of the clock phase of the clock signal is obtained, and the phase of the receiving target clock is obtained according to the effective range.
  • the step of the clock signal received by the application layer is adjusted, the application layer sends a data packet to the physical layer, and the application layer receives the data packet sent by the physical layer based on the data received by the application layer
  • the step of packet judging the validity of the clock signal includes:
  • the application layer sends a data packet to the physical layer, and the physical layer sends the received data packet to the application layer in a loopback manner;
  • the application layer verifies the received data packet, and marks the sending clock of the application layer corresponding to the data packet that has passed the verification;
  • the step of the application layer verifying the received data packet and marking the sending clock of the application layer corresponding to the data packet that has passed the verification includes:
  • the application layer compares the received data packet with the corresponding sent data packet, and if the data packets are the same, the verification is passed, and the sending clock of the application layer corresponding to the received data packet is marked.
  • the step of the application layer verifying the received data packet and marking the sending clock of the application layer corresponding to the data packet that has passed the verification includes:
  • the application layer uses a cyclic redundancy check code to verify the received data packet, and if the verification passes, the application layer sending clock corresponding to the received data packet is marked.
  • the step of acquiring the valid range of the clock phase of the clock signal and acquiring the phase of the receiving target clock according to the valid range includes:
  • the middle phase of the effective range is used as the phase of the reception target clock.
  • the present invention also provides an interface timing calibration device, which is applied in an interface coupled to the application layer and the physical layer, and the physical layer adopts a loopback mode, including:
  • the control unit is configured to adjust the step of the clock signal received by the application layer, the application layer sends a data packet to the physical layer, the application layer receives the data packet sent by the physical layer, and the application layer receives Judging the validity of the clock signal according to the data packet;
  • the processing unit is configured to obtain the valid range of the clock phase of the clock signal, and obtain the phase of the receiving target clock according to the valid range.
  • control unit includes:
  • An adjustment module configured to adjust the clock signal received by the application layer at a preset step within a preset period range
  • a sending module configured to send a data packet to the physical layer, and the physical layer outputs the received data packet in a loopback manner
  • a receiving module for receiving data packets sent by the physical layer
  • the verification module is used to verify the received data packet and mark the sending clock of the application layer corresponding to the data packet that has passed the verification.
  • the verification module is used to compare the received data packet with the corresponding sent data packet, if the data packet is the same, the verification is passed, and the application layer corresponding to the received data packet is sent The clock is marked.
  • the check module is configured to check the received data packet by using a cyclic redundancy check code, and if the check passes, mark the sending clock of the application layer corresponding to the received data packet .
  • the processing unit is configured to generate a valid range of clock phases according to all the marked sending clocks, and use the middle phase of the valid range as the phase of the receiving target clock.
  • the interface timing calibration method is applied to the interface coupled to the application layer and the physical layer.
  • the application layer sends the data packet to the physical layer and obtains the loopback of the physical layer.
  • Data packet in order to judge the validity of the clock signal according to the data packet received by the application layer; obtain the phase of the receiving target clock according to the clock phase valid range of the clock signal, so as to realize the selection of the best clock timing parameters according to different chips to make the interface
  • the effective window margin is maximized.
  • FIG. 1 is a method flowchart of an embodiment of the interface timing calibration method according to the present invention
  • FIG. 2 is a flowchart of an embodiment of the method for adjusting the step by which the application layer receives the clock signal to obtain the validity of the clock signal according to the present invention
  • FIG. 3 is a block diagram of an embodiment of the interface timing calibration device according to the present invention.
  • this embodiment provides an interface timing calibration method, which is applied to an interface coupled to an application layer and a physical layer (Physical Layer, PHY for short).
  • the physical layer adopts a loopback mode, including the following step:
  • the application layer sends a data packet to the physical layer, and the application layer receives the data packet sent by the physical layer according to the data packet received by the application layer Judging the validity of the clock signal;
  • the application layer is the media access control layer (Media Access Control, MAC for short) of the chip.
  • the interface in this embodiment is RGMII (Reduced Gigabit Media Independent Interface), which is a simplified gigabit media independent interface.
  • step S1 may include:
  • the application layer sends a data packet to the physical layer, and the physical layer sends the received data packet to the application layer in a loopback manner;
  • the physical layer loopback has two signal loopback methods, one is loopback at the RGMII interface of the physical layer, and the other is realized by loopback network cable. Both loopback methods need to be configured. Realization of registers at the physical layer.
  • the data packet sent by the application layer is a longer-length data packet (for example: 1514Byte) to ensure correctness, prevent window misjudgment, and ensure the balance between sending time and communication accuracy.
  • the application layer verifies the received data packet, and marks the sending clock of the application layer corresponding to the data packet that passes the verification;
  • the application layer may compare the received data packet with the corresponding sent data packet, and if the data packets are the same, the verification is passed, and the application layer corresponding to the received data packet The send clock is marked.
  • the application layer may use a cyclic redundancy check code to verify the received data packet, and if the verification is passed, the application layer transmission clock corresponding to the received data packet Mark it.
  • each step has a delay of 0.2ns as an example.
  • the adjustable range provided is 0-3ns, and the physical layer interface
  • the delay of the clock signal can be reversed through the internal registers of the chip, which is equivalent to an increase of 4ns delay (clock cycle is 8ns), and the internal clock of the physical layer has a fixed delay of 2ns. Therefore, when performing step adjustment, the delay of the received clock signal can be divided into 4 stages, as follows:
  • the first stage 0 ⁇ 3ns
  • the second stage 2ns ⁇ 5ns, adjust the application layer sending clock step on the basis of the internal clock delay of the outer physical layer 2ns;
  • the third stage 4ns ⁇ 7ns, after setting the register in the chip reversely, adjust the application layer sending clock step;
  • the fourth stage 6ns ⁇ 9ns, on the basis of the internal clock delay of the outer physical layer of 2ns, and after the internal registers of the chip are set in reverse, the application layer sends the clock step to be adjusted.
  • the above four segments are to adjust the timing of the sending clock with 0.2ns as a step.
  • the adjustment range covers one clock cycle.
  • the timing of the received clock signal is adjusted step by step at each stage, and the application layer Send data packets to the physical layer.
  • the physical layer feeds back the received data packets to the application layer through a loopback method; the application layer verifies the received data packets and sends the corresponding application layer to the data packets that pass the verification.
  • the clock is marked and adjusted step by step, and the sending clock of the application layer corresponding to each step is obtained for marking until the adjustment of all stages is completed.
  • step S2 may include:
  • the middle phase of the effective range is used as the phase of the reception target clock.
  • the phase of the receiving target clock can be set to the middle position of the effective range to ensure the stable and reliable data communication of the RGMII interface.
  • 2.5MHz, 25MHz or 125MHz can be used to calibrate the interface timing. Calibrate each data interface in the RGMII interface one by one.
  • the physical layer adopts the loopback mode, so that the application layer can receive the data packet sent by itself, and check the received data packet to determine whether the current RGMII interface clock phase passes the verification, and then Adjust the clock phase and repeat the packet sending and receiving and data packet checking operations in the previous step. After scanning the complete clock phase, find the valid range of the clock phase, and then set the clock phase to the middle position of the valid range of the clock phase to ensure the data of the RGMII interface
  • the communication is stable and reliable, so that the best timing parameters can be selected as the phase of the receiving target clock according to different chips, so as to maximize the effective window margin of the interface.
  • an interface timing calibration device is applied to an interface coupled to the application layer and the physical layer.
  • the physical layer adopts a loopback mode and includes: a control unit 1 and a processing unit 2, wherein:
  • the control unit 1 is configured to adjust the step of the clock signal received by the application layer, the application layer sends data packets to the physical layer, and the application layer receives data packets sent by the physical layer according to the application layer The received data packet judges the validity of the clock signal;
  • the application layer is the media access control layer of the chip.
  • the interface in this embodiment is RGMII, which is a simplified gigabit media independent interface.
  • the control unit 1 may include: an adjustment module 11, a sending module 12, a receiving module 13, and a verification module 14, wherein:
  • the adjustment module 11 is configured to adjust the clock signal received by the application layer at a preset step within a preset period range
  • the sending module 12 is configured to send a data packet to the physical layer, and the physical layer outputs the received data packet in a loopback manner;
  • the data packet sent by the application layer is a longer-length data packet (for example: 1514Byte) to ensure correctness, prevent window misjudgment, and ensure the balance between sending time and communication accuracy.
  • the receiving module 13 is configured to receive data packets sent by the physical layer
  • the verification module 14 is configured to verify the received data packet, and mark the sending clock of the application layer corresponding to the data packet that has passed the verification.
  • the verification module 14 can compare the received data packet with the corresponding sent data packet. If the data packet is the same, the verification is passed, and the application corresponding to the received data packet is checked. The sending clock of the layer is marked.
  • the check module 14 may also use a cyclic redundancy check code to check the received data packet, and if the check passes, then check the application layer corresponding to the received data packet. Send clock to mark.
  • the processing unit 2 is configured to obtain the valid range of the clock phase of the clock signal, and obtain the phase of the receiving target clock according to the valid range.
  • the processing unit 2 may generate the valid range of the clock phase according to all the marked sending clocks, and use the middle phase of the valid range as the phase of the receiving target clock.
  • 2.5MHz, 25MHz or 125MHz can be used to calibrate the interface timing. Calibrate each data interface in the RGMII interface one by one.
  • the interface timing calibration device adopts the loopback mode through the physical layer, so that the application layer can receive the data packet sent by itself, and check the received data packet to determine whether the current RGMII interface clock phase passes the verification, and then adjust the clock Phase and repeat the packet sending and receiving and data packet checking operations in the previous step. After scanning the complete clock phase, find the valid range of the clock phase, and then set the clock phase to the middle position of the valid range of the clock phase to ensure the stable data communication of the RGMII interface Reliable, so as to realize the selection of the best timing parameters according to different chips as the phase of the receiving target clock, so as to maximize the effective window margin of the interface.

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Abstract

本发明公开了一种接口时序校准方法及装置，属于通信技术领域。本发明接口时序校准方法应用在耦合于应用层与物理层的接口中，通过调整应用层接收时钟信号的步进，应用层将数据包发送至物理层，并获取物理层环回的数据包，以便于依据应用层接收的数据包判断时钟信号的有效性；根据时钟信号的时钟相位有效范围获取接收目标时钟的相位，从而实现根据不同芯片选择最佳的时钟时序参数，以使接口的有效窗口余量最大化。

Description

接口时序校准方法及装置 技术领域
本发明涉及通信技术领域，尤其涉及一种接口时序校准方法及装置。
背景技术
现有芯片接口随着芯片制造偏差的影响较大，芯片接口的数据与时钟时序之间容易出现较大偏差，芯片普遍采用固定的时序参数，有效窗口余量相对较小，从而造成产品良率较差的问题。
发明内容
针对现有芯片接口窗口余量小的问题，现提供一种旨在可根据不同芯片的选择最佳的时序参数的接口时序校准方法及装置。
一种接口时序校准方法，应用在耦合于应用层与物理层的接口中，所述物理层采用环回模式，包括下述步骤：
调整所述应用层接收时钟信号的步进，所述应用层向所述物理层发送数据包，所述应用层接收所述物理层发送的数据包，依据所述应用层接收的数据包判断所述时钟信号的有效性；
获取所述时钟信号的时钟相位有效范围，根据所述有效范围获取接收目标时钟的相位。
优选的，调整所述应用层接收时钟信号的步进，所述应用层向所述物理层发送数据包，所述应用层接收所述物理层发送的数据包，依据所述应用层接收的数据包判断所述时钟信号的有效性的步骤，包括：
在预设周期范围内以预设步进调整所述应用层接收时钟信号；
所述应用层发送数据包至所述物理层，所述物理层通过环回的方式将接收到的所述数据包发送至所述应用层；
所述应用层对接收到的所述数据包进行校验，对校验通过的所述数据包对应的应用层的发送时钟进行标记；
重复调整所述应用层接收时钟信号，直至完成所述预设周期范围内所有步进的调整。
优选的，所述应用层对接收到的所述数据包进行校验，对校验通过的所述数据包对应的应用层的发送时钟进行标记的步骤，包括：
所述应用层将接收到的所述数据包与相应的发送数据包进行比对，若数据包相同，则校验通过，对接收到的数据包对应的应用层的发送时钟进行标记。
优选的，所述应用层对接收到的所述数据包进行校验，对校验通过的所述数据包对应的应用层的发送时钟进行标记的步骤，包括：
所述应用层采用循环冗余校验码对接收到的所述数据包进行校验，若校验通过，则对接收到的数据包对应的应用层的发送时钟进行标记。
优选的，获取所述时钟信号的时钟相位有效范围，根据所述有效范围获取接收目标时钟的相位的步骤，包括：
根据标记的所有所述发送时钟生成时钟相位的有效范围；
将所述有效范围的中间相位作为所述接收目标时钟的相位。
本发明还提供一种接口时序校准装置，应用在耦合于应用层与物理层的接口中，所述物理层采用环回模式，包括：
控制单元，用于调整所述应用层接收时钟信号的步进，所述应用层向所述物理层发送数据包，所述应用层接收所述物理层发送的数据包，依据所述应用层接收的数据包判断所述时钟信号的有效性；
处理单元，用于获取所述时钟信号的时钟相位有效范围，根据所述有效范围获取接收目标时钟的相位。
优选的，所述控制单元包括：
调整模块，用于在预设周期范围内以预设步进调整所述应用层接收时钟信号；
发送模块，用于发送数据包至所述物理层，所述物理层通过环回的方式将接收到的所述数据包输出；
接收模块，用于对接收所述物理层发送的数据包；
校验模块，用于对接收到的所述数据包进行校验，对校验通过的所述数据包对应的应用层的发送时钟进行标记。
优选的，所述校验模块用于将接收到的所述数据包与相应的发送数据包进行比对，若数据包相同，则校验通过，对接收到的数据包对应的应用层的发送时钟进行标记。
优选的，所述校验模块用于采用循环冗余校验码对接收到的所述数据包进行校验，若校验通过，则对接收到的数据包对应的应用层的发送时钟进行标记。
优选的，所述处理单元用于根据标记的所有所述发送时钟生成时钟相位的有效范围，将所述有效范围的中间相位作为所述接收目标时钟的相位。
上述技术方案的有益效果：
本技术方案中，接口时序校准方法应用在耦合于应用层与物理层的接口中，通过调整应用层接收时钟信号的步进，应用层将数据包发送至物理层，并获取物理层环回的数据包，以便于依据应用层接收的数据包判断时钟信号的有效性；根据时钟信号的时钟相位有效范围获取接收目标时钟的相位，从而实现根据不同芯片选择最佳的时钟时序参数，以使接口的有效窗口余量最大化。
附图说明
图1为本发明所述的接口时序校准方法的一种实施例的方法流程图；
图2为本发明调整应用层接收时钟信号的步进获取时钟信号的有效性的一种实施例的方法流程图；
图3为本发明所述的接口时序校准装置的一种实施例的模块图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
需要说明的是，在不冲突的情况下，本发明中的实施例及实施例中的特征可以相互组合。
下面结合附图和具体实施例对本发明作进一步说明，但不作为本发明的限定。
如图1所示，本实施例提供了一种接口时序校准方法，应用在耦合于应用层与物理层(Physical Layer，简称PHY)的接口中，所述物理层采用环回模式，包括下述步骤：
S1.调整所述应用层接收时钟信号的步进，所述应用层向所述物理层发送数据包，所述应用层接收所述物理层发送的数据包，依据所述应用层接收的数据包判断所述时钟信号的有效性；
需要说明的是：应用层为芯片的媒体访问控制层(Media Access Control，简称MAC)。本实施例中的接口为RGMII(Reduced Gigabit Media Independent Interface)是简化的吉比特媒体独立接口。
参考图2所示，具体地，步骤S1可包括：
S11.在预设周期范围内以预设步进调整所述应用层接收时钟信号；
S12.所述应用层发送数据包至所述物理层，所述物理层通过环回的方式将接收到的所述数据包发送至所述应用层；
在本步骤中，物理层环回有两种信号环回方式，一种是在物理层的RGMII 接口处做环回，另外一种是通过环回网线实现，两种方式环回方式都需要配置物理层的寄存器实现。应用层发送数据包为长度较长的数据包(例如：1514Byte)以保证正确，防止窗口错判，保证发送时间与通信准确性之间的平衡。
S13.所述应用层对接收到的所述数据包进行校验，对校验通过的所述数据包对应的应用层的发送时钟进行标记；
进一步地，在步骤S13中所述应用层可将接收到的所述数据包与相应的发送数据包进行比对，若数据包相同，则校验通过，对接收到的数据包对应的应用层的发送时钟进行标记。
进一步地，在步骤S13中所述应用层可采用循环冗余校验码对接收到的所述数据包进行校验，若校验通过，则对接收到的数据包对应的应用层的发送时钟进行标记。
S14.判断是否完成对所述预设周期范围内所有步进的调整，若是，执行步骤S2；若否，执行步骤S11。
作为举例而非限定，在实际应用中以芯片的时钟信号内部有15个步进(step)，每个步进延迟为0.2ns为例，提供的可调节范围为0～3ns，物理层的接口的时钟信号延迟可通过芯片内部的寄存器设置反向，相当于增加了4ns的延迟(时钟周期为8ns)，另外物理层内部时钟有2ns的固定延迟。因此在进行步进调节时可以将接收时钟信号延迟分为4个阶段范围，具体如下：
第一阶段：0～3ns；
第二阶段：2ns～5ns，在外物理层内部时钟延迟2ns的基础上调节应用层发送时钟步进；
第三阶段：4ns～7ns，将芯片内部的寄存器设置反向后，调节应用层发送时钟步进；
第四阶段：6ns～9ns，在外物理层内部时钟延迟2ns的基础上，且将芯片内部的寄存器设置反向后，调节应用层发送时钟步进。
上述四段为以0.2ns为一个步进调整发送时钟的时序，调整范围覆盖了一个时钟周期，在实际应用时，分别在每一阶段逐个步进进行调整接收时钟信号的时序，并由应用层发送数据包至物理层，物理层通过环回的方式将接收到的数据包反馈至应用层；应用层对接收到的数据包进行校验，对校验通过的数据包对应的应用层的发送时钟进行标记，逐个步进进行调节，获取每一步进对应的应用层的发送时钟进行标记，直至完成所有阶段的调节。
S2.获取所述时钟信号的时钟相位有效范围，根据所述有效范围获取接收目标时钟的相位。
具体地，步骤S2可包括：
根据标记的所有所述发送时钟生成时钟相位的有效范围；
将所述有效范围的中间相位作为所述接收目标时钟的相位。
在本步骤中，通过获取的时钟相位的有效范围，可将接收目标时钟的相位设置为有效范围的中间位置，以确保RGMII接口的数据通信稳定可靠。
在实际应用中，可采用2.5MHz、25MHz或125MHz对接口时序校准。逐个对RGMII接口中的每一数据接口进行校准。
在本实施例中，通过物理层采用环回模式，使应用层可以收到其本身发送的数据包，并对收到的数据包做检查，判断当前的RGMII接口时钟相位是否通过校验，然后调整时钟相位并重复前一步的发包收包及数据包检查操作，扫描完整个时钟相位之后，找到时钟相位有效范围，然后将时钟相位设置为时钟相位有效范围的中间位置，以确保RGMII接口的数据通信稳定可靠，从而实现根据不同芯片选择最佳的时序参数作为接收目标时钟的相位，以使接口的有效窗口余量最大化。
如图3所示，一种接口时序校准装置，应用在耦合于应用层与物理层的接口中，所述物理层采用环回模式，包括：控制单元1和处理单元2，其中：
控制单元1，用于调整所述应用层接收时钟信号的步进，所述应用层向所述物理层发送数据包，所述应用层接收所述物理层发送的数据包，依据所述应 用层接收的数据包判断所述时钟信号的有效性；
需要说明的是：应用层为芯片的媒体访问控制层。本实施例中的接口为RGMII是简化的吉比特媒体独立接口。
所述控制单元1可包括：调整模块11、发送模块12、接收模块13和校验模块14，其中：
调整模块11，用于在预设周期范围内以预设步进调整所述应用层接收时钟信号；
发送模块12，用于发送数据包至所述物理层，所述物理层通过环回的方式将接收到的所述数据包输出；
物理层环回有两种信号环回方式，一种是在物理层的RGMII接口处做环回，另外一种是通过环回网线实现，两种方式环回方式都需要配置物理层的寄存器实现。应用层发送数据包为长度较长的数据包(例如：1514Byte)以保证正确，防止窗口错判，保证发送时间与通信准确性之间的平衡。
接收模块13，用于对接收所述物理层发送的数据包；
校验模块14，用于对接收到的所述数据包进行校验，对校验通过的所述数据包对应的应用层的发送时钟进行标记。
在本实施例中，所述校验模块14可将接收到的所述数据包与相应的发送数据包进行比对，若数据包相同，则校验通过，对接收到的数据包对应的应用层的发送时钟进行标记。
在本实施例中，所述校验模块14还可采用循环冗余校验码对接收到的所述数据包进行校验，若校验通过，则对接收到的数据包对应的应用层的发送时钟进行标记。
处理单元2，用于获取所述时钟信号的时钟相位有效范围，根据所述有效范围获取接收目标时钟的相位。
在本实施例中，所述处理单元2可根据标记的所有所述发送时钟生成时钟相位的有效范围，将所述有效范围的中间相位作为所述接收目标时钟的相位。
在实际应用中，可采用2.5MHz、25MHz或125MHz对接口时序校准。逐个对RGMII接口中的每一数据接口进行校准。
接口时序校准装置通过物理层采用环回模式，使应用层可以收到其本身发送的数据包，并对收到的数据包做检查，判断当前的RGMII接口时钟相位是否通过校验，然后调整时钟相位并重复前一步的发包收包及数据包检查操作，扫描完整个时钟相位之后，找到时钟相位有效范围，然后将时钟相位设置为时钟相位有效范围的中间位置，以确保RGMII接口的数据通信稳定可靠，从而实现根据不同芯片选择最佳的时序参数作为接收目标时钟的相位，以使接口的有效窗口余量最大化。
以上所述仅为本发明较佳的实施例，并非因此限制本发明的实施方式及保护范围，对于本领域技术人员而言，应当能够意识到凡运用本发明说明书及图示内容所作出的等同替换和显而易见的变化所得到的方案，均应当包含在本发明的保护范围内。

Claims (10)

  1. 一种接口时序校准方法，应用在耦合于应用层与物理层的接口中，所述物理层采用环回模式，其特征在于，包括下述步骤：
    调整所述应用层接收时钟信号的步进，所述应用层向所述物理层发送数据包，所述应用层接收所述物理层发送的数据包，依据所述应用层接收的数据包判断所述时钟信号的有效性；
    获取所述时钟信号的时钟相位有效范围，根据所述有效范围获取接收目标时钟的相位。
  2. 根据权利要求1所述的接口时序校准方法，其特征在于，调整所述应用层接收时钟信号的步进，所述应用层向所述物理层发送数据包，所述应用层接收所述物理层发送的数据包，依据所述应用层接收的数据包判断所述时钟信号的有效性的步骤，包括：
    在预设周期范围内以预设步进调整所述应用层接收时钟信号；
    所述应用层发送数据包至所述物理层，所述物理层通过环回的方式将接收到的所述数据包发送至所述应用层；
    所述应用层对接收到的所述数据包进行校验，对校验通过的所述数据包对应的应用层的发送时钟进行标记；
    重复调整所述应用层接收时钟信号，直至完成所述预设周期范围内所有步进的调整。
  3. 根据权利要求2所述的接口时序校准方法，其特征在于，所述应用层对接收到的所述数据包进行校验，对校验通过的所述数据包对应的应用层的发送时钟进行标记的步骤，包括：
    所述应用层将接收到的所述数据包与相应的发送数据包进行比对，若数据包相同，则校验通过，对接收到的数据包对应的应用层的发送时钟进行标记。
  4. 根据权利要求2所述的接口时序校准方法，其特征在于，所述应用层对接收到的所述数据包进行校验，对校验通过的所述数据包对应的应用层的发送时钟进行标记的步骤，包括：
    所述应用层采用循环冗余校验码对接收到的所述数据包进行校验，若校验通过，则对接收到的数据包对应的应用层的发送时钟进行标记。
  5. 根据权利要求2所述的接口时序校准方法，其特征在于，获取所述时钟信号的时钟相位有效范围，根据所述有效范围获取接收目标时钟的相位的步骤，包括：
    根据标记的所有所述发送时钟生成时钟相位的有效范围；
    将所述有效范围的中间相位作为所述接收目标时钟的相位。
  6. 一种接口时序校准装置，应用在耦合于应用层与物理层的接口中，所述物理层采用环回模式，其特征在于，包括：
    控制单元，用于调整所述应用层接收时钟信号的步进，所述应用层向所述物理层发送数据包，所述应用层接收所述物理层发送的数据包，依据所述应用层接收的数据包判断所述时钟信号的有效性；
    处理单元，用于获取所述时钟信号的时钟相位有效范围，根据所述有效范围获取接收目标时钟的相位。
  7. 根据权利要求1所述的接口时序校准装置，其特征在于，所述控制单元包括：
    调整模块，用于在预设周期范围内以预设步进调整所述应用层接收时钟信号；
    发送模块，用于发送数据包至所述物理层，所述物理层通过环回的方式将接收到的所述数据包输出；
    接收模块，用于对接收所述物理层发送的数据包；
    校验模块，用于对接收到的所述数据包进行校验，对校验通过的所述数据包对应的应用层的发送时钟进行标记。
  8. 根据权利要求7所述的接口时序校准装置，其特征在于，所述校验模块用于将接收到的所述数据包与相应的发送数据包进行比对，若数据包相同，则校验通过，对接收到的数据包对应的应用层的发送时钟进行标记。
  9. 根据权利要求7所述的接口时序校准装置，其特征在于，所述校验模块用于采用循环冗余校验码对接收到的所述数据包进行校验，若校验通过，则对接收到的数据包对应的应用层的发送时钟进行标记。
  10. 根据权利要求7所述的接口时序校准装置，其特征在于，所述处理单元用于根据标记的所有所述发送时钟生成时钟相位的有效范围，将所述有效范围的中间相位作为所述接收目标时钟的相位。
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