WO2020029023A1 - 波特率校准电路及串口芯片 - Google Patents

波特率校准电路及串口芯片 Download PDF

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Publication number
WO2020029023A1
WO2020029023A1 PCT/CN2018/099008 CN2018099008W WO2020029023A1 WO 2020029023 A1 WO2020029023 A1 WO 2020029023A1 CN 2018099008 W CN2018099008 W CN 2018099008W WO 2020029023 A1 WO2020029023 A1 WO 2020029023A1
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WIPO (PCT)
Prior art keywords
baud rate
receiving module
calibration
selector
counter
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PCT/CN2018/099008
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English (en)
French (fr)
Inventor
王慧昭
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2018/099008 priority Critical patent/WO2020029023A1/zh
Priority to CN201880001023.0A priority patent/CN109075742B/zh
Priority to EP18914926.3A priority patent/EP3637271B1/en
Priority to US16/657,261 priority patent/US10841021B2/en
Publication of WO2020029023A1 publication Critical patent/WO2020029023A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/02—Details
    • H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/20—Monitoring; Testing of receivers
    • H04B17/21—Monitoring; Testing of receivers for calibration; for correcting measurements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/044—Speed or phase control by synchronisation signals using special codes as synchronising signal using a single bit, e.g. start stop bit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
    • G06F13/426—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
    • G06F13/4278—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus using an embedded synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0262—Arrangements for detecting the data rate of an incoming signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/048—Speed or phase control by synchronisation signals using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/06—Speed or phase control by synchronisation signals the synchronisation signals differing from the information signals in amplitude, polarity or frequency or length

Definitions

  • the present application belongs to the field of communication technology, and particularly relates to a baud rate calibration circuit and a serial port chip.
  • the baud rate is a measure of the symbol symbol transmission rate.
  • 1 baud means 1 symbol symbol per second.
  • one symbol symbol corresponds to one bit, so one baud can also be understood as one bit per second.
  • the sending end and the receiving end must agree on a consistent baud rate in advance to achieve normal communication, and ensure that the data sent by the sending end is the same as the data received by the receiving end.
  • the inventors of the present application have found that the prior art has at least the following problems: due to the internal clock deviation of the communication ends, the baud rate of the data received by the receiving end and the baud rate of the data sent by the transmitting end will not match (see Figure 1 (Shown in Figure 2), which may cause abnormal reception of data at the receiving end, reduce the reliability of data transmission, and even affect normal data communications.
  • most of the existing baud rate calibration methods are based on the data frame of the preset word, that is, the sender and the receiver need to agree on a data frame of the preset word in advance, and perform data transmission between the sender and the receiver.
  • the transmitting end needs to send the data frame of the preset word first, so that the receiving end can perform the calibration of the baud rate according to the information when receiving the data frame of the preset word.
  • This method cannot realize the real-time calibration of the baud rate, and it is not suitable for a communication system where the communication environment changes too fast, and it has great limitations.
  • a technical problem to be solved in some embodiments of the present application is to provide a baud rate calibration circuit and a serial chip, which aim to achieve dynamic real-time calibration of the baud rate and improve the reliability of data reception.
  • the calibration circuit includes:
  • a first counter connected to the receiving module of the serial chip, and the first counter is used to record the first low-level duration of the data frame received by the receiving module;
  • the second counter is connected to the receiving module.
  • the second counter is used to receive the bit sampling pulses and record the number of bit sampling pulses in the first low-level duration.
  • the bit sampling pulses are received by the receiving module according to the current wave of the receiving module. Sampling data frames at a special rate;
  • the divider is connected to the first counter and the second counter, and the divider is used to calculate the calibration baud rate according to the number of bit sampling pulses in the first low-level duration and the first low-level duration;
  • the selector is connected with the receiving module and the divider.
  • the selector is used to output the calibration baud rate to the receiving module.
  • An embodiment of the present application further provides a serial port chip, which includes a receiving module and a baud rate calibration circuit as described above;
  • the receiving module is used to receive the data frame sent by the opposite end, send the start instruction and stop instruction according to the data frame, and is used to sample the data frame according to the current baud rate of the receiving module to generate a bit sampling pulse;
  • the baud rate calibration circuit is connected to the receiving module.
  • the baud rate calibration circuit is used to calculate the calibration baud rate according to the start command, stop command, and bit sampling pulse, and output the calibration baud rate to the receiving module.
  • the embodiment of the present application uses a first counter to record the first low-level duration of the data frame when the receiving module of the serial port chip receives the data frame, and uses a second counter to record the first low period.
  • the number of bit sampling pulses generated by the receiving module during the level duration to estimate the number of bits actually received by the receiving module during the first low level duration, so as to calculate the calibration baud rate, and calibrate the baud rate
  • the baud rate is output to the receiving module to update and replace the baud rate of the receiving module.
  • the actual baud rate of the current data transmission process can be obtained without relying on the data frame of the preset word, automatic recognition of the baud rate and dynamic real-time calibration can be achieved, and a high-accuracy baud rate can be obtained, effectively Improved the reliability of subsequent data reception by the receiving module.
  • the selector is also connected to the first counter.
  • the selector is specifically configured to output the calibration baud rate to the receiving module when the first low-level duration is less than the preset duration.
  • the selector judges whether the receiving module receives data incorrectly according to the comparison result between the first low-level duration and the preset duration, and selects when the first low-level duration is shorter than the preset duration.
  • the device outputs the calibration baud rate to the receiving module, and updates and replaces the baud rate of the receiving module, which can ensure the validity and timeliness of the baud rate calibration update and improve the reliability of subsequent data reception of the receiving module.
  • the preset duration is set by the selector according to the current baud rate of the receiving module.
  • the selector can set a more suitable preset duration, which effectively reduces the possibility of misjudgment.
  • the selector is also connected to a second counter.
  • the selector is specifically configured to output the calibration baud rate to the receiving module when the number of bit sampling pulses is less than a preset number during the first low-level duration.
  • the selector judges whether the receiving module receives data incorrectly or whether the internal clock of both ends of the communication is too large according to the comparison result between the number of bit sampling pulses and the preset number within the first low-level duration.
  • the selector outputs the calibration baud rate to the receiving module, and updates and replaces the baud rate of the receiving module, which can guarantee the baud rate.
  • the validity and timeliness of the rate calibration update improves the reliability of subsequent data reception of the receiving module.
  • the preset number is seven. A specific implementation form of the preset number is provided in this embodiment.
  • the selector is also connected to the sending module of the serial chip, and the selector is also used to output the calibration baud rate to the sending module.
  • the baud rate calibration circuit also updates the baud rate of the sending module.
  • the baud rate of the local serial chip sending module can be changed. The rate matches the baud rate of the receiving module of the serial port chip on the opposite end, which ensures the reliability of data transmission.
  • the calibration circuit further includes a calibration output register connected to the selector, and the calibration output register is used to output a preset signal after the selector outputs the calibration baud rate to the receiving module, wherein the preset signal is used to represent the baud Whether the rate calibration was successful.
  • This embodiment provides an implementation form of outputting a calibration result, which provides a basis for a technician to know whether the baud rate of the serial port chip is successfully calibrated through the content displayed by the host computer.
  • FIG. 1 is a data receiving timing diagram of a transmitting end baud rate greater than a receiving end baud rate
  • FIG. 2 is a timing chart of data reception in which the baud rate at the transmitting end is less than the baud rate at the receiving end;
  • FIG. 3 is a schematic structural diagram of a baud rate calibration circuit in the first embodiment of the present application.
  • FIG. 4 is a schematic diagram of a data structure of a data frame in the first embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a baud rate calibration circuit provided with a calibration output register 105 in the first embodiment of the present application, and the calibration output register 105 is connected to the host computer 30;
  • FIG. 6 is a schematic structural diagram of a baud rate calibration circuit in a second embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a baud rate calibration circuit in a third embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a first counter 101 and a second counter 102 of a baud rate calibration circuit connected to a selector 104 in an embodiment of the present application;
  • FIG. 9 is a schematic structural diagram of a baud rate calibration circuit in a fourth embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a serial chip in a fifth embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a serial chip in a sixth embodiment of the present application.
  • the first embodiment of the present application relates to a baud rate calibration circuit, as shown in FIG. 3.
  • the baud rate calibration circuit in this embodiment is located at the local end of the serial port chip, and can perform dynamic real-time calibration on the baud rate of the serial port chip receiving module 20, thereby improving the reliability of data reception of the receiving module 20.
  • the working principle of the baud rate calibration circuit in this embodiment is specifically described below:
  • the baud rate calibration circuit includes a first counter 101, a second counter 102, a divider 103, and a selector 104.
  • the first counter 101, the second counter 102, and the selector 104 are respectively connected to the divider 103, and when the baud rate calibration circuit is applied to the serial port chip, the first counter 101, the second counter 102, and the selector 104 are also connected to the serial port.
  • the receiving module 20 of the chip is connected.
  • the receiving module 20 when the receiving module 20 receives a data frame sent by the opposite end, the receiving module 20 sends a start instruction to the first counter 101 and the second counter 102, so that the first counter 101 and the second counter 102 start counting, and at the same time, the receiving module 20 also performs bit sampling according to the current baud rate, and returns the bit sampling pulses generated by the sampling to the second counter 102, so that the second counter 102 counts the number of bit sampling pulses.
  • the receiving module 20 when it detects the first high level of the data frame, it sends a stop instruction to the first counter 101 and the second counter 102, so that the first counter 101 records the first low level of the data frame.
  • the level duration causes the second counter 102 to record the number of bit sampling pulses in the first low level duration.
  • the baud rate calibration circuit can obtain the first low-level duration and estimate the number of bits actually received by the receiving module 20 within the first low-level duration, so that the calibration baud can be calculated by the divider 103 Rate, so that the selector 104 outputs the calibrated baud rate to the receiving module 20 to implement baud rate update and calibration of the receiving module 20.
  • the start bit is low level, and the check bit may or may not exist. It may be digital signal 0 or digital signal 1. Therefore, the check bit in FIG. 4 is marked with an “X” and the data segment Bit0.
  • the X in -Bit7 indicates that the data may be digital signal 0 or digital signal 1.
  • the end bit is high. When the data line is high and lasts for at least 10ms (as shown by TR in FIG. 4), it indicates that the data line is in an idle state. When an idle state is detected, if a high-to-low transition of the data line is detected, the subsequent low level must be the start level corresponding to the start bit.
  • the receiving module 20 can detect that the data line transitions from a high-level idle state to a low-level when receiving the data frame sent by the opposite end. At this time, the receiving module 20 reports to the first counter 101 and the second counter. 102 sends a start instruction, and then, when the receiving module 20 detects a data line transition from low to high for the first time, it sends a stop instruction to the first counter 101 and the second counter 102, thereby realizing the first counter 101 and the second counter
  • the count of 102 starts from the falling edge of the start bit of the data frame and counts to the end of the first rising edge (the beginning of the falling edge of the start bit of the data frame, and the time from the end of the first rising edge is the first time of the data frame A low duration).
  • the shorter the data transmission time the less the data reception is affected by the internal clock deviation of the communication end. Therefore, in this embodiment, the shorter the first low level duration, the smaller the count of the second counter 102.
  • the more accurate the number of bits actually received by the receiving module 20 within the first low-level duration estimated by the baud rate calibration circuit the more accurate the calculated calibration baud rate, and the higher the calibration success rate. Therefore, in this embodiment, when the digital signal of the data frame received by the receiving module 20 is exactly 1 except for the start bit, a 100% calibration success rate can be achieved.
  • the current baud rate of the receiving module 20 may be preset by a technician, or may be a baud rate used by the receiving module 20 when receiving the previous data frame.
  • the current baud rate of the receiving module 20 is 1Bd.
  • the receiving module 20 uses the 1 second of its internal clock as the sampling period to sample the data frame to generate a bit sample. pulse.
  • the bit sampling pulse acquired by the receiving module 20 may correspond to the pulse signal at the middle position of each bit.
  • the divider 103 when the divider 103 calculates the calibration baud rate according to the first low-level duration and the number of bit sampling pulses, the divider 103 performs the data output by the first counter 101 and the data output by the second counter 102
  • the division operation is the first low-level duration divided by the number of bit sampling pulses, and the operation result is rounded to obtain the division factor, and the calibration baud rate is obtained according to the division factor. In this way, it can be applied to any serial chip using an integer frequency divider, and has a wide application range.
  • the frequency division coefficient is [3.3 / 3], that is, 1, the calibration wave The rate is 1Bd.
  • the receiving module 20 can use the calibration baud rate to receive subsequent data frames.
  • the receiving module 20 may also perform bit sampling on the data frame according to the calibration baud rate. That is, the first counter 101 can still obtain the first low-level duration of the data frame currently received by the receiving module 20, and the second counter 102 can still record the number of bit sampling pulses within the first low-level duration, so as to divide
  • the calculator 103 calculates a new calibration baud rate. In this way, when the selector 104 outputs the newly calculated calibration baud rate to the receiving module 20 again, the baud rate of the receiving module 20 is updated again. In this way, a dynamic real-time calibration of the baud rate can be achieved.
  • the serial chip in this embodiment may be provided with a filter connected to the receiving module 20, and the filter is used to filter the data frames received by the receiving module 20, so that the operations of the receiving module 20 are based on filtering
  • the subsequent data frames are performed, so that not only the timing of the receiving module 20 sending the open command or the stop command is not disturbed by noise, but also the sampled samples of the receiving module 20 are filtered data frames for more accurate calibration.
  • the baud rate provides the basis.
  • the baud rate calibration circuit in this embodiment may further include a calibration output register 105 (as shown in FIG. 4).
  • the calibration output register 105 is connected to the selector 104.
  • the calibration output register 105 is used to output a preset signal after the selector 104 outputs the calibration baud rate to the receiving module 20, and the preset signal is used to characterize the baud rate of the serial chip. Whether the calibration was successful. For example, if the preset signal is a high-level signal, it indicates that the baud rate calibration of the serial chip is successful.
  • the calibration output register 105 is connected to the host computer 30, and the host computer 30 periodically detects the output signal of the calibration output register 105 and displays the detected output signal, so that the technicians can make use of the calibration output register displayed by the host computer 30
  • the output signal of 105 determines whether the baud rate of the serial chip is successfully calibrated, so that the technician can learn more effective information.
  • this embodiment has a simple structure of the baud rate calibration circuit, does not need to consume excessive resources, has low cost, and can obtain the actual baud of the current data transmission process without relying on a data frame of a preset word.
  • Rate, automatic identification and dynamic real-time calibration of the baud rate, high efficiency can improve the reliability of subsequent data reception of the receiving module 20, and provides a basis for the serial chip to be applicable to communication systems where the communication environment changes rapidly. It solves the problem of rising bit error rate caused by serial chip in extreme environment.
  • the baud rate calibration circuit can be bypassed directly, for example, the enable pins of the first counter 101 and the second counter 102 can be made low.
  • the second embodiment of the present application relates to a baud rate calibration circuit. As shown in FIG. 6, this embodiment is an improvement on the first embodiment. The main improvement is that the second counter 102 in this embodiment is also selected.
  • the selector 104 is connected, so that the selector 104 outputs the calibration baud rate to the receiving module 20 when the number of bit sampling pulses in the first low-level duration is less than the preset number, and updates the baud rate of the receiving module 20 Replacement can ensure the validity and timeliness of the baud rate calibration update.
  • the specific description is as follows:
  • the number of bit sampling pulses in the first low-level duration is greater than a preset number, it means that the receiving module 20 continues to receive multiple digital signals 0, and at this time, it is likely that the data reception error; or, communication
  • the internal clock of both ends has a large deviation.
  • the number of bit sampling pulses in the first low-level duration recorded by the second counter 102 is significantly different from the number of bits actually sent by the peer end. Therefore, it is calculated based on the data of the second counter 102
  • the calibration baud rate error is large.
  • the selector 104 should discard the currently calculated calibration baud rate and not update the baud rate of the receiving module 20 with the currently calculated calibration baud rate.
  • the selector 104 outputs the calibration baud rate to the receiving module 20 only when the number of bit sampling pulses in the first low-level duration is less than a preset number, which can ensure that the receiving module 20 receives Only when the possibility of data error is low and the internal clock deviation of the two ends of the communication is small, the baud rate is updated and replaced. The efficiency and timeliness of the baud rate calibration update is high.
  • the preset number may be preset in the selector 104 by a technician, for example, the preset number may be seven. It should be noted that the preset number can be set by a technician according to the data format of the data frame, and the specific form of the preset number is not limited in this embodiment.
  • the currently calculated calibration baud rate is discarded and the current baud rate is not used.
  • the calculated calibration baud rate is used to perform the baud rate calibration of the receiving module 20.
  • the selector 104 discards the currently calculated calibration baud rate, it can wait, so that when the receiving module 20 receives the next data frame, the divider 103 can recalculate the calibration baud rate, so that the selector 104 will divide the divider.
  • the recalculated calibration baud rate is output to the receiving module 20, and the baud rate of the receiving module 20 can still be updated and calibrated.
  • this embodiment can ensure the validity and timeliness of the baud rate calibration update, and further improves the reliability of subsequent data reception of the receiving module.
  • the third embodiment of the present application relates to a baud rate calibration circuit. As shown in FIG. 7, this embodiment is an improvement on the first embodiment. The main improvement lies in the first counter 101 in this embodiment. It is also connected to the selector 104, so that the selector 104 outputs the calibration baud rate to the receiving module 20 when the first low-level duration is shorter than the preset duration, and updates and replaces the baud rate of the receiving module 20, which can ensure Effectiveness and timeliness of baud rate calibration updates.
  • the specific description is as follows:
  • the selector 104 outputs the calibration baud rate to the receiving module 20 only when the first low-level duration is shorter than the preset duration. In this way, the baud rate is updated and replaced only when the receiving module 20 has a low probability of receiving data errors, which can ensure the validity and timeliness of the baud rate calibration update.
  • the preset duration may be preset in the selector 104 by a technician, or may be generated by the selector 104 based on the current baud rate of the receiving module 20. For example, when the current baud rate of the receiving module 20 is 1 Bd, the selector 104 may set a preset duration as the time required for transmitting 7 bits, that is, 7 seconds.
  • the selector 104 discards the currently calculated calibration baud rate when the first low-level duration is greater than or equal to the preset duration, the receiver module is not used at the currently calculated calibration baud rate. 20 baud rate calibration. However, after the selector 104 discards the currently calculated calibration baud rate, it can wait, so that when the receiving module 20 receives the next data frame, the divider 103 can recalculate the calibration baud rate, so that the selector 104 will divide the divider. 103 The recalculated calibration baud rate is output to the receiving module 20, and the baud rate of the receiving module 20 can still be updated and calibrated.
  • this embodiment can ensure the validity of the baud rate calibration update, and further ensure the reliability of subsequent data reception of the receiving module.
  • the first counter 101 and the second counter 102 may both be connected to the selector 104, as shown in FIG. 8.
  • the selector 104 is configured to output the calibration baud rate to the receiving module when the number of bit sampling pulses in the first low-level duration is less than a preset number and the first low-level duration is less than the preset duration.
  • the fourth embodiment of the present application relates to a baud rate calibration circuit. As shown in FIG. 9, this embodiment is improved on the basis of any of the above embodiments. The main improvement is that in this embodiment, the selector 104 also The current baud rate of the sending module 40 of the serial chip is calibrated, which provides a basis for the subsequent sending data of the serial chip to be reliably received.
  • the selector 104 is further connected to the sending module 40, and the selector 104 is further configured to output the calibration baud rate to the sending module 40.
  • duplex communication refers to an information interaction mode in which both ends of a communication can send and receive data at the same time.
  • the selector 104 outputs the calibrated baud rate to the sending module 40 to update the baud rate of the sending module 40
  • the baud rate of the sending module 40 at the local end and the receiving module of the peer end can be made.
  • the baud rate is matched to ensure the reliability of data transmission at both ends of the communication.
  • the above-mentioned example of the duplex communication is only for illustrative purposes, and this embodiment does not limit the specific application scenario of the 40 baud rate update of the sending module.
  • the fifth embodiment of the present application relates to a serial port chip. As shown in FIG. 10, the details are as follows:
  • the serial port chip includes a baud rate calibration circuit 10 and a receiving module 20, and the baud rate calibration circuit 10 is connected to the receiving module 20.
  • the receiving module 20 is configured to receive a data frame sent by a peer end, send a start instruction and a stop instruction according to the data frame, and is used to sample the data frame according to the current baud rate of the receiving module 20 to generate a bit sampling pulse.
  • the baud rate calibration circuit 10 is configured to calculate a calibration baud rate according to a start instruction, a stop instruction, and a bit sampling pulse, and output the calibration baud rate to the receiving module 20.
  • the automatic identification and dynamic real-time calibration of the baud rate of the receiving module 20 is realized, which has high efficiency, can improve the reliability of subsequent data reception of the receiving module 20, and provides a serial chip that can be applied to a communication system where the communication environment changes rapidly. Basically, it solves the problem of rising bit error rate caused by serial chip in extreme environment.
  • the baud rate calibration circuit 10 can be directly bypassed, and the operation is relatively convenient.
  • the serial port chip also includes a sending module 40 at its own end, and the baud rate calibration circuit 10 may also be connected to the sending module 40 of the serial chip.
  • the baud rate calibration circuit 10 can also output the calibration baud rate to the sending module 40 after calculating the calibration baud rate, so that the sending module 40 can send data based on the calibrated current baud rate.
  • the serial chip sent the data to be reliably received to provide the basis.
  • the sixth embodiment of the present application relates to a serial port chip, as shown in FIG. 11.
  • the sixth embodiment is improved on the basis of the fifth embodiment.
  • the main improvement is that in this embodiment, the serial port chip further includes a filter 50, which can avoid interference caused by noise and improve the calibration of the current baud rate. Accuracy.
  • the specific description is as follows:
  • the filter 50 is connected to the receiving module 20.
  • the filter 50 is configured to filter a data frame received by the receiving module 20.
  • the receiving module 20 when the receiving module 20 receives the data sent by the opposite serial chip, the receiving module 20 transmits the received data to the filter 50 for filtering, so that the filter 50 returns the filtered data to the receiving module. 20.
  • the subsequent operations of the receiving module 20 can be performed based on the filtered data frames, so that not only the timing of the receiving module 20 sending the start instruction and the stop instruction to the baud rate calibration circuit 10 is not disturbed by noise, but
  • the sampling sample of the receiving module 20 can be a filtered data frame, which provides a basis for obtaining a more accurate calibration baud rate.
  • the present embodiment has higher calibration accuracy of the current baud rate and higher reliability of subsequent data reception by the receiving module 20.

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Abstract

一种波特率校准电路及串口芯片，校准电路包括：第一计数器(101)，与串口芯片的接收模块(20)连接，第一计数器用于记录接收模块接收到的数据帧的第一个低电平时长；第二计数器(102)，与接收模块连接，第二计数器用于接收比特采样脉冲，并记录第一个低电平时长内的比特采样脉冲的数目；其中，比特采样脉冲由接收模块依据接收模块的当前波特率对数据帧进行采样生成；除法器(103)，与第一计数器以及第二计数器连接，除法器用于根据第一个低电平时长和第一个低电平时长内的比特采样脉冲的数目，计算校准波特率；选择器(104)，与接收模块以及除法器连接，选择器用于将校准波特率输出给接收模块。本方案可实现波特率的动态实时校准，提升数据接收的可靠性。

Description

波特率校准电路及串口芯片 技术领域
本申请属于通信技术领域，尤其涉及一种波特率校准电路及串口芯片。
背景技术
波特率是对码元符号传输速率的一种度量，1波特即指每秒传输1个码元符号。常见的串口通信系统中，1个码元符号对应一个比特，因而1波特也可以理解为每秒传输1个比特。并且常见的串口通信系统中，发送端和接收端必须事先约定一致的波特率才能实现正常通信，保证发送端发送的数据与接收端接收到的数据相同。
但是，本申请发明人发现现有技术至少存在以下问题：由于通信双端的内部时钟偏差，接收端接收数据的波特率与发送端发送数据的波特率会出现不匹配的情况(如图1、图2所示)，从而会出现接收端数据接收不正常，降低数据传输的可靠性，更有甚者会影响到正常的数据通信。然而，现有的波特率校准方法大多是基于预设字的数据帧进行的，即，发送端与接收端需要预先约定好一预设字的数据帧，在发送端与接收端进行数据传输时，发送端需要先发送预设字的数据帧，以便于接收端根据接收预设字的数据帧时的信息，进行波特率的校准。这种方式无法实现波特率的实时校准，不适用于通信环境变化过快的通信系统，具有很大的局限性。
发明内容
本申请部分实施例所要解决的一个技术问题在于提供一种波特率校准电路及串口芯片，旨在实现波特率的动态实时校准，提升数据接收的可靠性。
本申请的一个实施例提供了一种波特率校准电路，所述校准电路包括：
第一计数器，与串口芯片的接收模块连接，第一计数器用于记录接收模块接收到的数据帧的第一个低电平时长；
第二计数器，与接收模块连接，第二计数器用于接收比特采样脉冲，并记录第一个低电平时长内的比特采样脉冲的数目；其中，比特采样脉冲由接收模块依据接收模块的当前波特率对数据帧进行采样生成；
除法器，与第一计数器以及第二计数器连接，除法器用于根据第一个低电平时长和第一个低电平时长内的比特采样脉冲的数目，计算校准波特率；
选择器，与接收模块以及除法器连接，选择器用于将校准波特率输出给接收模块。
本申请实施例还提供了一种串口芯片，包括：接收模块以及如上述内容所述的波特率校准电路；
接收模块用于接收对端发送的数据帧，根据数据帧发送开始指令以及停止指令，并用于依据接收模块的当前波特率对数据帧进行采样，生成比特采样脉冲；
波特率校准电路，与接收模块连接，波特率校准电路用于根据开始指令、停止指令以及比特采样脉冲计算校准波特率，并将校准波特率输出给接收模块。
本申请实施例相对于现有技术而言，在串口芯片的接收模块接收到数据帧时，利用第一计数器记录数据帧的第一个低电平时长，并利用第二计数器记录第一个低电平时长内接收模块采样所产生的比特采样脉冲的数目，以估算出 第一个低电平时长内接收模块实际接收到的比特的数目，从而计算出校准波特率，并将校准波特率输出至接收模块，实现接收模块的波特率更新与替换。这样，无需依赖于预设字的数据帧，就能获取当前数据传输过程的实际波特率，实现了波特率的自动识别与动态实时校准，能够获取高精准度的波特率，有效地提升了接收模块后续数据接收的可靠性。
另外，选择器还与第一计数器连接，选择器具体用于在第一个低电平时长小于预设时长时，将校准波特率输出给接收模块。本实施例中，选择器根据第一个低电平时长与预设时长的比较结果，对接收模块是否数据接收错误进行判断，在第一个低电平时长小于预设时长的情况下，选择器才将校准波特率输出给接收模块，进行接收模块波特率的更新替换，能够保证波特率校准更新的有效性与及时性，提升了接收模块后续数据接收的可靠性。
另外，预设时长由选择器依据接收模块的当前波特率设置。本实施例中，选择器能够设置出较为合适的预设时长，有效地降低了误判的可能。
另外，选择器还与第二计数器连接，选择器具体用于在第一个低电平时长内比特采样脉冲的数目小于预设个数时，将校准波特率输出给接收模块。本实施例中，选择器根据第一个低电平时长内比特采样脉冲的数目与预设个数的比较结果，对接收模块是否数据接收错误或者通信双端的内部时钟是否偏差过大进行判断，在第一个低电平时长内比特采样脉冲的数目小于预设个数的情况下，选择器才将校准波特率输出给接收模块，进行接收模块波特率的更新替换，能够保证波特率校准更新的有效性与及时性，提升了接收模块后续数据接收的可靠性。
另外，预设个数为7。本实施例中提供了预设个数的具体实现形式。
另外，选择器还与串口芯片的发送模块连接，选择器还用于将校准波特率输出给发送模块。本实施例中，波特率校准电路也对发送模块的波特率进行更新，在本端串口芯片与对端串口芯片进行双工通信的情况下，能够令本端串口芯片发送模块的波特率与对端串口芯片接收模块的波特率匹配，保证了数据传输的可靠性。
另外，校准电路还包括：校准输出寄存器，与选择器连接，校准输出寄存器用于在选择器将校准波特率输出给接收模块后，输出预设信号；其中，预设信号用于表征波特率校准是否成功。本实施例提供了输出校准结果的一种实现形式，为技术人员能够通过上位机显示的内容，知晓串口芯片的波特率是否校准成功提供了基础。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1是发送端波特率大于接收端波特率的数据接收时序图；
图2是发送端波特率小于接收端波特率的数据接收时序图；
图3是本申请第一实施例中波特率校准电路的结构示意图；
图4是本申请第一实施例中一种数据帧的数据结构的示意图；
图5是本申请第一实施例中波特率校准电路设有校准输出寄存器105，且校准输出寄存器105与上位机30连接的结构示意图；
图6是本申请第二实施例中波特率校准电路的结构示意图；
图7是本申请第三实施例中波特率校准电路的结构示意图；
图8是本申请一实施例中波特率校准电路的第一计数器101、第二计数器102均与选择器104连接的结构示意图；
图9是本申请第四实施例中波特率校准电路的结构示意图；
图10是本申请第五实施例中串口芯片的结构示意图；
图11是本申请第六实施例中串口芯片的结构示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请部分实施例进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
本申请第一实施例涉及一种波特率校准电路，如图3所示。本实施例中的波特率校准电路在串口芯片本端侧，能够对串口芯片接收模块20的波特率进行动态实时校准，提升了接收模块20数据接收的可靠性。以下对本实施例中波特率校准电路的工作原理进行具体说明：
本实施例中，波特率校准电路包括：第一计数器101、第二计数器102、除法器103以及选择器104。其中，第一计数器101、第二计数器102以及选择器104分别与除法器103连接，且波特率校准电路应用于串口芯片时，第一计数器101、第二计数器102以及选择器104还与串口芯片的接收模块20连接。
具体地说，接收模块20接收对端发送的数据帧时，接收模块20向第一计数器101以及第二计数器102发送开始指令，令第一计数器101以及第二计数器102开始计数，同时，接收模块20还按照当前波特率进行比特采样，将采 样所生成的比特采样脉冲返回给第二计数器102，以便于第二计数器102对比特采样脉冲的数目进行计数。
更具体地说，接收模块20在检测到数据帧的第一个高电平时，向第一计数器101以及第二计数器102发送停止指令，从而令第一计数器101记录下数据帧的第一个低电平时长，令第二计数器102记录下第一个低电平时长内比特采样脉冲的数目。这样，波特率校准电路能够获取第一个低电平时长，并估算出第一个低电平时长内接收模块20实际接收到的比特的数目，从而能够通过除法器103计算出校准波特率，以便于选择器104将校准波特率输出给接收模块20，实现接收模块20的波特率更新与校准。
例如，假设数据帧的数据结构如图4所示。其中，起始位为低电平，校验位可能存在也可能不存在，可能为数字信号0也可能为数字信号1，所以图4中校验位中对应画有一“X”，数据段Bit0-Bit7中的X表示数据可能为数字信号0也可能为数字信号1，根据传送的内容而定，结束位为高电平。当数据线为高电平且持续至少10ms(如图4中TR所示)，说明数据线正处于空闲状态。当检测到空闲状态后，如果监测到数据线由高到低跳变，则其后的低电平必为起始位对应的开始电平。也就是说，接收模块20在接收对端发送的数据帧时，可以检测到数据线由高电平的空闲状态跳变到低电平，此时接收模块20向第一计数器101、第二计数器102发送开始指令，而后，接收模块20在第一次检测到数据线由低到高跳变时，向第一计数器101、第二计数器102发送停止指令，从而实现第一计数器101、第二计数器102的计数从数据帧的起始位的下降沿开始，记到第一个上升沿结束(数据帧的起始位的下降沿开始，至第一个上升沿结束的时长即为数据帧的第一个低电平时长)。
需要注意的是，数据传输时间越短，数据接收受通信双端内部时钟偏差的影响越小，因而本实施例中，第一个低电平时长越短，第二计数器102的计数越小，波特率校准电路所估算出的第一个低电平时长内接收模块20实际接收到的比特数目越准确，所计算出的校准波特率越精确，校准成功率越高。因此，本实施例中，在接收模块20接收到的数据帧的数字信号除起始位外，其余位恰好全为1时，能够实现百分之百的校准成功率。
本实施例中，接收模块20的当前波特率既可以由技术人员预设，也可以为接收模块20接收上一个数据帧时所用的波特率。如，接收模块20的当前波特率为1Bd，那在接收模块20接收对端发送的数据帧时，接收模块20以自身内部时钟的1秒作为采样周期，对数据帧进行采样，产生比特采样脉冲。其中，接收模块20采样所获取的比特采样脉冲可以与每个比特中间位置的脉冲信号对应。
本实施例中，除法器103在根据第一个低电平时长和比特采样脉冲的数目计算校准波特率时，除法器103将第一计数器101输出的数据与第二计数器102输出的数据进行除法运算，就是第一个低电平时长除以比特采样脉冲数目，并对运算结果取整，从而获取分频系数，根据分频系数获取校准波特率。这样，能够适用于任何使用整数分频器的串口芯片，应用范围较广。如，第一计数器101记录的第一个低电平时长为3.3秒，第二计数器102记录的比特采样脉冲的数目为3，则分频系数为[3.3/3]，即1，则校准波特率为1Bd。
需要注意的是，选择器104将校准波特率输出给接收模块20后，接收模块20便可以利用校准波特率进行后续数据帧的接收。并且，在接收模块20接收对端发送的下一个数据帧时，接收模块20还可以依据校准波特率对数据帧进 行比特采样。即，第一计数器101依然可以获取接收模块20当前接收的数据帧的第一个低电平时长，第二计数器102依然可以记录第一个低电平时长内比特采样脉冲的数目，从而令除法器103计算出新的校准波特率。这样，选择器104将新计算出的校准波特率再次输出给接收模块20时，就又一次对接收模块20的波特率进行了更新，如此，即可实现波特率的动态实时校准。
然而，上述对数据帧的数据格式、当前波特率以及校准波特率的举例仅作为示例性的说明，本实施例并不做任何限定。
值得一提的是，本实施例中的串口芯片可以设有一与接收模块20连接的滤波器，滤波器用以对接收模块20接收到的数据帧进行滤波，令接收模块20的操作均是基于滤波后的数据帧进行的，从而不仅能够令接收模块20发送开启指令、停止指令的时机不受噪声的干扰，而且能够令接收模块20的采样标本为滤波后的数据帧，为获取更加精准的校准波特率提供了基础。
并且，本实施例中波特率校准电路还可以包括校准输出寄存器105(如图4所示)。校准输出寄存器105与选择器104连接，校准输出寄存器105用于在选择器104将校准波特率输出给接收模块20后，输出预设信号，该预设信号用于表征串口芯片的波特率是否校准成功。如，预设信号为高电平信号，则表征串口芯片的波特率校准成功。
具体地说，校准输出寄存器105与上位机30连接，上位机30定期检测校准输出寄存器105的输出信号，并展示所检测到的输出信号，以便于技术人员根据上位机30所展示的校准输出寄存器105的输出信号，确定串口芯片的波特率是否校准成功，从而令技术人员能够了解到更多的有效信息。
本实施例相对于现有技术而言，波特率校准电路结构简单，不需要耗费 过多资源，成本较低，无需依赖于预设字的数据帧就能获取当前数据传输过程的实际波特率，实现了波特率的自动识别与动态实时校准，效率较高，能够提升接收模块20后续数据接收的可靠性，为串口芯片能够适用于通信环境变化过快的通信系统提供了基础，解决了串口芯片在极端环境下所产生的误码率上升问题。并且，在无需使用时，可以直接绕过波特率校准电路，如，令第一计数器101与第二计数器102的使能引脚为低电平。
本申请第二实施例涉及波特率校准电路，如图6所示，本实施例是在第一实施例基础上改进，主要改进之处在于：本实施例中的第二计数器102还与选择器104连接，令选择器104在第一个低电平时长内比特采样脉冲的数目小于预设个数时，才将校准波特率输出给接收模块20，进行接收模块20波特率的更新替换，能够保证波特率校准更新的有效性与及时性。以下进行具体说明：
具体地说，若第一个低电平时长内比特采样脉冲的数目大于预设个数，则说明接收模块20持续接收到多个数字信号0，此时很可能数据接收错误；或者，说明通信双端的内部时钟偏差较大。在上述情况下，第二计数器102所记录的第一个低电平时长内比特采样脉冲的数目，与对端实际发送的比特数目相差较大，因而基于第二计数器102的数据所计算出的校准波特率误差较大，选择器104应当舍弃当前计算出的校准波特率，不以当前计算出的校准波特率进行接收模块20的波特率更新。因而，本实施例中，选择器104在第一个低电平时长内比特采样脉冲的数目小于预设个数时，才将校准波特率输出给接收模块20，能够保证在接收模块20接收数据错误可能性较低、通信双端的内部时钟偏差较小的情况下，才进行波特率的更新替换，波特率校准更新的有效性与及时性较高。
更具体地说，预设个数可以由技术人员预设在选择器104中，如，预设个数可以为7。需要注意的是，预设个数可以由技术人员根据数据帧的数据格式进行设置，本实施例中并不对预设个数的具体形式做任何限定。
需要注意的是，本实施例中，虽然选择器104在第一个低电平时长内比特采样脉冲的数目大于预设个数的情况下，舍弃当前计算出的校准波特率，不以当前计算出的校准波特率进行接收模块20的波特率校准。但是，选择器104舍弃当前计算出的校准波特率后，可以进行等待，以便于接收模块20接收下一数据帧时，除法器103能够重新计算校准波特率，令选择器104将除法器103重新计算的校准波特率输出给接收模块20，依然能够实现接收模块20波特率的更新与校准。
本实施例相对第一实施例而言，能够保证波特率校准更新的有效性与及时性，进一步地提升了接收模块后续数据接收的可靠性。
本申请第三实施例涉及一种波特率校准电路，如图7所示，本实施例是在第一实施例基础上的改进，主要改进之处在于：本实施例中的第一计数器101还与选择器104连接，令选择器104在第一个低电平时长小于预设时长时，才将校准波特率输出给接收模块20，进行接收模块20波特率的更新替换，能够保证波特率校准更新的有效性与及时性。以下进行具体说明：
具体地说，若第一个低电平时长大于或等于预设时长，则说明接收模块20持续接收到多个数字信号0，此时很可能数据接收错误，选择器104应当舍弃当前计算出的校准波特率，不以当前计算出的校准波特率进行接收模块20的波特率更新。因而，本实施例中，选择器104在第一个低电平时长小于预设时长时，才将校准波特率输出给接收模块20。这样，在接收模块20接收数据 错误可能性较低的情况下，才进行波特率的更新替换，能够保证波特率校准更新的有效性与及时性。
更具体地说，预设时长可以由技术人员预设在选择器104中，也可以由选择器104基于接收模块20的当前波特率自行生成。如，接收模块20的当前波特率为1Bd时，选择器104可以设置预设时长为传输7个比特所需要的时间，即7秒。
需要注意的是，虽然选择器104在第一个低电平时长大于或等于预设时长的情况下，舍弃当前计算出的校准波特率，不以当前计算出的校准波特率进行接收模块20的波特率校准。但是，选择器104舍弃当前计算出的校准波特率后，可以进行等待，以便于接收模块20接收下一数据帧时，除法器103能够重新计算校准波特率，令选择器104将除法器103重新计算的校准波特率输出给接收模块20，依然能够实现接收模块20波特率的更新与校准。
本实施例相对第一实施例而言，能够保证波特率校准更新的有效性，进一步地保证了接收模块后续数据接收的可靠性。
需要注意的是，在一个实施例中，第一计数器101以及第二计数器102可以均与选择器104连接，如图8所示。并且，令选择器104在第一个低电平时长内比特采样脉冲的数目小于预设个数，以及第一个低电平时长小于预设时长时，才将校准波特率输出给接收模块20，进行接收模块20波特率的更新替换。这样，利用第一个低电平时长、第一个低电平时长内比特采样脉冲的数目进行双重判断，能够进一步地保证波特率校准更新的有效性与及时性。
本申请第四实施例涉及波特率校准电路，如图9所示，本实施例在上述任一实施例的基础上加以改进，主要改进之处在于：在本实施例中，选择器104 还对串口芯片的发送模块40的当前波特率进行校准，为串口芯片后续发送数据被可靠接收提供了基础。
具体地说，选择器104还与发送模块40连接，选择器104还用于将校准波特率输出给发送模块40。
更具体地说，双工通信是指通信双端可以同时发送和接收数据的信息交互方式。在双工通信的情况下，若选择器104将校准波特率输出给发送模块40，实现发送模块40的波特率更新，则能够令本端发送模块40的波特率与对端接收模块的波特率匹配，保证了通信双端数据传输的可靠性。然而，上述双工通信的举例仅作为示例性说明，本实施例并不对发送模块40波特率更新的具体应用场景做任何限定。
本申请第五实施例涉及一种串口芯片，如图10所示，详述如下：
具体地说，在串口芯片本端包括有波特率校准电路10与接收模块20，波特率校准电路10与接收模块20连接。接收模块20用于接收对端发送的数据帧，根据数据帧发送开始指令以及停止指令，并用于依据接收模块20的当前波特率对数据帧进行采样，生成比特采样脉冲。波特率校准电路10用于根据开始指令、停止指令以及比特采样脉冲计算校准波特率，并将校准波特率输出给接收模块20。这样，实现了接收模块20波特率的自动识别与动态实时校准，效率较高，能够提升接收模块20后续数据接收的可靠性，为串口芯片能够适用于通信环境变化过快的通信系统提供了基础，解决了串口芯片在极端环境下所产生的误码率上升问题。并且，在无需使用时，可以直接绕过波特率校准电路10，操作较为便捷。
更具体地说，串口芯片本端还包括有发送模块40，波特率校准电路10 还可以与串口芯片的发送模块40连接。这样，波特率校准电路10还可以在计算出校准波特率后，将校准波特率输出给发送模块40，从而令发送模块40能够基于校准后的当前波特率进行数据的发送，为串口芯片后续发送数据被可靠接收提供了基础。
本申请第六实施例涉及一种串口芯片，如图11所示。第六实施例在第五实施例的基础上加以改进，主要改进之处在于：在本实施例中，串口芯片还包括滤波器50，能够避免噪声带来的干扰，提高当前波特率的校准准确度。以下进行具体说明：
本实施例中，滤波器50与接收模块20连接。滤波器50用于对接收模块20接收到的数据帧进行滤波。
具体地说，在接收模块20接收对端串口芯片发送过来的数据时，接收模块20将所接收到的数据传输给滤波器50进行滤波，以便于滤波器50将滤波后的数据返回给接收模块20。这样，能够令接收模块20的后续操作均是基于滤波后的数据帧进行的，从而不仅能够令接收模块20向波特率校准电路10发送开启指令、停止指令的时机不受噪声的干扰，而且能够令接收模块20的采样标本为滤波后的数据帧，为获取更加精准的校准波特率提供了基础。
本实施例相对于第五实施例而言，当前波特率的校准准确度更高，接收模块20后续数据接收的可靠性也更高。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (10)

  1. 一种波特率校准电路，其特征在于，包括：
    第一计数器，与串口芯片的接收模块连接，所述第一计数器用于记录所述接收模块接收到的数据帧的第一个低电平时长；
    第二计数器，与所述接收模块连接，所述第二计数器用于接收比特采样脉冲，并记录所述第一个低电平时长内的比特采样脉冲的数目；其中，所述比特采样脉冲由所述接收模块依据所述接收模块的当前波特率对所述数据帧进行采样生成；
    除法器，与所述第一计数器以及所述第二计数器连接，所述除法器用于根据所述第一个低电平时长和所述第一个低电平时长内的比特采样脉冲的数目，计算校准波特率；
    选择器，与所述接收模块以及所述除法器连接，所述选择器用于将所述校准波特率输出给所述接收模块。
  2. 如权利要求1所述波特率校准电路，其中，所述选择器还与所述第一计数器连接，所述选择器具体用于在所述第一个低电平时长小于预设时长时，将所述校准波特率输出给所述接收模块。
  3. 如权利要求2所述波特率校准电路，其中，所述预设时长由所述选择器依据所述接收模块的当前波特率设置。
  4. 如权利要求1所述波特率校准电路，其中，所述选择器还与所述第二计数器连接，所述选择器具体用于在所述第一个低电平时长内比特采样脉冲的数目小于预设个数时，将所述校准波特率输出给所述接收模块。
  5. 如权利要求4所述波特率校准电路，其中，所述预设个数为7。
  6. 如权利要求1所述波特率校准电路，其中，所述选择器还与所述串口芯片的发送模块连接，所述选择器还用于将所述校准波特率输出给所述发送模块。
  7. 如权利要求1所述波特率校准电路，其中，所述校准电路还包括：
    校准输出寄存器，与所述选择器连接，所述校准输出寄存器用于在所述选择器将所述校准波特率输出给所述接收模块后，输出预设信号；其中，所述预设信号用于表征波特率校准是否成功。
  8. 一种串口芯片，其特征在于，包括：接收模块以及如权利要求1至7中任一项所述的波特率校准电路；
    所述接收模块用于接收对端发送的数据帧，根据所述数据帧发送开始指令以及停止指令，并用于依据所述接收模块的当前波特率对所述数据帧进行采样，生成比特采样脉冲；
    所述波特率校准电路，与所述接收模块连接，所述波特率校准电路用于根据所述开始指令、停止指令以及所述比特采样脉冲计算校准波特率，并将所述校准波特率输出给所述接收模块。
  9. 如权利要求8所述串口芯片，其中，所述串口芯片还包括：
    发送模块，与所述波特率校准电路连接；
    所述波特率校准电路还用于将所述校准波特率输出给所述发送模块。
  10. 如权利要求8所述串口芯片，其中，所述串口芯片还包括：
    滤波器，与所述接收模块连接，所述滤波器用于对所述接收模块接收到的数据帧进行滤波；
    所述接收模块具体用于依据所述接收模块的当前波特率对滤波后的所述数 据帧进行采样。
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