WO2021063303A1 - 获取数据流的时间戳的方法、装置、存储介质和电子装置 - Google Patents
获取数据流的时间戳的方法、装置、存储介质和电子装置 Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0647—Synchronisation among TDM nodes
- H04J3/065—Synchronisation among TDM nodes using timestamps
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
- H04J3/0697—Synchronisation in a packet node
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
- H04L7/0012—Synchronisation information channels, e.g. clock distribution lines by comparing receiver clock with transmitter clock
Definitions
- the present disclosure relates to the field of communications, for example, to a method, device, storage medium, and electronic device for obtaining a time stamp of a data stream.
- the Institute of Electrical and Electronics Engineers (IEEE) 1588 protocol was originally used to describe the protocol for precise clock synchronization in network measurement and control systems.
- IEEE 1588 protocol With the development of Ethernet technology, the IEEE1588 protocol has been applied to the Ethernet field, and the processing of the IEEE1588 protocol can be realized in Fast Ethernet, and the accuracy is very high.
- the time stamp is used to reflect the time point when a data block is generated in the data stream.
- the time stamp of the data block collected later must be greater than the time stamp of the data block collected first. With such a time stamp, the sequence of data blocks can be marked. In this way, to ensure the synchronization between the devices in the distributed control system.
- the device After the serializer-deserializer (SERDES) module of the device receives the data stream to be transmitted, the device needs to perform adaptive conversion on the data stream to be transmitted. However, after the device converts the data stream to be transmitted, there may be a data gap, that is, invalid data. Therefore, if the data stream to be transmitted after the conversion, that is, a data stream including invalid data, is time-stamped, an accurate time stamp cannot be obtained.
- SERDES serializer-deserializer
- the present disclosure provides a method, a device, a storage medium, and an electronic device for obtaining a time stamp of a data stream, so as to at least solve the problem that the accurate time stamp of a data stream cannot be obtained.
- a method for obtaining the timestamp of a data stream including:
- a device for obtaining the time stamp of a data stream including:
- the receiving module is configured to receive the data stream to be transmitted, and obtain the first frame header identifier of the data stream to be transmitted in the serializer/deserializer SERDES clock mode, wherein the first frame header identifier is used to characterize the data stream to be transmitted.
- a determining module configured to determine the time stamp of the data stream to be transmitted under the system clock based on the first frame header identifier
- An encapsulation module configured to encapsulate the timestamp to obtain the first target data frame
- the output module is configured to output the first target data frame.
- a storage medium is also provided, and a computer program is stored in the storage medium, wherein the computer program is configured to execute the above-mentioned method for obtaining a time stamp of a data stream when running.
- An electronic device including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the above-mentioned method for obtaining a time stamp of a data stream.
- FIG. 1 is a block diagram of the hardware structure of a terminal for executing a method for obtaining a time stamp of a data stream according to an embodiment of the present invention
- FIG. 2 is a schematic flowchart of a method for obtaining a time stamp of a data stream according to an embodiment of the present invention
- FIG. 3 is a schematic diagram of synchronization between the rising edge of the system clock and the first frame header identifier according to an embodiment of the present invention
- FIG. 4 is a schematic diagram of synchronization between the falling edge of the system clock and the first frame header identifier according to an embodiment of the present invention
- FIG. 5 is a schematic diagram of a frame format of a first target data frame provided by an embodiment of the present invention.
- Fig. 6 is a schematic structural diagram of an apparatus for obtaining a time stamp of a data stream according to an embodiment of the present invention.
- FIG. 1 is a hardware structural block diagram of a terminal for executing a method for obtaining a time stamp of a data stream according to an embodiment of the present invention.
- the terminal may include one or more (only one is shown in FIG. 1) processor 102 (the processor 102 may include, but is not limited to, a microprocessor (Microcontroller Unit, MCU) or a programmable logic device (Field A processing device such as a Programmable Gate Array, FPGA) and a memory 104 configured to store data.
- MCU microprocessor
- FPGA Programmable Gate Array
- the aforementioned terminal may also include a transmission device 106 and an input/output device 108 configured as a communication function.
- the structure shown in FIG. 1 is only for illustration, and it does not limit the structure of the foregoing terminal.
- the terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration from that shown in FIG.
- the memory 104 may be configured to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for obtaining the time stamp of a data stream in the embodiment of the present invention, and the processor 102 runs the computer program stored in the memory 104 A computer program to execute a variety of functional applications and data processing, that is, to implement the above-mentioned methods.
- the memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory.
- the memory 104 may include a memory remotely provided with respect to the processor 102, and these remote memories may be connected to the terminal through a network. Examples of the aforementioned networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.
- the transmission device 106 is configured to receive or transmit data via a network.
- the above-mentioned specific examples of the network may include a wireless network provided by the communication provider of the terminal.
- the transmission device 106 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to communicate with the Internet.
- the transmission device 106 may be a radio frequency (RF) module, which is configured to communicate with the Internet in a wireless manner.
- RF radio frequency
- a method for obtaining the time stamp of a data stream running on the above terminal is provided.
- the method can be applied to a chip with a SERDES interface, and the chip has at least a function of time stamping the data stream to be transmitted.
- This method can realize the 1588 function in the Flexible Optical Transport Network (Flexible Optical Transport Network, FLEXO) protocol, that is, the function of realizing frequency synchronization and phase synchronization between devices.
- FLEXO Flexible Optical Transport Network
- the method of obtaining the time stamp of the data stream can be applied to the following scenarios: when the data stream to be transmitted enters the chip, that is, at the entrance of the chip; and when the data to be transmitted is output to the chip, that is, at the exit of the chip. Get the timestamp of the data stream.
- the entrance of the chip and the exit of the chip are equivalent to the SERDES interface of the chip.
- the time stamp can be sampled at the SERDES to avoid the time stamp jitter caused by the memory or buffer and the gap conversion.
- FIG. 2 is a schematic flowchart of a method for obtaining a time stamp of a data stream according to an embodiment of the present invention. As shown in FIG. 2, the process includes the following steps:
- Step S202 Receive the data stream to be transmitted, and obtain the first frame header identifier of the data stream to be transmitted in the serializer/deserializer clock mode.
- the first frame header identifier is used to characterize the position of the frame header of the data stream.
- the foregoing first frame header identifier may be an alignment (Alignment Marker, AM) frame header identifier, referred to as AM identifier.
- the AM identification may be an identification generated by an external AM detection module in the serializer/deserializer clock mode, and the AM detection module is set inside the chip. After the chip receives the data stream to be transmitted, first, in the serializer/deserializer clock mode, the bit corresponding to the AM identifier generated by the AM detection module can be converted into the bit corresponding to the data stream to be transmitted.
- the above-mentioned AM identifier is 4 bits, and the data stream to be transmitted is 3 bits.
- the chip first splices the 3-bit data stream to be transmitted into a 6-bit data stream to be transmitted.
- the chip uses the header position identified by the AM to characterize the position of the frame header of the data stream to be transmitted.
- Step S204 Determine the time stamp of the data stream to be transmitted under the system clock based on the first frame header identifier.
- determining the time stamp of the data stream to be transmitted under the system clock means: converting the AM identifier in the serializer/deserializer clock mode to the AM identifier in the system clock mode.
- the system clock may include a system rising edge clock and a system falling edge clock.
- the system rising edge clock can be used to synchronize the above-mentioned AM identifier to obtain a time stamp T1 corresponding to the system rising edge clock.
- the system falling edge clock can be used to synchronize the above-mentioned AM identifier when the system falling edge clock is valid to obtain a time stamp T2 corresponding to the system falling edge clock. Then, based on the comparison between T1 and T2, the time stamp T0 of the data stream to be transmitted under the system clock is determined.
- Step S206 encapsulate the timestamp to obtain the first target data frame.
- the determined time stamp under the system clock is encapsulated according to a preset frame format.
- the preset frame format may include a check value used to characterize the correctness or error of the timestamp under the above-mentioned system clock.
- Step S208 Output the first target data frame.
- the foregoing step S202 may sequentially receive the foregoing data stream to be transmitted in the form of 1 bit; then, the output of the foregoing first target data frame may also be performed in the form of 1 bit. Finally, after the first target data frame is all output, the time stamp about the data stream to be transmitted can be obtained.
- the data stream to be transmitted is received, and the first frame header identifier of the data stream to be transmitted in the serializer/deserializer clock mode is obtained.
- the header identifier is used to characterize the position of the frame header of the data stream; secondly, based on the first header identifier, determine the timestamp of the data stream under the system clock; again, encapsulate the timestamp to obtain the first target data frame; finally, output the first Target data frame.
- the serializer/deserializer clock mode which is equivalent to the data clock mode
- the first frame header identifies the system clock domain conversion, encapsulation and a series of output processing, so as to obtain the accurate time stamp of the data stream to be transmitted, instead of converting the data stream to be transmitted in the data clock domain mode into the system clock domain
- the data stream to be transmitted under In this way, data gaps occurring after clock conversion of the data stream to be transmitted are avoided, and the situation that the time stamp sampling for the data stream to be transmitted after the conversion, that is, the data stream including invalid data, cannot obtain an accurate time stamp is avoided. Thereby, the problem that the accurate time stamp of the data stream cannot be obtained is solved, and the purpose of accurately obtaining the time stamp of the data stream is realized.
- receiving the data stream to be transmitted in step S202 and obtaining the first frame header identifier of the data stream to be transmitted in the serializer/deserializer clock mode may include the following steps:
- Step S202-11 Receive the data stream to be transmitted, and demultiplex the data stream to be transmitted in the serializer/deserializer clock mode to obtain N logical channel data, where N is an integer.
- FLEXO 4 logical channel data includes lane 0 (lane0) logical channel data, lane1 logical channel data, lane2 logical channel data, and lane3 logical channel data.
- step S202-12 when the position of the frame header of each logical channel data is determined, the position of the frame header of each logical channel data is obtained, and the second frame header identifier of each logical channel data is obtained.
- lane0 logical channel data it is assumed that lane0 logical channel data includes a data block, b data block, and c data block with an AM identifier.
- the search process suppose that after 10 bytes, a data block, b data block and c data block with the AM logo appear again; then, the chip judges that 10 bytes is the position of the frame header of the lane0 logical channel data. This position is the second frame header identifier AM0 of the lane0 logical channel data.
- the other three lanes can also search and determine the position of the corresponding frame header in the above-mentioned manner, that is, the second frame header identifier of each logical channel data.
- the second frame header identifiers of the other three lanes can be obtained as AM1, AM2, and AM3, respectively.
- Step S202-13 Determine the first frame header identifier based on the second frame header identifier of each logical channel data.
- the determination of the first frame header identifier may be based on the foregoing AM0, AM1, AM2, and AM3, and one of them is selected as the first frame header identifier AM.
- the above step S202-13 may include: selecting one channel data from the N logical channel data as the designated channel data; calculating the second frame header identifier of the other N-1 logical channel data relative to the second frame header of the designated logical channel data Identify multiple offsets; obtain the maximum offset of the multiple offsets, and determine that the second frame header identifier corresponding to the maximum offset is the first frame header identifier.
- the second frame header identifier AM0 of lane0 logical channel data can be used as a reference to calculate the multiple offsets of the second frame header identifier of N-1 logical channel data with respect to the second frame header identifier of the first logical channel data. . For example, calculate the offset of AM1 corresponding to lane1, AM2 corresponding to lane2, and AM3 corresponding to lane3 relative to AM0 corresponding to lane0 to obtain the first offset P1, the second offset P2, and the third offset P3. .
- the second frame header identifier of the logical channel data that has the largest offset, that is, the latest arrival, is selected as the first frame header identifier AM.
- the chip selects AM3 corresponding to the third offset P3 as the first frame header identifier AM.
- determining the time stamp of the data stream to be transmitted under the system clock based on the first frame header identifier in step S204 may include step S204-1: comparing the rising and falling edges of the system clock with the first A frame header is identified for synchronization, and the time stamp of the data stream to be transmitted is obtained under the system clock.
- the system clock may include a system rising edge clock and a system falling edge clock.
- the first frame header identifier When converting the first frame header identifier into the clock domain, it needs to be converted based on the system rising edge clock and the system falling edge clock respectively; then, the smaller value in the conversion result is selected as the time stamp of the data stream to be transmitted under the system clock .
- Step S204-1 can be implemented through the following steps:
- Step S204-11 Synchronize the rising edge of the system clock with the first frame header identifier to obtain the third frame header identifier of the data stream to be transmitted under the system clock.
- am_ind in FIG. 3 refers to the schematic diagram of the pulse corresponding to the AM identifier of the first frame header
- sys_clk refers to the schematic diagram of the pulse corresponding to the rising edge clock of the system.
- the system rising edge clock is valid, that is, the rising edge comes first, as shown in Figure 3 with a bold arrow.
- the pulse corresponding to the first frame header identifier AM identifier is synchronized by using the system rising edge clock to obtain the third frame header identifier corresponding to the system rising edge clock, that is, the above-mentioned time stamp T1.
- Step S204-12 Synchronize the falling edge of the system clock with the first frame header identifier to obtain the fourth frame header identifier of the data stream to be transmitted under the system clock.
- Am_ind in FIG. 4 refers to a schematic diagram of pulses corresponding to the first frame header identifier AM identifier
- am_ind in FIG. 4 refers to the same pulse as that indicated by am_ind in FIG. 3
- sys_clk refers to a schematic diagram of pulses corresponding to the falling edge clock of the system.
- Step S204-13 based on the third frame header identifier and the fourth frame header identifier, obtain the time stamp of the data stream to be transmitted under the system clock.
- the time stamp T0 of the data stream to be transmitted under the system clock can be determined.
- the above step S204-13 may be: comparing the third frame header identifier and the fourth frame header identifier; obtaining the smaller frame header identifier of the third frame header identifier and the fourth frame header identifier, and determining that the smaller frame header identifier is The time stamp of the data stream to be transmitted under the system clock.
- T1 is selected as the time stamp T0 of the data stream to be transmitted under the system clock.
- the encapsulation timestamp involved in step S206 to obtain the first target data frame may include the following steps:
- Step S206-11 Generate a Cyclic Redundancy Check (CRC).
- the CRC value of the cyclic redundancy check code may be a check value used to characterize the correctness or error of the time stamp under the system clock.
- the chip when receiving the data stream to be transmitted, the chip obtains the first time stamp of the data stream to be transmitted and the first CRC value corresponding to the first time stamp; and sends the first time stamp and the first CRC value to The receiving end; the receiving end obtains the first time stamp and the first CRC value and calculates the second CRC value according to the first time stamp; the receiving end judges whether the first CRC value and the second CRC value are the same, if they are the same, it means the obtained The timestamp is correct; if they are not the same, it means that the obtained timestamp is wrong.
- Step S206-12 encapsulate the time stamp and CRC based on the preset frame format to obtain the first target data frame.
- the format of the foregoing first target data frame may be similar to the format of the Time of Day (TOD) frame. Therefore, the foregoing first target data frame may also be referred to as a TOD-like frame.
- the start bit is fixed at 1bit and the value is 0, the frame header synchronization of the two words is 0x43, 0x4d, and the CRC is 1bit. (And the value is 0 or 1), the stop bit is fixed at 1bit and the value is 1.
- outputting the first target data frame in step S208 may include the following steps: broadening the pulse width of the first target data frame to obtain the second target data frame; outputting the second target data frame.
- the output sequence of the entire first target data frame may be: start bit, sync header, time stamp second part, time stamp nanosecond part, CRC stop bit.
- the sending of the first target data frame can be performed in a little-endian transfer mode. It can be seen that the method for obtaining the time stamp of a data stream provided by the embodiment of the present invention can achieve nanosecond synchronization accuracy.
- the time stamp sent must be expanded; that is, the pulse width of the first target data frame is expanded to obtain the second target data frame, and the second target data frame is output.
- Target data frame to ensure that the off-chip FPGA can sample every bit and can correctly recover the time stamp.
- it may be expanded proportionally according to the multiple relationship of the clocks of the sending end and the receiving end, and the configuration of the central processing unit (CPU). In this way, the off-chip FPGA with the same 1bit time stamp information can be sampled multiple times, and the 64bit time stamp can be correctly restored through the majority decision method.
- the off-chip FPGA can insert the Precision Time Protocol (PTP) abbreviation message in the next FLEXO frame after obtaining the chip's timestamp; in the receiving direction, record the AM identifier of each frame For the time stamp, select the time stamp corresponding to the PTP packet header according to the parsed PTP packet. In this way, the timestamps in the sending and receiving directions can be matched to complete the 1588 function.
- PTP Precision Time Protocol
- the method for obtaining the time stamp of a data stream provided by the embodiment of the present invention can realize the generation of a high-precision time stamp through the FLEXO AM identification, and realize the 1588 function.
- this method realizes time-stamping with the fixed frame header in the SERDES clock domain under the IEEE1588V2 protocol, which can effectively reduce the jitter of the time stamp and obtain a higher-precision time stamp.
- the method of the above embodiment can be implemented by software plus a necessary general hardware platform, or by hardware.
- the technical solution of the present disclosure can essentially be embodied in the form of a software product, and the computer software product is stored in a storage medium (such as Read-Only Memory (ROM)/Random Access Memory (RAM)) , Magnetic disk, optical disk), including multiple instructions to make a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) execute the method described in the embodiment of the present invention.
- ROM Read-Only Memory
- RAM Random Access Memory
- a terminal device which can be a mobile phone, a computer, a server, or a network device, etc.
- a device for obtaining the time stamp of a data stream is also provided.
- the device is configured to implement the above-mentioned embodiment, and what has been described will not be repeated.
- the term "module" can implement a combination of software and/or hardware with predetermined functions.
- Fig. 6 is a schematic structural diagram of an apparatus for obtaining a time stamp of a data stream according to an embodiment of the present invention. As shown in Fig. 6, the apparatus includes:
- the receiving module 62 is configured to receive the data stream to be transmitted, and obtain the first frame header identifier of the data stream to be transmitted in the serializer/deserializer SERDES clock mode.
- the first frame header identifier is used to characterize the frame header of the data stream. Position; determining module 64, set to determine the time stamp of the data stream to be transmitted under the system clock based on the first frame header identification; encapsulation module 66, set to encapsulate the time stamp to obtain the first target data frame; output module 68, set to Output the first target data frame.
- the receiving module 62 in this application may include: a receiving unit configured to receive the data stream to be transmitted, and demultiplex the data stream to be transmitted in the SERDES clock mode to obtain N logical channel data, where N Is an integer; the first obtaining unit is set to obtain the position of the frame head of each logical channel data in the case of determining the position of the frame head of each logical channel data to obtain the second frame head of each logical channel data Identification; the determining unit is set to determine the first frame header identification based on the second frame header identification of each logical channel data.
- the determining unit may include: a selection subunit, which is set to select one channel data from N logical channel data as the designated channel data; and a calculation subunit, which is set to calculate the second frame header identifier of the other N-1 logical channel data. Multiple offsets of the second frame header identifier of the designated logical channel data; the acquisition subunit is set to acquire the maximum offset of the multiple offsets, and determine the second frame header identifier corresponding to the maximum offset It is the first frame header identification.
- the determining module 64 in this application is configured to synchronize the rising and falling edges of the system clock with the first frame header identifier to obtain the time stamp.
- the determining module 64 in this application may include: a first synchronization unit configured to synchronize the rising edge of the system clock with the first frame header identifier to obtain the third frame header of the data stream to be transmitted under the system clock Identification; the second synchronization unit is set to synchronize the falling edge of the system clock with the first frame header identification to obtain the fourth frame header identification of the data stream to be transmitted under the system clock; the second acquisition unit is set to be based on the third The frame header identifier and the fourth frame header identifier are used to obtain the timestamp.
- the second acquiring unit may include: a comparison subunit, configured to compare the third frame header identifier and the fourth frame header identifier; and the determining subunit, configured to select from the third frame header identifier and the fourth frame header identifier according to the comparison result Make sure that the smaller frame header is identified as a timestamp.
- the encapsulation module 66 in the present application may include: a generating unit, configured to generate a cyclic redundancy check code CRC; and an encapsulating unit, configured to encapsulate the time stamp and CRC based on a preset frame format to obtain the first Target data frame.
- a generating unit configured to generate a cyclic redundancy check code CRC
- an encapsulating unit configured to encapsulate the time stamp and CRC based on a preset frame format to obtain the first Target data frame.
- the output module 68 in the present application may include: a stretching unit configured to stretch the pulse width of the first target data frame to obtain the second target data frame; the output unit configured to output the second target data frame.
- the above-mentioned multiple modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to this: the above-mentioned modules are all located in the same processor; or, the above-mentioned multiple modules are respectively in the form of any combination. Located in different processors.
- the embodiment of the present invention also provides a storage medium in which a computer program is stored, wherein the computer program is configured to execute the steps in any one of the foregoing method embodiments when running.
- the aforementioned storage medium may be configured to store a computer program for executing the following steps:
- S1 Receive the data stream to be transmitted, and obtain the first frame header identifier of the data stream to be transmitted in the serializer/deserializer SERDES clock mode, and the first frame header identifier is used to characterize the position of the frame header of the data stream.
- S2 Determine the time stamp of the data stream to be transmitted under the system clock based on the first frame header identifier.
- the foregoing storage medium may include, but is not limited to: U disk, ROM, RAM, mobile hard disk, magnetic disk, or optical disk, and other media that can store computer programs.
- An embodiment of the present invention also provides an electronic device, including a memory and a processor, the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the foregoing method embodiments.
- the aforementioned electronic device may further include a transmission device and an input-output device, wherein the transmission device is connected to the aforementioned processor, and the input-output device is connected to the aforementioned processor.
- the foregoing processor may be configured to execute the following steps through a computer program:
- S2 Determine the time stamp of the data stream to be transmitted under the system clock based on the first frame header identifier.
- the above-mentioned multiple modules or multiple steps of the present disclosure can be implemented by a general computing device. They can be concentrated on a single computing device or distributed on a network composed of multiple computing devices. Optionally, they can be It is implemented by the program code executable by the computing device, so that they can be stored in the storage device to be executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, Or they can be made into multiple integrated circuit modules respectively, or multiple modules or steps of them can be made into a single integrated circuit module to achieve. In this way, the present disclosure is not limited to any specific combination of hardware and software.
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Abstract
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Claims (11)
- 一种获取数据流的时间戳的方法,包括:接收待传输数据流,并获取串行器/解串器SERDES时钟模式下的所述待传输数据流的第一帧头标识,其中,所述第一帧头标识用于表征所述待传输数据流的帧头的位置;基于所述第一帧头标识,确定所述待传输数据流在系统时钟下的时间戳;封装所述时间戳得到第一目标数据帧;输出所述第一目标数据帧。
- 根据权利要求1所述的方法,其中,所述接收待传输数据流,并获取SERDES时钟模式下的所述待传输数据流的第一帧头标识,包括:接收所述待传输数据流,并在所述SERDES时钟模式下对所述待传输数据流进行解复用,得到N条逻辑通道数据,其中,N为整数;在判断出每条逻辑通道数据的帧头的位置的情况下,获取每条逻辑通道数据的帧头的位置,得到每条逻辑通道数据的第二帧头标识;基于每条逻辑通道数据的第二帧头标识,确定所述第一帧头标识。
- 根据权利要求2所述的方法,其中,所述基于每条逻辑通道数据的第二帧头标识,确定所述第一帧头标识,包括:从所述N条逻辑通道数据中选择一条通道数据作为指定通道数据;计算所述N条逻辑通道数据中除所述指定通道数据外的N-1条逻辑通道数据的第二帧头标识相对于所述指定逻辑通道数据的第二帧头标识的多个偏移量;获取所述多个偏移量中的最大偏移量,并确定所述最大偏移量对应的第二帧头标识为所述第一帧头标识。
- 根据权利要求1所述的方法,其中,所述基于所述第一帧头标识,确定所述待传输数据流在系统时钟下的时间戳,包括:将所述系统时钟的上升沿和下降沿与所述第一帧头标识进行同步,得到所述待传输数据流在所述系统时钟下的时间戳。
- 根据权利要求4所述的方法,其中,所述将所述系统时钟的上升沿和下降沿与所述第一帧头标识进行同步,得到所述待传输数据流在所述系统时钟下的时间戳,包括:将所述系统时钟的上升沿与所述第一帧头标识进行同步,得到所述待传输数据流在所述系统时钟下的第三帧头标识;将所述系统时钟的下降沿与所述第一帧头标识进行同步,得到所述待传输数据流在所述系统时钟下的第四帧头标识;基于所述第三帧头标识和所述第四帧头标识,获取所述时间戳。
- 根据权利要求5所述的方法,其中,所述基于所述第三帧头标识和所述第四帧头标识,获取所述时间戳,包括:比较所述第三帧头标识和所述第四帧头标识;根据比较结果,从所述第三帧头标识和所述第四帧头标识中确定较小的帧头标识为所述时间戳。
- 根据权利要求1所述的方法,其中,所述封装所述时间戳得到第一目标数据帧,包括:生成循环冗余校验码CRC;基于预设的帧格式将所述时间戳和所述CRC进行封装,得到所述第一目标数据帧。
- 根据权利要求1所述的方法,其中,所述输出所述第一目标数据帧,包括:展宽所述第一目标数据帧的脉冲宽度得到第二目标数据帧;输出所述第二目标数据帧。
- 一种获取数据流的时间戳的装置,包括:接收模块,设置为接收待传输数据流,并获取串行器/解串器SERDES时钟模式下的所述待传输数据流的第一帧头标识,其中,所述第一帧头标识用于表征所述待传输数据流的帧头的位置;确定模块,设置为基于所述第一帧头标识,确定所述待传输数据流在系统时钟下的时间戳;封装模块,设置为封装所述时间戳得到第一目标数据帧;输出模块,设置为输出所述第一目标数据帧。
- 一种计算机可读的存储介质,存储有计算机程序,其中,所述计算机程序被设置为运行时执行所述权利要求1至8中任一项所述的获取数据流的时间戳的方法。
- 一种电子装置,包括存储器和处理器,其中,所述存储器中存储有计算机程序,所述处理器被设置为运行所述计算机程序以执行所述权利要求1至8中任一项所述的获取数据流的时间戳的方法。
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