WO2021035547A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

Info

Publication number
WO2021035547A1
WO2021035547A1 PCT/CN2019/102887 CN2019102887W WO2021035547A1 WO 2021035547 A1 WO2021035547 A1 WO 2021035547A1 CN 2019102887 W CN2019102887 W CN 2019102887W WO 2021035547 A1 WO2021035547 A1 WO 2021035547A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
electrode pattern
layer
display substrate
dummy
Prior art date
Application number
PCT/CN2019/102887
Other languages
English (en)
French (fr)
Inventor
李云龙
卢鹏程
刘李
敖雨
田元兰
朱志坚
张大成
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN201980001498.4A priority Critical patent/CN112740416B/zh
Priority to US16/958,821 priority patent/US20220384553A1/en
Priority to EP19933241.2A priority patent/EP4024468A4/en
Priority to PCT/CN2019/102887 priority patent/WO2021035547A1/zh
Publication of WO2021035547A1 publication Critical patent/WO2021035547A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • At least one embodiment of the present disclosure relates to a display substrate, a manufacturing method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • An organic light emitting diode usually includes a first electrode, a second electrode, and an organic electroluminescent element sandwiched between the two electrodes.
  • the organic electroluminescent element includes a light-emitting functional layer
  • the light-emitting functional layer includes a light-emitting layer
  • the light-emitting functional layer may also include At least one of the hole transport layer, the hole injection layer, the electron transport layer, and the electron injection layer, and the organic electroluminescent unit can emit light when the first electrode and the second electrode are electrically driven.
  • the mainstream production process of the light-emitting functional layer is to use a fine metal mask (FMM) to vapor-deposit the light-emitting functional layer, and a sputtering process and an etching process are used to fabricate the first electrode.
  • FMM fine metal mask
  • silicon-based OLEDs are required to have high resolution, and high resolution will bring higher process difficulties.
  • At least one embodiment of the present disclosure relates to a display substrate, a manufacturing method thereof, and a display device.
  • At least one embodiment of the present disclosure provides a display substrate.
  • the display substrate includes: a base substrate, a first insulating layer, a first electrode pattern, a connecting electrode pattern, a second electrode, a light-emitting function layer, and a first filling layer
  • the first insulating layer is located on the base substrate;
  • the first electrode pattern is located in the display area of the display substrate, the first electrode pattern includes a plurality of first electrodes spaced apart from each other, and the first electrodes are configured to Receiving pixel drive signals;
  • connecting electrode patterns are located in the peripheral area of the display substrate, the connecting electrode patterns surround the first electrode pattern;
  • the second electrode is located in the display area and the peripheral area, and is connected to the connecting electrode
  • the patterns are connected, the second electrode and the first electrode pattern are spaced apart from each other, the second electrode is configured to receive a first power signal;
  • the light-emitting function layer is located between the first electrode pattern and the second electrode
  • the first filling layer is located between the connecting electrode
  • the first electrode pattern includes an edge first electrode close to the connecting electrode pattern, and the first filling layer is connected to the connecting electrode pattern and the edge first electrode, respectively. Electrode contact.
  • the connecting electrode pattern has a ring shape.
  • the second electrode is in contact with the first filling layer.
  • the first filling layer includes an insulating layer.
  • the first filling layer includes at least one conductive filling part and at least one insulating filling part, the edge first electrode is in contact with the insulating filling part, and the edge first The electrode and the conductive filling part are spaced apart from each other.
  • the first filling layer includes a plurality of conductive filling parts and a plurality of insulating filling parts, and the plurality of conductive filling parts and the plurality of insulating filling parts are alternately arranged.
  • At least two of the pattern density of the plurality of conductive filling portions, the pattern density of the connection electrode pattern, and the pattern density of the first electrode pattern are the same.
  • the display substrate provided by an embodiment of the present disclosure further includes a pixel definition layer.
  • the pixel definition layer includes a plurality of pixel definition portions, and the pixel definition portions are located between adjacent first electrodes.
  • the first filling layer or at least one insulating filling portion of the first filling layer and the pixel definition layer are located in the same layer.
  • the first electrode pattern and the connection electrode pattern are located on the same layer.
  • the display substrate provided by an embodiment of the present disclosure further includes a second filling layer, the second filling layer includes at least one second filling portion, the connection electrode pattern includes a plurality of connection electrodes, and the second filling portion is located adjacent to each other. Connect between electrodes.
  • the second filling layer includes an insulating layer.
  • the second filling layer and the first filling layer are located in the same layer.
  • the light-emitting function layer is in contact with the first filling layer.
  • the light-emitting function layer is in contact with a part of the first filling layer.
  • the first electrode is an anode of a light-emitting element
  • the second electrode is a cathode of the light-emitting element
  • the base substrate includes a silicon wafer.
  • At least one embodiment of the present disclosure further provides a display device including any display substrate described in the first aspect.
  • At least one embodiment of the present disclosure further provides a manufacturing method of a display substrate, including: forming a first insulating layer on a base substrate; forming a first electrode pattern, the first electrode pattern being located in a display area of the display substrate,
  • the first electrode pattern includes a plurality of first electrodes spaced apart from each other, the first electrodes are configured to receive pixel driving signals; and a connecting electrode pattern is formed, and the connecting electrode pattern is located in a peripheral area of the display substrate.
  • a connection electrode pattern surrounds the first electrode pattern; a second electrode is formed, the second electrode is located in the display area and the peripheral area, the second electrode is connected to the connection electrode pattern, and the second electrode Spaced apart from the first electrode pattern, the second electrode is configured to receive a first power signal; forming a light-emitting function layer, and the light-emitting function layer is located between the first electrode pattern and the second electrode; And forming a first filling layer, the first filling layer being located between the connecting electrode pattern and the first electrode pattern; the first filling layer and the light-emitting function layer are different layers, the first filling layer
  • the electrode pattern and the connection electrode pattern are located on a side of the first insulating layer away from the base substrate and are in contact with the first insulating layer, respectively, and the first insulating layer is located on the first electrode pattern
  • a portion between and the connecting electrode pattern has a groove, and the first filling layer is at least partially located in the groove.
  • the first electrode pattern includes a first electrode close to the edge of the connection electrode pattern, and the first filling layer is connected to the connection electrode pattern and the connection electrode pattern, respectively. Edge first electrode contact.
  • the second electrode is in contact with the first filling layer.
  • the manufacturing method of the display substrate provided by an embodiment of the present disclosure further includes forming a pixel defining layer, the pixel defining layer includes a plurality of pixel defining portions, and the first electrode pattern includes a plurality of first electrodes spaced apart from each other; the pixel The defining part is located between adjacent first electrodes.
  • the pixel definition layer and the first filling layer are formed by the same patterning process, and the first electrode pattern and the connecting electrode pattern are formed by the same patterning process form.
  • forming the first filling layer includes forming at least one conductive filling part and forming at least one insulating filling part, the first electrode pattern, the connecting electrode pattern, and the The at least one conductive filling part is formed by the same patterning process; and the pixel definition layer and the at least one insulating filling part are formed by the same patterning process.
  • the manufacturing method of the display substrate provided by an embodiment of the present disclosure further includes forming a second filling layer, the second filling layer includes at least one second filling portion, the connection electrode pattern includes a plurality of connection electrodes, and the second filling layer The portion is located between adjacent connection electrodes; the second filling layer is formed in the same patterning process for forming the pixel definition layer and the at least one insulating filling portion.
  • At least one embodiment of the present disclosure provides a display substrate, including: a first electrode pattern, a connecting electrode pattern, a second electrode, and a light-emitting function layer;
  • the first electrode pattern is located in the display area of the display substrate and includes A plurality of first electrodes spaced apart from each other, the first electrodes are configured to receive pixel driving signals;
  • the connection electrode pattern is located in the peripheral area of the display substrate and includes a plurality of connection electrodes;
  • the second electrode is located in the display area and The peripheral area is connected to the connecting electrode pattern, the second electrode and the first electrode pattern are spaced apart from each other, the second electrode is configured to receive a first power signal;
  • the light emitting function layer is located on the first electrode pattern.
  • the connecting electrode pattern surrounds the first electrode pattern, and at least two of the plurality of connecting electrodes are in block shapes separated from each other.
  • the display substrate provided by an embodiment of the present disclosure further includes a base substrate and a first insulating layer on the base substrate, and the first electrode pattern and the connecting electrode pattern are located far away from the first insulating layer.
  • One side of the base substrate is in contact with the first insulating layer.
  • a portion of the first insulating layer located between adjacent first electrodes has a first groove
  • a portion of the first insulating layer located between adjacent connecting electrodes The part has a second groove, and the size of the first groove and the second groove in a direction perpendicular to the base substrate are equal.
  • the shape of the connecting electrode is the same as the shape of the first electrode.
  • the pattern density of the connection electrode pattern is the same as the pattern density of the first electrode pattern.
  • the display substrate provided by an embodiment of the present disclosure further includes a first dummy electrode pattern.
  • the first dummy electrode pattern includes a plurality of first dummy electrodes; the first dummy electrode pattern is located between the connection electrode pattern and the first dummy electrode. Between the electrode patterns, the shape of the first dummy electrode is the same as the shape of the first electrode.
  • the pattern density of the first dummy electrode pattern is the same as the pattern density of the first electrode pattern.
  • a portion of the first insulating layer that overlaps the plurality of first dummy electrodes in a direction perpendicular to the base substrate is not provided with via holes.
  • the display substrate provided by an embodiment of the present disclosure further includes a second dummy electrode pattern, and the second dummy electrode pattern includes a plurality of second dummy electrodes; the second dummy electrode pattern is located at a distance from the first dummy electrode pattern to the connecting electrode pattern.
  • the shape of the second dummy electrode is the same as the shape of the first electrode.
  • the pattern density of the second dummy electrode pattern is the same as the pattern density of the first electrode pattern.
  • a portion of the first insulating layer that overlaps the plurality of second dummy electrodes in a direction perpendicular to the base substrate is not provided with via holes.
  • the display substrate provided by an embodiment of the present disclosure further includes an insulating filling layer covering the plurality of first dummy electrodes, and the plurality of first dummy electrodes and the insulating filling layer constitute a first filling layer,
  • the first electrode pattern includes a first electrode close to the edge of the connection electrode, and the insulating filling layer is in contact with the connection electrode and the edge first electrode, respectively.
  • the second electrode is in contact with the insulating filling layer.
  • the edge first electrode and the plurality of first dummy electrodes are insulated from each other.
  • the display substrate provided by an embodiment of the present disclosure further includes a pixel defining layer, the pixel defining layer includes a plurality of pixel defining portions, and the pixel defining portions are located between adjacent first electrodes.
  • the insulating filling layer and the pixel definition layer are located in the same layer.
  • the display substrate provided by an embodiment of the present disclosure further includes a second filling layer, the second filling layer includes at least one second filling portion, and the second filling portion is located between adjacent connecting electrodes.
  • the second filling portions are respectively in contact with the adjacent connecting electrodes.
  • the second filling layer includes an insulating layer.
  • the second filling layer and the insulating filling layer are located in the same layer.
  • the insulating filling layer includes a plurality of insulating filling portions, and the insulating filling portions are located between adjacent first dummy electrodes.
  • the light-emitting function layer is in contact with the first filling layer.
  • the light-emitting function layer is in contact with a part of the first filling layer.
  • the connecting electrode pattern has a ring shape.
  • the first electrode is an anode of a light-emitting element
  • the second electrode is a cathode of the light-emitting element
  • the base substrate includes a silicon wafer.
  • At least one embodiment of the present disclosure further provides a display device including any display substrate in the second aspect described above.
  • At least one embodiment of the present disclosure further provides a manufacturing method of a display substrate, including: forming a first electrode pattern, the first electrode pattern is located in a display area of the display substrate and includes a plurality of first electrodes spaced apart from each other, The first electrode is configured to receive a pixel driving signal; forming a connecting electrode pattern, the connecting electrode pattern is located in the peripheral area of the display substrate, and includes a plurality of connecting electrodes; forming a second electrode, the second electrode is located The display area and the peripheral area are connected to the connection electrode pattern, the second electrode and the first electrode pattern are spaced apart from each other, and the second electrode is configured to receive a first power signal; and forming A light-emitting functional layer, the light-emitting functional layer is located between the first electrode pattern and the second electrode; the connecting electrode pattern surrounds the first electrode pattern, and at least two of the plurality of connecting electrodes are mutually Spaced blocks.
  • the pattern density of the connecting electrode pattern is the same as the pattern density of the first electrode pattern.
  • the manufacturing method of the display substrate provided by an embodiment of the present disclosure further includes: forming a first dummy electrode pattern, the first dummy electrode pattern includes a plurality of first dummy electrodes; the first dummy electrode pattern is located in the connecting electrode pattern And the first electrode pattern; the pattern density of the first dummy electrode pattern is the same as the pattern density of the first electrode pattern.
  • the manufacturing method of the display substrate provided by an embodiment of the present disclosure further includes forming an insulating filling layer, wherein the insulating filling layer covers the plurality of first dummy electrodes, the plurality of first dummy electrodes and the insulating filling layer A first filling layer is formed, the first electrode pattern includes a first electrode close to the edge of the connecting electrode, and the insulating filling layer is in contact with the connecting electrode and the edge first electrode, respectively.
  • the manufacturing method of the display substrate provided by an embodiment of the present disclosure further includes: forming a second dummy electrode pattern, wherein the second dummy electrode pattern includes a plurality of second dummy electrodes; the second dummy electrode pattern is located at the connection On the side of the electrode pattern away from the first electrode pattern, the pattern density of the second dummy electrode pattern is the same as the pattern density of the first electrode pattern.
  • the manufacturing method of the display substrate provided by an embodiment of the present disclosure further includes: forming a pixel defining layer, wherein the pixel defining layer includes a plurality of pixel defining portions, and the pixel defining portions are located between adjacent first electrodes.
  • the manufacturing method of the display substrate provided by an embodiment of the present disclosure further includes: forming a second filling layer, wherein the second filling layer includes at least one second filling portion, and the second filling portion is located between adjacent connecting electrodes .
  • the manufacturing method of the display substrate provided by an embodiment of the present disclosure further includes forming a first dummy electrode pattern, a second dummy electrode pattern, a pixel definition layer, an insulating filling layer, and a second filling layer;
  • the first dummy electrode pattern includes a plurality of A first dummy electrode, the first dummy electrode pattern is located between the connection electrode pattern and the first electrode pattern;
  • the second dummy electrode pattern includes a plurality of second dummy electrodes;
  • the second dummy electrode pattern Located on a side of the connecting electrode pattern away from the first electrode pattern, the pixel defining layer includes a plurality of pixel defining portions, and the pixel defining portions are located between adjacent first electrodes;
  • the insulating filling layer covers The plurality of first dummy electrodes;
  • the second filling layer includes at least one second filling portion, the second filling portion is located between adjacent connection electrodes; the same patterning process is used to form the pixel definition layer, the An insulating
  • the insulating filling layer includes a plurality of insulating filling portions, and the insulating filling portions are located between adjacent first dummy electrodes.
  • At least one embodiment of the present disclosure further provides a display substrate, including: a first electrode pattern, a connecting electrode pattern, a second electrode, a light-emitting function layer, and a first dummy electrode pattern; the first electrode pattern is located on the display
  • the display area of the substrate includes a plurality of first electrodes spaced apart from each other, the first electrodes are configured to receive pixel driving signals;
  • the connection electrode pattern is located in the peripheral area of the display substrate;
  • the second electrodes are located in the display area and The peripheral area is connected to the connecting electrode pattern, the second electrode and the first electrode pattern are spaced apart from each other, the second electrode is configured to receive a first power signal;
  • the light emitting function layer is located on the first electrode pattern.
  • the first dummy electrode pattern includes a plurality of first dummy electrodes, the connection electrode pattern surrounds the first electrode pattern, and the first dummy electrode pattern is located on the connection electrode Between the pattern and the first electrode pattern, at least two of the plurality of first dummy electrodes are in a block shape spaced apart from each other.
  • the display substrate provided by an embodiment of the present disclosure further includes a base substrate and a first insulating layer on the base substrate, and the first electrode pattern, the connection electrode pattern, and the first dummy electrode pattern are located on the base substrate.
  • the side of the first insulating layer away from the base substrate is in contact with the first insulating layer.
  • a portion of the first insulating layer that overlaps the plurality of first dummy electrodes in a direction perpendicular to the base substrate is not provided with via holes.
  • the first dummy electrode floats.
  • connection electrode pattern includes a plurality of connection electrodes, and the connection electrodes are in a block shape.
  • the shape of the connecting electrode is the same as the shape of the first electrode
  • the shape of the first dummy electrode is the same as the shape of the first electrode
  • the pattern density of the connecting electrode pattern is the same as the pattern density of the first electrode pattern
  • the pattern density of the first dummy electrode pattern is the same as the pattern density of the first electrode pattern.
  • the pattern density is the same.
  • the display substrate provided in an embodiment of the present disclosure further includes a second dummy electrode pattern, and the second dummy electrode pattern includes a plurality of second dummy electrodes; the second dummy electrode pattern is located far from the connecting electrode pattern. One side of the first electrode pattern.
  • a portion of the first insulating layer that overlaps the plurality of second dummy electrodes in a direction perpendicular to the base substrate is not provided with via holes.
  • the second dummy electrode has a block shape, and the shape of the second dummy electrode is the same as the shape of the first electrode.
  • the pattern density of the second dummy electrode pattern is the same as the pattern density of the first electrode pattern.
  • At least one of the portion of the first insulating layer between adjacent first electrodes and the portion of the first insulating layer between adjacent connecting electrodes has Groove.
  • the display substrate provided by an embodiment of the present disclosure further includes an insulating filling layer covering the plurality of first dummy electrodes, and the plurality of first dummy electrodes and the insulating filling layer constitute a first filling layer,
  • the first electrode pattern includes a first electrode close to the edge of the connection electrode, and the insulating filling layer is in contact with the connection electrode and the edge first electrode, respectively.
  • the second electrode is in contact with the insulating filling layer.
  • the edge first electrode and the plurality of first dummy electrodes are insulated from each other.
  • the display substrate provided by an embodiment of the present disclosure further includes a pixel definition layer.
  • the pixel definition layer includes a plurality of pixel definition portions, and the pixel definition portions are located between adjacent first electrodes.
  • the insulating filling layer and the pixel definition layer are located in the same layer.
  • the display substrate provided by an embodiment of the present disclosure further includes a second filling layer, the second filling layer includes at least one second filling portion, and the second filling portion is located between adjacent connecting electrodes.
  • the second filling portions are respectively in contact with the adjacent connecting electrodes.
  • the second filling layer includes an insulating layer.
  • the second filling layer and the insulating filling layer are located in the same layer.
  • the display substrate provided by an embodiment of the present disclosure further includes a sensor electrode pattern, the sensor electrode pattern includes a plurality of sensor electrodes; the sensor electrode is in a block shape, and the sensor electrode is configured to receive a detection driving signal.
  • the shape of the sensor electrode and the shape of the first electrode are the same.
  • the pattern density of the sensor electrode pattern is the same as the pattern density of the first electrode pattern.
  • the display substrate provided in an embodiment of the present disclosure further includes a third filling layer, the third filling layer includes a plurality of third filling portions, and the third filling portions are located at adjacent sensor electrodes and adjacent sensor electrodes. And at least one of the first dummy electrodes.
  • the light-emitting function layer is in contact with the first filling layer.
  • the light-emitting function layer is in contact with a part of the first filling layer.
  • the connecting electrode pattern has a ring shape.
  • the first electrode is an anode of a light-emitting element
  • the second electrode is a cathode of the light-emitting element
  • the base substrate includes a silicon wafer.
  • At least one embodiment of the present disclosure further provides a display device including any display substrate described in the third aspect.
  • At least one embodiment of the present disclosure further provides a manufacturing method of a display substrate, including: forming a first electrode pattern, the first electrode pattern is located in a display area of the display substrate and includes a plurality of first electrodes spaced apart from each other, The first electrode is configured to receive a pixel driving signal; forming a connecting electrode pattern, the connecting electrode pattern is located in the peripheral area of the display substrate; forming a second electrode, the second electrode is located in the display area and the The peripheral area is connected to the connecting electrode pattern, the second electrode and the first electrode pattern are spaced apart from each other, and the second electrode is configured to receive a first power signal; forming a light-emitting function layer, the light-emitting function A layer is located between the first electrode pattern and the second electrode; and a first dummy electrode pattern is formed.
  • the first dummy electrode pattern includes a plurality of first dummy electrodes; and the connection electrode pattern surrounds the first dummy electrode.
  • An electrode pattern, the first dummy electrode pattern is located between the connection electrode pattern and the first electrode pattern, and at least two of the plurality of first dummy electrodes are in a block shape spaced apart from each other.
  • the first dummy electrode is in a block shape, and the pattern density of the first dummy electrode pattern is the same as the pattern density of the first electrode pattern.
  • the manufacturing method of the display substrate provided by an embodiment of the present disclosure further includes: forming a second dummy electrode pattern, the second dummy electrode pattern includes a plurality of second dummy electrodes; the second dummy electrode pattern is located in the connecting electrode pattern On the side far away from the first electrode pattern, the pattern density of the second dummy electrode pattern is the same as the pattern density of the first electrode pattern.
  • the manufacturing method of the display substrate provided by an embodiment of the present disclosure further includes forming an insulating filling layer, wherein the insulating filling layer covers the plurality of first dummy electrodes, the plurality of first dummy electrodes and the insulating filling layer A first filling layer is formed, the first electrode pattern includes a first electrode close to the edge of the connecting electrode, and the insulating filling layer is in contact with the connecting electrode and the edge first electrode, respectively.
  • the manufacturing method of the display substrate provided by an embodiment of the present disclosure further includes: forming a sensor electrode pattern, wherein the sensor electrode pattern includes a plurality of sensor electrodes; the sensor electrode is in a block shape, and the pattern density of the sensor electrode pattern is equal to The pattern density of the first electrode patterns is the same.
  • the manufacturing method of the display substrate provided by an embodiment of the present disclosure further includes: forming a pixel defining layer, wherein the pixel defining layer includes a plurality of pixel defining portions, and the pixel defining portions are located between adjacent first electrodes.
  • the manufacturing method of the display substrate provided by an embodiment of the present disclosure further includes: forming a second filling layer, wherein the second filling layer includes at least one second filling portion, and the second filling portion is located between adjacent connecting electrodes .
  • the manufacturing method of the display substrate provided by an embodiment of the present disclosure further includes: forming a third filling layer, the third filling layer includes a plurality of third filling parts, and the third filling parts are located at adjacent sensor electrodes and adjacent sensor electrodes. Between the sensor electrode and at least one of the first dummy electrodes.
  • the manufacturing method of the display substrate provided by an embodiment of the present disclosure further includes forming a second dummy electrode pattern, a sensor electrode pattern, a pixel definition layer, an insulating filling layer, a second filling layer, and a third filling layer;
  • the sensor electrode pattern includes multiple Sensor electrodes;
  • the second dummy electrode pattern includes a plurality of second dummy electrodes;
  • the second dummy electrode pattern is located on a side of the connecting electrode pattern away from the first electrode pattern;
  • the pixel definition layer includes A plurality of pixel defining parts, the pixel defining part is located between adjacent first electrodes;
  • the insulating filling layer covers the plurality of first dummy electrodes;
  • the second filling layer includes at least one second filling part, so The second filling portion is located between adjacent connecting electrodes;
  • the third filling layer includes a plurality of third filling portions, and the third filling portions are located between adjacent sensor electrodes, adjacent sensor electrodes, and first Between at least one of a
  • the insulating filling layer includes a plurality of insulating filling portions, and the insulating filling portions are located between adjacent first dummy electrodes.
  • FIG. 1 is a schematic plan view of an organic light emitting diode display substrate
  • FIGS. 2A to 2D are schematic diagrams of a manufacturing method of a first electrode pattern in an organic light emitting diode display substrate
  • FIG. 3 is a schematic plan view of an organic light emitting diode display substrate
  • FIG. 4 is a schematic cross-sectional view of an organic light emitting diode display substrate
  • 5A is a cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • 5B is a cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • 6A is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • 6B is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 7A is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 7B is a schematic cross-sectional view of a display substrate provided by an embodiment of the disclosure.
  • FIG. 8A is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 8B is a cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 9 is a top view of a first electrode pattern, a connecting electrode pattern, and a conductive filling part in a display substrate provided by an embodiment of the present disclosure.
  • FIG. 10 is a top view of a first filling layer, a second filling layer, and a pixel definition layer in a display substrate provided by an embodiment of the present disclosure
  • FIG. 11 is a schematic diagram of area division of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic top view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 13A is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 13B is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • 14A is a cross-sectional view of a display substrate provided by an embodiment of the disclosure.
  • 14B is a cross-sectional view of a display substrate provided by an embodiment of the disclosure.
  • FIG. 15 is a top view of an insulating filling layer, a second filling layer, and a pixel definition layer in a display substrate provided by an embodiment of the present disclosure
  • FIG. 16 is a schematic diagram of area division of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 17A is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • 17B is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 18 is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • 19 is a top view of a structure formed by patterning a pixel defining film in a display substrate provided by an embodiment of the present disclosure
  • FIG. 20 is a cross-sectional view of a display substrate provided by an embodiment of the disclosure.
  • FIG. 21 is a schematic diagram of a conductive film formed in a manufacturing method of a display substrate provided by an embodiment of the disclosure.
  • FIG. 22 is a schematic diagram of a pixel definition film formed in a method for manufacturing a display substrate provided by an embodiment of the disclosure.
  • FIG. 23 is a schematic diagram of a circuit principle of a silicon-based organic light-emitting display panel provided by some embodiments of the present disclosure.
  • the manufacturing process of the first electrode usually includes: forming a conductive layer on the base substrate by a sputtering process; forming a photoresist pattern on the side of the conductive layer away from the base substrate; Using the photoresist pattern as a mask, the conductive layer is etched to form a first electrode pattern, and the photoresist pattern is removed.
  • the material of the conductive layer includes indium tin oxide, but is not limited thereto.
  • the inventor of the present application found that in the process of etching the conductive layer, the first electrode pattern needs to be formed in the display area of the organic light emitting diode display device, and the conductive layer in the peripheral area of the organic light emitting diode display device is electrically conductive.
  • the layer part needs to be completely or partially removed, and the pattern density of the display area and the peripheral area are different, resulting in a larger difference in the amount of conductive material that needs to be etched away in the display area and the peripheral area in a unit area under the same dry etching process. Big.
  • the selectivity of the dry etching process is poor.
  • it is easy to cause the process film thickness and size uniformity of the final first electrode pattern to be difficult to control and on the other hand, it is easy to cause over-etching of the insulating layer under the first electrode pattern. phenomenon.
  • FIG. 1 is a schematic plan view of an organic light emitting diode display substrate.
  • the organic light emitting diode display substrate 10 includes a display area 11 and a peripheral area 12 surrounding the display area 11; the display area 11 is provided with a first electrode pattern 13; the first electrode pattern 13 includes a plurality of first electrodes 130 , Thereby driving the light emitting layer (not shown) in the light emitting diode display substrate 10 to emit light.
  • FIGS. 2A-2D are schematic diagrams of a manufacturing method of a first electrode pattern in an organic light emitting diode display substrate.
  • an insulating layer 15 is formed on the base substrate 16, and a conductive layer 17 is formed on the side of the insulating layer 15 away from the base substrate 16.
  • the conductive layer 17 is away from the insulating layer 15
  • the photoresist pattern 18 is formed on one side of the surface; as shown in FIG. 2C, the conductive layer 17 is etched using the photoresist pattern 18 as a mask to form the first electrode pattern 13; as shown in FIG. 2D, the photoresist is stripped Pattern 18.
  • the organic light emitting diode display substrate includes a display area and a peripheral area.
  • the portion of the conductive layer located in the display area is dry-etched to form a first electrode pattern, and the portion of the conductive layer located in the peripheral area The part is completely removed, which results in a large difference in the amount of conductive material that needs to be etched away in the display area and the peripheral area in a unit area under the same dry etching process, resulting in uneven etching.
  • the etching parameters such as dry etching gas concentration, flow rate, etc.
  • the portion of the conductive layer located in the display area is prone to over-etching, resulting in the formation of The process film thickness and size uniformity of the first electrode pattern are difficult to control.
  • the poor selectivity of the dry etching process it is easy to cause the insulating layer under the first electrode pattern to be etched, causing various defects .
  • the pattern density of the conductive pattern in the peripheral area is different from the pattern density of the first electrode pattern in the display area, and the pattern density of the peripheral area and the display area are very different.
  • the pattern density of the conductive patterns in the peripheral area is less than the pattern density of the first electrode patterns in the display area, and the peripheral area may not be provided with conductive patterns or be provided with a small amount of conductive patterns.
  • the concentration of active groups, sidewall protective substances, etc. near the surface of the conductive layer 17 in the display area and the peripheral area is uniformly distributed. Therefore, the activity per unit area of the area with high pattern density
  • the groups and sidewall protection substances have fewer active groups and sidewall protection substances per unit area than the areas with low pattern density.
  • the etching depth of the areas with high pattern density is less than the etching depth of the areas with low pattern density.
  • This is the so-called loading effect, which causes the etching depth of the peripheral area to be greater than the etching depth of the display area, so that the portion of the conductive layer 17 located in the peripheral area and the portion of the conductive layer 17 located below the display area.
  • the amount of loss (Loss) of the insulating layer material There is a big difference in the amount of loss (Loss) of the insulating layer material.
  • the loss of the portion of the insulating layer 15 located in the peripheral region 12 is large, it is easy to cause a short circuit or poor contact of the subsequent film layers.
  • FIG. 3 is a schematic plan view of an organic light emitting diode display substrate.
  • the peripheral area 12 of the display substrate shown in FIG. 3 includes the connection electrode area 12a, and thus, the peripheral area 12 includes three areas: the connection electrode area 12a, the first dummy area 121, and the second dummy area.
  • Two dummy area 122 The first dummy area 121 is located between the connection electrode area 12 a and the display area 11, and the second dummy area 122 is located on the side of the connection electrode area 12 a away from the display area 11.
  • the second dummy area 122 is located on the side of the connection electrode area 12 a away from the first dummy area 121.
  • the provision of the first dummy area 121 can avoid short circuiting of the components in the display area and the connecting electrode area 12a that need to be insulated from each other, and the provision of the second dummy area 122 can facilitate the packaging of the display substrate and improve the packaging effect.
  • FIG. 4 is a schematic cross-sectional view of an organic light emitting diode display substrate.
  • FIG. 4 may be a cross-sectional view of FIG. 3.
  • an insulating layer 01 is provided on the base substrate 16, and a via 011 and a via 012 are provided in the insulating layer 01.
  • the via 011 and the via 012 are filled with conductive materials to form connectors, respectively. Including metals such as tungsten, but not limited to this.
  • the connecting electrode 14 and the first electrode pattern 13 on the same layer.
  • the first electrode pattern 13 includes a plurality of first electrodes 130.
  • the first electrode 130 is connected to a lower element such as the drain of a thin film transistor (not shown in the figure) through a connector located in the via hole 011, and the connecting electrode 14 is connected to the lower connecting line ( (Not shown in the figure) connected.
  • the pixel defining layer 01 is formed after the connecting electrode 14 and the first electrode pattern 13 are formed.
  • the pixel defining layer 01 includes a plurality of pixel defining portions 010, and a plurality of pixels are arranged between adjacent first electrodes 130.
  • the plurality of pixel defining parts 010 may be connected to each other and formed integrally, but is not limited thereto.
  • the pixel definition layer 01 may include a plurality of hollow areas to respectively expose the plurality of first electrodes 130.
  • the pixel definition layer 01 is configured to define a plurality of sub-pixels. For example, each hollow area corresponds to a sub-pixel.
  • each first electrode 130 corresponds to one sub-pixel.
  • FIG. 4 after forming the pixel defining layer 01, the light emitting function layer 03 is formed, and the light emitting function layer 03 covers the first electrode pattern 13 and the pixel defining layer 01.
  • the second electrode 04 is formed.
  • the second electrode 04 and the first electrode pattern 13 are spaced apart from each other to prevent the second electrode 04 and the first electrode 130 from being directly connected. 04 is connected to the connecting electrode 14.
  • the first electrode 130 may be made of a transparent conductive material, for example, the transparent conductive material includes indium tin oxide, but is not limited thereto.
  • the connecting electrode and the first electrode pattern are formed in the same layer, the part of the conductive layer located in the first dummy area 121 and the part of the conductive layer located in the second dummy area 122 need to be etched in one piece, and there is also uneven etching in the process. Sex.
  • the second electrode 04 has a large height drop, which is likely to cause the second electrode to break and reduce the reliability of the connection between the second electrode and the connecting electrode. Sex.
  • a common display substrate only has a pixel definition layer in the display area, and there is no pixel definition layer material in the peripheral area (non-pixel area), which results in uneven contact between the second electrode and the connecting electrode.
  • the second electrode can be made of metal.
  • the second electrode can be made of at least one metal material such as magnesium and silver, but it is not limited to this, and can be determined according to needs.
  • a display substrate, a manufacturing method thereof, and a display device are provided.
  • the embodiments of the present disclosure provide the first filling layer 104a to reduce the height difference of the second electrode 106 and/or improve the etching uniformity.
  • FIG. 5A is a cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate 100a includes a first electrode pattern 103, a connection electrode pattern 103a, a second electrode 106, and a first filling layer 104a.
  • the connection electrode pattern 103a surrounds the first electrode pattern 103 (see FIG. 3).
  • the second electrode 106 is connected to the connection electrode pattern 103a.
  • the second electrode 106 and the first electrode pattern 103 are spaced apart from each other.
  • the second electrode 106 is configured to receive the first power signal.
  • the first filling layer 104a is located between the connection electrode pattern 103a and the first electrode pattern 103.
  • the second electrode 106 is not in contact with the first electrode pattern 103.
  • the display substrate includes a base substrate 101.
  • the second electrode 106 and the first electrode pattern 103 are spaced apart from each other in a direction parallel to the base substrate 101, and the second electrode 106 and the first electrode pattern 103 are spaced apart from each other in a direction perpendicular to the base substrate 101.
  • the connection electrode pattern 103a and the first electrode pattern 103 are spaced apart from each other in a direction parallel to the base substrate 101.
  • the display substrate 100 a includes a display area 11 and a peripheral area 12, and the peripheral area 12 surrounds the display area 11.
  • the first electrode pattern 103 is located in the display area 11 of the display substrate; the connecting electrode pattern 103 a is located in the peripheral area 12 of the display substrate, and the second electrode 106 is located in the display area 11 and the peripheral area 12.
  • the second electrode 106 has a block shape and extends from the display area 11 to the peripheral area 12.
  • the height difference of the second electrode 106 can be reduced, and the connection reliability of the second electrode 106 and the connecting electrode pattern 103a can be improved.
  • the first electrode pattern 103 includes a plurality of first electrodes 1030 spaced apart from each other, and the first electrodes 1030 are configured to receive pixel driving signals.
  • the first electrode pattern 103 includes an edge first electrode 103e, the edge first electrode 103e is close to the connection electrode pattern 103a, and the first filling layer 104a is in contact with the connection electrode pattern 103a and the edge first electrode 103e, for example, the first filling layer 104a is The insulating layer facilitates the separation of the edge first electrode 103e and the second electrode 106 from each other.
  • the edge first electrode 103e is the first electrode 1030 closest to the connection electrode pattern 103a.
  • the side surface of the first filling layer 104a is in contact with the side surface of the connecting electrode pattern 103a and the side surface of the edge first electrode 103e, respectively.
  • the second electrode 106 in the display substrate provided by an embodiment of the present disclosure, in order to reduce the height difference of the second electrode, the second electrode 106 is in contact with the first filling layer 104a.
  • FIG. 5B is a cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • the difference between the display substrate 100aa shown in FIG. 5B and the display substrate 100a shown in FIG. 5A is that the first insulating layer 102 of the display substrate 100aa is provided with a groove G.
  • the groove G is formed in the process of etching the conductive film, and the arrangement of the groove G can facilitate the distance between adjacent first electrodes and improve the stability of the etching process.
  • the groove G located between the edge first electrode 103e and the connection electrode pattern 103a in the first insulating layer 102 has a larger size in the direction perpendicular to the base substrate 101 than in the first insulating layer 102.
  • FIG. 6A is a schematic cross-sectional view of a display substrate provided by an embodiment of the disclosure.
  • the difference between the display substrate 100b and the display substrate 100a is that the connection electrode pattern 103a includes a plurality of connection electrodes 103a0.
  • the connection electrode pattern 103a includes an edge connection electrode 103ae close to the first electrode pattern 103, and the side surface of the first filling layer 104a is in contact with the side surface of the edge connection electrode 103ae and the side surface of the edge first electrode 103e, respectively.
  • the edge connection electrode 103ae is the connection electrode 103a0 closest to the first electrode pattern 103.
  • FIG. 6B is a cross-sectional view of a display substrate provided by an embodiment of the disclosure.
  • the display substrate 100bb shown in FIG. 6B is different in that the first insulating layer 102 of the display substrate 100bb is provided with a groove G.
  • the groove G in the first insulating layer 102 between the edge first electrode 103e and the connecting electrode 103a0 near the edge first electrode 103e has a larger size in the direction perpendicular to the base substrate 101 than the first The size of the groove G in the insulating layer 102 between the adjacent first electrodes 1030 in the direction perpendicular to the base substrate 101.
  • a part of the first filling layer 104a is filled in the groove G between the edge first electrode 103e and the connection electrode pattern 103a.
  • FIG. 7A is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • the difference between the display substrate 100c and the display substrate 100a is that the first filling layer 104a includes at least one conductive filling part 103d1 and at least one insulating filling part 104a0, and the edge first electrode 103e is in contact with the insulating filling part 104a0.
  • the edge first electrode 103e and the plurality of conductive filling portions 103d1 are insulated from each other.
  • FIG. 7A shows three insulating filling portions 104a0 and two conductive filling portions 103d1.
  • the number of insulating filling portions 104a0 and the number of conductive filling portions 103d1 are not limited to those shown in the figure, and can be determined according to needs.
  • the pattern density of the plurality of conductive filling portions 103d1 is the same as the pattern density of the first electrode pattern 103, but it is not limited thereto.
  • the first filling layer 104a includes a plurality of conductive filling parts 103d1 and a plurality of insulating filling parts 104a0, a plurality of conductive filling parts 103d1 and a plurality of insulating filling parts.
  • 104a0 is set alternately.
  • the insulating filling portion 104a0 is located in the adjacent conductive filling portion 103d1.
  • FIG. 7B is a cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • the difference between the display substrate 100cc shown in FIG. 7B and the display substrate 100c shown in FIG. 7A is that a groove G is provided in the first insulating layer 102 of the display substrate 100cc. As shown in FIG.
  • the size of the groove G in the first insulating layer 102 between the edge first electrode 103e and the connecting electrode 103a0 near the edge first electrode 103e in the direction perpendicular to the base substrate 101 is equal to the first
  • the size of G in the direction perpendicular to the base substrate 101 is equal to the size of the groove G in the first insulating layer 102 between adjacent first electrodes 1030 in the direction perpendicular to the base substrate 101.
  • a part of the insulating filling portion 104a0 is filled in the groove G in the first insulating layer 102 between the adjacent connecting electrodes 103a0.
  • a part of the insulating filling portion 104a0 is filled in the groove G in the first insulating layer 102 between the connection electrode pattern 103a and the conductive filling portion 103d1.
  • a part of the insulating filling portion 104a0 is filled in the groove G in the first insulating layer 102 between the edge first electrode 103e and the conductive filling portion 103d1.
  • FIG. 8A is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • the difference between the display substrate 100d and the display substrate 100c is that the connection electrode pattern 103a includes a plurality of connection electrodes 103a0, the display substrate 100d further includes a second filling layer 104b, and the second filling layer 104b includes at least one second filling layer.
  • the second filling portion 104b0 is located between the adjacent connecting electrodes 103a0.
  • the second filling portion 104b0 is in contact with the adjacent connection electrode 103a0, respectively.
  • the pattern density of the plurality of conductive filling portions 103d1 the pattern density of the first electrode pattern 103, and the pattern density of the plurality of connection electrodes 103a0 are the same, but not limited thereto.
  • FIG. 8B is a cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate 100dd shown in FIG. 8B is different in that a groove G is provided in the first insulating layer 102 of the display substrate 100dd.
  • the first insulating layer 102 includes a plurality of grooves G, and the dimensions of the plurality of grooves G in the direction perpendicular to the base substrate 101 are all the same. All the grooves G in the first insulating layer 102 have the same size in the direction perpendicular to the base substrate 101.
  • the size of the groove G in the first insulating layer 102 between the edge first electrode 103e and the connecting electrode 103a0 near the edge first electrode 103e in the direction perpendicular to the base substrate 101 is equal to that of the first insulating layer 102
  • the dimension of the groove G between adjacent first electrodes 1030 in the direction perpendicular to the base substrate 101, and the groove G between adjacent conductive filling portions 103d1 in the first insulating layer 102 is vertical
  • the dimension in the direction of the base substrate 101 is equal to the dimension of the groove G in the first insulating layer 102 between adjacent first electrodes 1030 in the direction perpendicular to the base substrate 101.
  • the dimension of the groove G located between the adjacent first connection electrodes 103a0 in the direction perpendicular to the base substrate 101 is equal to that of the groove G located between the adjacent first electrodes 1030 in the first insulating layer 102. Dimension in the direction of the base substrate 101.
  • the second filling layer 104b is an insulating layer.
  • the second filling layer 104b and the first filling layer 104a are located in the same layer, and can be formed by the same film layer using the same patterning process to save manufacturing process.
  • the pattern density of the first electrode pattern 103, the pattern density of the plurality of conductive filling portions 103d1, and the pattern density of the connecting electrode pattern 103a are all the same, so that the etching uniformity can be improved, and the second electrode can be improved.
  • the connection reliability between 106 and the connection electrode pattern 103a improves the performance of the display substrate.
  • the display substrate further includes a light-emitting function layer 105, which is located between the first electrode pattern 103 and the second electrode 106, and has a light-emitting function.
  • the layer 105 and the first filling layer 104a are different layers.
  • the light-emitting function layer 105 is in contact with the first filling layer 104a.
  • the first electrode pattern 103 and the second electrode 106 are spaced apart from each other by the first filling layer 104a and the light emitting function layer 105.
  • the light-emitting function layer 105 is in contact with a part of the first filling layer 104a.
  • the display substrate further includes a pixel definition layer 104, and the pixel definition layer 104 includes a plurality of pixel definition portions 1040; Each is located between adjacent first electrodes 1030.
  • the plurality of first electrodes 1030 are spaced apart from each other.
  • the plurality of first electrodes 1030 are spaced apart from each other in a direction parallel to the base substrate 101.
  • the plurality of first electrodes 1030 are independent of each other and separated from each other.
  • the first electrode pattern 103 and the connecting electrode pattern 103a are located on the same layer, and can be formed by the same film layer using the same patterning process to save manufacturing process.
  • the display substrate further includes a base substrate 101 and a first insulating layer 102 on the base substrate 101.
  • the first insulating layer 102 includes a first via V1 and a second via V2.
  • the first via hole V1 and the second via hole V2 are filled with a conductive material to respectively form a connection member.
  • the conductive material includes metal such as tungsten, but is not limited thereto.
  • On the first insulating layer 102 are the connection electrode pattern 103a and the first electrode pattern 103 located in the same layer.
  • the first electrode pattern 103 includes a plurality of first electrodes 1030.
  • the first electrode 1030 is connected to the underlying element such as the drain of a thin film transistor (not shown in the figure) through a connector located in the second via hole V2, and the connection electrode 103a0 or the connection electrode pattern 103a is located in the first via hole V1.
  • the connecting piece is connected to the lower connecting line (not shown in the figure).
  • the first electrode pattern 103 and the connection electrode pattern 103a are located on the side of the first insulating layer 102 away from the base substrate 101 and are in contact with the first insulating layer 102, respectively.
  • a portion of the first insulating layer 102 located between the first electrode pattern 103 and the connecting electrode pattern 103a has a groove, and the first filling layer 104a is at least partially located in the groove G.
  • connection electrode pattern 103a and the first electrode pattern 103 are in contact with the first insulating layer 102, respectively.
  • the peripheral area 12 includes a first dummy area 121 and a second dummy area 122.
  • the first dummy area 121 is located between the connection electrode area 12 a and the display area 11, and the second dummy area 122 is located on the side of the connection electrode area 12 a away from the display area 11.
  • the orthographic projection of the first filling layer 104a on the base substrate 101 and the orthographic projection of the light-emitting function layer 105 on the base substrate 101 partially overlap.
  • the first filling layer 104a and the pixel definition layer 104 are located in the same layer, and can be formed by the same film layer using the same patterning process to save manufacturing process.
  • At least one insulating filling portion 104a0 and the pixel definition layer 104 are located in the same layer, and can be formed by the same film layer using the same patterning process to save manufacturing process.
  • the first electrode pattern 103, the at least one conductive filling portion 103d1, and the connecting electrode pattern 103a are located on the same layer, and the same film layer can use the same patterning process Formed to save manufacturing process.
  • the second filling layer 104b, the first filling layer 104a and the pixel definition layer 104 are located in the same layer, and can be formed by the same film layer using the same patterning process to save manufacturing process.
  • the multi-conductive filling portion 103d1, the connection electrode pattern 103a, and the first electrode pattern 103 are in contact with the first insulating layer 102, respectively.
  • the portion of the first insulating layer 102 directly below the conductive filling portion 103d1 is not provided with a via hole.
  • a first via hole V1 is provided in a portion of the first insulating layer 102 directly below the connection electrode 103a0.
  • a portion of the first insulating layer 102 directly below the first electrode 1030 is provided with a second via hole V2.
  • the first electrode in the first electrode pattern may be the anode of the light-emitting element
  • the second electrode may be the cathode of the light-emitting element.
  • the connecting electrode is connected to the second electrode and is spaced apart from the first electrode. That is, the two electrodes of the light-emitting element may be the first electrode and the second electrode, respectively.
  • the connecting electrode may have a ring shape. In this case, the connecting electrode may be referred to as a cathode ring.
  • the light-emitting element may include a light-emitting functional layer.
  • the light-emitting functional layer includes a light-emitting layer.
  • the light-emitting functional layer may also include at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer. Drive to emit light.
  • the light emitting element includes, for example, an organic light emitting diode, but is not limited thereto.
  • FIG. 9 is a top view of a first electrode pattern, a connecting electrode pattern, and a conductive filling part in a display substrate provided by an embodiment of the present disclosure.
  • the pattern density of the first electrode pattern 103, the pattern density of the connection electrode pattern 103, and the pattern density of the plurality of conductive filling portions 103d1 may be the same.
  • FIG. 9 shows the connection electrode 103a0, the conductive filling portion 103d1, and the first electrode 1030.
  • the shape of the first electrode 1030, the shape of the connecting electrode 1030, and the shape of the conductive filling portion 103d1 may be the same, but are not limited thereto.
  • each connection electrode 103a0 located in the connection electrode area 12a in FIG. 9 is externally connected. That is, each connection electrode 103a0 is connected to the connection member in the via hole directly below it.
  • Each connection electrode 103a0 is connected to a connector in a via hole in the first insulating layer that is in contact with the connection electrode 103a0.
  • the portion of the insulating layer in contact with each conductive filling portion 103d1 that is located below the conductive filling portion 103d1 is not provided with a via hole at the position corresponding to the conductive filling portion 103d1.
  • the connection electrode pattern 103a has a ring shape.
  • FIG. 10 is a top view of a first filling layer, a second filling layer and a pixel definition layer in a display substrate provided by an embodiment of the present disclosure.
  • FIG. 10 shows the first filling layer 104a, the second filling layer 104b, and the pixel defining layer 104.
  • the patterned structure of the pixel definition film includes a plurality of hollow areas HR.
  • the pixel definition film can cover the entire surface of the base substrate 101.
  • the plurality of hollow areas HR includes a hollow area HR0 located in the display area 11, a hollow area HR1 located in the first dummy area 121, and a hollow area HR2 located in the connection electrode area 12a.
  • the hollow area HR0 is configured to expose the first electrode 1030
  • the hollow area HR1 is configured to expose the conductive filling portion 103d1
  • the hollow area HR2 is configured to expose the connection electrode 103a0.
  • FIGS. 9 and 10 may correspond to the display panel shown in FIG. 8A, but are not limited thereto.
  • a second dummy electrode pattern may also be provided in the second dummy region 121 in FIGS. 9 and 10, the second dummy electrode pattern may include a plurality of second dummy electrodes, and the pattern density of the second dummy electrode pattern may be the same as that of the first electrode pattern. The density is the same.
  • At least one embodiment of the present disclosure further provides a display device including any display substrate in the first aspect described above.
  • the display device includes, for example, a micro OLED display device, but is not limited thereto.
  • At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate including: forming a first insulating layer on a base substrate; forming a first electrode pattern 103, the first electrode pattern 103 is located in the display area 11, and the first electrode pattern 103 It includes a plurality of first electrodes 1030 spaced apart from each other, the first electrodes 1030 are configured to receive pixel driving signals; a connection electrode pattern 103a is formed, and the connection electrode pattern 103a is located in the peripheral area 12 (the connection electrode area 12a in the peripheral area 12), and is connected The electrode pattern 103a surrounds the first electrode pattern 103; a second electrode 106 is formed, the second electrode 106 is located in the display area 11 and the peripheral area 12, the second electrode 106 is connected to the connection electrode pattern 103a, and the second electrode 106 is connected to the first electrode pattern 103 Are spaced apart from each other, the second electrodes are configured to receive the first power signal; form a light-emitting function layer 105, which is located between the first
  • the first electrode pattern includes an edge first electrode close to the connecting electrode pattern, and the first filling layer is in contact with the connecting electrode pattern and the edge first electrode, respectively.
  • the second electrode is in contact with the first filling layer.
  • the manufacturing method of the display substrate provided by an embodiment of the present disclosure further includes forming a pixel defining layer, wherein the pixel defining layer includes a plurality of pixel defining portions, and the first electrode pattern includes a plurality of first electrodes spaced apart from each other; the pixel defining portions are located in the same phase. Between adjacent first electrodes.
  • the pixel definition layer and the first filling layer are formed using the same patterning process, and the first electrode pattern and the connecting electrode pattern are formed using the same patterning process.
  • forming the first filling layer includes forming at least one conductive filling portion and forming at least one insulating filling portion.
  • the first electrode pattern, the connecting electrode pattern, and the at least one conductive filling portion adopt Are formed by the same patterning process; and the pixel definition layer and the at least one insulating filling part are formed by the same patterning process.
  • the manufacturing method of the display substrate provided by an embodiment of the present disclosure further includes forming a second filling layer, wherein the second filling layer includes at least one second filling portion, the connecting electrode pattern includes a plurality of connecting electrodes, and the second filling portion is located adjacent to each other. Between the connecting electrodes; the second filling layer is formed in the same patterning process for forming the pixel definition layer and the at least one insulating filling portion.
  • forming the first filling layer 104a includes forming at least one conductive filling part 103d1 and forming at least one insulating filling part 104a0, the edge first electrode 103e is in contact with the insulating filling part 104a0, The edge first electrode 103e and the conductive filling portion 103d1 are insulated from each other.
  • the edge first electrode 103e is close to the connection electrode pattern 103a.
  • the edge first electrode 103e is the first electrode 1030 closest to the connection electrode pattern 103a.
  • forming the first filling layer 104a includes forming at least one conductive filling portion 103d1 and forming at least one insulating filling portion 104a0.
  • forming the first filling layer 104a includes forming a plurality of conductive filling parts 103d1 and forming a plurality of insulating filling parts 104a0, a plurality of conductive filling parts 103d1 and a plurality of insulating filling parts 104a0 is set alternately.
  • the manufacturing method further includes forming a pixel defining layer 104.
  • the forming of the pixel defining layer 104 includes forming a plurality of pixel defining portions 1040, and the first electrode pattern 103 includes a plurality of pixels spaced apart from each other.
  • One first electrode 1030; each of the plurality of pixel defining portions 1040 is located between adjacent first electrodes 1030.
  • the first filling layer 104a or at least one insulating filling portion 104a0 and the pixel defining layer 104 are formed from the same film layer and using the same patterning process.
  • the first electrode pattern 103 and the connecting electrode pattern 103a are formed from the same film layer using the same patterning process.
  • the manufacturing method further includes forming a second filling layer 104b, forming the second filling layer 104b includes forming at least one second filling portion 104b0, and the connecting electrode pattern 103a includes a plurality of The connection electrode 103a0, and the second filling portion 104b0 is located between the adjacent connection electrodes 103a0.
  • the second filling portion 104b0 is in contact with the adjacent connecting electrode 103a0, respectively.
  • the second filling layer 104b is an insulating layer.
  • the second filling layer 104b and the first filling layer 104a are formed from the same film layer using the same patterning process.
  • the light-emitting function layer 105 is in contact with the first filling layer 104a.
  • the light-emitting function layer 105 is in contact with a part of the first filling layer 104a.
  • the manufacturing method of the display substrate includes: forming the first electrode pattern 103 located in the display area 11 of the display substrate; forming the connecting electrode pattern 103a located in the peripheral area 12 of the display substrate, and the peripheral area 12 surrounds the display area 11.
  • Forming a second electrode 106 the second electrode 106 is connected to the connecting electrode pattern 103a, the second electrode 106 is located in the display area 11 and the peripheral area 12, the second electrode 106 and the first electrode pattern 103 are spaced apart from each other; forming a light-emitting function layer 105, The light-emitting function layer 105 is located between the first electrode pattern 103 and the second electrode 106; and a first filling layer 104a is formed, and the first filling layer 104a is located between the connection electrode pattern 103a and the first electrode pattern 103.
  • any display substrate shown in FIGS. 5A to 8A can be formed.
  • the manufacturing method of the display substrate includes: forming a first insulating layer on a base substrate; forming a conductive film on the first insulating layer, and performing a patterning process on the conductive film to simultaneously form a first electrode pattern 103 and the connection electrode pattern 103a; the pixel definition film is formed on the first electrode pattern 103 and the connection electrode pattern 103a, and the pixel definition film is subjected to a patterning process to form the first filling layer 104a and the pixel definition layer 104 at the same time; in the first A light-emitting function layer 105 is formed on the filling layer 104a and the pixel definition layer 104; a second electrode 106 is formed on the light-emitting function layer 105.
  • any display substrate shown in FIGS. 5A to 8A can be formed.
  • the manufacturing method of the display substrate includes: forming an insulating film on a base substrate 101, and patterning the insulating film to form a first via hole V1 and a second via hole V2 to form the first insulating layer 102;
  • the first via hole V1 and the second via hole V2 are filled with conductive materials to form connectors, respectively; a conductive film is formed on the first insulating layer 102 and the connectors, and a patterning process is performed on the conductive film to simultaneously form the first electrode pattern 103 and the connection electrode pattern 103a; a pixel definition film is formed on the first electrode pattern 103 and the connection electrode pattern 103, and a patterning process is performed on the pixel definition film to form the first filling layer 104a and the pixel definition layer 104 at the same time; in the first A light-emitting function layer 105 is formed on the filling layer 104a and the pixel definition layer 104; a second electrode 106 is formed on the light-emitting function layer
  • the manufacturing method of the display substrate includes: forming an insulating film on a base substrate 101, and patterning the insulating film to form a first via hole V1 and a second via hole V2 to form the first insulating layer 102;
  • the first via hole V1 and the second via hole V2 are filled with conductive materials to form connectors, respectively; a conductive film is formed on the first insulating layer 102 and the connectors, and a patterning process is performed on the conductive film to simultaneously form the first electrode pattern 103.
  • the electrode pattern 103a and the at least one conductive filling portion 103d1 Connect the electrode pattern 103a and the at least one conductive filling portion 103d1; form a pixel definition film on the first electrode pattern 103, the connection electrode pattern 103 and the at least one conductive filling portion 103d1, and perform a patterning process on the pixel definition film to form simultaneously
  • the display substrate shown in FIG. 7A can be formed.
  • the manufacturing method of the display substrate includes: forming an insulating film on a base substrate 101, and patterning the insulating film to form a first via hole V1 and a second via hole V2 to form the first insulating layer 102;
  • the first via hole V1 and the second via hole V2 are filled with conductive materials to form connectors, respectively; a conductive film is formed on the first insulating layer 102 and the connectors, and a patterning process is performed on the conductive film to simultaneously form the first electrode pattern 103.
  • connection electrode pattern 103a includes a plurality of connection electrodes 103a0; forming a pixel definition film on the first electrode pattern 103, the connection electrode pattern 103 and the at least one conductive filling portion 103d1,
  • the pixel defining film undergoes a patterning process to simultaneously form the pixel defining layer 104, at least one insulating filling portion 104a0 and the second filling layer 104b; forming a light-emitting function layer 105 on the pixel defining layer 104 and the at least one insulating filling portion 104a0;
  • a second electrode 106 is formed on the functional layer 105. Using this manufacturing method, the display substrate shown in FIG. 8A can be formed.
  • the above-mentioned manufacturing method can be used to form the display substrate described in the first aspect, and the display substrate can be any of the above-mentioned display substrates.
  • the specific description of the display substrate refer to the above, and will not be repeated here.
  • embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device.
  • FIG. 11 is a schematic diagram of area division of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate includes a display area 11 and a peripheral area 12.
  • the peripheral area 12 includes a connecting electrode area 12a. Therefore, the peripheral area 12 includes three areas: a connecting electrode area 12a, a first dummy area 121, and a second dummy area. ⁇ 122.
  • the first dummy area 121 is located between the connection electrode area 12 a and the display area 11, and the second dummy area 122 is located on the side of the connection electrode area 12 a away from the display area 11.
  • the second dummy area 122 is located on the side of the connection electrode area 12 a away from the first dummy area 121.
  • the provision of the first dummy region 121 can avoid short circuiting of the components in the display region and the connecting electrode region 12a that need to be insulated from each other, and the provision of the second dummy region 122 can facilitate the packaging of the display substrate and improve the packaging effect.
  • FIG. 12 is a schematic top view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 12 shows a top view of the structure formed by the conductive film after a patterning process.
  • FIG. 12 shows the display area 11, the peripheral area 12, the connection electrode area 12a, the first dummy area 121, and the second dummy area 122.
  • FIG. 12 also shows the first electrode 1030, the first dummy electrode de10, the second dummy electrode de20, and the connection electrode 103a0.
  • the first electrode 1030 is located in the display area 11, the first dummy electrode de10 is located in the first dummy area 121, the second dummy electrode de20 is located in the second dummy area 122, and the connection electrode 103a0 is located in the connection electrode area 12a.
  • the connection electrode pattern 103a has a ring shape.
  • the first dummy electrode de10 has a block shape.
  • the second dummy electrode de20 has a block shape.
  • the connecting electrode 103a0 has a block shape.
  • the first electrode 1030 has a block shape.
  • the block shape includes polygons, but is not limited thereto.
  • the shapes of the first electrode 1030, the first dummy electrode de10, the second dummy electrode de20, and the connection electrode 103a0 are the same, but are not limited to this.
  • FIG. 13A is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate 200a includes: a first electrode pattern 103 located in the display area 11 of the display substrate, and includes a plurality of first electrodes 1030 spaced apart from each other, the first electrodes are configured to receive pixel driving signals;
  • the pattern 103a is located in the connection electrode area 12a of the display substrate and includes a plurality of connection electrodes 103a0; the connection electrode area 12a surrounds the display area 11.
  • the plurality of connection electrodes 103a0 surround the plurality of first electrodes 1030.
  • the display substrate further includes a second electrode 106 connected to a plurality of connecting electrodes 103a0; a peripheral area 12 surrounds the display area 11,
  • the peripheral area 12 includes a connection electrode area 12a and a first dummy area 121; the second electrode 106 is located in the display area 11 and the peripheral area 12, and the second electrode 106 and the first electrode pattern 103 are spaced apart from each other.
  • the second electrode is configured to receive the first power signal.
  • the pattern density of the connection electrode pattern 103a and the pattern density of the first electrode pattern 103 are the same.
  • the display substrate 200a further includes a first dummy electrode pattern de1, which is located in the first dummy region 121 and includes a plurality of The first dummy electrode de10.
  • the first dummy area 121 is located between the connection electrode area 12a and the display area 11.
  • the pattern density of the first dummy electrode pattern de1 and the pattern density of the first electrode pattern 103 are the same.
  • the display substrate further includes a second dummy electrode pattern de2, which is located in the second dummy area 122 and includes a plurality of second dummy electrodes de20;
  • the two dummy regions 122 are located on the side of the connection electrode region 12 a away from the display region 11.
  • the pattern density of the second dummy electrode pattern de2 and the pattern density of the first electrode pattern 103 are the same.
  • a first filling layer 104a is provided in the first dummy area 121, and the first filling layer 104a includes a plurality of first dummy electrodes de10 and an insulating filling layer 104c.
  • the first electrode pattern 103 includes an edge first electrode 103e close to the connecting electrode 103a0, and the insulating filling layer 104c is in contact with the connecting electrode 103a0 and the edge first electrode 103e, respectively.
  • the edge first electrode 103e is the first electrode 1030 closest to the connection electrode 103a0.
  • the second electrode 106 is in contact with the insulating filling layer 104c.
  • the edge first electrode 103e and the plurality of first dummy electrodes de10 are insulated from each other.
  • the display substrate further includes a pixel definition layer 104, and the pixel definition layer 104 includes a plurality of pixel definition portions 1040.
  • each of the plurality of pixel defining parts 1040 is located between adjacent first electrodes 1030.
  • the insulating filling layer 104c and the pixel defining layer 104 are located in the same layer, and can be formed by the same film layer using the same patterning process to save manufacturing process.
  • the first electrode pattern 103 and the connecting electrode pattern 103a are located on the same layer, and can be formed by the same film layer using the same patterning process to save manufacturing process.
  • the display substrate further includes a second filling layer 104b, the second filling layer 104b includes at least one second filling portion 104b0, and the second filling portion 104b0 is located adjacent to each other. Connect between the electrodes 103a0. As shown in FIG. 13A, in the display substrate provided by an embodiment of the present disclosure, the second filling portion 104b0 is in contact with the adjacent connecting electrode 103a0, respectively.
  • the second filling layer 104b is an insulating layer.
  • the second filling layer 104b and the insulating filling layer 104c are located in the same layer, and can be formed by the same film layer using the same patterning process to save manufacturing process.
  • the display substrate further includes a light-emitting function layer 105, the light-emitting function layer 105 is located between the first electrode pattern 103 and the second electrode 106, and the light-emitting function layer 105 and The insulating filling layer 104c is in contact.
  • the light-emitting function layer 105 is in contact with the insulating filling layer 104c.
  • the light-emitting function layer 105 is in contact with a part of the insulating filling layer 104c.
  • the first dummy electrode de10 is not externally connected, and the portion of the first insulating layer directly below the first dummy electrode de10 that is in contact with it is not disposed.
  • the hole please refer to the description of the first dummy electrode 103d1.
  • the first via V1 and the second via V2 reference may be made to the previous description, which will not be repeated here.
  • FIG. 13A takes the insulating filling layer 104c completely covering the plurality of first dummy electrodes de10 as an example for illustration, but it is not limited to this.
  • FIG. 13B is a cross-sectional view of a display substrate provided by an embodiment of the disclosure.
  • the display substrate 200aa shown in FIG. 13B differs in that a groove G is provided in the first insulating layer 102 of the display substrate 200aa.
  • the size of the groove G in the first insulating layer 102 in the display area 11 in the direction perpendicular to the base substrate 101 is equal to the groove G in the first insulating layer 102 in the peripheral area 12 The size in the direction perpendicular to the base substrate 101.
  • all the grooves G in the first insulating layer 102 have the same size in the direction perpendicular to the base substrate 101.
  • the groove G of the dummy area 121 and the groove G of the first insulating layer 102 located in the display area 11 have the same size in the direction perpendicular to the base substrate 101.
  • FIG. 14A is a cross-sectional view of a display substrate provided by an embodiment of the disclosure.
  • the difference between the display substrate 200b and the display substrate 200a shown in FIG. 13A is that the insulating filling layer 104c may include a plurality of hollow regions HR11 to respectively expose the plurality of first dummy electrodes de10, and the second electrode 106 is insulated The hollow area in the filling layer 104c is connected to the first dummy electrode de10.
  • the insulating filling layer 104c includes a plurality of insulating filling portions 104c0. As shown in FIG.
  • the insulating filling portion 104c0 is located between adjacent first dummy electrodes de10, or between adjacent first dummy electrodes de10 and edge first electrodes 103e, or between adjacent first dummy electrodes de10 And the connection electrode 103a0.
  • FIG. 14B is a cross-sectional view of a display substrate provided by an embodiment of the disclosure.
  • the display substrate 200bb shown in FIG. 14B is different in that the first insulating layer 102 of the display substrate 200bb is provided with a groove G.
  • the size of the groove G in the first insulating layer 102 in the display area 11 in the direction perpendicular to the base substrate 101 is equal to the groove G in the first insulating layer 102 in the peripheral area 12
  • the size in the direction perpendicular to the base substrate 101 For example, all the grooves G in the first insulating layer 102 have the same size in the direction perpendicular to the base substrate 101.
  • the groove G of the dummy area 121 and the groove G of the first insulating layer 102 located in the display area 11 have the same size in the direction perpendicular to the base substrate 101.
  • FIG. 15 is a top view of an insulating filling layer, a second filling layer, and a pixel defining layer in a display substrate provided by an embodiment of the disclosure.
  • FIG. 15 shows the insulating filling layer 104c, the second filling layer 104b, and the pixel defining layer 104.
  • the patterned structure of the pixel definition film includes a plurality of hollow areas HR.
  • the plurality of hollow areas HR include a hollow area HR0 located in the display area 11 and a hollow area HR2 located in the second dummy area 122.
  • the hollow area HR0 is configured to expose the first electrode 1030, and the hollow area HR2 is configured to expose the connection electrode 103a0.
  • the insulating filling layer, the second filling layer, and the pixel defining layer shown in FIG. 15 may be a top view of the insulating filling layer 104c, the second filling layer 104b, and the pixel defining layer 104 in FIG. 13A.
  • the top view of the first filling layer, the second filling layer, and the pixel definition layer shown in FIG. 14A can refer to FIG. 10, but is not limited thereto.
  • At least one embodiment of the present disclosure further provides a display device including any display substrate in the second aspect described above.
  • the display device includes a micro OLED display device.
  • At least one embodiment of the present disclosure further provides a manufacturing method of a display substrate, including: forming a first electrode pattern 103, the first electrode pattern 103 is located in the display area 11 of the display substrate, and includes a plurality of first electrodes 1030 spaced apart from each other, The first electrode is configured to receive the pixel driving signal; a connecting electrode pattern 103a is formed.
  • the connecting electrode pattern 103a is located in the connecting electrode area 12a of the display substrate and includes a plurality of connecting electrodes 103a0.
  • the connecting electrode area 12a surrounds the display area 11;
  • the electrode 106, the second electrode 106 are located in the display area 11 and the peripheral area 12, the second electrode 106 is connected to the connecting electrode pattern 103a, the second electrode 106 and the first electrode pattern 103 are spaced apart from each other, and the second electrode is configured to receive the first power signal.
  • the plurality of connection electrodes 103a0 surround the plurality of first electrodes 1030.
  • the connection electrode 103a0 has a block shape.
  • the pattern density of the connecting electrode pattern 103a is the same as the pattern density of the first electrode pattern 103.
  • the manufacturing method of the display substrate provided by an embodiment of the present disclosure further includes: forming a first dummy electrode pattern de1, which is located in the first dummy area 121 of the display substrate and includes a plurality of first dummy electrodes de10; A dummy area 121 is located between the connection electrode area 12a and the display area 11; in order to improve the etching uniformity, the pattern density of the first dummy electrode pattern de1 and the pattern density of the first electrode pattern 103 are the same.
  • the first dummy electrode de10 has a block shape.
  • the peripheral area 12 includes a connection electrode area 12 a and a first dummy area 121.
  • the manufacturing method of the display substrate provided by an embodiment of the present disclosure further includes: forming a second dummy electrode pattern de2, the second dummy electrode pattern de2 is located in the second dummy area 122 of the display substrate and includes a plurality of second dummy electrodes de20; The two dummy regions 122 are located on the side of the connecting electrode region 12a away from the display region 11.
  • the pattern density of the second dummy electrode pattern de2 and the pattern density of the first electrode pattern 103 are the same.
  • the second dummy electrode de20 has a block shape.
  • the peripheral area 12 includes a connection electrode area 12 a, a first dummy area 121 and a second dummy area 122.
  • a first filling layer 104a is formed in the first dummy region 121.
  • the first filling layer 104a includes a plurality of first dummy electrodes de10 and an insulating filling layer 104c.
  • the pattern 103 includes an edge first electrode 103e adjacent to the connection electrode 103a0, and the insulating filling layer 104c is in contact with the connection electrode 103a0 and the edge first electrode 103e, respectively.
  • the second electrode 106 is in contact with the insulating filling layer 104c.
  • the edge first electrode 103e and the plurality of first dummy electrodes de10 are insulated from each other.
  • the manufacturing method further includes: forming a pixel defining layer 104, the pixel defining layer 104 includes a plurality of pixel defining portions 1040, each of the plurality of pixel defining portions 1040 is located Between adjacent first electrodes 1030.
  • the insulating filling layer 104c and the pixel defining layer 104 are formed from the same film layer using the same patterning process.
  • the first electrode pattern 103 and the connecting electrode pattern 103a are formed from the same film layer using the same patterning process.
  • the manufacturing method of the display substrate provided by an embodiment of the present disclosure further includes: forming a second filling layer 104b, the second filling layer 104b includes at least one second filling portion 104b0, and the second filling portion 104b0 is located between adjacent connecting electrodes 103a0.
  • the second filling portion 104b0 is in contact with the adjacent connection electrode 103a0, respectively.
  • the second filling layer 104b is an insulating layer.
  • the second filling layer 104b and the first filling layer 104a are formed from the same film layer using the same patterning process.
  • the manufacturing method of the display substrate provided by an embodiment of the present disclosure further includes: forming a light-emitting function layer 105, the light-emitting function layer 105 is located between the first electrode pattern 103 and the second electrode 106, and the light-emitting function layer 105 is in contact with the first filling layer 104a .
  • the light-emitting function layer 105 is in contact with a part of the first filling layer 104a.
  • the manufacturing method of the display substrate includes: forming a first electrode pattern, the first electrode pattern is located in the display area of the display substrate, and includes a plurality of first electrodes spaced apart from each other; and forming a connecting electrode pattern ,
  • the connection electrode pattern is located in the peripheral area of the display substrate and includes a plurality of connection electrodes; and a second electrode is formed, the second electrode is located in the display area and the peripheral area, and is connected to the connection electrode
  • the patterns are connected, and the second electrode and the first electrode pattern are spaced apart from each other; the connecting electrode pattern surrounds the first electrode pattern, and the connecting electrode is in a block shape.
  • the manufacturing method of the display substrate includes: forming an insulating film on a base substrate 101, and patterning the insulating film to form a first via hole V1 and a second via hole V2 to form the first insulating layer 102;
  • the first via hole V1 and the second via hole V2 are filled with conductive materials to form connectors, respectively; a conductive film is formed on the first insulating layer 102 and the connectors, and a patterning process is performed on the conductive film to simultaneously form the first electrode pattern 103.
  • connection electrode pattern 103a and the first dummy electrode pattern de1 includes a plurality of connection electrodes 103a0; forming a pixel definition film on the first electrode pattern 103, the connection electrode pattern 103 and the first dummy electrode pattern de1,
  • the pixel defining film undergoes a patterning process to simultaneously form the pixel defining layer 104, the insulating filling layer 104c, and the second filling layer 104b; forming the light emitting function layer 105 on the pixel defining layer 104 and the insulating filling layer 104c; on the light emitting function layer 105
  • the second electrode 106 is formed. Using this manufacturing method, the display substrate shown in FIG. 13A can be formed.
  • the manufacturing method of the display substrate includes: forming an insulating film on a base substrate 101, and patterning the insulating film to form a first via hole V1 and a second via hole V2 to form the first insulating layer 102;
  • the first via hole V1 and the second via hole V2 are filled with conductive materials to form connectors, respectively; a conductive film is formed on the first insulating layer 102 and the connectors, and a patterning process is performed on the conductive film to simultaneously form the first electrode pattern 103.
  • connection electrode pattern 103a and the first dummy electrode pattern de1 includes a plurality of connection electrodes 103a0; forming a pixel definition film on the first electrode pattern 103, the connection electrode pattern 103 and the first dummy electrode pattern de1,
  • the pixel defining film undergoes a patterning process to simultaneously form the pixel defining layer 104, at least one insulating filling portion 104c0 and the second filling layer 104b; forming a light-emitting function layer 105 on the pixel defining layer 104 and the at least one insulating filling portion 104c0;
  • a second electrode 106 is formed on the functional layer 105. Using this manufacturing method, the display substrate shown in FIG. 14A can be formed.
  • embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device.
  • FIG. 16 is a schematic diagram of area division of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate further includes a sensor region R1.
  • the portion of the first dummy region 121 between the sensor region R1 and the connection electrode region 12a is a first dummy sub-region 1211; a second dummy sub-region 1211;
  • the area 1212 is located between the sensor area R1 and the display area 11.
  • FIG. 16 also shows a pad area (pad area) R2.
  • the pad area R2 can be used for an external circuit.
  • FIG. 17A is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 17A may be a schematic cross-sectional view of M-N in the display substrate shown in FIG. 18.
  • the display substrate 300a includes a first electrode pattern 103, a connection electrode pattern 103a, and a first dummy electrode pattern de1.
  • the first electrode pattern 103 is located in the display area 11 of the display substrate, and includes a plurality of first electrodes 1030 spaced apart from each other.
  • the first electrode is configured to receive a pixel driving signal.
  • the connection electrode pattern 103a is located in the connection electrode area 12a of the display substrate and includes a plurality of connection electrodes 103a0.
  • the first dummy electrode pattern de1 is located in the first dummy area 121 of the display substrate and includes a plurality of first dummy electrodes de10. The provision of the first dummy electrode pattern de1 can help improve the etching uniformity.
  • connection electrode area 12a surrounds the display area 11, and the first dummy area 121 is located between the connection electrode area 12a and the display area 11.
  • the connection electrode pattern 103 a surrounds the first electrode pattern 103, and the first dummy electrode pattern de1 surrounds the first electrode pattern 103.
  • the first dummy electrode pattern de1 is located between the connection electrode pattern 103a and the first electrode pattern 103.
  • the connection electrode pattern 103a has a ring shape.
  • the display substrate provided by an embodiment of the present disclosure further includes a second electrode 106, which is connected to the connection electrode 103a0; the peripheral area 12 of the display substrate surrounds the display area 11, and the peripheral area 12 includes the connection The electrode area 12a and the first dummy area 121; the second electrode 106 is located in the display area 11 and the peripheral area 12, and the second electrode 106 and the first electrode pattern 103 are spaced apart from each other.
  • the second electrode is configured to receive the first power signal.
  • At least one of the pattern density of the connection electrode pattern 103a and the pattern density of the first dummy electrode pattern de1 is the same as the pattern density of the first electrode pattern 103.
  • the display substrate provided by an embodiment of the present disclosure further includes a sensor electrode pattern 103b.
  • the sensor electrode pattern 103b is located in the sensor region R1 of the display substrate and includes a plurality of sensor electrodes 103b0.
  • the sensor electrode 103b0 is configured to receive a detection drive signal.
  • the pattern density of the sensor electrode pattern 103b and the pattern density of the first electrode pattern 103 are the same.
  • the display substrate provided by an embodiment of the present disclosure further includes a second dummy electrode pattern de2.
  • the second dummy electrode pattern de2 is located in the second dummy area 122 of the display substrate and includes a plurality of second dummy electrodes. de20;
  • the second dummy area 122 is located on the side of the connecting electrode area 12a away from the display area 11.
  • the pattern density of the second dummy electrode pattern de2 and the pattern density of the first electrode pattern 103 are the same.
  • the pattern density of the first electrode pattern 103, the pattern density of the connection electrode pattern 103a, the pattern density of the sensor electrode pattern 103b, the pattern density of the first dummy electrode pattern de1, and the second dummy pattern is the same.
  • a first filling layer 104a is provided in the first dummy sub-region 1211, and the first filling layer 104a includes a plurality of first dummy electrodes de10 and an insulating filling layer 104c; the first electrode pattern 103 includes The edge first electrode 103e and the insulating filling layer 104c adjacent to the electrode 103a0 are in contact with the connecting electrode 103a0 and the edge first electrode 103e, respectively.
  • the second electrode 106 is in contact with the insulating filling layer 104c.
  • the edge first electrode 103e and the plurality of first dummy electrodes de10 are insulated from each other.
  • the display substrate further includes a pixel defining layer 104, and the pixel defining layer 104 includes a plurality of pixel defining portions 1040, and each of the plurality of pixel defining portions 1040 is located between adjacent first electrodes 1030.
  • the insulating filling layer 104c and the pixel defining layer 104 are located in the same layer, and can be formed by the same film layer using the same patterning process to save manufacturing process.
  • the first electrode pattern 103, the connection electrode pattern 103a, the sensor electrode pattern 103b, the first dummy electrode pattern de1 and the second dummy electrode pattern de2 are located in the same layer, and can be formed by the same film layer using the same patterning process , In order to save the production process.
  • the display substrate further includes a second filling layer 104b, the second filling layer 104b includes at least one second filling portion 104b0, and the second filling portion 104b0 is located between adjacent connecting electrodes 103a0.
  • the second filling layer 104b is an insulating layer.
  • the second filling portions 104b0 are in contact with adjacent connection electrodes 103a0, respectively.
  • the second filling layer 104b and the first filling layer 104a are located in the same layer, and can be formed by the same film layer using the same patterning process to save manufacturing process.
  • the display substrate further includes a third filling layer 1043, and the third filling layer 1043 includes a plurality of third filling portions 10430, and the third filling portions 10430 are located on the adjacent sensor electrode 103b0 and the adjacent sensor electrode 103b. And at least one of the first dummy electrodes.
  • FIG. 17A uses an example in which the third filling portion 10430 is located between adjacent sensor electrodes 103b0.
  • the third filling layer 1043 and the pixel definition layer 104 are located in the same layer, and can be formed by the same film layer using the same patterning process to save manufacturing process.
  • the pixel definition layer 104, the insulating filling layer 104c, the second filling layer 104b, and the third filling layer 1043 are located in the same layer.
  • the display substrate further includes a light-emitting function layer 105, the light-emitting function layer 105 is located between the first electrode pattern 103 and the second electrode 106, and the light-emitting function layer 105 is in contact with the first filling layer 104a.
  • the light-emitting function layer 105 is in contact with a part of the first filling layer 104a.
  • the light-emitting function layer 105 extends to the first dummy sub-region 1211.
  • the light-emitting function layer 105 covers the entire display area 11, the sensor area R1, the second dummy sub-area 1212, and a part of the first dummy sub-area 1211, so as to prevent the light-emitting function layer 105 from being vapor-deposited on the connecting electrode area 122 to cause the first electrode and the second electrode Short circuit.
  • the second electrode 106 extends from the display area 11 to the second dummy area 122 of the peripheral area 12 to facilitate the connection between the second electrode 106 and the connection electrode 103a0.
  • the light-emitting function layer 105 is in contact with the sensor electrode pattern 103b.
  • the light-emitting function layer 105 is not in contact with the first dummy electrode de10 located in the second dummy sub-region 1212, but it is not limited to this.
  • a second insulating layer IS is further provided on the base substrate 101, and a conductive pattern 109 is provided on the second insulating layer IS.
  • the conductive pattern 109 includes a first conductive portion 1091, a second conductive portion 1092, and a second conductive portion 1092. Three conductive parts 1093.
  • the second insulating layer IS includes a third via V11, a fourth via V21, and a fifth via V31.
  • the third via V11, the fourth via V21, and the fifth via V31 are respectively filled with conductive materials to form a connection member.
  • the first electrode 1030 is connected to the connector in the fourth via hole V21 through the first conductive portion 1091.
  • the connecting electrode 103a0 is connected to the connecting member in the third via V11 through the second conductive portion 1092.
  • the sensor electrode 103b0 is connected to the connector in the fifth via hole V31 through the third conductive portion 1093. It should be noted that another structure is provided between the base substrate 101 and the second insulating layer IS, and this other structure is not shown in FIG. 17A.
  • the display substrate further includes an encapsulation layer 107.
  • the encapsulation layer 107 is configured to encapsulate the light-emitting element to prevent water and oxygen from attacking.
  • the encapsulation layer 107 covers the second electrode 106 and the second dummy electrode pattern de2.
  • the encapsulation layer 107 may cover the entire base substrate 101 and the structure thereon.
  • FIG. 17B is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate 300aa shown in FIG. 17B is different in that the first insulating layer 102 of the display substrate 300aa is provided with a groove G.
  • the size of the groove G in the first insulating layer 102 in the display area 11 in the direction perpendicular to the base substrate 101 is equal to the groove G in the first insulating layer 102 in the peripheral area 12
  • the size in the direction perpendicular to the base substrate 101 For example, all the grooves G in the first insulating layer 102 have the same size in the direction perpendicular to the base substrate 101.
  • the grooves G of 11 have the same size in the direction perpendicular to the base substrate 101.
  • FIG. 18 is a top view of a structure formed by patterning a conductive film in a display substrate provided by an embodiment of the present disclosure. Other structures in the display substrate are not shown, please refer to FIG. 17A or FIG. 17B.
  • FIG. 18 shows the sensor electrode 103b0.
  • the shape of the sensor electrode 103b0, the shape of the first electrode 1030, the shape of the connecting electrode 103a0, the shape of the first dummy electrode de10 and the shape of the second dummy electrode de20 are the same, but are not limited thereto.
  • FIG. 18 shows the sensor electrode 103b0.
  • the shape of the sensor electrode 103b0, the shape of the first electrode 1030, the shape of the connecting electrode 103a0, the shape of the first dummy electrode de10 and the shape of the second dummy electrode de20 are the same, but are not limited thereto.
  • FIG. 18 shows the shape of the sensor electrode 103b0, the shape of the first electrode 1030, the shape of the connecting electrode 103
  • the pattern density of the sensor electrode pattern 103b, the pattern density of the first electrode pattern 103, the pattern density of the connection electrode pattern 103a, the pattern density of the first dummy electrode pattern de1, and the pattern density of the second dummy electrode pattern de2 the same. That is, the pattern density of the plurality of sensor electrodes 103b0, the pattern density of the plurality of first electrodes 1030, the pattern density of the plurality of connection electrodes 103a0, the pattern density of the plurality of first dummy electrodes de10, and the pattern of the plurality of second dummy electrodes de20 The density is the same.
  • the first dummy electrode de10 has a block shape.
  • the block-shaped first dummy electrode de10 can also refer to FIG. 12.
  • the second dummy electrode de20 has a block shape.
  • the block-shaped second dummy electrode de20 can also refer to FIG. 12.
  • the sensor electrode 103b0, the first electrode 1030, the connection electrode 103a0, the first dummy electrode de10, and the second dummy electrode de20 are all in a block shape.
  • FIG. 19 is a top view of a structure formed by patterning a pixel defining film in a display substrate provided by an embodiment of the present disclosure. Compared with the structure shown in FIG. 15, FIG. 19 shows the third filling portion 10430 and the hollow area HR3. The hollow area HR3 is configured to expose the sensor electrode 103b0 (not shown in FIG. 19, refer to FIGS. 17A and 17B).
  • FIG. 20 is a cross-sectional view of a display substrate provided by an embodiment of the disclosure.
  • the difference between the display substrate 300b shown in FIG. 20 and the display substrate 300a shown in FIG. 17A is that the portion of the insulating filling layer 104c located in the second dummy sub-region 1212 includes the hollow region HR22.
  • the hollow area HR22 is configured to expose the first dummy electrode de10 located in the second dummy sub-area 1212.
  • the light-emitting function layer 105 is in contact with the first dummy electrode de10 located in the second dummy sub-region 1212. As shown in FIGS. 17A and 20, the light-emitting function layer 105 is not in contact with the first dummy electrode de10 located in the first dummy sub-region 1211.
  • At least one embodiment of the present disclosure further provides a display device including any display substrate in the third aspect described above.
  • the display device includes a micro OLED display device, but is not limited thereto.
  • the display substrate provided in the third aspect has more sensor regions R1 than the display substrate provided in the second aspect, and the rest can refer to the description of the second aspect.
  • At least one embodiment of the present disclosure further provides a manufacturing method of a display substrate, including: forming a first electrode pattern, the first electrode pattern is located in a display area of the display substrate and includes a plurality of first electrodes spaced apart from each other, The first electrode is configured to receive a pixel driving signal; forming a connecting electrode pattern, the connecting electrode pattern is located in the peripheral area of the display substrate, and includes a plurality of connecting electrodes; forming a second electrode, the second electrode is located The display area and the peripheral area are connected to the connection electrode pattern, the second electrode and the first electrode pattern are spaced apart from each other, and the second electrode is configured to receive a first power signal; A functional layer, the light-emitting functional layer is located between the first electrode pattern and the second electrode; and a first dummy electrode pattern is formed, the first dummy electrode pattern includes a plurality of first dummy electrodes; the connection An electrode pattern surrounds the first electrode pattern, the first dummy electrode pattern is located between the connection electrode pattern and the first electrode pattern
  • At least one embodiment of the present disclosure further provides a manufacturing method of a display substrate, including: forming a first electrode pattern 103, the first electrode pattern 103 is located in the display area 11 of the display substrate and includes a plurality of first electrodes 1030 spaced apart from each other; A connection electrode pattern 103a is formed.
  • the connection electrode pattern 103a is located in the connection electrode area 12a of the display substrate and includes a plurality of connection electrodes 103a0.
  • a second electrode 106 is formed.
  • the second electrode 106 is located in the display area 11 and the peripheral area 12.
  • the second electrode 106 Connected to the connection electrode pattern 103a, the second electrode 106 and the first electrode pattern 103 are spaced apart from each other; and a first dummy electrode pattern de1 is formed.
  • the first dummy electrode pattern de1 is located in the first dummy area 121 of the display substrate and includes a plurality of A dummy electrode de10; the connection electrode pattern 103a surrounds the first electrode pattern 103, and the first dummy electrode pattern is located between the connection electrode pattern and the first electrode pattern.
  • the first dummy electrode pattern de1 surrounds the first electrode pattern 103.
  • connection electrode area 12a surrounds the display area 11, and the first dummy area 121 is located between the connection electrode area 12a and the display area 11.
  • the present disclosure further provides a method for manufacturing a display substrate, the pattern density of the first electrode pattern 103, the pattern density of the connection electrode pattern 103a and the pattern density of the first dummy electrode pattern de1 are the same.
  • At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate further including forming a second dummy electrode pattern de2, which is located in the second dummy area 122 of the display substrate and includes a plurality of second dummy electrodes. Electrode de20; the second dummy area 122 is located on the side of the connecting electrode area 12a away from the display area 11, the pattern density of the second dummy electrode pattern de2 and the pattern density of the first electrode pattern 103 are the same.
  • At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate that further includes forming a sensor electrode pattern 103b.
  • the sensor electrode pattern 103b is located in the sensor region R1 of the display substrate and includes a plurality of sensor electrodes 103b0;
  • the pattern density is the same as the pattern density of the first electrode pattern 103.
  • the second dummy sub-region 1212 is located between the sensor region R1 and the display region 11; the first dummy region 121 is located between the sensor region R1 and the connection electrode
  • the part between the regions 12a is the first dummy sub-region 1211; a first filling layer 104a is formed in the first dummy sub-region 1211.
  • the first filling layer 104a includes a plurality of first dummy electrodes de10 and an insulating filling layer 104c.
  • the pattern 103 includes an edge first electrode 103e adjacent to the connection electrode 103a0, and the insulating filling layer 104c is in contact with the connection electrode 103a0 and the edge first electrode 103e, respectively.
  • the second electrode 106 is in contact with the insulating filling layer 104c.
  • the edge first electrode 103e and the plurality of first dummy electrodes de10 are insulated from each other.
  • At least one embodiment of the present disclosure also provides a method for manufacturing a display substrate.
  • the method further includes forming a pixel definition layer 104.
  • the pixel definition layer 104 includes a plurality of pixel definition portions 1040. Each is located between adjacent first electrodes 1030.
  • the insulating filling layer 104c and the pixel defining layer 104 are formed from the same film layer and using the same patterning process.
  • the first electrode pattern 103 and the connecting electrode pattern 103a are formed from the same film layer using the same patterning process.
  • At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate further including forming a second filling layer 104b, the second filling layer 104b includes at least one second filling portion 104b0, the second filling portion 104b0 is located adjacent to the connecting electrode Between 103a0.
  • the second filling portion 104b0 is in contact with the adjacent connection electrode 103a0, respectively.
  • the second filling layer 104b is an insulating layer.
  • the second filling layer 104b and the first filling layer 104a are formed from the same film layer using the same patterning process.
  • At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate that further includes forming a third filling layer 1043.
  • the third filling layer 1043 includes a plurality of third filling portions 10430, and the third filling portions 10430 are located at adjacent sensor electrodes. 103b0, between at least one of the adjacent third dummy electrode, the adjacent sensor electrode 103b0, and the third dummy electrode.
  • the third filling layer 1043 and the pixel defining layer 104 are formed from the same film layer and using the same patterning process.
  • the light-emitting function layer 105 is in contact with the first filling layer 104a.
  • the light-emitting function layer 105 is in contact with a part of the first filling layer 104a.
  • the light-emitting function layer 105 is in contact with the sensor electrode pattern 103b.
  • the light-emitting function layer 105 is in contact with the first dummy electrode de10 located in the second dummy subregion.
  • the manufacturing method of the display substrate includes: forming an insulating film on a base substrate 101, and patterning the insulating film to form a first via V1, a second via V2, and a third via V3 to form a first via V1, a second via V2, and a third via V3.
  • the connection electrode pattern 103a includes a plurality of connection electrodes 103a.
  • the electrode pattern 103b includes a plurality of sensor electrodes 103b0, the first dummy electrode pattern de1 includes a plurality of first dummy electrodes de10, and the second dummy electrode pattern de2 includes a plurality of second dummy electrodes de20; in the first electrode pattern 103, the connection electrode pattern 103a.
  • a pixel defining film is formed on the first dummy electrode pattern de1 and the sensor electrode pattern 103b, and a patterning process is performed on the pixel defining film to simultaneously form the pixel defining layer 104, the insulating filling layer 104c, the second filling layer 104b, and the third filling Layer 1043; a light-emitting function layer 105 is formed on the pixel definition layer 104, an insulating filling layer 104c, and the third filling layer 1043; a second electrode 106 is formed on the light-emitting function layer 105.
  • the display substrate shown in FIGS. 17A and 18 can be formed.
  • the pattern density of the A pattern refers to the density of multiple A included in the pattern, for example, it may refer to the number of A per unit area, but is not limited thereto.
  • the pattern density of the first electrode pattern 103 can refer to the density of the plurality of first electrodes 1030 in the first electrode pattern 103, and the rest of the related content can be referred to here.
  • the first connecting member cn1 is located in the first via hole V1
  • the second connecting member cn2 is located in the second via hole V2.
  • the reference signs in the remaining drawings are not given.
  • connection electrode pattern has a ring shape.
  • the base substrate 101 may include a silicon wafer, but is not limited thereto.
  • At least one of the first insulating layer and the second insulating layer includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.
  • the sensor electrode may be configured to measure at least one of parameters such as temperature and brightness.
  • the configuration of the sensor electrode may be the same as the configuration of the sub-pixels of the display area.
  • the block-shaped element is a pattern, and there is no hollow area in it.
  • the first electrode pattern 103 is not block-shaped, because there are hollow areas between the different first electrodes 1030 it includes, and the first electrode 1030 is block-shaped, because the first electrode 1030 is not There is a hollow area.
  • the display area includes a plurality of light-emitting elements, and the plurality of light-emitting elements can emit light for image display, and the peripheral area does not emit light.
  • FIG. 21 is a schematic diagram of a conductive film formed in a method for manufacturing a display substrate provided by an embodiment of the disclosure.
  • the conductive film 0103 can cover the entire surface of the base substrate, and form the first electrode pattern and the elements on the same layer as the first electrode pattern through the patterning process.
  • the element located on the same layer as the first electrode pattern includes at least one of a connection electrode pattern, a first dummy electrode pattern, a second dummy electrode pattern, a sensor electrode pattern, and the like.
  • the conductive film is formed directly on the first insulating layer 102, and the patterned structure of the conductive film is in contact with the first insulating layer 102.
  • the patterned structure formed by the conductive film includes at least one of a first electrode, a connecting electrode, a first dummy electrode, a second dummy electrode, and a sensor electrode.
  • FIG. 22 is a schematic diagram of a pixel definition film formed in a method for manufacturing a display substrate provided by an embodiment of the disclosure.
  • the pixel definition film 0104 can cover the entire surface of the base substrate, and form a pixel definition layer through a patterning process, and an element located on the same layer as the pixel definition layer.
  • the element located in the same layer as the pixel definition layer includes at least one of a first filling layer, an insulating filling layer, a second filling layer, and a third filling layer.
  • the groove in the first insulating layer 102 located in the display area 11 may be referred to as the first groove G1
  • the groove in the first insulating layer 102 located in the peripheral area 12 may be referred to as the second groove G1.
  • the portion of the first insulating layer 102 that overlaps the plurality of conductive filling portions 103d1 in the direction perpendicular to the base substrate 101 is not provided with via holes.
  • the first insulating layer 102 is connected to the plurality of first dummy electrodes de10 in a direction perpendicular to the base substrate 101. No vias are provided in the overlapping part.
  • the first insulating layer 102 is connected to the plurality of second dummy electrodes de20 in a direction perpendicular to the base substrate 101. No vias are provided in the overlapping part.
  • the overlapped portion of the first electrodes 1030 is provided with a via V2.
  • the portion of the first insulating layer 102 that overlaps the plurality of sensor electrodes 1030 in the direction perpendicular to the base substrate 101 is provided with via holes V3. .
  • the conductive filling portion 103d1 floats, the first dummy electrode de10 floats, and the second dummy electrode de20 Float.
  • floating refers to not receiving pixel drive signals.
  • the floating structure does not directly receive the first power signal.
  • the floating structure can receive the first power signal indirectly.
  • the first electrode is configured to receive a pixel driving signal
  • the second electrode is configured to receive a first power signal
  • the sensor electrode is configured to receive a detection driving signal.
  • the pixel driving signal includes, for example, at least one of a second power signal VDD, a data signal, a gate signal, a light emission control signal EM, and a reset control signal RE.
  • the silicon wafer includes a silicon-based substrate and a circuit structure on the silicon-based substrate, and the circuit structure includes a pixel circuit, a detection circuit, and the like.
  • FIG. 23 is a schematic diagram of a circuit principle of a silicon-based organic light-emitting display panel provided by some embodiments of the present disclosure.
  • the silicon-based organic light emitting display panel includes a plurality of light emitting elements L located in the display area 11 and a pixel circuit 110 coupled to each light emitting element L in a one-to-one correspondence.
  • the pixel circuit 110 includes a driving transistor.
  • the pixel circuit 110 is configured to provide pixel driving signals.
  • the silicon-based organic light-emitting display panel may further include a plurality of voltage control circuits 120 located in the peripheral area 12 of the silicon-based organic light-emitting display panel.
  • At least two pixel circuits 110 in a row share a voltage control circuit 120, and the first pole of the driving transistor in a row of pixel circuits 110 is coupled to the common voltage control circuit 120, and the second pole of each driving transistor is connected to the corresponding light emitting circuit.
  • the element L is coupled.
  • the voltage control circuit 120 is configured to output the initialization signal Vinit to the first pole of the driving transistor in response to the reset control signal RE, control the corresponding light emitting element L to reset; and in response to the light emission control signal EM, output the second power signal VDD To the first pole of the driving transistor to drive the light-emitting element L to emit light.
  • the voltage control circuit 120 By sharing the voltage control circuit 120, the structure of each pixel circuit in the display area 101 can be simplified, and the occupied area of the pixel circuit in the display area 11 can be reduced, so that more pixel circuits and light-emitting elements can be arranged in the display area 11 to achieve high PPI. Organic light emitting display panel.
  • the voltage control circuit 120 outputs the initialization signal Vinit to the first pole of the driving transistor under the control of the reset control signal RE to control the reset of the corresponding light-emitting element, so as to avoid the voltage pair applied to the light-emitting element when the previous frame emits light. The effect of the next frame of light, thereby improving the afterimage phenomenon.
  • the first electrode of the driving transistor is one of the source or drain
  • the second electrode of the driving transistor is the other of the source or drain.
  • the light-emitting element may include an organic light-emitting diode, but is not limited thereto.
  • the silicon-based organic light emitting display panel may further include a plurality of pixel units PX located in the display area 11, each pixel unit PX includes a plurality of sub-pixels; each sub-pixel includes a light-emitting element L and a pixel circuit 110 respectively.
  • the pixel unit PX may include three sub-pixels of different colors. The three sub-pixels may be red sub-pixels, green sub-pixels, and blue sub-pixels, respectively.
  • the pixel unit PX may also include 4, 5 or more sub-pixels, which need to be designed and determined according to the actual application environment, which is not limited here.
  • the pixel circuits 110 in at least two adjacent sub-pixels in the same row can share one voltage control circuit 120.
  • all the pixel circuits 110 in the same row can share one voltage control circuit 120.
  • the pixel circuits 110 in two, three or more adjacent sub-pixels in the same row may share one voltage control circuit 120, which is not limited here. In this way, by sharing the voltage control circuit 120, the area occupied by the pixel circuit in the display area A can be reduced.
  • the two electrodes of the light-emitting element L may be a first electrode 1030 and a second electrode 106, respectively.
  • the first electrode 1030 is the anode of the light-emitting element L
  • the second electrode 106 is the cathode of the light-emitting element L.
  • the first electrode 1030 is connected to the pixel circuit 110, and the second electrode 106 can be input with the first power signal VSS.
  • the first power signal VSS may be transmitted to the second electrode 106 through the connection line and the connection electrode 103a0.
  • the element A surrounds the element B, which can mean that the element A is located on at least one side of the element B, and the element A surrounds at least part of the element B.
  • Element B is not limited to a closed figure.
  • the elements located on the same layer can be subjected to the same patterning process from the same film layer.
  • elements located on the same layer may be located on the surface of the same element away from the base substrate.
  • the patterning or patterning process may include only a photolithography process, or a photolithography process and an etching step, or may include other processes for forming predetermined patterns such as printing and inkjet.
  • the photolithography process refers to the process including film formation, exposure, development, etc., using photoresist, mask, exposure machine, etc. to form patterns.
  • the corresponding patterning process can be selected according to the structure formed in the embodiment of the present disclosure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示基板（300a）及其制作方法、显示装置。显示基板（300a）包括：第一电极图案（103）、连接电极图案（103a）、第二电极（106）、发光功能层（105）以及第一虚设电极图案（de1）；第一电极图案（103）位于显示基板（300a）的显示区（11），并包括彼此间隔的多个第一电极（1030），第一电极（1030）被配置为接收像素驱动信号；连接电极图案（103a）位于显示基板（300a）的周边区（12）；第二电极（106）位于显示区（11）和周边区（12），并与连接电极图案（103a）相连，第二电极（106）与第一电极图案（103）彼此间隔，第二电极（106）被配置为接收第一电源信号；发光功能层（105）位于第一电极图案（103）和第二电极（106）之间；第一虚设电极图案（de1）包括多个第一虚设电极（de10），连接电极图案（103a）围绕第一电极图案（103），第一虚设电极图案（de1）位于连接电极图案（103a）和第一电极图案（103）之间，多个第一虚设电极（de10）中的至少两个呈彼此隔开的块状。

Description

显示基板及其制作方法、显示装置 技术领域
本公开至少一实施例涉及一种显示基板及其制作方法、显示装置。
背景技术
随着显示装置市场的不断发展，有机发光二极管(Organic Light Emitting Diode，OLED)显示器因其具有自发光、对比度高、厚度薄、视角广响应速度快、可弯折以及使用温度范围广等优点成为了当前的主流的显示装置之一,并成为各大厂商的研究热点。
有机发光二极管通常包括第一电极、第二电极和夹在两个电极之间的有机电致发光元件，有机电致发光元件包括发光功能层，发光功能层包括发光层，发光功能层还可以包括空穴传输层、空穴注入层、电子传输层和电子注入层至少之一，有机电致发单元可在第一电极和第二电极的电驱动进行发光。通常，发光功能层的主流制作工艺是利用精细金属掩模板(Fine Metal Mask，FMM)来蒸镀发光功能层，而采用溅射工艺和刻蚀工艺来制作第一电极。
基于AR/VR产品特性，要求硅基OLED具有高的分辨率，高分辨率会带来较高的工艺难度。
发明内容
本公开的至少一实施例涉及一种显示基板及其制作方法、显示装置。
第一方面，本公开至少一实施例提供一种显示基板，显示基板包括：衬底基板、第一绝缘层、第一电极图案、连接电极图案、第二电极、发光功能层以及第一填充层；第一绝缘层位于所述衬底基板上；第一电极图案位于所述显示基板的显示区，所述第一电极图案包括彼此间隔的多个第一电极，所述第一电极被配置为接收像素驱动信号；连接电极图案位于所述显示基板的周边区，所述连接电极图案围绕所述第一电极图案；第二电极位于所述显示区和所述周边区，并与所述连接电极图案相连，所述第二电极与所述第一电极图案彼此间隔，所述第二电极被配置为接收第一电源信号；发光功能层位于所述第一电极图案和所述第二电极之间；第一填充层位于所述连接电极图 案和所述第一电极图案之间；所述第一填充层和所述发光功能层为不同的层；所述第一电极图案和所述连接电极图案位于所述第一绝缘层的远离所述衬底基板的一侧并分别与所述第一绝缘层接触，所述第一绝缘层的位于所述第一电极图案和所述连接电极图案之间的部分具有凹槽，所述第一填充层至少部分位于所述凹槽中。
在本公开一实施例提供的显示基板中，所述第一电极图案包括靠近所述连接电极图案的边缘第一电极，所述第一填充层分别与所述连接电极图案和所述边缘第一电极接触。
在本公开一实施例提供的显示基板中，所述连接电极图案呈环形。
在本公开一实施例提供的显示基板中，所述第二电极与所述第一填充层接触。
在本公开一实施例提供的显示基板中，所述第一填充层包括绝缘层。
在本公开一实施例提供的显示基板中，所述第一填充层包括至少一个导电填充部和至少一个绝缘填充部，所述边缘第一电极与所述绝缘填充部接触，所述边缘第一电极与所述导电填充部彼此间隔。
在本公开一实施例提供的显示基板中，所述第一填充层包括多个导电填充部和多个绝缘填充部，所述多个导电填充部和所述多个绝缘填充部交替设置。
在本公开一实施例提供的显示基板中，所述多个导电填充部的图案密度、所述连接电极图案的图案密度和所述第一电极图案的图案密度中至少两个相同。
本公开一实施例提供的显示基板还包括像素定义层，所述像素定义层包括多个像素定义部，所述像素定义部位于相邻第一电极之间。
在本公开一实施例提供的显示基板中，所述第一填充层或所述第一填充层中的至少一个绝缘填充部与所述像素定义层位于同一层。
在本公开一实施例提供的显示基板中，所述第一电极图案与所述连接电极图案位于同一层。
本公开一实施例提供的显示基板还包括第二填充层，所述第二填充层包括至少一个第二填充部，所述连接电极图案包括多个连接电极，所述第二填充部位于相邻连接电极之间。
在本公开一实施例提供的显示基板中，所述第二填充层包括绝缘层。
在本公开一实施例提供的显示基板中，所述第二填充层和所述第一填充层位于同一层。
在本公开一实施例提供的显示基板中，所述发光功能层与所述第一填充层接触。
在本公开一实施例提供的显示基板中，所述发光功能层与部分所述第一填充层接触。
在本公开一实施例提供的显示基板中，所述第一电极为发光元件的阳极，所述第二电极为所述发光元件的阴极。
在本公开一实施例提供的显示基板中，所述衬底基板包括硅晶圆。
本公开至少一实施例还提供一种显示装置，包括第一方面中所述的任一显示基板。
本公开至少一实施例还提供一种显示基板的制作方法，包括：在衬底基板上形成第一绝缘层；形成第一电极图案，所述第一电极图案位于所述显示基板的显示区，所述第一电极图案包括彼此间隔的多个第一电极，所述第一电极被配置为接收像素驱动信号；形成连接电极图案，所述连接电极图案位于所述显示基板的周边区，所述连接电极图案围绕所述第一电极图案；形成第二电极，所述第二电极位于所述显示区和所述周边区，所述第二电极与所述连接电极图案相连，所述第二电极与所述第一电极图案彼此间隔，所述第二电极被配置为接收第一电源信号；形成发光功能层，所述发光功能层位于所述第一电极图案和所述第二电极之间；以及形成第一填充层，所述第一填充层位于所述连接电极图案和所述第一电极图案之间；所述第一填充层和所述发光功能层为不同的层，所述第一电极图案和所述连接电极图案位于所述第一绝缘层的远离所述衬底基板的一侧并分别与所述第一绝缘层接触，所述第一绝缘层的位于所述第一电极图案和所述连接电极图案之间的部分具有凹槽，所述第一填充层至少部分位于所述凹槽中。
在本公开一实施例提供的显示基板的制作方法中，所述第一电极图案包括靠近所述连接电极图案的边缘第一电极，所述第一填充层分别与所述连接电极图案和所述边缘第一电极接触。
在本公开一实施例提供的显示基板的制作方法中，所述第二电极与所述 第一填充层接触。
本公开一实施例提供的显示基板的制作方法还包括形成像素定义层，所述像素定义层包括多个像素定义部，所述第一电极图案包括彼此间隔的多个第一电极；所述像素定义部位于相邻第一电极之间。
在本公开一实施例提供的显示基板的制作方法中，所述像素定义层和所述第一填充层采用同一构图工艺形成，并且所述第一电极图案和所述连接电极图案采用同一构图工艺形成。
在本公开一实施例提供的显示基板的制作方法中，形成所述第一填充层包括形成至少一个导电填充部和形成至少一个绝缘填充部，所述第一电极图案、所述连接电极图案和所述至少一个导电填充部采用同一构图工艺形成；并且所述像素定义层和所述至少一个绝缘填充部采用同一构图工艺形成。
本公开一实施例提供的显示基板的制作方法还包括形成第二填充层，所述第二填充层包括至少一个第二填充部，所述连接电极图案包括多个连接电极，所述第二填充部位于相邻连接电极之间；在形成所述像素定义层和所述至少一个绝缘填充部的同一构图工艺中形成所述第二填充层。
第二方面，本公开至少一实施例提供一种显示基板，包括：第一电极图案、连接电极图案、第二电极以及发光功能层；第一电极图案位于所述显示基板的显示区，并包括彼此间隔的多个第一电极，所述第一电极被配置为接收像素驱动信号；连接电极图案位于所述显示基板的周边区，并包括多个连接电极；第二电极位于所述显示区和所述周边区，并与所述连接电极图案相连，所述第二电极与所述第一电极图案彼此间隔，所述第二电极被配置为接收第一电源信号；发光功能层位于所述第一电极图案和所述第二电极之间；所述连接电极图案围绕所述第一电极图案，所述多个连接电极中至少两个呈彼此隔开的块状。
本公开一实施例提供的显示基板还包括衬底基板和位于所述衬底基板上的第一绝缘层，所述第一电极图案和所述连接电极图案位于所述第一绝缘层的远离所述衬底基板的一侧并与所述第一绝缘层接触。
在本公开一实施例提供的显示基板中，所述第一绝缘层的位于相邻第一电极之间的部分具有第一凹槽，所述第一绝缘层的位于相邻连接电极之间的部分具有第二凹槽，所述第一凹槽和所述第二凹槽在垂直于所述衬底基板的 方向上的尺寸相等。
在本公开一实施例提供的显示基板中，所述连接电极的形状和所述第一电极的形状相同。
在本公开一实施例提供的显示基板中，所述连接电极图案的图案密度和所述第一电极图案的图案密度相同。
本公开一实施例提供的显示基板还包括第一虚设电极图案，所述第一虚设电极图案包括多个第一虚设电极；所述第一虚设电极图案位于所述连接电极图案和所述第一电极图案之间，所述第一虚设电极的形状和所述第一电极的形状相同。
在本公开一实施例提供的显示基板中，所述第一虚设电极图案的图案密度和所述第一电极图案的图案密度相同。
在本公开一实施例提供的显示基板中，所述第一绝缘层的在垂直于所述衬底基板的方向上与所述多个第一虚设电极交叠的部分不设置过孔。
本公开一实施例提供的显示基板还包括第二虚设电极图案，所述第二虚设电极图案包括多个第二虚设电极；所述第二虚设电极图案位于所述连接电极图案的远离所述第一电极图案的一侧，所述第二虚设电极的形状和所述第一电极的形状相同。
在本公开一实施例提供的显示基板中，所述第二虚设电极图案的图案密度和所述第一电极图案的图案密度相同。
在本公开一实施例提供的显示基板中，所述第一绝缘层的在垂直于所述衬底基板的方向上与所述多个第二虚设电极交叠的部分不设置过孔。
本公开一实施例提供的显示基板还包括绝缘填充层，所述绝缘填充层覆盖所述多个第一虚设电极，所述多个第一虚设电极和所述绝缘填充层构成第一填充层，所述第一电极图案包括靠近所述连接电极的边缘第一电极，所述绝缘填充层分别与所述连接电极和所述边缘第一电极接触。
在本公开一实施例提供的显示基板中，所述第二电极与所述绝缘填充层接触。
在本公开一实施例提供的显示基板中，所述边缘第一电极与所述多个第一虚设电极彼此绝缘。
本公开一实施例提供的显示基板还包括像素定义层，所述像素定义层包 括多个像素定义部，所述像素定义部位于相邻第一电极之间。
在本公开一实施例提供的显示基板中，所述绝缘填充层与所述像素定义层位于同一层。
本公开一实施例提供的显示基板还包括第二填充层，所述第二填充层包括至少一个第二填充部，所述第二填充部位于相邻连接电极之间。
在本公开一实施例提供的显示基板中，所述第二填充部分别与所述相邻连接电极接触。
在本公开一实施例提供的显示基板中，所述第二填充层包括绝缘层。
在本公开一实施例提供的显示基板中，所述第二填充层和所述绝缘填充层位于同一层。
在本公开一实施例提供的显示基板中，所述绝缘填充层包括多个绝缘填充部，所述绝缘填充部位于相邻第一虚设电极之间。
在本公开一实施例提供的显示基板中，所述发光功能层与所述第一填充层接触。
在本公开一实施例提供的显示基板中，所述发光功能层与部分所述第一填充层接触。
在本公开一实施例提供的显示基板中，所述连接电极图案呈环形。
在本公开一实施例提供的显示基板中，所述第一电极为发光元件的阳极，所述第二电极为所述发光元件的阴极。
在本公开一实施例提供的显示基板中，所述衬底基板包括硅晶圆。
本公开至少一实施例还提供一种显示装置，包括上述第二方面中任一显示基板。
本公开至少一实施例还提供一种显示基板的制作方法，包括：形成第一电极图案，所述第一电极图案位于所述显示基板的显示区，并包括彼此间隔的多个第一电极，所述第一电极被配置为接收像素驱动信号；形成连接电极图案，所述连接电极图案位于所述显示基板的周边区，并包括多个连接电极；形成第二电极，所述第二电极位于所述显示区和所述周边区，并与所述连接电极图案相连，所述第二电极与所述第一电极图案彼此间隔，所述第二电极被配置为接收第一电源信号；以及形成发光功能层，所述发光功能层位于所述第一电极图案和所述第二电极之间；所述连接电极图案围绕所述第一电极 图案，所述多个连接电极中至少两个呈彼此隔开的块状。
在本公开一实施例提供的显示基板的制作方法中，所述连接电极图案的图案密度和所述第一电极图案的图案密度相同。
本公开一实施例提供的显示基板的制作方法还包括：形成第一虚设电极图案，所述第一虚设电极图案包括多个第一虚设电极；所述第一虚设电极图案位于所述连接电极图案和所述第一电极图案之间；所述第一虚设电极图案的图案密度和所述第一电极图案的图案密度相同。
本公开一实施例提供的显示基板的制作方法还包括形成绝缘填充层，其中，所述绝缘填充层覆盖所述多个第一虚设电极，所述多个第一虚设电极和所述绝缘填充层构成第一填充层，所述第一电极图案包括靠近所述连接电极的边缘第一电极，所述绝缘填充层分别与所述连接电极和所述边缘第一电极接触。
本公开一实施例提供的显示基板的制作方法还包括：形成第二虚设电极图案，其中，所述第二虚设电极图案包括多个第二虚设电极；所述第二虚设电极图案位于所述连接电极图案的远离所述第一电极图案的一侧，所述第二虚设电极图案的图案密度和所述第一电极图案的图案密度相同。
本公开一实施例提供的显示基板的制作方法还包括：形成像素定义层，其中，所述像素定义层包括多个像素定义部，所述像素定义部位于相邻第一电极之间。
本公开一实施例提供的显示基板的制作方法还包括：形成第二填充层，其中，所述第二填充层包括至少一个第二填充部，所述第二填充部位于相邻连接电极之间。
本公开一实施例提供的显示基板的制作方法还包括形成第一虚设电极图案、第二虚设电极图案、像素定义层、绝缘填充层和第二填充层；所述第一虚设电极图案包括多个第一虚设电极，所述第一虚设电极图案位于所述连接电极图案和所述第一电极图案之间；所述第二虚设电极图案包括多个第二虚设电极；所述第二虚设电极图案位于所述连接电极图案的远离所述第一电极图案的一侧，所述像素定义层包括多个像素定义部，所述像素定义部位于相邻第一电极之间；所述绝缘填充层覆盖所述多个第一虚设电极；所述第二填充层包括至少一个第二填充部，所述第二填充部位于相邻连接电极之间；采 用同一构图工艺形成所述像素定义层、所述绝缘填充层和所述第二填充层；采用同一构图工艺形成所述第一电极图案、所述连接电极图案、所述第一虚设电极图案和所述第二虚设电极图案。
在本公开一实施例提供的显示基板的制作方法中，所述绝缘填充层包括多个绝缘填充部，所述绝缘填充部位于相邻第一虚设电极之间。
第三方面，本公开至少一实施例还提供一种显示基板，包括：第一电极图案、连接电极图案、第二电极、发光功能层以及第一虚设电极图案；第一电极图案位于所述显示基板的显示区，并包括彼此间隔的多个第一电极，所述第一电极被配置为接收像素驱动信号；连接电极图案位于所述显示基板的周边区；第二电极位于所述显示区和所述周边区，并与所述连接电极图案相连，所述第二电极与所述第一电极图案彼此间隔，所述第二电极被配置为接收第一电源信号；发光功能层位于所述第一电极图案和所述第二电极之间；第一虚设电极图案包括多个第一虚设电极，所述连接电极图案围绕所述第一电极图案，所述第一虚设电极图案位于所述连接电极图案和所述第一电极图案之间，所述多个第一虚设电极中的至少两个呈彼此隔开的块状。
本公开一实施例提供的显示基板还包括衬底基板和位于所述衬底基板上的第一绝缘层，所述第一电极图案、所述连接电极图案和所述第一虚设电极图案位于所述第一绝缘层的远离所述衬底基板的一侧并与所述第一绝缘层接触。
在本公开一实施例提供的显示基板中，所述第一绝缘层的在垂直于所述衬底基板的方向上与所述多个第一虚设电极交叠的部分不设置过孔。
在本公开一实施例提供的显示基板中，所述第一虚设电极浮置。
在本公开一实施例提供的显示基板中，所述连接电极图案包括多个连接电极，所述连接电极呈块状。
在本公开一实施例提供的显示基板中，所述连接电极的形状与所述第一电极的形状相同，所述第一虚设电极的形状与所述第一电极的形状相同。
在本公开一实施例提供的显示基板中，所述连接电极图案的图案密度与所述第一电极图案的图案密度相同、所述第一虚设电极图案的图案密度和所述第一电极图案的图案密度相同。
在本公开一实施例提供的显示基板还包括第二虚设电极图案，所述第二 虚设电极图案包括多个第二虚设电极；所述第二虚设电极图案位于所述连接电极图案的远离所述第一电极图案的一侧。
在本公开一实施例提供的显示基板中，所述第一绝缘层的在垂直于所述衬底基板的方向上与所述多个第二虚设电极交叠的部分不设置过孔。
在本公开一实施例提供的显示基板中，所述第二虚设电极呈块状，所述第二虚设电极的形状和所述第一电极的形状相同。
在本公开一实施例提供的显示基板中，所述第二虚设电极图案的图案密度和所述第一电极图案的图案密度相同。
在本公开一实施例提供的显示基板中，所述第一绝缘层的位于相邻第一电极之间的部分、所述第一绝缘层的位于相邻连接电极之间的部分至少之一具有凹槽。
本公开一实施例提供的显示基板还包括绝缘填充层，所述绝缘填充层覆盖所述多个第一虚设电极，所述多个第一虚设电极和所述绝缘填充层构成第一填充层，所述第一电极图案包括靠近所述连接电极的边缘第一电极，所述绝缘填充层分别与所述连接电极和所述边缘第一电极接触。
在本公开一实施例提供的显示基板中，所述第二电极与所述绝缘填充层接触。
在本公开一实施例提供的显示基板中，所述边缘第一电极与所述多个第一虚设电极彼此绝缘。
本公开一实施例提供的显示基板还包括像素定义层，所述像素定义层包括多个像素定义部，所述像素定义部位于相邻第一电极之间。
在本公开一实施例提供的显示基板中，所述绝缘填充层与所述像素定义层位于同一层。
本公开一实施例提供的显示基板还包括第二填充层，所述第二填充层包括至少一个第二填充部，所述第二填充部位于相邻连接电极之间。
在本公开一实施例提供的显示基板中，所述第二填充部分别与所述相邻连接电极接触。
在本公开一实施例提供的显示基板中，所述第二填充层包括绝缘层。
在本公开一实施例提供的显示基板中，所述第二填充层和所述绝缘填充层位于同一层。
本公开一实施例提供的显示基板还包括传感器电极图案，所述传感器电极图案包括多个传感器电极；所述传感器电极呈块状，所述传感器电极被配置为接收检测驱动信号。
在本公开一实施例提供的显示基板中，所述传感器电极的形状和所述第一电极的形状相同。
在本公开一实施例提供的显示基板中，所述传感器电极图案的图案密度和所述第一电极图案的图案密度相同。
在本公开一实施例提供的显示基板还包括第三填充层，所述第三填充层包括多个第三填充部，所述第三填充部位于相邻传感器电极、相邻的所述传感器电极和所述第一虚设电极中至少之一之间。
在本公开一实施例提供的显示基板中，所述发光功能层与所述第一填充层接触。
在本公开一实施例提供的显示基板中，所述发光功能层与部分所述第一填充层接触。
在本公开一实施例提供的显示基板中，所述连接电极图案呈环形。
在本公开一实施例提供的显示基板中，所述第一电极为发光元件的阳极，所述第二电极为所述发光元件的阴极。
在本公开一实施例提供的显示基板中，所述衬底基板包括硅晶圆。
本公开至少一实施例还提供一种显示装置，包括第三方面中所述的任一显示基板。
本公开至少一实施例还提供一种显示基板的制作方法，包括：形成第一电极图案，所述第一电极图案位于所述显示基板的显示区，并包括彼此间隔的多个第一电极，所述第一电极被配置为接收像素驱动信号；形成连接电极图案，所述连接电极图案位于所述显示基板的周边区；形成第二电极，所述第二电极位于所述显示区和所述周边区，并与所述连接电极图案相连，所述第二电极与所述第一电极图案彼此间隔，所述第二电极被配置为接收第一电源信号；形成发光功能层，所述发光功能层位于所述第一电极图案和所述第二电极之间；以及形成第一虚设电极图案，所述第一虚设电极图案包括多个第一虚设电极；所述连接电极图案围绕所述第一电极图案，所述第一虚设电极图案位于所述连接电极图案和所述第一电极图案之间，所述多个第一虚设 电极中的至少两个呈彼此隔开的块状。
在本公开一实施例提供的显示基板的制作方法中，所述第一虚设电极呈块状，所述第一虚设电极图案的图案密度和所述第一电极图案的图案密度相同。
本公开一实施例提供的显示基板的制作方法还包括：形成第二虚设电极图案，所述第二虚设电极图案包括多个第二虚设电极；所述第二虚设电极图案位于所述连接电极图案的远离所述第一电极图案的一侧，所述第二虚设电极图案的图案密度和所述第一电极图案的图案密度相同。
本公开一实施例提供的显示基板的制作方法还包括形成绝缘填充层，其中，所述绝缘填充层覆盖所述多个第一虚设电极，所述多个第一虚设电极和所述绝缘填充层构成第一填充层，所述第一电极图案包括靠近所述连接电极的边缘第一电极，所述绝缘填充层分别与所述连接电极和所述边缘第一电极接触。
本公开一实施例提供的显示基板的制作方法还包括：形成传感器电极图案，其中，所述传感器电极图案包括多个传感器电极；所述传感器电极呈块状，所述传感器电极图案的图案密度和所述第一电极图案的图案密度相同。
本公开一实施例提供的显示基板的制作方法还包括：形成像素定义层，其中，所述像素定义层包括多个像素定义部，所述像素定义部位于相邻第一电极之间。
本公开一实施例提供的显示基板的制作方法还包括：形成第二填充层，其中，所述第二填充层包括至少一个第二填充部，所述第二填充部位于相邻连接电极之间。
本公开一实施例提供的显示基板的制作方法还包括：形成第三填充层，所述第三填充层包括多个第三填充部，所述第三填充部位于相邻传感器电极、相邻的所述传感器电极和所述第一虚设电极中至少之一之间。
本公开一实施例提供的显示基板的制作方法还包括形成第二虚设电极图案、传感器电极图案、像素定义层、绝缘填充层、第二填充层和第三填充层；所述传感器电极图案包括多个传感器电极；所述第二虚设电极图案包括多个第二虚设电极；所述第二虚设电极图案位于所述连接电极图案的远离所述第一电极图案的一侧；所述像素定义层包括多个像素定义部，所述像素定义部 位于相邻第一电极之间；所述绝缘填充层覆盖所述多个第一虚设电极；所述第二填充层包括至少一个第二填充部，所述第二填充部位于相邻连接电极之间；所述第三填充层包括多个第三填充部，所述第三填充部位于相邻传感器电极、相邻的所述传感器电极和所述第一虚设电极中至少之一之间；采用同一构图工艺形成所述像素定义层、所述绝缘填充层、所述第二填充层和所述第三填充层；采用同一构图工艺形成所述第一电极图案、所述连接电极图案、所述第一虚设电极图案、所述第二虚设电极图案和所述传感器电极图案。
在本公开一实施例提供的制作方法中，所述绝缘填充层包括多个绝缘填充部，所述绝缘填充部位于相邻第一虚设电极之间。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种有机发光二极管显示基板的平面示意图；
图2A至图2D为一种有机发光二极管显示基板中第一电极图案的制作方法的示意图；
图3为一种有机发光二极管显示基板的平面示意图；
图4为一种有机发光二极管显示基板的剖视示意图；
图5A为本公开一实施例提供的一种显示基板的剖视图；
图5B为本公开一实施例提供的一种显示基板的剖视图；
图6A为本公开一实施例提供的一种显示基板的剖视示意图；
图6B为本公开一实施例提供的一种显示基板的剖视示意图；
图7A为本公开一实施例提供的一种显示基板的剖视示意图；
图7B为本公开一实施例提供的一种显示基板的剖视示意图
图8A为本公开一实施例提供的一种显示基板的剖视示意图；
图8B为本公开一实施例提供的一种显示基板的剖视图；
图9为本公开一实施例提供的显示基板中的第一电极图案、连接电极图案和导电填充部的俯视图；
图10为本公开一实施例提供的显示基板中的第一填充层、第二填充层和 像素定义层的俯视图；
图11为本公开一实施例提供的一种显示基板的区域划分示意图；
图12为本公开一实施例提供的一种显示基板的俯视示意图；
图13A为本公开一实施例提供的一种显示基板的剖视示意图；
图13B为本公开一实施例提供的一种显示基板的剖视示意图；
图14A为本公开一实施例提供的显示基板的剖视图；
图14B为本公开一实施例提供的显示基板的剖视图；
图15为本公开一实施例提供的显示基板中的绝缘填充层、第二填充层和像素定义层的俯视图；
图16为本公开一实施例提供的一种显示基板的区域划分示意图；
图17A为本公开一实施例提供的一种显示基板的剖视示意图；
图17B为本公开一实施例提供的一种显示基板的剖视示意图；
图18为本公开一实施例提供的一种显示基板的剖视示意图；
图19为本公开一实施例提供的显示基板中的像素定义薄膜经构图后形成的结构的俯视图；
图20为本公开一实施例提供的显示基板的剖视图；
图21为本公开的实施例提供的显示基板的制作方法中形成的导电薄膜的示意图；
图22为本公开的实施例提供的显示基板的制作方法中形成的像素定义薄膜的示意图；以及
图23为本公开一些实施例提供的一种硅基有机发光显示面板的电路原理示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属 领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在有机发光二极管显示装置的制作工艺中，第一电极的制作工艺通常包括：采用溅射工艺在衬底基板上形成导电层；在导电层的远离衬底基板的一侧形成光刻胶图案；以该光刻胶图案为掩膜对导电层进行刻蚀以形成第一电极图案、以及去除光刻胶图案。例如，导电层的材料包括氧化铟锡，但不限于此。
在研究中，本申请的发明人发现，在对导电层进行刻蚀的过程中，该有机发光二极管显示装置的显示区需要形成第一电极图案，而该有机发光二极管显示装置的周边区的导电层部分需要被完全或部分去除，显示区和周边区的图形密度不同，从而导致在同一干刻工艺下，在单位面积内，显示区和周边区需要被刻蚀去掉的导电材料的量差异较大。而干刻工艺的选择性较差，从而一方面容易导致最后形成的第一电极图案的工艺膜厚、和尺寸均一性难以管控，另一方面容易导致第一电极图案下的绝缘层发生过刻现象。
图1为一种有机发光二极管显示基板的平面示意图。如图1所示，该有机发光二极管显示基板10包括显示区11和围绕显示区11的周边区12；显示区11设置有第一电极图案13；第一电极图案13包括多个第一电极130，从而驱动该发光二极管显示基板10中的发光层(未示出)进行发光。
图2A-图2D为一种有机发光二极管显示基板中第一电极图案的制作方法的示意图。如图2A所示，在衬底基板16上形成绝缘层15，在绝缘层15的远离衬底基板16的一侧形成导电层17；如图2B所示，在导电层17的远离绝缘层15的一侧形成光刻胶图案18；如图2C所示，以光刻胶图案18为掩膜对导电层17进行刻蚀以形成第一电极图案13；如图2D所示，剥离光刻胶图案18。
如图1和图2A-图2D所示，该有机发光二极管显示基板包括显示区和周边区，导电层的位于显示区的部分被干刻以形成第一电极图案，而导电层的位于周边区的部分被完全去除，从而导致在同一干刻工艺下，在单位面积内，显示区和周边区需要被刻蚀去掉的导电材料的量差异较大，从而导致刻蚀的不均匀性。当设置足够刻蚀掉导电层的位于周边区的部分的刻蚀参数(例如，干刻气体浓度、流速等)时，导电层的位于显示区的部分容易产生过刻现象，从而导致所形成的第一电极图案的工艺膜厚、和尺寸均一性难以管控，另一方面，由于干刻工艺的选择性较差，从而容易导致第一电极图案下的绝缘层也被刻蚀，造成各种不良。
通常，周边区的导电图案的图案密度(Pattern density)与显示区的第一电极图案的图案密度不相同，并且周边区和显示区的图案密度有很大差异。例如，周边区的导电图案的图案密度小于显示区的第一电极图案的图案密度，周边区可不设置导电图案或设置少量的导电图案。对导电层17进行干刻时，显示区和周边区的导电层17的表面附近的活性基团、侧壁保护物质等的浓度是均匀分布的，因此，图案密度高的区域单位面积上的活性基团和侧壁保护物质要比图案密度低的区域单位面积上的活性基团和侧壁保护物质少，从而，图案密度高的区域的刻蚀深度小于图案密度低的区域的刻蚀深度，这就是所谓的负载效应(Loading effect)，从而导致周边区的刻蚀深度大于显示区的刻蚀深度，可使得导电层17的位于周边区的部分和导电层17的位于显示区的部分的下方的绝缘层材料的损失(Loss)量有较大差异。
发明人发现，绝缘层15的位于周边区12的部分的损失量大于绝缘层15的位于显示区11的部分的损失量。当绝缘层15的位于周边区12的部分的损失量较大时，容易造成短路或后续膜层接触不良。
图3为一种有机发光二极管显示基板的平面示意图。与图1所示的显示基板相比，图3所示的显示基板的周边区12包括连接电极区12a，从而，周边区12包括三个区域：连接电极区12a、第一虚设区121和第二虚设区122。第一虚设区121位于连接电极区12a和显示区11之间，第二虚设区122位于连接电极区12a的远离显示区11的一侧。如图3所示，第二虚设区122位于连接电极区12a的远离第一虚设区121的一侧。设置第一虚设区121可避免显示区和连接电极区12a的需彼此绝缘的元件短路，设置第二虚设区122可 利于显示基板的封装，利于提高封装效果。
图4为一种有机发光二极管显示基板的剖视示意图。图4可为图3的剖视图。如图4所示，衬底基板16上设有绝缘层01，绝缘层01中设有过孔011和过孔012，过孔011和过孔012中填充导电材料以分别形成连接件，导电材料包括金属例如钨，但不限于此。绝缘层01上为位于同一层的连接电极14和第一电极图案13。第一电极图案13包括多个第一电极130。第一电极130通过位于过孔011中的连接件与下方的元件例如薄膜晶体管的漏极(图中未示出)相连，连接电极14通过位于过孔012中的连接件与下方的连接线(图中未示出)相连。如图4所示，在形成连接电极14和第一电极图案13之后形成像素定义层01，像素定义层01包括多个像素定义部010，相邻的第一电极130之间设有多个像素定义部010中的一个。例如，多个像素定义部010可彼此相连并一体形成，但不限于此。像素定义层01可包括多个镂空区以分别暴露多个第一电极130。像素定义层01被配置为定义多个子像素。例如，每个镂空区对应一个子像素。例如，每个第一电极130对应一个子像素。如图4所示，形成像素定义层01后形成发光功能层03，发光功能层03覆盖第一电极图案13和像素定义层01。如图4所示，形成发光功能层03后，形成第二电极04，第二电极04与第一电极图案13彼此彼此间隔，以避免第二电极04和第一电极130直接相连，第二电极04与连接电极14相连。例如，第一电极130可采用透明导电材料制作，例如，透明导电材料包括氧化铟锡，但不限于此。
当连接电极与第一电极图案同层形成时，导电层的位于第一虚设区121的部分以及导电层的位于第二虚设区122的部分需要整块刻蚀，也存在工艺上刻蚀不均匀性。
如图4所示，在发光功能层03的靠近连接电极区12a的边界位置处，第二电极04存在较大的高度落差，容易造成第二电极断裂以及降低第二电极与连接电极的连接可靠性。通常的显示基板只在显示区具有像素定义层，周边区(非像素区)无像素定义层材料，从而，导致第二电极与连接电极的接触不平坦。第二电极可采用金属制作。例如，第二电极可采用镁、银等至少之一的金属材料来制作，但不限于此，可根据需要而定。
为了解决上述提出的第二电极存在较大的高度落差，容易造成第二电极 断裂以及降低第二电极与连接电极的连接可靠性以及刻蚀不均匀性至少之一的问题，本公开的实施例提供一种显示基板及其制作方法、显示装置。
第一方面，本公开的实施例通过设置第一填充层104a来减小第二电极106的高度落差和/或提高刻蚀均匀性。
图5A为本公开一实施例提供的一种显示基板的剖视图。如图5A所示，显示基板100a包括：第一电极图案103、连接电极图案103a、第二电极106和第一填充层104a。连接电极图案103a围绕第一电极图案103(参见图3)。第二电极106与连接电极图案103a相连。第二电极106与第一电极图案103彼此间隔。第二电极106被配置为接收第一电源信号。第一填充层104a位于连接电极图案103a和第一电极图案103之间。
例如，如图5A所示，第二电极106与第一电极图案103不接触。例如，如图5A所示，显示基板包括衬底基板101。第二电极106与第一电极图案103在平行于衬底基板101的方向上彼此间隔，并且第二电极106与第一电极图案103在垂直于衬底基板101的方向上彼此间隔。例如，连接电极图案103a和第一电极图案103在平行于衬底基板101的方向上彼此间隔。
如图5A所示，显示基板100a包括：显示区11和周边区12，周边区12围绕显示区11。第一电极图案103位于显示基板的显示区11；连接电极图案103a位于显示基板的周边区12，第二电极106位于显示区11和周边区12。例如，第二电极106呈块状，从显示区11延伸到周边区12。
本公开的实施例提供的显示基板，通过设置第一填充层104a，可减小第二电极106的高度落差，提高第二电极106和连接电极图案103a的连接可靠性。
例如，如图5A所示，第一电极图案103包括彼此间隔的多个第一电极1030，第一电极1030被配置为接收像素驱动信号。第一电极图案103包括边缘第一电极103e，边缘第一电极103e靠近连接电极图案103a，第一填充层104a分别与连接电极图案103a和边缘第一电极103e接触，例如，第一填充层104a为绝缘层，从而利于边缘第一电极103e与第二电极106的彼此分隔。例如，边缘第一电极103e为最靠近连接电极图案103a的第一电极1030。
如图5A所示，在本公开一实施例提供的显示基板中，第一填充层104a的侧面分别与连接电极图案103a的侧面和边缘第一电极103e的侧面接触。
如图5A所示，在本公开一实施例提供的显示基板中，为了减小第二电极的高度落差，第二电极106与第一填充层104a接触。
图5B为本公开一实施例提供的一种显示基板的剖视图。图5B所示的显示基板100aa与图5A所示的显示基板100a相比，区别在于：显示基板100aa的第一绝缘层102中设有凹槽G。凹槽G在刻蚀导电薄膜的过程中形成，凹槽G的设置可以利于相邻第一电极彼此间隔，利于提高刻蚀工艺稳定性。如图5B所示，第一绝缘层102中的位于边缘第一电极103e和连接电极图案103a之间的凹槽G在垂直于衬底基板101的方向上的尺寸大于第一绝缘层102中的位于相邻第一电极1030之间的凹槽G或第一绝缘层102中的位于相邻第一电极1030之间的凹槽G在垂直于衬底基板101的方向上的尺寸。图5B所示，第一填充层104a的一部分填充在边缘第一电极103e和连接电极图案103a之间的凹槽G内。
图6A为本公开一实施例提供的一种显示基板的剖视示意图。如图6A所示，显示基板100b与显示基板100a的区别在于：连接电极图案103a包括多个连接电极103a0。如图6A所示，连接电极图案103a包括靠近第一电极图案103的边缘连接电极103ae，第一填充层104a的侧面分别与边缘连接电极103ae的侧面和边缘第一电极103e的侧面接触。边缘连接电极103ae为最靠近第一电极图案103的连接电极103a0。
图6B为本公开一实施例提供的一种显示基板的剖视图。图6B所示的显示基板100bb与图6A所示的显示基板100b相比，区别在于：显示基板100bb的第一绝缘层102中设有凹槽G。图6B所示，第一绝缘层102中的位于边缘第一电极103e和靠近边缘第一电极103e的连接电极103a0之间的凹槽G在垂直于衬底基板101的方向上的尺寸大于第一绝缘层102中的位于相邻第一电极1030之间的凹槽G在垂直于衬底基板101的方向上的尺寸。图6B所示，第一填充层104a的一部分填充在边缘第一电极103e和连接电极图案103a之间的凹槽G内。
图7A为本公开一实施例提供的一种显示基板的剖视示意图。如图7A所示，显示基板100c与显示基板100a的区别在于：第一填充层104a包括至少一个导电填充部103d1和至少一个绝缘填充部104a0，边缘第一电极103e与绝缘填充部104a0接触。例如，边缘第一电极103e与多个导电填充部103d1 彼此绝缘。图7A中示出了三个绝缘填充部104a0和两个导电填充部103d1。本公开的实施例中，绝缘填充部104a0的个数和导电填充部103d1的个数不限于图中所示，可根据需要而定。例如，多个导电填充部103d1的图案密度和第一电极图案103的图案密度相同，但不限于此。
如图7A所示，在本公开一实施例提供的显示基板中，第一填充层104a包括多个导电填充部103d1和多个绝缘填充部104a0，多个导电填充部103d1和多个绝缘填充部104a0交替设置。例如，绝缘填充部104a0位于相邻导电填充部103d1。
图7B为本公开一实施例提供的一种显示基板的剖视图。图7B所示的显示基板100cc与图7A所示的显示基板100c相比，区别在于：显示基板100cc的第一绝缘层102中设有凹槽G。图7B所示，第一绝缘层102中的位于边缘第一电极103e和靠近边缘第一电极103e的连接电极103a0之间的凹槽G在垂直于衬底基板101的方向上的尺寸等于第一绝缘层102中的位于相邻第一电极1030之间的凹槽G在垂直于衬底基板101的方向上的尺寸，并且第一绝缘层102中的位于相邻连接电极103a0之间的凹槽G在垂直于衬底基板101的方向上的尺寸等于第一绝缘层102中的位于相邻第一电极1030之间的凹槽G在垂直于衬底基板101的方向上的尺寸。图7B所示，绝缘填充部104a0的一部分填充在第一绝缘层102中的位于相邻连接电极103a0之间的凹槽G中。图7B所示，绝缘填充部104a0的一部分填充在第一绝缘层102中的位于连接电极图案103a和导电填充部103d1之间的凹槽G中。图7B所示，绝缘填充部104a0的一部分填充在第一绝缘层102中的位于边缘第一电极103e和导电填充部103d1之间的凹槽G中。
图8A为本公开一实施例提供的一种显示基板的剖视示意图。如图8A所示，显示基板100d与显示基板100c的区别在于：连接电极图案103a包括多个连接电极103a0，显示基板100d还包括第二填充层104b，第二填充层104b包括至少一个第二填充部104b0，第二填充部104b0位于相邻连接电极103a0之间。例如，第二填充部104b0分别与该相邻连接电极103a0接触。例如，多个导电填充部103d1的图案密度、第一电极图案103的图案密度和多个连接电极103a0的图案密度相同，但不限于此。
图8B为本公开一实施例提供的一种显示基板的剖视图。图8B所示的显 示基板100dd与图8A所示的显示基板100d相比，区别在于：显示基板100dd的第一绝缘层102中设有凹槽G。图8B所示，第一绝缘层102中包括多个凹槽G，多个凹槽G在垂直于衬底基板101的方向上的尺寸均相同。第一绝缘层102中所有凹槽G在垂直于衬底基板101的方向上的尺寸均相同。例如，第一绝缘层102中的位于边缘第一电极103e和靠近边缘第一电极103e的连接电极103a0之间的凹槽G在垂直于衬底基板101的方向上的尺寸等于第一绝缘层102中的位于相邻第一电极1030之间的凹槽G在垂直于衬底基板101的方向上的尺寸，第一绝缘层102中的位于相邻导电填充部103d1之间的凹槽G在垂直于衬底基板101的方向上的尺寸等于第一绝缘层102中的位于相邻第一电极1030之间的凹槽G在垂直于衬底基板101的方向上的尺寸，第一绝缘层102中的位于相邻第一连接电极103a0之间的凹槽G在垂直于衬底基板101的方向上的尺寸等于第一绝缘层102中的位于相邻第一电极1030之间的凹槽G在垂直于衬底基板101的方向上的尺寸。
如图8A所示，在本公开一实施例提供的显示基板中，第二填充层104b为绝缘层。例如，第二填充层104b和第一填充层104a位于同一层，可由同一膜层采用同一构图工艺形成，以节省制作工艺。
例如，如图8A所示，第一电极图案103的图案密度、多个导电填充部103d1的图案密度和连接电极图案103a的图案密度均相同，从而可提高刻蚀均匀性，进而提高第二电极106与连接电极图案103a的连接可靠性，提高显示基板的性能。
如图5A至图8A所示，在本公开的实施例提供的显示基板中，显示基板还包括发光功能层105，发光功能层105位于第一电极图案103和第二电极106之间，发光功能层105与第一填充层104a为不同的层。例如，发光功能层105与第一填充层104a接触。例如，第一电极图案103和第二电极106通过第一填充层104a和发光功能层105彼此间隔。
如图5A至图8A所示，在本公开一实施例提供的显示基板中，发光功能层105与部分第一填充层104a接触。
如图5A至图8A所示，在本公开一实施例提供的显示基板中，显示基板还包括像素定义层104，像素定义层104包括多个像素定义部1040；多个像素定义部1040中的每个位于相邻第一电极1030之间。例如，多个第一电极 1030彼此间隔。例如，多个第一电极1030在平行于衬底基板101的方向上彼此间隔。例如，多个第一电极1030彼此独立，彼此分隔。
如图5A至图8A所示，在本公开一实施例提供的显示基板中，第一电极图案103与连接电极图案103a位于同一层，可由同一膜层采用同一构图工艺形成，以节省制作工艺。
如图5A至图8A所示，显示基板还包括衬底基板101，以及位于衬底基板101上的第一绝缘层102。第一绝缘层102包括第一过孔V1和第二过孔V2。第一过孔V1和第二过孔V2中填充导电材料以分别形成连接件，导电材料包括金属例如钨，但不限于此。第一绝缘层102上为位于同一层的连接电极图案103a和第一电极图案103。第一电极图案103包括多个第一电极1030。第一电极1030通过位于第二过孔V2中的连接件与下方的元件例如薄膜晶体管的漏极(图中未示出)相连，连接电极103a0或连接电极图案103a通过位于第一过孔V1中的连接件与下方的连接线(图中未示出)相连。如图5B、图6B、图7B至图8B所示，第一电极图案103和连接电极图案103a位于第一绝缘层102的远离衬底基板101的一侧并分别与第一绝缘层102接触，第一绝缘层102的位于第一电极图案103和连接电极图案103a之间的部分具有凹槽，第一填充层104a至少部分位于凹槽G中。
如图5A至图8A所示，连接电极图案103a和第一电极图案103分别与第一绝缘层102接触。
如图5A至图8A所示，周边区12包括第一虚设区121和第二虚设区122。第一虚设区121位于连接电极区12a和显示区11之间，第二虚设区122位于连接电极区12a的远离显示区11的一侧。
如图5A至图8A所示，第一填充层104a在衬底基板101上的正投影与发光功能层105在衬底基板101上的正投影部分重叠。
例如，如图5A和图6A所示，第一填充层104a与像素定义层104位于同一层，可由同一膜层采用同一构图工艺形成，以节省制作工艺。
如图7A所示，在本公开一实施例提供的显示基板中，至少一个绝缘填充部104a0与像素定义层104位于同一层，可由同一膜层采用同一构图工艺形成，以节省制作工艺。
如图7A和图8A所示，在本公开一实施例提供的显示基板中，第一电极 图案103、至少一个导电填充部103d1与连接电极图案103a位于同一层，可由同一膜层采用同一构图工艺形成，以节省制作工艺。
例如，如图8A所示，第二填充层104b、第一填充层104a和像素定义层104位于同一层，可由同一膜层采用同一构图工艺形成，以节省制作工艺。
如图7A至图8A所示，多导电填充部103d1、连接电极图案103a和第一电极图案103分别与第一绝缘层102接触。
如图7A至图8A所示，第一绝缘层102的位于导电填充部103d1正下方的部分不设置过孔。第一绝缘层102的位于连接电极103a0正下方的部分设置第一过孔V1。第一绝缘层102的位于第一电极1030正下方的部分设置第二过孔V2。
例如，第一电极图案中的第一电极可为发光元件的阳极，第二电极可为发光元件的阴极。连接电极与第二电极相连，并与第一电极彼此间隔设置。即，发光元件的两个电极可分别为第一电极和第二电极。连接电极可呈环状，此情况下，连接电极可称作阴极环。发光元件可包括发光功能层。发光功能层包括发光层，发光功能层还可以包括空穴传输层、空穴注入层、电子传输层和电子注入层至少之一，有机电致发光元件可在第一电极和第二电极的电驱动进行发光。发光元件例如包括有机发光二极管，但不限于此。
图9为本公开一实施例提供的显示基板中的第一电极图案、连接电极图案和导电填充部的俯视图。如图9所示，第一电极图案103的图案密度、连接电极图案103的图案密度和多个导电填充部103d1的图案密度可相同。图9示出了连接电极103a0、导电填充部103d1和第一电极1030。例如，如图9所示，第一电极1030的形状、连接电极1030的形状和导电填充部103d1的形状可相同，但不限于此。例如，图9中位于连接电极区12a内的每个连接电极103a0都进行外连接。即，每个连接电极103a0都与位于其正下方的过孔中的连接件相连。每个连接电极103a0都与和该连接电极103a0接触的第一绝缘层中的过孔中的连接件相连。例如，与每个导电填充部103d1接触的绝缘层中位于导电填充部103d1下方的部分在对应导电填充部103d1的位置不设置过孔。例如，连接电极图案103a呈环形。
图10为本公开一实施例提供的显示基板中的第一填充层、第二填充层和像素定义层的俯视图。图10示出了第一填充层104a、第二填充层104b和像 素定义层104。如图10所示，像素定义薄膜经构图后的结构包括多个镂空区HR。像素定义薄膜可整面覆盖衬底基板101。多个镂空区HR包括位于显示区11的镂空区HR0、位于第一虚设区121的镂空区HR1和位于连接电极区12a的镂空区HR2。镂空区HR0被配置为暴露第一电极1030，镂空区HR1被配置为暴露导电填充部103d1，镂空区HR2被配置为暴露连接电极103a0。
图9和图10所示的俯视图可对应图8A所示的显示面板，但不限于此。图9和图10中的第二虚设区121内也可以设置第二虚设电极图案，第二虚设电极图案可包括多个第二虚设电极，第二虚设电极图案的图案密度可与第一电极图案的密度相同。
本公开至少一实施例还提供一种显示装置，包括上述第一方面中任一显示基板。显示装置例如包括微OLED显示装置，但不限于此。
本公开至少一实施例还提供一种显示基板的制作方法包括：在衬底基板上形成第一绝缘层；形成第一电极图案103，第一电极图案103位于显示区11，第一电极图案103包括彼此间隔的多个第一电极1030，第一电极1030被配置为接收像素驱动信号；形成连接电极图案103a，连接电极图案103a位于周边区12(周边区12中的连接电极区12a)，连接电极图案103a围绕第一电极图案103；形成第二电极106，第二电极106位于显示区11和周边区12，第二电极106与连接电极图案103a相连，第二电极106与第一电极图案103彼此间隔，第二电极被配置为接收第一电源信号；形成发光功能层105，发光功能层105位于第一电极图案103和第二电极106之间；以及形成第一填充层104a，第一填充层104a位于连接电极图案103a和第一电极图案103之间；第一填充层104a和发光功能层105为不同的层，所述第一电极图案和所述连接电极图案位于所述第一绝缘层的远离所述衬底基板的一侧并分别与所述第一绝缘层接触，所述第一绝缘层的位于所述第一电极图案和所述连接电极图案之间的部分具有凹槽，所述第一填充层至少部分位于所述凹槽中。
在本公开一实施例提供的显示基板的制作方法中，第一电极图案包括靠近连接电极图案的边缘第一电极，第一填充层分别与连接电极图案和边缘第一电极接触。
在本公开一实施例提供的显示基板的制作方法中，第二电极与第一填充 层接触。
本公开一实施例提供的显示基板的制作方法还包括形成像素定义层，其中，像素定义层包括多个像素定义部，第一电极图案包括彼此间隔的多个第一电极；像素定义部位于相邻第一电极之间。
在本公开一实施例提供的显示基板的制作方法中，像素定义层和第一填充层采用同一构图工艺形成，并且第一电极图案和连接电极图案采用同一构图工艺形成。
在本公开一实施例提供的显示基板的制作方法中，形成第一填充层包括形成至少一个导电填充部和形成至少一个绝缘填充部，第一电极图案、连接电极图案和至少一个导电填充部采用同一构图工艺形成；并且像素定义层和至少一个绝缘填充部采用同一构图工艺形成。
本公开一实施例提供的显示基板的制作方法还包括形成第二填充层，其中，第二填充层包括至少一个第二填充部，连接电极图案包括多个连接电极，第二填充部位于相邻连接电极之间；在形成像素定义层和至少一个绝缘填充部的同一构图工艺中形成第二填充层。
在本公开一实施例提供的显示基板的制作方法中，形成第一填充层104a包括形成至少一个导电填充部103d1和形成至少一个绝缘填充部104a0，边缘第一电极103e与绝缘填充部104a0接触，边缘第一电极103e与导电填充部103d1彼此绝缘。边缘第一电极103e靠近连接电极图案103a。例如，边缘第一电极103e为最靠近连接电极图案103a的第一电极1030。
在本公开一实施例提供的显示基板的制作方法中，形成第一填充层104a包括形成至少一个导电填充部103d1和形成至少一个绝缘填充部104a0。
在本公开一实施例提供的显示基板的制作方法中，形成第一填充层104a包括形成多个导电填充部103d1和形成多个绝缘填充部104a0，多个导电填充部103d1和多个绝缘填充部104a0交替设置。
在本公开一实施例提供的显示基板的制作方法中，该制作方法还包括形成像素定义层104，形成像素定义层104包括形成多个像素定义部1040，第一电极图案103包括彼此间隔的多个第一电极1030；多个像素定义部1040中的每个位于相邻第一电极1030之间。
在本公开一实施例提供的显示基板的制作方法中，第一填充层104a或至 少一个绝缘填充部104a0与像素定义层104由同一膜层采用同一构图工艺形成。
在本公开一实施例提供的显示基板的制作方法中，第一电极图案103与连接电极图案103a由同一膜层采用同一构图工艺形成。
在本公开一实施例提供的显示基板的制作方法中，该制作方法还包括形成第二填充层104b，形成第二填充层104b包括形成至少一个第二填充部104b0，连接电极图案103a包括多个连接电极103a0，第二填充部104b0位于相邻连接电极103a0之间。
在本公开一实施例提供的显示基板的制作方法中，第二填充部104b0分别与相邻连接电极103a0接触。
在本公开一实施例提供的显示基板的制作方法中，第二填充层104b为绝缘层。
在本公开一实施例提供的显示基板的制作方法中，第二填充层104b和第一填充层104a由同一膜层采用同一构图工艺形成。
在本公开一实施例提供的显示基板的制作方法中，发光功能层105与第一填充层104a接触。
在本公开一实施例提供的显示基板的制作方法中，发光功能层105与部分第一填充层104a接触。
本公开一实施例提供的显示基板的制作方法包括：形成位于显示基板的显示区11的第一电极图案103；形成位于显示基板的周边区12的连接电极图案103a，周边区12围绕显示区11；形成第二电极106，第二电极106与连接电极图案103a相连，第二电极106位于显示区11和周边区12，第二电极106与第一电极图案103彼此间隔；形成发光功能层105，发光功能层105位于第一电极图案103和第二电极106之间；以及形成第一填充层104a，第一填充层104a位于连接电极图案103a和第一电极图案103之间。采用该方法可形成图5A至图8A所示的任一显示基板。
本公开一实施例提供的显示基板的制作方法包括：在衬底基板上形成第一绝缘层；在第一绝缘层上形成导电薄膜，对导电薄膜进行一次构图工艺，以同时形成第一电极图案103和连接电极图案103a；在第一电极图案103和连接电极图案103a上形成像素定义薄膜，对像素定义薄膜进行一次构图工 艺，以同时形成第一填充层104a和像素定义层104；在第一填充层104a和像素定义层104上形成发光功能层105；在发光功能层105上形成第二电极106。采用该方法可形成图5A至图8A所示的任一显示基板。
本公开一实施例提供的显示基板的制作方法包括：在衬底基板101上形成绝缘薄膜，对绝缘薄膜进行构图形成第一过孔V1和第二过孔V2以形成第一绝缘层102；在第一过孔V1和第二过孔V2中填充导电材料以分别形成连接件；在第一绝缘层102以及连接件上形成导电薄膜，对导电薄膜进行一次构图工艺，以同时形成第一电极图案103和连接电极图案103a；在第一电极图案103和连接电极图案103上形成像素定义薄膜，对像素定义薄膜进行一次构图工艺，以同时形成第一填充层104a和像素定义层104；在第一填充层104a和像素定义层104上形成发光功能层105；在发光功能层105上形成第二电极106。采用该方法可形成图5A至图8A所示的任一显示基板。
本公开一实施例提供的显示基板的制作方法包括：在衬底基板101上形成绝缘薄膜，对绝缘薄膜进行构图形成第一过孔V1和第二过孔V2以形成第一绝缘层102；在第一过孔V1和第二过孔V2中填充导电材料以分别形成连接件；在第一绝缘层102以及连接件上形成导电薄膜，对导电薄膜进行一次构图工艺，以同时形成第一电极图案103、连接电极图案103a和至少一个导电填充部103d1；在第一电极图案103、连接电极图案103和至少一个导电填充部103d1上形成像素定义薄膜，对像素定义薄膜进行一次构图工艺，以同时形成像素定义层104和至少一个绝缘填充部104a0；在像素定义层104和至少一个绝缘填充部104a0上形成发光功能层105；在发光功能层105上形成第二电极106。采用该制作方法可以形成图7A所示的显示基板。
本公开一实施例提供的显示基板的制作方法包括：在衬底基板101上形成绝缘薄膜，对绝缘薄膜进行构图形成第一过孔V1和第二过孔V2以形成第一绝缘层102；在第一过孔V1和第二过孔V2中填充导电材料以分别形成连接件；在第一绝缘层102以及连接件上形成导电薄膜，对导电薄膜进行一次构图工艺，以同时形成第一电极图案103、连接电极图案103a和至少一个导电填充部103d1，连接电极图案103a包括多个连接电极103a0；在第一电极图案103、连接电极图案103和至少一个导电填充部103d1上形成像素定义薄膜，对像素定义薄膜进行一次构图工艺，以同时形成像素定义层104、至 少一个绝缘填充部104a0和第二填充层104b；在像素定义层104和至少一个绝缘填充部104a0上形成发光功能层105；在发光功能层105上形成第二电极106。采用该制作方法可以形成图8A所示的显示基板。
例如，采用上述制作方法可形成第一方面中所述的显示基板，显示基板可为上述任一显示基板，对于显示基板的具体描述，可参见上述，在此不再赘述。
第二方面，为了减小第二电极106的高度落差和/或提高刻蚀均匀性，本公开的实施例提供一种显示基板及其制作方法和显示装置。
图11为本公开一实施例提供的一种显示基板的区域划分示意图。如图11所示，显示基板包括显示区11和周边区12，周边区12包括连接电极区12a，从而，周边区12包括三个区域：连接电极区12a、第一虚设区121和第二虚设区122。第一虚设区121位于连接电极区12a和显示区11之间，第二虚设区122位于连接电极区12a的远离显示区11的一侧。如图11所示，第二虚设区122位于连接电极区12a的远离第一虚设区121的一侧。设置第一虚设区121可避免显示区和连接电极区12a的需彼此绝缘的元件短路，设置第二虚设区122可利于显示基板的封装，利于提高封装效果。
图12为本公开一实施例提供的一种显示基板的俯视示意图。图12示出了导电薄膜经一次构图工艺后形成的结构的俯视图。图12示出了显示区11、周边区12、连接电极区12a、第一虚设区121和第二虚设区122。图12还示出了第一电极1030、第一虚设电极de10、第二虚设电极de20和连接电极103a0。第一电极1030位于显示区11、第一虚设电极de10位于第一虚设区121、第二虚设电极de20位于第二虚设区122，连接电极103a0位于连接电极区12a。例如，连接电极图案103a呈环形。
例如，如图12所示，为了提高刻蚀均匀性，第一虚设电极de10呈块状。例如，如图12所示，为了提高刻蚀均匀性，第二虚设电极de20呈块状。如图12所示，为了提高刻蚀均匀性，连接电极103a0呈块状。例如，如图12所示，第一电极1030呈块状。例如，块状包括多边形，但不限于此。例如，如图12所示，第一电极1030、第一虚设电极de10、第二虚设电极de20和连接电极103a0的形状相同，但不限于此。
图13A为本公开一实施例提供的一种显示基板的剖视示意图。如图13A 所示，显示基板200a包括：第一电极图案103，位于显示基板的显示区11，并包括彼此间隔的多个第一电极1030，第一电极被配置为接收像素驱动信号；连接电极图案103a，位于显示基板的连接电极区12a，并包括多个连接电极103a0；连接电极区12a围绕显示区11。例如，如图12和图13A所示，多个连接电极103a0围绕多个第一电极1030。
如图12和图13A所示，在本公开一实施例提供的显示基板中，显示基板还包括第二电极106，第二电极106与多个连接电极103a0相连；周边区12围绕显示区11，周边区12包括连接电极区12a和第一虚设区121；第二电极106位于显示区11和周边区12，第二电极106与第一电极图案103彼此间隔。第二电极被配置为接收第一电源信号。
如图12和图13A所示，为了提高刻蚀均匀性，连接电极图案103a的图案密度和第一电极图案103的图案密度相同。
如图12和图13A所示，在本公开一实施例提供的显示基板中，显示基板200a还包括第一虚设电极图案de1，第一虚设电极图案de1位于第一虚设区121，并包括多个第一虚设电极de10。第一虚设区121位于连接电极区12a和显示区11之间，为了提高刻蚀均匀性，第一虚设电极图案de1的图案密度和第一电极图案103的图案密度相同。
如图12和图13A所示，在本公开一实施例提供的显示基板中，显示基板还包括第二虚设电极图案de2，位于第二虚设区122，并包括多个第二虚设电极de20；第二虚设区122位于连接电极区12a的远离显示区11的一侧。为了提高刻蚀均匀性，第二虚设电极图案de2的图案密度和第一电极图案103的图案密度相同。
如图13A所示，在本公开一实施例提供的显示基板中，在第一虚设区121设有第一填充层104a，第一填充层104a包括多个第一虚设电极de10和绝缘填充层104c，第一电极图案103包括靠近连接电极103a0的边缘第一电极103e，绝缘填充层104c分别与连接电极103a0和边缘第一电极103e接触。例如，边缘第一电极103e为最靠近连接电极103a0的第一电极1030。
如图13A所示，在本公开一实施例提供的显示基板中，第二电极106与绝缘填充层104c接触。
如图13A所示，在本公开一实施例提供的显示基板中，边缘第一电极 103e与多个第一虚设电极de10彼此绝缘。
在本公开一实施例提供的显示基板中，显示基板还包括像素定义层104，像素定义层104包括多个像素定义部1040。例如，多个像素定义部1040中的每个位于相邻第一电极1030之间。
如图13A所示，在本公开一实施例提供的显示基板中，绝缘填充层104c与像素定义层104位于同一层，可由同一膜层采用同一构图工艺形成，以节省制作工艺。
如图13A所示，在本公开一实施例提供的显示基板中，第一电极图案103与连接电极图案103a位于同一层，可由同一膜层采用同一构图工艺形成，以节省制作工艺。
如图13A所示，在本公开一实施例提供的显示基板中，显示基板还包括第二填充层104b，第二填充层104b包括至少一个第二填充部104b0，第二填充部104b0位于相邻连接电极103a0之间。如图13A所示，在本公开一实施例提供的显示基板中，第二填充部104b0分别与相邻连接电极103a0接触。
如图13A所示，在本公开一实施例提供的显示基板中，第二填充层104b为绝缘层。例如，第二填充层104b和绝缘填充层104c位于同一层，可由同一膜层采用同一构图工艺形成，以节省制作工艺。
如图13A所示，在本公开一实施例提供的显示基板中，显示基板还包括发光功能层105，发光功能层105位于第一电极图案103和第二电极106之间，发光功能层105与绝缘填充层104c接触。进一步例如，发光功能层105与绝缘填充层104c接触。
如图13A所示，在本公开一实施例提供的显示基板中，发光功能层105与部分绝缘填充层104c接触。
如图13A所示，在本公开一实施例提供的显示基板中，第一虚设电极de10不外连接，与其接触的下方的第一绝缘层的位于第一虚设电极de10正下方的部分不设置过孔，可参照对于第一虚设电极103d1的描述。对于第一过孔V1和第二过孔V2可参照之前的描述，在此不再赘述。
本公开的实施例中，图13A以绝缘填充层104c完全覆盖多个第一虚设电极de10为例进行说明，但不限于此。
图13B为本公开一实施例提供的显示基板的剖视图。图13B所示的显示 基板200aa与图13A所示的显示基板200a相比，区别在于：显示基板200aa的第一绝缘层102中设有凹槽G。图13B所示，第一绝缘层102中的位于显示区11内的凹槽G在垂直于衬底基板101的方向上的尺寸等于第一绝缘层102中的位于周边区12内的凹槽G在垂直于衬底基板101的方向上的尺寸。例如，第一绝缘层102中的所有凹槽G在垂直于衬底基板101的方向上的尺寸均相等。图13B所示，第一绝缘层102中的位于第二虚设区122的凹槽G、第一绝缘层102中的位于连接虚设区12a的凹槽G、第一绝缘层102中的位于第一虚设区121的凹槽G、以及第一绝缘层102中的位于显示区11的凹槽G在垂直于衬底基板101的方向上的尺寸均相等。
图14A为本公开一实施例提供的显示基板的剖视图。如图14A所示，显示基板200b与图13A所示的显示基板200a的区别在于：绝缘填充层104c可包括多个镂空区HR11以分别暴露多个第一虚设电极de10，第二电极106通过绝缘填充层104c中的镂空区与第一虚设电极de10相连。绝缘填充层104c包括多个绝缘填充部104c0。如图14A所示，绝缘填充部104c0位于相邻第一虚设电极de10之间，或位于相邻的第一虚设电极de10和边缘第一电极103e之间、或位于相邻的第一虚设电极de10和连接电极103a0之间。
图14B为本公开一实施例提供的显示基板的剖视图。图14B所示的显示基板200bb与图14A所示的显示基板200b相比，区别在于：显示基板200bb的第一绝缘层102中设有凹槽G。图14B所示，第一绝缘层102中的位于显示区11内的凹槽G在垂直于衬底基板101的方向上的尺寸等于第一绝缘层102中的位于周边区12内的凹槽G在垂直于衬底基板101的方向上的尺寸。例如，第一绝缘层102中的所有凹槽G在垂直于衬底基板101的方向上的尺寸均相等。图14B所示，第一绝缘层102中的位于第二虚设区122的凹槽G、第一绝缘层102中的位于连接虚设区12a的凹槽G、第一绝缘层102中的位于第一虚设区121的凹槽G、以及第一绝缘层102中的位于显示区11的凹槽G在垂直于衬底基板101的方向上的尺寸均相等。
图15为本公开一实施例提供的显示基板中的绝缘填充层、第二填充层和像素定义层的俯视图。图15示出了绝缘填充层104c、第二填充层104b和像素定义层104。如图15所示，像素定义薄膜经构图后的结构包括多个镂空区HR。多个镂空区HR包括位于显示区11的镂空区HR0和位于第二虚设区122 的镂空区HR2。镂空区HR0被配置为暴露第一电极1030，镂空区HR2被配置为暴露连接电极103a0。图15所示的绝缘填充层、第二填充层和像素定义层可为图13A中的绝缘填充层104c、第二填充层104b和像素定义层104的俯视图。例如，图14A所示的第一填充层、第二填充层和像素定义层的俯视图可参照图10，但不限于此。
本公开至少一实施例还提供一种显示装置，包括上述第二方面中任一显示基板。例如，显示装置包括微OLED显示装置。
本公开至少一实施例还提供一种显示基板的制作方法，包括：形成第一电极图案103，第一电极图案103位于显示基板的显示区11，并包括彼此间隔的多个第一电极1030，第一电极被配置为接收像素驱动信号；形成连接电极图案103a，连接电极图案103a位于显示基板的连接电极区12a，并包括多个连接电极103a0，连接电极区12a围绕显示区11；形成第二电极106，第二电极106位于显示区11和周边区12，第二电极106与连接电极图案103a相连，第二电极106与第一电极图案103彼此间隔，第二电极被配置为接收第一电源信号。多个连接电极103a0围绕多个第一电极1030。连接电极103a0呈块状。
在本公开一实施例提供的显示基板的制作方法中，为了提高刻蚀均匀性，连接电极图案103a的图案密度和第一电极图案103的图案密度相同。
本公开一实施例提供的显示基板的制作方法还包括：形成第一虚设电极图案de1，第一虚设电极图案de1位于显示基板的第一虚设区121，并包括多个第一虚设电极de10；第一虚设区121位于连接电极区12a和显示区11之间；为了提高刻蚀均匀性，第一虚设电极图案de1的图案密度和第一电极图案103的图案密度相同。例如，第一虚设电极de10呈块状。周边区12包括连接电极区12a和第一虚设区121。
本公开一实施例提供的显示基板的制作方法还包括：形成第二虚设电极图案de2，第二虚设电极图案de2位于显示基板的第二虚设区122，并包括多个第二虚设电极de20；第二虚设区122位于连接电极区12a的远离显示区11的一侧，为了提高刻蚀均匀性，第二虚设电极图案de2的图案密度和第一电极图案103的图案密度相同。例如，第二虚设电极de20呈块状。周边区12包括连接电极区12a、第一虚设区121和第二虚设区122。
在本公开一实施例提供的显示基板的制作方法中，在第一虚设区121形成第一填充层104a，第一填充层104a包括多个第一虚设电极de10和绝缘填充层104c，第一电极图案103包括与连接电极103a0相邻的边缘第一电极103e，绝缘填充层104c分别与连接电极103a0和边缘第一电极103e接触。
在本公开一实施例提供的显示基板的制作方法中，第二电极106与绝缘填充层104c接触。
在本公开一实施例提供的显示基板的制作方法中，边缘第一电极103e与多个第一虚设电极de10彼此绝缘。
在本公开一实施例提供的显示基板的制作方法中，制作方法还包括：形成像素定义层104，像素定义层104包括多个像素定义部1040，多个像素定义部1040中的每个位于相邻第一电极1030之间。
在本公开一实施例提供的显示基板的制作方法中，绝缘填充层104c与像素定义层104由同一膜层采用同一构图工艺形成。
在本公开一实施例提供的显示基板的制作方法中，第一电极图案103与连接电极图案103a由同一膜层采用同一构图工艺形成。
本公开一实施例提供的显示基板的制作方法还包括：形成第二填充层104b，第二填充层104b包括至少一个第二填充部104b0，第二填充部104b0位于相邻连接电极103a0之间。例如，第二填充部104b0分别与相邻连接电极103a0接触。例如，第二填充层104b为绝缘层。在本公开一实施例提供的显示基板的制作方法中，第二填充层104b和第一填充层104a由同一膜层采用同一构图工艺形成。
本公开一实施例提供的显示基板的制作方法还包括：形成发光功能层105，发光功能层105位于第一电极图案103和第二电极106之间，发光功能层105与第一填充层104a接触。
在本公开一实施例提供的显示基板的制作方法中，发光功能层105与部分第一填充层104a接触。
本公开一实施例提供的显示基板的制作方法包括：形成第一电极图案，所述第一电极图案位于所述显示基板的显示区，并包括彼此间隔的多个第一电极；形成连接电极图案，所述连接电极图案位于所述显示基板的周边区，并包括多个连接电极；以及形成第二电极，所述第二电极位于所述显示区和 所述周边区，并与所述连接电极图案相连，所述第二电极与所述第一电极图案彼此间隔；所述连接电极图案围绕所述第一电极图案，所述连接电极呈块状。
本公开一实施例提供的显示基板的制作方法包括：在衬底基板101上形成绝缘薄膜，对绝缘薄膜进行构图形成第一过孔V1和第二过孔V2以形成第一绝缘层102；在第一过孔V1和第二过孔V2中填充导电材料以分别形成连接件；在第一绝缘层102以及连接件上形成导电薄膜，对导电薄膜进行一次构图工艺，以同时形成第一电极图案103、连接电极图案103a和第一虚设电极图案de1，连接电极图案103a包括多个连接电极103a0；在第一电极图案103、连接电极图案103和第一虚设电极图案de1上形成像素定义薄膜，对像素定义薄膜进行一次构图工艺，以同时形成像素定义层104、绝缘填充层104c和第二填充层104b；在像素定义层104和绝缘填充层104c上形成发光功能层105；在发光功能层105上形成第二电极106。采用该制作方法可以形成图13A所示的显示基板。
本公开一实施例提供的显示基板的制作方法包括：在衬底基板101上形成绝缘薄膜，对绝缘薄膜进行构图形成第一过孔V1和第二过孔V2以形成第一绝缘层102；在第一过孔V1和第二过孔V2中填充导电材料以分别形成连接件；在第一绝缘层102以及连接件上形成导电薄膜，对导电薄膜进行一次构图工艺，以同时形成第一电极图案103、连接电极图案103a和第一虚设电极图案de1，连接电极图案103a包括多个连接电极103a0；在第一电极图案103、连接电极图案103和第一虚设电极图案de1上形成像素定义薄膜，对像素定义薄膜进行一次构图工艺，以同时形成像素定义层104、至少一个绝缘填充部104c0和第二填充层104b；在像素定义层104和至少一个绝缘填充部104c0上形成发光功能层105；在发光功能层105上形成第二电极106。采用该制作方法可以形成图14A所示的显示基板。
第三方面，为了减小第二电极106的高度落差和/或提高刻蚀均匀性，本公开的实施例提供一种显示基板及其制作方法和显示装置。
图16为本公开一实施例提供的一种显示基板的区域划分示意图。与图11所示的显示基板相比，显示基板还包括传感器区R1，第一虚设区121的位于传感器区R1和连接电极区12a之间的部分为第一虚设子区1211；第二 虚设子区1212位于传感器区R1和显示区11之间。图16还示出了接垫区(pad区)R2。接垫区R2可用来外接电路。
图17A为本公开一实施例提供的一种显示基板的剖视示意图。图17A可为图18中所示的显示基板中M-N处的剖视示意图。如图17A所示，该显示基板300a包括：第一电极图案103、连接电极图案103a、以及第一虚设电极图案de1。第一电极图案103位于显示基板的显示区11，并包括彼此间隔的多个第一电极1030。第一电极被配置为接收像素驱动信号。连接电极图案103a位于显示基板的连接电极区12a，并包括多个连接电极103a0。多个连接电极103a0中至少两个呈彼此隔开的块状。第一虚设电极图案de1位于显示基板的第一虚设区121，并包括多个第一虚设电极de10。设置第一虚设电极图案de1可利于提高刻蚀均匀性。
如图16和图17A所示，连接电极区12a围绕显示区11，第一虚设区121位于连接电极区12a和显示区11之间。连接电极图案103a围绕第一电极图案103，第一虚设电极图案de1围绕第一电极图案103。第一虚设电极图案de1位于连接电极图案103a和第一电极图案103之间。例如，连接电极图案103a呈环形。
例如，如图17A所示，本公开一实施例提供的显示基板还包括第二电极106，第二电极106与连接电极103a0相连；显示基板的周边区12围绕显示区11，周边区12包括连接电极区12a和第一虚设区121；第二电极106位于显示区11和周边区12，第二电极106与第一电极图案103彼此间隔。第二电极被配置为接收第一电源信号。
例如，如图17A所示，连接电极图案103a的图案密度和第一虚设电极图案de1的图案密度中至少一个与第一电极图案103的图案密度相同。
例如，如图17A所示，本公开一实施例提供的显示基板还包括传感器电极图案103b，传感器电极图案103b位于显示基板的传感器区R1，并包括多个传感器电极103b0。传感器电极103b0被配置为接收检测驱动信号。例如，传感器电极图案103b的图案密度和第一电极图案103的图案密度相同。
例如，如图17A所示，本公开一实施例提供的显示基板还包括第二虚设电极图案de2，第二虚设电极图案de2位于显示基板的第二虚设区122，并包括多个第二虚设电极de20；第二虚设区122位于连接电极区12a的远离显示 区11的一侧。例如，第二虚设电极图案de2的图案密度和第一电极图案103的图案密度相同。在本公开一实施例提供的显示基板中，第一电极图案103的图案密度、连接电极图案103a的图案密度、传感器电极图案103b的图案密度、第一虚设电极图案de1的图案密度和第二虚设电极图案de2的图案密度均相同。
例如，如图17A所示，在第一虚设子区1211设有第一填充层104a，第一填充层104a包括多个第一虚设电极de10和绝缘填充层104c；第一电极图案103包括与连接电极103a0相邻的边缘第一电极103e，绝缘填充层104c分别与连接电极103a0和边缘第一电极103e接触。例如，如图17A所示，第二电极106与绝缘填充层104c接触。例如，如图17A所示，边缘第一电极103e与多个第一虚设电极de10彼此绝缘。
例如，如图17A所示，显示基板还包括像素定义层104，像素定义层104包括多个像素定义部1040，多个像素定义部1040中的每个位于相邻第一电极1030之间。
例如，如图17A所示，绝缘填充层104c与像素定义层104位于同一层，可由同一膜层采用同一构图工艺形成，以节省制作工艺。
例如，如图17A所示，第一电极图案103、连接电极图案103a、传感器电极图案103b、第一虚设电极图案de1和第二虚设电极图案de2位于同一层，可由同一膜层采用同一构图工艺形成，以节省制作工艺。
例如，如图17A所示，显示基板还包括第二填充层104b，第二填充层104b包括至少一个第二填充部104b0，第二填充部104b0位于相邻连接电极103a0之间。例如，第二填充层104b为绝缘层。例如，如图17A所示，第二填充部104b0分别与相邻连接电极103a0接触。
例如，如图17A所示，第二填充层104b和第一填充层104a位于同一层，可由同一膜层采用同一构图工艺形成，以节省制作工艺。
例如，如图17A所示，显示基板还包括第三填充层1043，第三填充层1043包括多个第三填充部10430，第三填充部10430位于相邻传感器电极103b0、相邻的传感器电极103b0和第一虚设电极中至少之一之间。图17A以第三填充部10430位于相邻传感器电极103b0之间为例进行说明。
例如，如图17A所示，第三填充层1043与像素定义层104位于同一层， 可由同一膜层采用同一构图工艺形成，以节省制作工艺。例如，如图17A所示，像素定义层104、绝缘填充层104c、第二填充层104b、第三填充层1043位于同一层。
例如，如图17A所示，显示基板还包括发光功能层105，发光功能层105位于第一电极图案103和第二电极106之间，发光功能层105与第一填充层104a接触。例如，发光功能层105与部分第一填充层104a接触。例如，如图17A所示，发光功能层105延伸到第一虚设子区1211。发光功能层105覆盖整个显示区11、传感器区R1、第二虚设子区1212和部分第一虚设子区1211，以防止发光功能层105蒸镀到连接电极区122造成第一电极和第二电极短路。例如，如图17A所示，第二电极106从显示区11延伸到周边区12的第二虚设区122，以利于第二电极106与连接电极103a0的连接。
例如，如图17A所示，发光功能层105与传感器电极图案103b接触。例如，如图17A所示，发光功能层105与位于第二虚设子区1212内的第一虚设电极de10不接触，但不限于此。
如图17A所示，在衬底基板101上还设有第二绝缘层IS，第二绝缘层IS上设有导电图案109，导电图案109包括第一导电部1091、第二导电部1092和第三导电部1093。第二绝缘层IS包括第三过孔V11、第四过孔V21、第五过孔V31。第三过孔V11、第四过孔V21、第五过孔V31中分别填充导电材料以形成连接件。第一电极1030通过第一导电部1091与第四过孔V21中的连接件相连。连接电极103a0通过第二导电部1092与第三过孔V11中的连接件相连。传感器电极103b0通过第三导电部1093与第五过孔V31中的连接件相连。需要说明的是，在衬底基板101和第二绝缘层IS之间还设有其他结构，图17A中并没有示出该其他结构。
如图17A所示，显示基板还包括封装层107。封装层107被配置为封装发光元件，以避免水氧侵袭。如图17A所示，封装层107覆盖第二电极106以及第二虚设电极图案de2。如图17A所示，封装层107可覆盖整个衬底基板101以及其上的结构。
图17B为本公开一实施例提供的一种显示基板的剖视示意图。图17B所示的显示基板300aa与图17A所示的显示基板300a相比，区别在于：显示基板300aa的第一绝缘层102中设有凹槽G。图17B所示，第一绝缘层102 中的位于显示区11内的凹槽G在垂直于衬底基板101的方向上的尺寸等于第一绝缘层102中的位于周边区12内的凹槽G在垂直于衬底基板101的方向上的尺寸。例如，第一绝缘层102中的所有凹槽G在垂直于衬底基板101的方向上的尺寸均相等。图17B所示，第一绝缘层102中的位于第二虚设区122的凹槽G、第一绝缘层102中的位于连接虚设区12a的凹槽G、第一绝缘层102中的位于第一虚设区121(包括第一虚设子区1211和第二虚设子区1212)的凹槽G、第一绝缘层102中的位于传感器区R1的凹槽G以及第一绝缘层102中的位于显示区11的凹槽G在垂直于衬底基板101的方向上的尺寸均相等。
图18为本公开一实施例提供的显示基板中的导电薄膜经构图后形成的结构的俯视图。显示基板中的其他结构未示出，可参照图17A或图17B。与图12示出的结构相比，图18示出了传感器电极103b0。如图18所示，传感器电极103b0的形状、第一电极1030的形状、连接电极103a0的形状、第一虚设电极de10的形状和第二虚设电极案de20的形状相同，但不限于此。如图18所示，传感器电极图案103b的图案密度、第一电极图案103的图案密度、连接电极图案103a的图案密度、第一虚设电极图案de1的图案密度和第二虚设电极图案de2的图案密度相同。即，多个传感器电极103b0的图案密度、多个第一电极1030的图案密度、多个连接电极103a0的图案密度、多个第一虚设电极de10的图案密度和多个第二虚设电极de20的图案密度相同。
例如，如图18所示，第一虚设电极de10呈块状。呈块状的第一虚设电极de10也可参照图12。
例如，如图18所示，第二虚设电极de20呈块状。呈块状的第二虚设电极de20也可参照图12。
例如，如图18所示，传感器电极103b0、第一电极1030、连接电极103a0、第一虚设电极de10和第二虚设电极de20均呈块状。
图19为本公开一实施例提供的显示基板中的像素定义薄膜经构图后形成的结构的俯视图。与图15所示的结构相比，图19示出了第三填充部10430以及镂空区HR3。镂空区HR3被配置为暴露传感器电极103b0(图19未示出，参照图17A和图17B)。
图20为本公开一实施例提供的显示基板的剖视图。图20所示的显示基 板300b与图17A所示的显示基板300a的区别在于：绝缘填充层104c位于第二虚设子区1212的部分包括镂空区HR22。镂空区HR22被配置为暴露位于第二虚设子区1212的第一虚设电极de10。发光功能层105与位于第二虚设子区1212的第一虚设电极de10接触。如图17A和图20所示，发光功能层105与位于第一虚设子区1211的第一虚设电极de10不接触。
本公开至少一实施例还提供一种显示装置，包括上述第三方面中的任一显示基板。显示装置包括微OLED显示装置，但不限于此。第三方面提供的显示基板比第二方面提供的显示基板多了传感器区R1，其余可参照第二方面的描述。
本公开至少一实施例还提供一种显示基板的制作方法，包括：形成第一电极图案，所述第一电极图案位于所述显示基板的显示区，并包括彼此间隔的多个第一电极，所述第一电极被配置为接收像素驱动信号；形成连接电极图案，所述连接电极图案位于所述显示基板的周边区，并包括多个连接电极；形成第二电极，所述第二电极位于所述显示区和所述周边区，并与所述连接电极图案相连，所述第二电极与所述第一电极图案彼此间隔，所述第二电极被配置为接收第一电源信号；形成发光功能层，所述发光功能层位于所述第一电极图案和所述第二电极之间；以及形成第一虚设电极图案，所述第一虚设电极图案包括多个第一虚设电极；所述连接电极图案围绕所述第一电极图案，所述第一虚设电极图案位于所述连接电极图案和所述第一电极图案之间，所述多个第一虚设电极中的至少两个呈彼此隔开的块状。
本公开至少一实施例还提供一种显示基板的制作方法，包括：形成第一电极图案103，第一电极图案103位于显示基板的显示区11，并包括彼此间隔的多个第一电极1030；形成连接电极图案103a，连接电极图案103a位于显示基板的连接电极区12a，并包括多个连接电极103a0；形成第二电极106，第二电极106位于显示区11和周边区12，第二电极106与连接电极图案103a相连，第二电极106与第一电极图案103彼此间隔；以及形成第一虚设电极图案de1，第一虚设电极图案de1位于显示基板的第一虚设区121，并包括多个第一虚设电极de10；连接电极图案103a围绕第一电极图案103，所述第一虚设电极图案位于所述连接电极图案和所述第一电极图案之间。第一虚设电极图案de1围绕第一电极图案103。
例如，连接电极区12a围绕显示区11，第一虚设区121位于连接电极区12a和显示区11之间。
例如，在本公开至少一实施例还提供一种显示基板的制作方法中，第一电极图案103的图案密度、连接电极图案103a的图案密度和第一虚设电极图案de1的图案密度相同。
例如，本公开至少一实施例还提供一种显示基板的制作方法还包括形成第二虚设电极图案de2，第二虚设电极图案de2位于显示基板的第二虚设区122，并包括多个第二虚设电极de20；第二虚设区122位于连接电极区12a的远离显示区11的一侧，第二虚设电极图案de2的图案密度和第一电极图案103的图案密度相同。
例如，本公开至少一实施例还提供一种显示基板的制作方法还包括形成传感器电极图案103b，传感器电极图案103b位于显示基板的传感器区R1，并包括多个传感器电极103b0；传感器电极图案103b的图案密度和第一电极图案103的图案密度相同。
例如，在本公开至少一实施例还提供一种显示基板的制作方法中，第二虚设子区1212位于传感器区R1和显示区11之间；第一虚设区121的位于传感器区R1和连接电极区12a之间的部分为第一虚设子区1211；在第一虚设子区1211形成第一填充层104a，第一填充层104a包括多个第一虚设电极de10和绝缘填充层104c，第一电极图案103包括与连接电极103a0相邻的边缘第一电极103e，绝缘填充层104c分别与连接电极103a0和边缘第一电极103e接触。
例如，在本公开至少一实施例还提供一种显示基板的制作方法中，第二电极106与绝缘填充层104c接触。
例如，在本公开至少一实施例还提供一种显示基板的制作方法中，边缘第一电极103e与多个第一虚设电极de10彼此绝缘。
例如，在本公开至少一实施例还提供一种显示基板的制作方法中，该方法还包括形成像素定义层104，像素定义层104包括多个像素定义部1040，多个像素定义部1040中的每个位于相邻第一电极1030之间。
例如，在本公开至少一实施例还提供一种显示基板的制作方法中，绝缘填充层104c与像素定义层104由同一膜层采用同一构图工艺形成。
例如，在本公开至少一实施例还提供一种显示基板的制作方法中，第一电极图案103与连接电极图案103a由同一膜层采用同一构图工艺形成。
例如，本公开至少一实施例还提供一种显示基板的制作方法还包括形成第二填充层104b，第二填充层104b包括至少一个第二填充部104b0，第二填充部104b0位于相邻连接电极103a0之间。例如，第二填充部104b0分别与相邻连接电极103a0接触。例如，第二填充层104b为绝缘层。例如，第二填充层104b和第一填充层104a由同一膜层采用同一构图工艺形成。
例如，本公开至少一实施例还提供一种显示基板的制作方法还包括形成第三填充层1043，第三填充层1043包括多个第三填充部10430，第三填充部10430位于相邻传感器电极103b0、相邻第三虚设电极、相邻的传感器电极103b0和第三虚设电极中至少之一之间。例如，第三填充层1043与像素定义层104由同一膜层采用同一构图工艺形成。
例如，在本公开至少一实施例还提供一种显示基板的制作方法中，发光功能层105与第一填充层104a接触。例如，发光功能层105与部分第一填充层104a接触。例如，发光功能层105与传感器电极图案103b接触。
例如，在本公开至少一实施例还提供一种显示基板的制作方法中，发光功能层105与位于第二虚设子区内的第一虚设电极de10接触。
本公开一实施例提供的显示基板的制作方法包括：在衬底基板101上形成绝缘薄膜，对绝缘薄膜进行构图形成第一过孔V1、第二过孔V2和第三过孔V3以形成第一绝缘层102；在第一过孔V1、第二过孔V2和第三过孔V3中填充导电材料以分别形成连接件；在第一绝缘层102以及连接件上形成导电薄膜，对导电薄膜进行一次构图工艺，以同时形成第一电极图案103、连接电极图案103a、第一虚设电极图案de1、第二虚设电极图案de2和传感器电极图案103b，连接电极图案103a包括多个连接电极103a0，传感器电极图案103b包括多个传感器电极103b0，第一虚设电极图案de1包括多个第一虚设电极de10，第二虚设电极图案de2包括多个第二虚设电极de20；在第一电极图案103、连接电极图案103a、第一虚设电极图案de1和传感器电极图案103b上形成像素定义薄膜，对像素定义薄膜进行一次构图工艺，以同时形成像素定义层104、绝缘填充层104c、第二填充层104b和第三填充层1043；在像素定义层104、绝缘填充层104c和第三填充层1043上形成发光功能层 105；在发光功能层105上形成第二电极106。采用该制作方法可以形成图17A和图18所示的显示基板。
例如，本公开的实施例中，A图案的图案密度是指该图案中包括的多个A的密度，例如，可指单位面积内的A的个数，但不限于此。例如，第一电极图案103的图案密度可指第一电极图案103中多个第一电极1030的密度，其余相关内容可参照于此。
例如，本公开的实施例中，如图5A所示，第一连接件cn1位于第一过孔V1中，第二连接件cn2位于第二过孔V2中。其余附图中的附图标记未给出。
例如，本公开的实施例中，如图9、图12和图18所示，连接电极图案呈环形。
例如，本公开的实施例中，衬底基板101可包括硅晶圆，但不限于此。
例如，本公开的实施例中，第一绝缘层、第二绝缘层至少之一包括氧化硅、氮化硅、氮氧化硅中至少之一。
例如，本公开的实施例中，传感器电极可被配置为测量温度、亮度等至少之一的参数。例如，传感器电极的构造可与显示区的子像素的构造相同。
例如，本公开的实施例中，块状的元件为一个图案，其内不存在镂空区。例如，本公开的实施例中，第一电极图案103不是块状，因其包括的不同的第一电极1030之间存在镂空区，而第一电极1030呈块状，因第一电极1030内不存在镂空区。
例如，本公开的实施例中，显示区包括多个发光元件，多个发光元件可发光以进行图像显示，周边区不发光。
图21为本公开的实施例提供的显示基板的制作方法中形成的导电薄膜的示意图。导电薄膜0103可整面覆盖衬底基板，并经构图工艺形成第一电极图案，以及与第一电极图案位于同一层的元件。与第一电极图案位于同一层的元件包括连接电极图案、第一虚设电极图案、第二虚设电极图案、传感器电极图案等至少之一。在本公开的实施例中，导电薄膜直接形成在第一绝缘层102之上，由导电薄膜经构图形成的结构与第一绝缘层102接触。由导电薄膜经构图形成的结构包括第一电极、连接电极、第一虚设电极、第二虚设电极、传感器电极至少之一。
图22为本公开的实施例提供的显示基板的制作方法中形成的像素定义薄膜的示意图。像素定义薄膜0104可整面覆盖衬底基板，并经构图工艺形成像素定义层，以及与像素定义层位于同一层的元件。与像素定义层位于同一层的元件包括第一填充层、绝缘填充层、第二填充层、第三填充层至少之一。
在本公开的实施例中，第一绝缘层102中的位于显示区11中凹槽可称作第一凹槽G1，第一绝缘层102中的位于周边区12中凹槽可称作第二凹槽G2。
在本公开的实施例中，如图7A至图8B所示，第一绝缘层102的在垂直于衬底基板101的方向上与多个导电填充部103d1交叠的部分不设置过孔。
在本公开的实施例中，如图13A至图14B、图17A至图17B以及图20所示，第一绝缘层102的在垂直于衬底基板101的方向上与多个第一虚设电极de10交叠的部分不设置过孔。
在本公开的实施例中，如图13A至图14B、图17A至图17B以及图20所示，第一绝缘层102的在垂直于衬底基板101的方向上与多个第二虚设电极de20交叠的部分不设置过孔。
在本公开的实施例中，如图8A至图8B、图13A至图14B、图17A至图17B以及图20所示，第一绝缘层102的在垂直于衬底基板101的方向上与多个连接电极103a0交叠的部分设置过孔V1。
在本公开的实施例中，如图8A至图8B、图13A至图14B、图17A至图17B以及图20所示，第一绝缘层102的在垂直于衬底基板101的方向上与多个第一电极1030交叠的部分设置过孔V2。
在本公开的实施例中，如图17A至图17B以及图20所示，第一绝缘层102的在垂直于衬底基板101的方向上与多个传感器电极1030交叠的部分设置过孔V3。
在本公开的实施例中，如图8A至图8B、图13A至图13B、以及图17A至图17B所示，导电填充部103d1浮置，第一虚设电极de10浮置，第二虚设电极de20浮置。例如，浮置是指不接收像素驱动信号。在某些实施例中，浮置的结构不直接接收第一电源信号。在某些实施例中，浮置的结构可间接接收第一电源信号。
在本公开的实施例中，第一电极被配置为接收像素驱动信号，所述第二电极被配置为接收第一电源信号，传感器电极被配置为接收检测驱动信号。 像素驱动信号例如包括第二电源信号VDD、数据信号、栅信号、发光控制信号EM、复位控制信号RE中至少之一。
在本公开的实施例中，硅晶圆包括硅基衬底和位于硅基衬底上的电路结构，电路结构包括像素电路，检测电路等。
图23为本公开一些实施例提供的一种硅基有机发光显示面板的电路原理示意图。该硅基有机发光显示面板包括位于显示区11中的多个发光元件L以及与各发光元件L一一对应耦接的像素电路110，像素电路110包括驱动晶体管。像素电路110被配置为提供像素驱动信号。并且，该硅基有机发光显示面板还可以包括位于硅基有机发光显示面板的周边区12中的多个电压控制电路120。例如，一行中至少两个像素电路110共用一个电压控制电路120，且一行像素电路110中驱动晶体管的第一极与共用的电压控制电路120耦接，各驱动晶体管的第二极与对应的发光元件L耦接。电压控制电路120被配置为响应于复位控制信号RE，将初始化信号Vinit输出至驱动晶体管的第一极，控制对应的发光元件L复位；以及响应于发光控制信号EM，将第二电源信号VDD输出至驱动晶体管的第一极，以驱动发光元件L发光。通过共用电压控制电路120，可以简化显示区域101中各像素电路的结构，降低显示区11中像素电路的占用面积，从而可以使显示区11设置更多的像素电路和发光元件，实现高PPI的有机发光显示面板。并且，电压控制电路120在复位控制信号RE的控制下将初始化信号Vinit输出至驱动晶体管的第一极，控制对应的发光元件复位，从而可以避免上一帧发光时加载于发光元件上的电压对下一帧发光的影响，进而改善残影现象。例如，驱动晶体管的第一极为源极或漏极之一，驱动晶体管的第二极为源极或漏极之另一。本公开的实施例中，发光元件可包括有机发光二极管，但不限于此。
例如，该硅基有机发光显示面板还可以包括位于显示区11的多个像素单元PX，每个像素单元PX包括多个子像素；各子像素分别包括一个发光元件L与一个像素电路110。进一步地，像素单元PX可以包括3个不同颜色的子像素。这3个子像素可以分别为红色子像素、绿色子像素以及蓝色子像素。当然，像素单元PX也可以包括4个、5个或更多的子像素，这需要根据实际应用环境来设计确定，在此不作限定。
例如，可以使同一行中相邻的至少两个子像素中的像素电路110共用一 个电压控制电路120。例如，如图23所示，可以使同一行中的所有像素电路110共用一个电压控制电路120。或者，也可以使同一行中相邻的两个、三个或更多子像素中的像素电路110共用一个电压控制电路120，在此不作限定。这样，通过共用电压控制电路120可以降低显示区A中像素电路的占用面积。
如图26所示，发光元件L的两个电极可分别为第一电极1030和第二电极106。例如，第一电极1030为发光元件L的阳极，第二电极106为发光元件L的阴极。第一电极1030与像素电路110相连，第二电极106可被输入第一电源信号VSS。第一电源信号VSS可通过连接线以及连接电极103a0传输到第二电极106。
在本公开的实施例中，元件A围绕元件B，可指元件A位于元件B的至少一侧，元件A围绕至少部分的元件B即可。元件B不限定为封闭的图形。
在本公开的实施例中，位于同一层的元件可由同一膜层经同一构图工艺行程。例如，位于同一层的元件可位于同一个元件的远离衬底基板的表面上。
需要说明的是，为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在本公开的实施例中，构图或构图工艺可只包括光刻工艺，或包括光刻工艺以及刻蚀步骤，或者可以包括打印、喷墨等其他用于形成预定图形的工艺。光刻工艺是指包括成膜、曝光、显影等工艺过程，利用光刻胶、掩模板、曝光机等形成图形。可根据本公开的实施例中所形成的结构选择相应的构图工艺。
在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (41)

  1. 一种显示基板，包括：
    第一电极图案，位于所述显示基板的显示区，并包括彼此间隔的多个第一电极，所述第一电极被配置为接收像素驱动信号；
    连接电极图案，位于所述显示基板的周边区；
    第二电极，位于所述显示区和所述周边区，并与所述连接电极图案相连，所述第二电极与所述第一电极图案彼此间隔，所述第二电极被配置为接收第一电源信号；
    发光功能层，位于所述第一电极图案和所述第二电极之间，以及
    第一虚设电极图案，包括多个第一虚设电极，
    其中，所述连接电极图案围绕所述第一电极图案，所述第一虚设电极图案位于所述连接电极图案和所述第一电极图案之间，所述多个第一虚设电极中的至少两个呈彼此隔开的块状。
  2. 根据权利要求1所述的显示基板，还包括衬底基板和位于所述衬底基板上的第一绝缘层，其中，所述第一电极图案、所述连接电极图案和所述第一虚设电极图案位于所述第一绝缘层的远离所述衬底基板的一侧并与所述第一绝缘层接触。
  3. 根据权利要求2所述的显示基板，其中，所述第一绝缘层的在垂直于所述衬底基板的方向上与所述多个第一虚设电极交叠的部分不设置过孔。
  4. 根据权利要求2或3所述的显示基板，其中，所述第一虚设电极浮置。
  5. 根据权利要求2-4任一项所述的显示基板，其中，所述连接电极图案包括多个连接电极，所述连接电极呈块状。
  6. 根据权利要求5所述的显示基板，其中，所述连接电极的形状与所述第一电极的形状相同，所述第一虚设电极的形状与所述第一电极的形状相同。
  7. 根据权利要求2-6任一项所述的显示基板，其中，所述连接电极图案的图案密度与所述第一电极图案的图案密度相同、所述第一虚设电极图案的图案密度和所述第一电极图案的图案密度相同。
  8. 根据权利要求2-6任一项所述的显示基板，还包括第二虚设电极图案，其中，所述第二虚设电极图案包括多个第二虚设电极；所述第二虚设电极图 案位于所述连接电极图案的远离所述第一电极图案的一侧。
  9. 根据权利要求8所述的显示基板，其中，所述第一绝缘层的在垂直于所述衬底基板的方向上与所述多个第二虚设电极交叠的部分不设置过孔。
  10. 根据权利要求8或9所述的显示基板，其中，所述第二虚设电极呈块状，所述第二虚设电极的形状和所述第一电极的形状相同。
  11. 根据权利要求8-10任一项所述的显示基板，其中，所述第二虚设电极图案的图案密度和所述第一电极图案的图案密度相同。
  12. 根据权利要求2-11任一项所述的显示基板，其中，所述第一绝缘层的位于相邻第一电极之间的部分、所述第一绝缘层的位于相邻连接电极之间的部分至少之一具有凹槽。
  13. 根据权利要求2-12任一项所述的显示基板，还包括绝缘填充层，其中，所述绝缘填充层覆盖所述多个第一虚设电极，所述多个第一虚设电极和所述绝缘填充层构成第一填充层，所述第一电极图案包括靠近所述连接电极的边缘第一电极，所述绝缘填充层分别与所述连接电极和所述边缘第一电极接触。
  14. 根据权利要求13所述的显示基板，其中，所述第二电极与所述绝缘填充层接触。
  15. 根据权利要求13或14所述的显示基板，其中，所述边缘第一电极与所述多个第一虚设电极彼此绝缘。
  16. 根据权利要求13-15任一项所述的显示基板，还包括像素定义层，其中，所述像素定义层包括多个像素定义部，所述像素定义部位于相邻第一电极之间。
  17. 根据权利要求16所述的显示基板，其中，所述绝缘填充层与所述像素定义层位于同一层。
  18. 根据权利要求13-17任一项所述的显示基板，还包括第二填充层，其中，所述第二填充层包括至少一个第二填充部，所述第二填充部位于相邻连接电极之间。
  19. 根据权利要求18所述的显示基板，其中，所述第二填充部分别与所述相邻连接电极接触。
  20. 根据权利要求18或19所述的显示基板，其中，所述第二填充层包 括绝缘层。
  21. 根据权利要求18-20任一项所述的显示基板，其中，所述第二填充层和所述绝缘填充层位于同一层。
  22. 根据权利要求1-21任一项所述的显示基板，还包括传感器电极图案，其中，所述传感器电极图案包括多个传感器电极；所述传感器电极呈块状，所述传感器电极被配置为接收检测驱动信号。
  23. 根据权利要求22所述的显示基板，所述传感器电极的形状和所述第一电极的形状相同。
  24. 根据权利要求22或23所述的显示基板，所述传感器电极图案的图案密度和所述第一电极图案的图案密度相同。
  25. 根据权利要求22-24任一项所述的显示基板，还包括第三填充层，其中，所述第三填充层包括多个第三填充部，所述第三填充部位于相邻传感器电极、相邻的所述传感器电极和所述第一虚设电极中至少之一之间。
  26. 根据权利要求1-25任一项所述的显示基板，其中，所述发光功能层与所述第一填充层接触。
  27. 根据权利要求26所述的显示基板，其中，所述发光功能层与部分所述第一填充层接触。
  28. 根据权利要求1-27任一项所述的显示基板，其中，所述连接电极图案呈环形。
  29. 根据权利要求1-28任一项所述的显示基板，其中，所述第一电极为发光元件的阳极，所述第二电极为所述发光元件的阴极。
  30. 根据权利要求2-21任一项所述的显示基板，其中，所述衬底基板包括硅晶圆。
  31. 一种显示装置，包括权利要求1-30任一项所述的显示基板。
  32. 一种显示基板的制作方法，包括：
    形成第一电极图案，所述第一电极图案位于所述显示基板的显示区，并包括彼此间隔的多个第一电极，所述第一电极被配置为接收像素驱动信号；
    形成连接电极图案，所述连接电极图案位于所述显示基板的周边区；
    形成第二电极，所述第二电极位于所述显示区和所述周边区，并与所述连接电极图案相连，所述第二电极与所述第一电极图案彼此间隔，所述第二 电极被配置为接收第一电源信号；
    形成发光功能层，所述发光功能层位于所述第一电极图案和所述第二电极之间；以及
    形成第一虚设电极图案，所述第一虚设电极图案包括多个第一虚设电极，
    其中，所述连接电极图案围绕所述第一电极图案，所述第一虚设电极图案位于所述连接电极图案和所述第一电极图案之间，所述多个第一虚设电极中的至少两个呈彼此隔开的块状。
  33. 根据权利要求32所述的制作方法，其中，所述第一虚设电极呈块状，所述第一虚设电极图案的图案密度和所述第一电极图案的图案密度相同。
  34. 根据权利要求32或33所述的制作方法，还包括：形成第二虚设电极图案，其中，所述第二虚设电极图案包括多个第二虚设电极；所述第二虚设电极图案位于所述连接电极图案的远离所述第一电极图案的一侧，所述第二虚设电极图案的图案密度和所述第一电极图案的图案密度相同。
  35. 根据权利要求32-34任一项所述的制作方法，还包括形成绝缘填充层，其中，所述绝缘填充层覆盖所述多个第一虚设电极，所述多个第一虚设电极和所述绝缘填充层构成第一填充层，所述第一电极图案包括靠近所述连接电极的边缘第一电极，所述绝缘填充层分别与所述连接电极和所述边缘第一电极接触。
  36. 根据权利要求35所述的制作方法，还包括：形成传感器电极图案，其中，所述传感器电极图案包括多个传感器电极；所述传感器电极呈块状，所述传感器电极图案的图案密度和所述第一电极图案的图案密度相同。
  37. 根据权利要求32-36任一项所述的制作方法，还包括：形成像素定义层，其中，所述像素定义层包括多个像素定义部，所述像素定义部位于相邻第一电极之间。
  38. 根据权利要求36或37所述的制作方法，还包括：形成第二填充层，其中，所述第二填充层包括至少一个第二填充部，所述第二填充部位于相邻连接电极之间。
  39. 根据权利要求38所述的制作方法，还包括：形成第三填充层，所述第三填充层包括多个第三填充部，所述第三填充部位于相邻传感器电极、相邻的所述传感器电极和所述第一虚设电极中至少之一之间。
  40. 根据权利要求32所述的制作方法，还包括形成第二虚设电极图案、传感器电极图案、像素定义层、绝缘填充层、第二填充层和第三填充层，其中，
    所述传感器电极图案包括多个传感器电极；
    所述第二虚设电极图案包括多个第二虚设电极；所述第二虚设电极图案位于所述连接电极图案的远离所述第一电极图案的一侧；
    所述像素定义层包括多个像素定义部，所述像素定义部位于相邻第一电极之间；
    所述绝缘填充层覆盖所述多个第一虚设电极；
    所述第二填充层包括至少一个第二填充部，所述第二填充部位于相邻连接电极之间；
    所述第三填充层包括多个第三填充部，所述第三填充部位于相邻传感器电极、相邻的所述传感器电极和所述第一虚设电极中至少之一之间；
    采用同一构图工艺形成所述像素定义层、所述绝缘填充层、所述第二填充层和所述第三填充层；
    采用同一构图工艺形成所述第一电极图案、所述连接电极图案、所述第一虚设电极图案、所述第二虚设电极图案和所述传感器电极图案。
  41. 根据权利要求40所述的制作方法，其中，所述绝缘填充层包括多个绝缘填充部，所述绝缘填充部位于相邻第一虚设电极之间。
PCT/CN2019/102887 2019-08-27 2019-08-27 显示基板及其制作方法、显示装置 WO2021035547A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201980001498.4A CN112740416B (zh) 2019-08-27 2019-08-27 显示基板及其制作方法、显示装置
US16/958,821 US20220384553A1 (en) 2019-08-27 2019-08-27 Display substrate and manufacturing method thereof, and display device
EP19933241.2A EP4024468A4 (en) 2019-08-27 2019-08-27 DISPLAY SUBSTRATE, METHOD FOR MAKING IT AND DISPLAY DEVICE
PCT/CN2019/102887 WO2021035547A1 (zh) 2019-08-27 2019-08-27 显示基板及其制作方法、显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/102887 WO2021035547A1 (zh) 2019-08-27 2019-08-27 显示基板及其制作方法、显示装置

Publications (1)

Publication Number Publication Date
WO2021035547A1 true WO2021035547A1 (zh) 2021-03-04

Family

ID=74683977

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/102887 WO2021035547A1 (zh) 2019-08-27 2019-08-27 显示基板及其制作方法、显示装置

Country Status (4)

Country Link
US (1) US20220384553A1 (zh)
EP (1) EP4024468A4 (zh)
CN (1) CN112740416B (zh)
WO (1) WO2021035547A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112714966A (zh) * 2019-08-27 2021-04-27 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
WO2021035546A1 (zh) 2019-08-27 2021-03-04 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
KR20240062158A (ko) * 2022-10-25 2024-05-09 삼성디스플레이 주식회사 표시 패널

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150034921A1 (en) * 2013-08-05 2015-02-05 Samsung Display Co., Ltd. Organic light-emitting display apparatus including a shield layer and method of manufacturing the same
CN106935628A (zh) * 2015-12-30 2017-07-07 乐金显示有限公司 柔性有机发光二极管显示装置
CN107665062A (zh) * 2016-07-29 2018-02-06 三星显示有限公司 显示装置
CN109509771A (zh) * 2017-09-15 2019-03-22 三星显示有限公司 显示装置
CN109860204A (zh) * 2017-11-30 2019-06-07 三星显示有限公司 显示装置及其制造方法
CN110098223A (zh) * 2018-01-31 2019-08-06 三星显示有限公司 显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3997888B2 (ja) * 2002-10-25 2007-10-24 セイコーエプソン株式会社 電気光学装置、電気光学装置の製造方法及び電子機器
KR100698689B1 (ko) * 2004-08-30 2007-03-23 삼성에스디아이 주식회사 발광 표시장치와 그의 제조방법
JP6114664B2 (ja) * 2013-08-29 2017-04-12 株式会社ジャパンディスプレイ 有機ｅｌ表示装置
KR20160149384A (ko) * 2015-06-17 2016-12-28 삼성디스플레이 주식회사 표시 장치
CN107799577B (zh) * 2017-11-06 2019-11-05 武汉华星光电半导体显示技术有限公司 Amoled显示面板及amoled显示器
KR102534121B1 (ko) * 2018-01-25 2023-05-19 삼성디스플레이 주식회사 디스플레이 장치
JP7320407B2 (ja) * 2019-08-26 2023-08-03 株式会社ジャパンディスプレイ 表示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150034921A1 (en) * 2013-08-05 2015-02-05 Samsung Display Co., Ltd. Organic light-emitting display apparatus including a shield layer and method of manufacturing the same
CN106935628A (zh) * 2015-12-30 2017-07-07 乐金显示有限公司 柔性有机发光二极管显示装置
CN107665062A (zh) * 2016-07-29 2018-02-06 三星显示有限公司 显示装置
CN109509771A (zh) * 2017-09-15 2019-03-22 三星显示有限公司 显示装置
CN109860204A (zh) * 2017-11-30 2019-06-07 三星显示有限公司 显示装置及其制造方法
CN110098223A (zh) * 2018-01-31 2019-08-06 三星显示有限公司 显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4024468A4 *

Also Published As

Publication number Publication date
EP4024468A1 (en) 2022-07-06
CN112740416A (zh) 2021-04-30
EP4024468A4 (en) 2022-09-21
US20220384553A1 (en) 2022-12-01
CN112740416B (zh) 2024-07-26

Similar Documents

Publication Publication Date Title
US11716877B2 (en) Organic light-emitting display device and method of manufacturing the same
WO2021035546A1 (zh) 显示基板及其制作方法、显示装置
US10504976B2 (en) OLED display device and method of manufacturing the same
US9640589B2 (en) Organic electroluminescent display panel and display device
WO2020233284A1 (zh) 显示面板及其制作方法、显示装置
US11362278B2 (en) Method of forming organic light-emitting display panel
WO2021035547A1 (zh) 显示基板及其制作方法、显示装置
CN112714955B (zh) 显示基板、显示面板及显示基板的制备方法
WO2020154875A1 (zh) 像素单元及其制造方法和双面oled显示装置
CN111930264B (zh) 一种触控显示面板和触控显示装置
JP2019012684A (ja) Ｏｌｅｄ表示装置及びその製造方法
KR101978779B1 (ko) 유기발광 다이오드 표시장치 및 그 제조 방법
JP7547384B2 (ja) 表示基板及びその製造方法、表示装置
KR20190063966A (ko) 전계발광 표시장치
WO2021035537A1 (zh) 有机发光二极管显示基板及其制作方法和显示装置
CN117082943A (zh) 显示面板及其制备方法
KR20150070544A (ko) 유기 발광 표시장치 및 그 제조방법
WO2021035548A1 (zh) 显示基板及其制作方法、显示装置
JP2016170935A (ja) 電気光学装置の製造方法
KR20150075135A (ko) 유기전계발광 표시장치 및 그 제조 방법
KR102309842B1 (ko) 유기 발광 다이오드 표시장치 및 그 제조방법
WO2021035529A1 (zh) 电子装置基板及其制作方法、电子装置
KR102361967B1 (ko) 유기전계발광 표시장치
JP5381414B2 (ja) 発光パネルの製造方法及び発光パネルの製造装置
WO2024065313A1 (zh) 显示面板及其制备方法、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19933241

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2019933241

Country of ref document: EP

Effective date: 20220328