WO2021031262A1 - 适用于现场可编程逻辑阵列的改进电磁暂态仿真方法 - Google Patents
适用于现场可编程逻辑阵列的改进电磁暂态仿真方法 Download PDFInfo
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- the invention relates to a power system, in particular to an improved electromagnetic transient simulation method suitable for a field programmable logic array.
- Electromagnetic transient simulation is an important tool for power system safety analysis and control research. Electromagnetic transient simulation is divided into offline simulation and real-time simulation. At present, electromagnetic transient offline simulation software such as Matlab/Simulink, PSCAD/EMTDC, etc. generally have problems such as slow simulation speed, long time-consuming, and no support for real-time interaction with external hardware. Meet higher experimental requirements such as Hardware-in-Loop (HiL). At this time, electromagnetic transient real-time simulation stands out due to its high computational efficiency, good accuracy, and strong interactivity, and has gradually attracted widespread attention.
- electromagnetic transient offline simulation software such as Matlab/Simulink, PSCAD/EMTDC, etc.
- HiL Hardware-in-Loop
- electromagnetic transient real-time simulation platforms such as RTDS, RT-LAB, etc. have been widely used in the research of power systems. They all use Field Programmable Gate Array (FPGA) architecture to implement power electronics containing power electronics. Real-time simulation of system electromagnetic transient. Unlike serial hardware such as CPUs, FPGAs have the advantages of strong computing power and high-parallel architecture to ensure computing speed and truly realize real-time simulation of electromagnetic transients with small steps.
- FPGA Field Programmable Gate Array
- the traditional EMTP algorithm is designed based on the CPU architecture. There are a large number of serial structures in the algorithm flow. Direct compilation and running on FPGA will consume a lot of FPGA hardware resources and reduce the efficiency and real-time performance of real-time simulation.
- the invention compresses the simulation cycle flow in the FPGA by integrating the topology parameters, and greatly improves the efficiency of electromagnetic transient real-time simulation.
- the purpose of the present invention is to provide a method suitable for field programmable logic array (FPGA), which avoids complicated initialization operations in the field programmable logic array (FPGA) At the same time, the process of the main part of the simulation loop in the FPGA is compressed to the greatest extent, and the efficiency of the electromagnetic transient simulation based on the FPGA is greatly improved.
- FPGA field programmable logic array
- An improved electromagnetic transient simulation method suitable for field programmable logic arrays is characterized in that the method includes the following steps, wherein steps 1) to 5) are the initialization phase, and step 6) is the main part of the simulation cycle:
- Step 1) Number the branches and nodes in the circuit to be simulated in sequence, and the number of the ground node is 0;
- Step 2 Form the incidence matrix M of the circuit to be simulated according to the following rules:
- Step 3 Form the branch equivalent admittance vector Y eq , node admittance matrix Y n , voltage coefficient matrix ⁇ and current coefficient matrix ⁇ of the historical current source expression of the circuit to be simulated according to the following sub-steps:
- each resistance branch, inductance branch, capacitance branch and switch branch with its accompanying circuit model.
- Each accompanying circuit contains an equivalent admittance and a parallel historical current source (for resistance, The expressions of the equivalent admittance and historical current source of the inductance and capacitance branches can be found in the electromagnetic transient simulation textbook, while the equivalent admittance of the switching branch and the expression of the historical current source can be found in the small step size of the power electronic switch Model related literature);
- Each Norton equivalent circuit includes an equivalent admittance and a parallel equivalent current source
- the equivalent admittances of all branches are formed into a branch equivalent admittance column vector Y eq according to the branch numbers, and the historical current sources of all branches are formed into a branch historical current source column vector I his according to the branch numbers,
- the equivalent current sources of all branches are grouped into a branch equivalent current source column vector I src according to the branch numbers.
- I src For resistance, inductance, capacitance, and switching branches, the element at the corresponding position in I src is zero.
- the elements at corresponding positions in I his are zero;
- the node admittance matrix Y n of the circuit to be simulated can be calculated (the specific method can refer to the electromagnetic transient simulation textbook);
- Step 4 According to the incidence matrix M, branch equivalent admittance vector Y eq and node admittance matrix Y n of the circuit to be simulated, form the node voltage/branch current coefficient matrix P and historical current directly used in the main body of the simulation cycle Source coefficient matrix Q:
- M T is the transpose operation on the correlation matrix
- I is N brn * N brn unit matrix
- Step 5 Convert the initial historical current source vector Set to zero, the current simulation time n is set to 1, the initialization phase is completed, the above steps are completed in the host computer;
- Step 6 The main part of the simulation loop, the algorithm is compiled in the field programmable logic array (FPGA), which mainly completes the following functions:
- the equivalent current source vector It is automatically updated with the size of the independent voltage source and independent current source.
- the diagonal elements corresponding to the switch branches in the diagonal matrix ⁇ and ⁇ change with the switch state, while other elements are fixed.
- step 6) Repeat step 6) until the specified simulation time or receive an early termination instruction, the simulation ends.
- the present invention is initialized in the host computer, the simulation topology parameters are integrated into two matrices, and the loop simulation is performed in the field programmable logic array (FPGA). Only simple matrix calculations are required to obtain the electrical The parameters avoid complicated initialization operations in FPGA, and at the same time compress the flow of the main part of the simulation loop in FPGA to the greatest extent.
- FPGA field programmable logic array
- the electromagnetic transient simulation using the method of the present invention has a higher resource utilization rate than the traditional electromagnetic transient simulation method, and greatly improves the efficiency of the FPGA-based electromagnetic transient simulation.
- electromagnetic transient simulation it is necessary to improve its calculation efficiency while ensuring its accuracy.
- the traditional EMTP algorithm is based on the CPU architecture. There are a large number of serial structures in the algorithm. Directly running in the FPGA will consume a lot of resources, affect the efficiency of the simulation, and reduce the simulation. Real-time.
- the complicated initialization operation is carried out in the host computer, and only the main part of the simulation cycle is performed in the FPGA. Simultaneously, the simulation process is compressed to the greatest extent in algorithm, which saves FPGA hardware resources and improves the simulation speed.
- Figure 1 is a comparison of the voltage and current waveforms of the transformer under the method of the present invention and offline simulation, where a is the offline simulation result of the power electronics simulation software PLECS, and b is the real-time simulation result of the method of the present invention;
- FIG. 2 is a dual active bridge (Dual Active Bridge, DAB) circuit diagram
- Fig. 3 is a flowchart of an improved electromagnetic transient simulation method suitable for a field programmable logic array according to the present invention.
- DAB Dual Active Bridge
- the hardware is mainly the PXIe chassis of National Instruments (NI), and the PXIe-8135 is the PXIe controller, which is mainly responsible for the simulation of the DAB control system. It is performed through Ethernet and the host computer. Communication, display real-time simulation waveform on the host computer; PXIe-7975R is an FPGA module, which is mainly responsible for the simulation of the DAB circuit part, and is connected to the external controller and oscilloscope through the I/O port for hardware-in-the-loop simulation. Real-time communication between the two through PXIe bus to complete real-time simulation.
- NI National Instruments
- the host computer program, the PXIe controller program and the FPGA module program for real-time simulation carried out by the method of the present invention are all realized by programming through the Labview development environment of National Instruments (NI).
- NI National Instruments
- the host computer can communicate with the PXIe controller and display simulation waveforms at the same time; the PXIe controller can communicate with the host computer, read and write data from the FPGA module, and simulate the DAB control system.
- the above program does not belong to the protection scope of the present invention, and there are related program examples on the official website of National Instruments (NI), so it will not be described in detail.
- the present invention is programmed by Labview and implemented by FPGA module.
- Fig. 3 is a flowchart of an improved electromagnetic transient simulation method suitable for field programmable logic array.
- Step 1) Number the branches and nodes in the circuit to be simulated respectively in turn, where the number of the ground node is 0, as shown in Figure 2;
- Step 2 Form the incidence matrix M of the circuit to be simulated:
- Step 3 According to the following sub-steps, form the branch equivalent admittance vector Y eq , node admittance matrix Y n , voltage coefficient matrix ⁇ and current coefficient matrix ⁇ of the historical current source expression of the circuit to be simulated:
- the equivalent admittances of all branches are formed into a branch equivalent admittance column vector Y eq according to the branch numbers, and the historical current sources of all branches are formed into a branch historical current source column vector I his according to the branch numbers,
- the equivalent current sources of all branches are grouped into a branch equivalent current source column vector I src according to the branch numbers.
- the element at the corresponding position in I src is zero.
- the elements at the corresponding positions in I his are zero (the specific values of I his and I src in the calculation are detailed in step 6);
- the node admittance matrix Y n of the circuit to be simulated can be calculated (the specific method can refer to the electromagnetic transient simulation textbook);
- Step 4 According to the incidence matrix M, branch equivalent admittance vector Y eq and node admittance matrix Y n of the circuit to be simulated, form the node voltage/branch current coefficient matrix P and historical current directly used in the main body of the simulation cycle Source coefficient matrix Q:
- I the inverse matrix of the nodal admittance matrix
- M T is the transposed matrix of the incidence matrix
- I is the identity matrix with dimension N brn *N brn
- N brn the number of circuits to be simulated
- Step 5 Convert the initial historical current source vector Set to zero, the current simulation time n is set to 1, the initialization phase is completed, the above steps are completed in the host computer;
- FPGA field programmable logic array
- the equivalent current source vector It is automatically updated with the size of the independent voltage source and independent current source.
- the diagonal elements corresponding to the switch branches in the diagonal matrix ⁇ and ⁇ change with the switch state, while other elements are fixed.
- step 6) Repeat step 6) until the specified simulation time or receive an early termination instruction, the simulation ends.
- Table 1 is the DAB circuit parameters for real-time simulation under the method of the present invention
- Table 2 is the utilization of hardware resources during the real-time simulation of DAB under the method of the present invention
- Table 3 is the simulation step size for real-time simulation of DAB under the method of the present invention And the running time of each cycle in one step.
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Abstract
一种适用于现场可编程逻辑阵列(Field Programmable Gate Array，FPGA)的改进电磁暂态仿真方法，在其初始化阶段，将待仿真电路的拓扑参数整合进两个矩阵参数，在其仿真循环主体部分，只需进行简单的矩阵乘法运算，即可得到每一个仿真时刻上的电压电流信息。避免了在现场可编程逻辑阵列中进行复杂的初始化操作，同时最大限度地压缩了FPGA中仿真循环主体部分的流程，大幅提升了基于FPGA的电磁暂态仿真效率。
Description
本发明涉及电力系统，特别是一种适用于现场可编程逻辑阵列的改进电磁暂态仿真方法。
电磁暂态仿真是电力系统安全分析与控制研究的重要工具。电磁暂态仿真分为离线仿真与实时仿真，目前电磁暂态离线仿真软件如Matlab/Simulink，PSCAD/EMTDC等普遍存在仿真速度慢、耗时长且不支持与外部硬件进行实时交互等问题，从而无法满足更高的如硬件在环(Hardware-in-Loop，HiL)等的实验需求。此时，电磁暂态实时仿真凭借计算效率高、精度好、交互性强等特征脱颖而出，逐渐得到广泛关注。
加拿大的H.W.Dommel教授于20世纪60年代末提出基于EMTP的电磁暂态仿真算法，由于其具有仿真速度快、精度高且数值稳定性较好等特点，逐渐成为电磁暂态仿真的主流算法。目前的电磁暂态离线仿真软件主要基于EMTP法进行开发，但EMTP算法大多在基于CPU的通用计算机上运行，受限于硬件计算能力及高串行度处理模式，难以支持含高频电力电子器件的电力系统电磁暂态实时仿真。
目前电磁暂态实时仿真平台如RTDS、RT-LAB等已广泛应用于电力系统的研究中，他们均采用了现场可编程逻辑阵列(Field Programmable Gate Array，FPGA)架构来实现含电力电子器件的电力系统电磁暂态实时仿真。不同于CPU等串行硬件，FPGA具有计算能力强、高并行度架构等优势，保证计算速度，真正实现小步长电磁暂态仿真的实时化。
传统的EMTP算法是基于CPU架构设计的，算法流程上存在大量串行结构，直接编译在FPGA上运行，会消耗大量FPGA硬件资源，降低实时仿真的效率与实时性。本发明通过整合拓扑参数，压缩FPGA中仿真循环流程，大幅提升了电磁暂态实时仿真的效率。
发明内容
针对传统EMTP电磁暂态仿真算法的不足，本发明的目的在于提供一种适用于现场可编程逻辑阵列(FPGA)方法，该方法避免了在现场可编程逻辑阵列(FPGA)中进行复杂的初始化操作，同时最大限度地压缩了FPGA中仿真循环主体部分的流程，大幅提升了基于FPGA的电磁暂态仿真效率。
本发明的技术解决方案如下：
一种适用于现场可编程逻辑阵列的改进电磁暂态仿真方法，其特征在于该方法包括下列步骤，其中步骤1)到步骤5)是初始化阶段，步骤6)是仿真循环主体部分：
步骤1)将待仿真电路中的支路和节点分别依次进行编号，其中接地节点的编号为0；
步骤2)根据以下规则形成待仿真电路的关联矩阵M:
2.1)如果支路p和节点q相连，且支路p定义的电流正方向是流出节点q，则M(q,p)＝1；
2.2)如果支路p和节点q相连，且支路p定义的电流正方向是流入节点q，则M(q,p)＝-1；
2.3)如果支路p和节点q不相连，则则M(q,p)＝0；
步骤3)按照以下子步骤形成待仿真电路的支路等效导纳向量Y
eq、节点导纳矩阵Y
n、历史电流源表达式的电压系数矩阵ɑ和电流系数矩阵β：
3.1)将各个电阻支路、电感支路、电容支路和开关支路，分别用其伴随电路模型替换，每个伴随电路分别包含一个等效导纳和一个并联的历史电流源(对于电阻、电感、电容支路的等效导纳和历史电流源的表达式可以查阅电磁暂态仿真教材得到，而开关支路的等效导纳和历史电流源的表达式可以查阅电力电子开关小步长模型相关文献得到)；
3.2)独立电压源支路和独立电流源支路都用诺顿等效电路表示，每个诺顿等 效电路包含一个等效导纳和一个并联的等效电流源；
3.3)将所有支路的等效导纳按支路编号组成支路等效导纳列向量Y
eq，将所有支路的历史电流源按支路编号组成支路历史电流源列向量I
his，将所有支路的等效电流源按支路编号组成支路等效电流源列向量I
src，对于电阻、电感、电容和开关支路，其在I
src中对应位置的元素为零，对于独立电压源和独立电流源支路，其在I
his中对应位置的元素为零；
3.4)根据各个支路的等效导纳，可以计算待仿真电路的节点导纳矩阵Y
n(具体方法可以参考电磁暂态仿真教材)；
3.5)根据3.1)中查阅到的各个支路的历史电流源表达式，将第n+1个仿真时刻的历史电流源向量
和第n个仿真时刻的支路电压向量
和支路电流向量
的关系表示成如下形式，则可以得到历史电流源表达式的电压系数矩阵α和电流系数矩阵β：
步骤4)根据待仿真电路的关联矩阵M、支路等效导纳向量Y
eq和节点导纳矩阵Y
n，形成仿真循环主体中直接用到的节点电压/支路电流系数矩阵P和历史电流源系数矩阵Q：
其中，
是对节点导纳矩阵的求逆运算，M
T是对关联矩阵的转置运算，I是N
brn*N
brn的单位矩阵，N
brn为待仿真电路支路数；
步骤5)将初始历史电流源向量
置零，当前仿真时刻n置1，初始化阶段完成，以上步骤在上位机中完成；
步骤6)仿真循环主体部分，算法编译在现场可编程逻辑阵列(FPGA)中，主要完成以下功能：
6.1)根据当前仿真时刻的历史电流源向量
和等效电流源向量
计算当前仿真时刻的节点电压向量
和支路电流向量
6.2)与此同时，根据当前仿真时刻的历史电流源向量
和等效电流源向量
更新下一仿真时刻的历史电流源向量
其中，等效电流源向量
是随独立电压源、独立电流源的大小自动更新，对角阵α和β中开关支路对应的对角元素随开关状态变，而其他元素固定不变。
6.3)重复运行步骤6)，直到指定的仿真时刻或收到提前终止的指令时，仿真结束。
本发明的技术效果:
1)本发明在上位机中进行初始化，将仿真拓扑参数整合为两个矩阵，在现场可编程逻辑阵列(FPGA)中进行循环仿真，只需进行简单矩阵计算即可得到每个仿真时刻的电气参数，避免了在FPGA中进行复杂的初始化操作，同时最大程度上压缩了FPGA中仿真循环主体部分的流程。
2)采用本发明方法进行电磁暂态仿真比传统电磁暂态仿真方法的资源利用率更高，大幅提升了基于FPGA的电磁暂态仿真效率。对于电磁暂态仿真，在保证其精度的同时要提高其计算效率，而传统EMTP算法基于CPU架构，算法上存在大量串行结构，直接运行在FPGA中会消耗大量资源，影响仿真效率，降低仿真的实时性。本发明方法中，将复杂的初始化操作放在上位机中进行，在FPGA中只进行仿真循环主体部分，同时在算法上最大程度压缩了仿真流程，既节约FPGA硬件资源也提升了仿真速度。
图1是本发明方法与离线仿真下的变压器电压与电流的波形对比，其中a 为电力电子仿真软件PLECS的离线仿真结果，b为采用本发明方法的实时仿真结果；
图2是双有源桥(Dual Active Bridge，DAB)电路图；
图3是本发明适用于现场可编程逻辑阵列的改进电磁暂态仿真方法流程图。
为便于理解，下面将以一个如图2所示的双有源桥(Dual Active Bridge，DAB)电路为例，对本发明进行阐述，但不应以此限制本发明的保护范围。
运用本发明方法具体实现DAB的实时仿真时，硬件主要为美国国家仪器(NI)公司的PXIe机箱，其中PXIe-8135为PXIe控制器，主要负责DAB控制系统的仿真，通过以太网与上位机进行通信，在上位机上显示实时仿真波形；PXIe-7975R为FPGA模块，主要负责DAB电路部分的仿真，通过I/O端口与外置控制器和示波器相连，进行硬件在环仿真。两者之间通过PXIe总线进行实时通信，完成实时仿真。
通过本发明方法开展实时仿真的上位机程序、PXIe控制器程序和FPGA模块程序均通过美国国家仪器(NI)公司的Labview开发环境进行编程实现。利用Labview开发环境，上位机可以与PXIe控制器的进行通信，同时显示仿真波形等；PXIe控制器可以与上位机进行通信、从FPGA模块中读取和写入数据、模拟DAB的控制系统等。上述程序不属于本发明的保护范围，且在美国国家仪器(NI)公司官网上有相关的程序范例，故不再详细描述。本发明通过Labview编程，通过FPGA模块具体实施，图3是适用于现场可编程逻辑阵列的改进电磁暂态仿真方法流程图。
本发明适用于现场可编程逻辑阵列的改进电磁暂态仿真方法实施例子的步骤如下：
步骤1)将待仿真电路中的支路和节点分别依次进行编号，其中接地节点的编号为0，如图2所示；
步骤2)形成待仿真电路的关联矩阵M：
步骤3)按照以下子步骤形成待仿真电路的支路等效导纳向量Y
eq、节点导纳矩阵Y
n、历史电流源表达式的电压系数矩阵α和电流系数矩阵β：
3.1)将各个电阻支路、电感支路、电容支路和开关支路，分别用其伴随电路模型替换，每个伴随电路分别包含一个等效导纳和一个并联的历史电流源，支路的等效模型如图1所示；
3.2)独立电压源支路和独立电流源支路都用诺顿等效电路表示，每个诺顿等效电路包含一个等效导纳和一个并联的等效电流源；
3.3)将所有支路的等效导纳按支路编号组成支路等效导纳列向量Y
eq，将所有支路的历史电流源按支路编号组成支路历史电流源列向量I
his，将所有支路的等效电流源按支路编号组成支路等效电流源列向量I
src，对于电阻、电感、电容和开关支路，其在I
src中对应位置的元素为零，对于独立电压源和独立电流源支路，其在I
his中对应位置的元素为零(I
his、I
src在计算中的具体数值详见步骤6)；
Y
eq＝[100 1600 2 2 2 2 0 3.3 2 2 2 2 400 0]
T
3.4)根据各个支路的等效导纳，可以计算待仿真电路的节点导纳矩阵Y
n(具体方法可以参考电磁暂态仿真教材)；
3.5)根据3.1)中查阅到的各个支路的历史电流源表达式，将第n+1个仿真时刻的历史电流源向量
和第n个仿真时刻的支路电压向量
和支路电流向量
的关系表示成如下形式，则可以得到历史电流源表达式的电压系数矩阵α和电流系数矩阵β(具体计算数值详见步骤6)：
步骤4)根据待仿真电路的关联矩阵M、支路等效导纳向量Y
eq和节点导纳矩阵Y
n，形成仿真循环主体中直接用到的节点电压/支路电流系数矩阵P和历史电流源系数矩阵Q：
其中，
是节点导纳矩阵的逆矩阵，M
T是关联矩阵的转置矩阵，I是维度为 N
brn*N
brn的单位矩阵，N
brn为待仿真电路支路数；
步骤5)将初始历史电流源向量
置零，当前仿真时刻n置1，初始化阶段完成，以上步骤在上位机中完成；
步骤6)仿真循环主体部分，算法编译在现场可编程逻辑阵列(FPGA)中，主要完成以下功能(以n＝10为例)：
6.1)根据当前仿真时刻的历史电流源向量
和等效电流源向量
计算当前仿真时刻的节点电压向量
和支路电流向量
6.2)与此同时，根据当前仿真时刻的历史电流源向量
和等效电流源向量
更新下一仿真时刻的历史电流源向量
α'＝[0 -1 1 -1 -1 1 0 0 1 -1 -1 1 -1 0],α＝diag(α')
14×14
β'＝[0 0 1 0.66 0.66 1 1 0 1 0.66 0.66 1 0 0],β＝diag(β')
14×14
其中，等效电流源向量
是随独立电压源、独立电流源的大小自动更新，对角阵α和β中开关支路对应的对角元素随开关状态变，而其他元素固定不变。
6.3)重复运行步骤6)，直到指定的仿真时刻或收到提前终止的指令时，仿真结束。
α'＝[0 -1 1 -1 -1 1 0 0 1 -1 -1 1 -1 0],α＝diag(α')
14×14
β'＝[0 0 1 0.66 0.66 1 1 0 1 0.66 0.66 1 0 0],β＝diag(β')
14×14
表1是本发明方法下进行实时仿真的DAB电路参数；表2是本发明方法下对DAB进行实时仿真时硬件资源的利用情况；表3是本发明方法下对DAB进行实时仿真的仿真步长与每个循环在一个步长中的运行时间。
表1 DAB电路参数
表1
表2 硬件资源利用情况
表2
表3 实时性
表3
Claims (1)
- 一种适用于现场可编程逻辑阵列的改进电磁暂态仿真方法，其特征在于该方法包括初始化阶段和仿真循环阶段，具体步骤如下：初始化阶段，在上位机PC中完成：步骤1)将待仿真电路中的支路和节点分别依次进行编号，其中接地节点的编号为0；步骤2)根据以下规则形成待仿真电路的关联矩阵M：2.1)如果支路p和节点q相连，且支路p定义的电流正方向是流出节点q，则M(q,p)＝1；2.2)如果支路p和节点q相连，且支路p定义的电流正方向是流入节点q，则M(q,p)＝-1；2.3)如果支路p和节点q不相连，则M(q,p)＝0；步骤3)按照以下子步骤形成待仿真电路的支路等效导纳向量Y eq、节点导纳矩阵Y n、历史电流源表达式的电压系数矩阵α和电流系数矩阵β：3.1)将各个电阻支路、电感支路、电容支路和开关支路，分别用其伴随电路模型替换，每个伴随电路分别包含一个等效导纳和一个并联的历史电流源；3.2)独立电压源支路和独立电流源支路都用诺顿等效电路表示，每个诺顿等效电路包含一个等效导纳和一个并联的等效电流源；3.3)将所有支路的等效导纳按支路编号组成支路等效导纳列向量Y eq，将所有支路的历史电流源按支路编号组成支路历史电流源列向量I his，将所有支路的等效电流源按支路编号组成支路等效电流源列向量I src，对于电阻、电感、电容和开关支路，其在I src中对应位置的元素为零，对于独立电压源和独立电流源支路，其在I his中对应位置的元素为零；3.4)根据各个支路的等效导纳，计算待仿真电路的节点导纳矩阵Y n；3.5)计算历史电流源表达式的电压系数矩阵α和电流系数矩阵β，公式如下：
其中，为第n+1个仿真时刻的历史电流源向量，
为第n个仿真时刻的支路电压向量，
为第n个仿真时刻的支路电流向量；
步骤4)根据待仿真电路的关联矩阵M、支路等效导纳向量Y eq和节点导纳矩阵Y n，形成节点电压/支路电流系数矩阵P和历史电流源系数矩阵Q：
其中，是节点导纳矩阵的逆矩阵，M T是关联矩阵的转置矩阵，I是维度为N brn*N brn的单位矩阵，N brn为待仿真电路支路数；
步骤5)将初始历史电流源向量置零，当前仿真时刻n置1，初始化阶段完成；
仿真循环阶段，在现场可编程逻辑阵列FPGA中完成：步骤6)根据当前仿真时刻的历史电流源向量和等效电流源向量
计算当前仿真时刻的节点电压向量
和支路电流向量
并更新下一仿真时刻的历史电流源向量
公式如下：
其中，等效电流源向量是随独立电压源、独立电流源的大小自动更新，对角阵α和β中开关支路对应的对角元素随开关状态即时变化，而其他元素固定不变；
步骤7)当前仿真时刻n＝n+1，返回步骤6)，重复运行，直到指定的仿真时 刻或收到提前终止的指令时，仿真结束。
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