WO2021027277A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2021027277A1
WO2021027277A1 PCT/CN2020/078248 CN2020078248W WO2021027277A1 WO 2021027277 A1 WO2021027277 A1 WO 2021027277A1 CN 2020078248 W CN2020078248 W CN 2020078248W WO 2021027277 A1 WO2021027277 A1 WO 2021027277A1
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Prior art keywords
layer
array substrate
line
source
electrode plate
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PCT/CN2020/078248
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English (en)
French (fr)
Inventor
方亮
丁玎
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/768,896 priority Critical patent/US11233075B2/en
Publication of WO2021027277A1 publication Critical patent/WO2021027277A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate and a display panel.
  • the driving circuit is generally designed as a 7T1C compensation circuit as shown in Figure 1.
  • the gate layer of the circuit design adopts a double-layer design, and the two gates are used as storage capacitors.
  • the existing display device has the problem of high production cost, which needs to be solved.
  • the present application provides a novel array substrate and a display panel to alleviate the problem of high production cost of existing display devices.
  • the application provides an array substrate, which includes:
  • the gate layer is formed on the gate insulating layer, and is patterned to form the first electrode plate, the gate, and the scan line of the storage capacitor;
  • the source and drain layer is formed on the interlayer insulating layer and patterned to form the second electrode plate, source and drain of the storage capacitor;
  • a passivation layer is formed on the source and drain layers and the interlayer insulating layer.
  • the second electrode plate is provided with a gap, and a first connection via is provided in the area corresponding to the gap; the source and drain layer is also patterned with a first connection line, the One end of the first connection line is connected to the first electrode plate through the first connection via hole, and the other end is connected to the doped region of the target thin film transistor through the second connection via hole.
  • the first electrode plate is formed with a protrusion, and a third connection via is provided in the corresponding area of the protrusion;
  • the source and drain layer is also patterned with a second connection line, One end of the second connection line is connected to the first electrode plate through the third connection via, and the other end is connected to the doped region of the target thin film transistor through the fourth connection via.
  • the source and drain layers are also patterned to form power lines and power connection lines, and the second electrode plate is connected to the power lines through the power connection lines.
  • the power connection line is a hollow mesh structure.
  • the source and drain layers are further patterned to form power lines, and one side of the second electrode plate is integrated with the power lines.
  • the gate layer is also patterned to form a signal reset line, and the signal reset line is interrupted in the corresponding region of the channel region;
  • the source and drain layer is also patterned to form a reset connection line
  • the signal reset line is connected to one end of the reset connection line through the fifth connection via, and the other end of the reset connection line is connected to the signal reset line of the adjacent sub-pixel through the sixth connection via.
  • the source and drain layers are also patterned to form a reset transfer line, the signal reset line is connected to one end of the reset transfer line through the seventh connection via, and the other end of the reset transfer line passes through the Eight connection vias are connected to the channel region of the target thin film transistor.
  • the material of the source and drain layer is at least one of molybdenum, aluminum, aluminum nickel alloy, molybdenum tungsten alloy, chromium, copper, or titanium aluminum alloy.
  • the material of the interlayer insulating layer is silicon nitride or silicon oxide.
  • the material of the gate layer is at least one of molybdenum, aluminum, aluminum nickel alloy, molybdenum tungsten alloy, chromium, copper, or titanium aluminum alloy.
  • the material of the gate insulating layer is at least one of silicon nitride, silicon oxide, or silicon oxynitride.
  • the material of the buffer layer is at least one of silicon nitride or silicon oxide.
  • the material of the barrier layer is silicon oxide.
  • the substrate is one of a glass substrate, a quartz substrate, and a resin substrate.
  • the substrate is a flexible substrate.
  • the material for which the substrate is a flexible substrate includes polyimide.
  • the present application also provides a display panel, which includes any of the above-mentioned array substrates.
  • the display panel is an LCD display panel
  • the LCD display panel further includes:
  • Liquid crystal filled between the color filter substrate and the array substrate Liquid crystal filled between the color filter substrate and the array substrate.
  • the display panel is an OLED display panel
  • the OLED display panel further includes:
  • a pixel definition layer formed on the passivation layer, patterned to form a light-emitting definition area
  • the packaging layer is formed on the common electrode layer.
  • the array substrate includes a stacked substrate, a buffer layer, an active layer, a gate insulating layer, a gate layer, an interlayer insulating layer, a source and drain layer, and a passivation layer ;
  • the first electrode plate of the storage capacitor is formed in the gate layer, and the second electrode plate of the storage capacitor and various functional connection lines are formed in the source and drain layer.
  • the current path between the film layers saves a layer of gate structure, saves a mask, reduces production costs, and alleviates the problem of high production costs in existing display devices.
  • FIG. 1 is a circuit design diagram of a conventional display device.
  • FIG. 2 is a schematic diagram of the structure of the array substrate provided by this application.
  • FIG. 3 is a first plan view of the active layer of the array substrate provided by this application.
  • FIG. 4 is a first plan view of the gate layer of the array substrate provided by this application.
  • FIG. 5 is a first plan view of the source and drain layers of the array substrate provided by this application.
  • FIG. 6 is a schematic diagram of a first plane superposition of the active layer, the gate layer and the source and drain layers of the array substrate provided by this application.
  • FIG. 7 is a second plan view of the active layer of the array substrate provided by this application.
  • FIG. 8 is a second plan schematic view of the gate layer of the array substrate provided by this application.
  • FIG. 9 is a second plan schematic view of the source and drain layers of the array substrate provided by this application.
  • FIG. 10 is a schematic diagram of a second plane superposition of the active layer, the gate layer, and the source and drain layers of the array substrate provided by this application.
  • the present application provides an array substrate and a display panel.
  • the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the application, and not used to limit the application.
  • an array substrate including:
  • the gate layer is formed on the gate insulating layer, and is patterned to form the first electrode plate, the gate, and the scan line of the storage capacitor;
  • the source and drain layer is formed on the interlayer insulating layer and patterned to form the second electrode plate, source and drain of the storage capacitor;
  • a passivation layer is formed on the source and drain layers and the interlayer insulating layer.
  • the present application provides an array substrate, which adopts a single gate layer design.
  • the first electrode plate of the storage capacitor is formed in the gate layer, and the second electrode plate of the storage capacitor and various functional connecting lines are formed in the source and drain layers.
  • the current paths between different film layers are realized through each functional connection line, thereby eliminating a layer of gate structure, saving a mask, reducing production costs, and alleviating the problem of high production costs in existing display devices.
  • the array substrate 10 provided by the present application includes:
  • the substrate 101 can be one of a glass substrate, a quartz substrate, a resin substrate, and the like.
  • the substrate 101 may also be a flexible substrate, and the material of the flexible substrate may include polyimide.
  • a barrier layer 102 on the substrate 101 in this embodiment, the material of the barrier layer 102 may include silicon oxide.
  • the buffer layer 103 is located on the barrier layer 102; the buffer layer 103 is mainly used to buffer the pressure between the layer structure of the film, and may also have a certain function of blocking water and oxygen; in this embodiment, the buffer layer
  • the material of the layer 103 may include one or more combinations of silicon nitride or silicon oxide.
  • the active layer 104 is located on the buffer layer 103; in this embodiment, the active layer 104 includes an active region 1041, and the active region 1041 includes a channel region 10411 and is located on both sides of the channel region 10411
  • the doped region 10412 can be formed by blocking the channel region 10411 by the corresponding gate layer 103, and performing ion doping processes on the regions on both sides of the channel region 10411.
  • the material of the gate insulating layer 105 can be other insulating inorganic materials such as silicon nitride, silicon oxide, or silicon oxynitride.
  • the gate layer 106 is located on the gate insulating layer 105; the gate layer 106 is patterned to form the first electrode plate 1061 of the storage capacitor, the gate electrode and the scan line 1062, and the first electrode plate 1061 is one at the same time
  • the gate of a thin film transistor; the material of the gate layer 106 can usually be one of molybdenum, aluminum, aluminum-nickel alloy, molybdenum tungsten alloy, chromium, or copper, or a combination of the foregoing metal materials Things.
  • the material can be one of molybdenum, aluminum, aluminum-nickel alloy, molybdenum tungsten alloy, chromium, copper or titanium aluminum alloy, or a combination of the above-mentioned metal materials.
  • the gate layer 106 is located on the active layer 104.
  • the gate layer 106 includes a gate, a signal reset line VI, scan lines Scan (N), Scan (N-1), an enable signal line Em, and a storage capacitor first electrode plate 1061, so The gate, the signal reset line VI, the scan lines Scan (N), Scan (N-1), the enable signal line Em, and the storage capacitor first electrode plate 1061 are formed in the same photomask process.
  • the gate layer 106 further includes a signal reset line VI.
  • the signal reset line VI is interrupted in the corresponding area of the active layer 104.
  • the source and drain layer 108 is located on the gate layer 106.
  • the source-drain layer 108 includes a source electrode, a drain electrode, a data signal line Vdata, a power supply line VDD, a storage capacitor second electrode plate 1081, a signal reset connection line 1082, a first connection line 1083, and a signal Reset transfer line 1084, said source, said drain, said data signal line Vdata, said power line VDD, said storage capacitor second electrode plate 1081, said signal reset connection line 1082, said first The connection line 1083 and the signal reset transfer line 1084 are formed in the same photomask process.
  • the second electrode plate 1081 of the storage capacitor formed by the source and drain layer 108 has a gap for setting a first connection via, and one end of the first connection line 1083 passes through the The first connection via is connected to the first electrode plate 1061; the other end of the first connection line 1083 is connected to the active layer 104 through the second via.
  • the shape of the gap is at least one of a rectangle, a trapezoid, a circular ring, and a triangle.
  • the shape of the notch is rectangular.
  • one end of the signal reset connection line 1082 is connected to the signal reset line VI through a fifth connection via, and the other end of the reset connection line 1082 is connected to an adjacent sub-pixel through a sixth connection via.
  • the signal reset connection line 1082 is parallel to the signal reset line VI.
  • the width of the signal reset connection line 1082 is greater than the width of the signal reset line VI to reduce resistance and reduce voltage drop.
  • one end of the signal reset transfer line 1084 is connected to the signal reset line VI through a seventh connection via, and the other end of the signal reset transfer line 1084 is connected to the signal reset line VI through an eighth connection via.
  • the active layer 104 is connected.
  • the angle between the signal reset transfer line 1084 and the signal reset connection line 1082 is an acute angle.
  • the power line VDD is integrated with the second electrode plate 1081 of the storage capacitor.
  • the sum of the line width of the power line VDD and the width of the second electrode plate 1081 of the storage capacitor is equal to the width of the first electrode plate 1061 of the storage capacitor.
  • the gate layer 106 is located on the active layer 104.
  • the gate layer 106 includes a gate, a signal reset line VI, scan lines Scan (N), Scan (N-1), an enable signal line Em, and a storage capacitor first electrode plate 1061, so The gate, the signal reset line VI, the scan lines Scan (N), Scan (N-1), the enable signal line Em, and the storage capacitor first electrode plate 1061 are formed in the same photomask process.
  • the first electrode plate 1061 of the storage capacitor formed by the gate layer 106 has a protrusion, and the interlayer insulating layer 107 is provided with a third connection in the area corresponding to the protrusion. hole.
  • the shape of the protrusion is at least one of a rectangle, a trapezoid, a circular ring, and a triangle. In this embodiment, the shape of the protrusion is rectangular.
  • the source and drain layer 108 is located on the gate layer 106.
  • the source-drain layer 108 includes a source electrode, a drain electrode, a data signal line Vdata, a power supply line VDD, a storage capacitor second electrode plate 1081, a signal reset connection line 1082, a second connection line 1083, and a signal Reset transfer line 1084 and power connection line 1085, said source, said drain, said data signal line Vdata, said power line VDD, said storage capacitor second electrode plate 1081, said signal reset connection line 1082 , The second connection line 1083, the signal reset transfer line 1084 and the power connection line 1085 are formed in the same photomask process.
  • one end of the second connection line 1083 is connected to the first electrode plate 1061 through the third connection via; the other end of the second connection line 1083 is connected through a fourth via The active layer 104.
  • one end of the signal reset connection line 1082 is connected to the signal reset line VI through a fifth connection via, and the other end of the reset connection line 1082 is connected to an adjacent sub-pixel through a sixth connection via.
  • the signal reset connection line 1082 is parallel to the signal reset line VI.
  • the width of the signal reset connection line 1082 is greater than the width of the signal reset line VI to reduce resistance and reduce voltage drop.
  • one end of the signal reset transfer line 1084 is connected to the signal reset line VI through a seventh connection via, and the other end of the signal reset transfer line 1084 is connected to the signal reset line VI through an eighth connection via.
  • the active layer 104 is connected.
  • the angle between the signal reset transfer line 1084 and the signal reset connection line 1082 is an acute angle.
  • the second electrode plate 1081 is connected to the power line VDD through the power connection line 1085.
  • the power connection line 1085 is perpendicular to the power line VDD and perpendicular to one side of the second electrode plate 1081.
  • the number of the power connection wires 1085 is greater than two.
  • the power connection line 1085 is a hollow mesh structure to form a parallel circuit for data signal transmission, which reduces the resistance of the metal wire for transmitting the data signal and reduces the voltage drop; in addition, the mesh structure design method can reduce the metal An abnormal disconnection caused by a broken wire.
  • the present application also provides a display panel, the display panel includes an array substrate, and the array substrate includes:
  • the gate layer is formed on the gate insulating layer, and is patterned to form the first electrode plate, the gate, and the scan line of the storage capacitor;
  • the source and drain layer is formed on the interlayer insulating layer and patterned to form the second electrode plate, source and drain of the storage capacitor;
  • a passivation layer is formed on the source and drain layers and the interlayer insulating layer.
  • the embodiment of the application provides a display panel, the display panel includes an array substrate, and the array substrate includes a stacked substrate, a buffer layer, an active layer, a gate insulating layer, a gate layer, an interlayer insulating layer, source and drain Electrode layer and passivation layer; using a single gate layer design, the first electrode plate of the storage capacitor is formed in the gate layer, and the second electrode plate of the storage capacitor and various functional connection lines are formed in the source and drain layer.
  • Each functional connection line realizes a current path between different film layers, thereby eliminating a layer of gate structure, saving a mask, reducing production costs, and alleviating the problem of high production costs in existing display devices.
  • the second electrode plate is provided with a gap, and a first connection via is provided in the area corresponding to the gap; the source and drain layer is further patterned with a first connection line, One end of a connection line is connected to the first electrode plate through the first connection via hole, and the other end is connected to the doped region of the target thin film transistor through the second connection via hole.
  • the first electrode plate is formed with a protrusion, and a third connection via is provided in the area corresponding to the protrusion; the source and drain layer is also patterned with a second connection line, so One end of the second connection line is connected to the first electrode plate through the third connection via hole, and the other end is connected to the doped region of the target thin film transistor through the fourth connection via hole.
  • the source and drain layers are further patterned to form a power line and a power connection line, and the second electrode plate is connected to the power line through the power connection line.
  • the source and drain layers are further patterned to form power lines, and one side of the second electrode plate is integrated with the power lines.
  • the gate layer is further patterned to form a signal reset line, and the signal reset line is interrupted in the corresponding area of the active region; the source and drain layer is also patterned to form a reset connection line, The signal reset line is connected to one end of the reset connection line through a fifth connection via, and the other end of the reset connection line is connected to a signal reset line of an adjacent sub-pixel through a sixth connection via.
  • the source and drain layers are also patterned to form a reset transfer line
  • the signal reset line is connected to one end of the reset transfer line through the seventh connection via
  • the other end of the reset transfer line passes through the eighth connection via.
  • the connection via is connected to the doped region of the target thin film transistor.
  • the display panel is an LCD display panel
  • the LCD display panel further includes:
  • Liquid crystal filled between the color filter substrate and the array substrate Liquid crystal filled between the color filter substrate and the array substrate.
  • the display panel is an OLED display panel
  • the OLED display panel further includes:
  • a pixel definition layer formed on the passivation layer, patterned to form a light-emitting definition area
  • the packaging layer is formed on the common electrode layer.
  • this application also provides a method for manufacturing an array substrate, including:
  • the embodiment of the application provides a method for preparing an array substrate.
  • the preparation method is to sequentially prepare a buffer layer, an active layer, a gate insulating layer, a gate layer, an interlayer insulating layer, a source and drain layer, and Passivation layer.
  • the first electrode plate of the storage capacitor is formed in the gate layer
  • the second electrode plate of the storage capacitor and various functional connection lines are formed in the source and drain layer, and different films are realized through each functional connection line.
  • the current path between the layers saves a layer of gate structure, saves a mask, reduces production costs, and alleviates the problem of high production costs in existing display devices.
  • the embodiments of the application provide a method for preparing an array substrate, a display panel, and an array substrate.
  • the array substrate includes a substrate, a buffer layer, an active layer, a gate insulating layer, a gate layer, an interlayer insulating layer, Source drain layer and passivation layer.
  • the first electrode plate of the storage capacitor is formed in the gate layer
  • the second electrode plate of the storage capacitor and various functional connection lines are formed in the source and drain layer, and different films are realized through each functional connection line.
  • the current path between the layers saves a layer of gate structure, saves a mask, reduces production costs, and alleviates the problem of high production costs in existing display devices.

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Abstract

本申请提供一种阵列基板及显示面板，其采用单栅极层设计，在栅极层内形成存储电容的第一电极板，在源漏极层内形成存储电容的第二电极板和各种功能连接线，通过各功能连接线实现不同膜层间的电流通路，从而省去了一层栅极结构，节省了一道光罩，降低了生产成本，缓解了现有显示装置存在生产成本高的问题。

Description

阵列基板及显示面板
本申请要求于2019年08月12日提交中国专利局、申请号为201910740864.X、发明名称为“阵列基板及显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其是涉及一种阵列基板及显示面板。
 背景技术
现有显示装置为精确控制电流大小，改善发光均一性，驱动电路一般为如图1所示的7T1C补偿电路设计，该电路设计的栅极层采用双层设计，两层栅极分别作为储存电容的第一电极板和第二电极板。
然而，双层栅极的设计方式，增加了产品的生产成本。
因此，现有显示装置存在生产成本高的问题，需要解决。
 技术问题
本申请提供一种新型阵列基板及显示面板，以缓解现有显示装置存在生产成本高的问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种阵列基板，其包括：
衬底；
缓冲层，形成于所述衬底上；
有源层，形成于所述缓冲层上，图案化形成薄膜晶体管的有源区，所述有源区包括掺杂区和沟道区；
栅极绝缘层，形成于所述有源层及所述缓冲层上；
栅极层，形成于所述栅极绝缘层上，图案化形成储存电容的第一电极板、栅极、扫描线；
层间绝缘层，形成于所述栅极层及所述栅极绝缘层上；
源漏极层，形成于所述层间绝缘层上，图案化形成所述储存电容的第二电极板、源极、漏极；
钝化层，形成于所述源漏极层以及所述层间绝缘层上。
在本申请的阵列基板中，所述第二电极板设置有缺口，所述缺口对应区域内设置有第一连接过孔；所述源漏极层还图案化形成有第一连接线，所述第一连接线的一端通过所述第一连接过孔，连接所述第一电极板，另一端通过第二连接过孔连接目标薄膜晶体管的掺杂区。
在本申请的阵列基板中，所述第一电极板形成有突出部，所述突出部对应区域内设置有第三连接过孔；所述源漏极层还图案化形成有第二连接线，所述第二连接线的一端通过所述第三连接过孔，连接所述第一电极板，另一端通过第四连接过孔连接目标薄膜晶体管的掺杂区。
在本申请的阵列基板中，所述源漏极层还图案化形成电源线以及电源连接线，所述第二电极板通过所述电源连接线与所述电源线连接。
在本申请的阵列基板中，所述电源连接线为镂空的网状结构。
在本申请的阵列基板中，所述源漏极层还图案化形成电源线，所述第二电极板的一侧边与所述电源线一体。
在本申请的阵列基板中，所述栅极层还图案化形成信号复位线，所述信号复位线在所述沟道区对应区域内中断；所述源漏极层还图案化形成复位连接线，信号复位线通过第五连接过孔连接所述复位连接线的一端，所述复位连接线的另一端通过第六连接过孔连接相邻子像素的信号复位线。
在本申请的阵列基板中，所述源漏极层还图案化形成复位转接线，信号复位线通过第七连接过孔连接所述复位转接线的一端，所述复位转接线的另一端通过第八连接过孔连接目标薄膜晶体管的沟道区。
在本申请的阵列基板中，所述源漏极层的材料为钼、铝、铝镍合金、钼钨合金、铬、铜或钛铝合金中的至少一种。
在本申请的阵列基板中，所述层间绝缘层的材料为氮化硅或氧化硅。
在本申请的阵列基板中，所述栅极层的材料为钼、铝、铝镍合金、钼钨合金、铬、铜或钛铝合金中的至少一种。
在本申请的阵列基板中，所述栅极绝缘层的材料为氮化硅、氧化硅或氮氧化硅中的至少一种。
在本申请的阵列基板中，所述缓冲层的材料为氮化硅或氧化硅中的至少一种。
在本申请的阵列基板中，所述阻挡层的材料为氧化硅。
在本申请的阵列基板中，所述衬底为玻璃基板、石英基板、树脂基板中的一种。
在本申请的阵列基板中，所述衬底为柔性基板。
在本申请的阵列基板中，所述衬底为柔性基板的材料包括聚酰亚胺。
同时，本申请还提供一种显示面板，其包括以上任一所述的阵列基板。
在本申请提供显示面板中，所述显示面板为LCD显示面板，所述LCD显示面板还包括：
彩膜基板；
填充于所述彩膜基板和所述阵列基板之间的液晶。
在本申请提供显示面板中，所述显示面板为OLED显示面板，所述OLED显示面板还包括：
像素定义层，形成于所述钝化层上，图案化形成发光定义区；
发光材料层，形成于所述发光定义区内；
公共电极层，形成于所述发光材料层以及所述像素定义层上；
封装层，形成于所述公共电极层上。
 有益效果
本申请提供一种阵列基板及显示面板，其阵列基板包括层叠设置的衬底、缓冲层、有源层、栅极绝缘层、栅极层、层间绝缘层、源漏极层和钝化层；采用单栅极层设计，在栅极层内形成存储电容的第一电极板，在源漏极层内形成存储电容的第二电极板和各种功能连接线，通过各功能连接线实现不同膜层间的电流通路，从而省去了一层栅极结构，节省了一道光罩，降低了生产成本，缓解了现有显示装置存在生产成本高的问题。
 附图说明
图1为现有显示装置的电路设计图。
图2为本申请提供的阵列基板的结构示意图。
图3为本申请提供的阵列基板的有源层的第一种平面示意图。
图4为本申请提供的阵列基板的栅极层的第一种平面示意图。
图5为本申请提供的阵列基板的源漏极层的第一种平面示意图。
图6为本申请提供的阵列基板的有源层、栅极层和源漏极层的第一种平面叠加示意图。
图7为本申请提供的阵列基板的有源层的第二种平面示意图。
图8为本申请提供的阵列基板的栅极层的第二种平面示意图。
图9为本申请提供的阵列基板的源漏极层的第二种平面示意图。
图10为本申请提供的阵列基板的有源层、栅极层和源漏极层的第二种平面叠加示意图。
 本发明的实施方式
本申请提供一种阵列基板及显示面板，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
为缓解现有显示装置存在成本过高的问题，本申请实施例提供一种阵列基板，包括：
衬底；
缓冲层，形成于所述衬底上；
有源层，形成于所述缓冲层上，图案化形成薄膜晶体管的有源区，所述有源区包括掺杂区和沟道区；
栅极绝缘层，形成于所述有源层及所述缓冲层上；
栅极层，形成于所述栅极绝缘层上，图案化形成储存电容的第一电极板、栅极、扫描线；
层间绝缘层，形成于所述栅极层及所述栅极绝缘层上；
源漏极层，形成于所述层间绝缘层上，图案化形成所述储存电容的第二电极板、源极、漏极；
钝化层，形成于所述源漏极层以及所述层间绝缘层上。
本申请提供一种阵列基板，采用单栅极层设计，在栅极层内形成存储电容的第一电极板，在源漏极层内形成存储电容的第二电极板和各种功能连接线，通过各功能连接线实现不同膜层间的电流通路，从而省去了一层栅极结构，节省了一道光罩，降低了生产成本，缓解了现有显示装置存在生产成本高的问题。
在一种实施例中，如图2所示，本申请提供的阵列基板10包括：
衬底10；在本实施例中，所述衬底101可以为玻璃基板、石英基板、树脂基板等中的一种。所述衬底101还可以为柔性基板，所述柔性基板的材料可以包括聚酰亚胺。
位于所述衬底101上的阻挡层102；在本实施例中，所述阻挡层102的材料可以包括氧化硅。
位于所述阻挡层102上的缓冲层103；所述缓冲层103主要用于缓冲膜层质结构之间的压力，并且还可以具有一定阻水氧的功能；在本实施例中，所述缓冲层103的材料可以包括氮化硅或氧化硅中的一种或一种以上的组合物。
位于所述缓冲层103上的有源层104；在本实施例中，所述有源层104包括有源区1041，所述有源区1041包括沟道区10411和位于沟道区10411两侧的掺杂区10412；所述掺杂区10412可以由对应的栅极层103阻挡所述沟道区10411，并对所述沟道区10411两侧的区域进行离子掺杂工艺而形成。
位于所述有源层104和所述缓冲层上的栅极绝缘层105，所述栅极绝缘层105主要用于将所述有源层104与位于所述有源层104上的金属层隔离；在本实施例中，所述栅极绝缘层105的材料可以为氮化硅、氧化硅或氮氧化硅等其他绝缘的无机材料。
位于所述栅极绝缘层105上的栅极层106；所述栅极层106图案化形成储存电容的第一电极板1061、栅极和扫描线1062，所述第一电极板1061同时为一薄膜晶体管的栅极；所述栅极层106的材料通常可以采用钼、铝、铝镍合金、钼钨合金、铬、或铜等金属中的一种，也可以使用上述几种金属材料的组合物。
位于所述栅极绝缘层105和所述栅极层106上的层间绝缘层107，所述层间绝缘层主要用于将所述栅极层106和位于所述栅极层106上的金属层隔离；在本实施例中，所述层间绝缘层107的材料为氮化硅或氧化硅。
位于所述层间绝缘层107上的源漏极层108；所述源漏极层108图案化形成存储电容的第二电极板1081、源极1082、漏极1083；所述源漏极层108的材料可以采用钼、铝、铝镍合金、钼钨合金、铬、铜或钛铝合金等金属中的一种，也可以使用上述几种金属材料的组合物。
在一种实施例中，参照图3至图6，在本申请提供的阵列基板中：
所述栅极层106位于所述有源层104上。
在本实施例中，所述栅极层106包括栅极、信号复位线VI、扫描线Scan（N）、Scan（N-1）、使能信号线Em和储存电容第一电极板1061，所述栅极、信号复位线VI、扫描线Scan（N）、Scan（N-1）、使能信号线Em和所述储存电容第一电极板1061在同一道光罩工艺中形成。
在本实施例中，所述栅极层106还包括信号复位线VI。所述信号复位线VI在所述有源层104对应区域中断。
所述源漏极层108位于所述栅极层106上。
在本实施例中，所述源漏极层108包括源极、漏极、数据信号线Vdata、电源线VDD、储存电容第二电极板1081、信号复位连接线1082、第一连接线1083和信号复位转接线1084，所述源极、所述漏极、所述数据信号线Vdata、所述电源线VDD、所述储存电容第二电极板1081、所述信号复位连接线1082、所述第一连接线1083和所述信号复位转接线1084在同一道光罩工艺中形成。
在一种实施例中，所述源漏极层108形成的所述储存电容第二电极板1081上有缺口，用于设置第一连接过孔，所述第一连接线1083的一端通过所述第一连接过孔与所述第一电极板1061连接；所述第一连接线1083的另一端通过第二过孔连接有源层104。
在一种实施例中,所述缺口的形状为矩形、梯形、圆环形、三角形中的至少一种。在本实施中，所述缺口的形状为矩形。
在一种实施例中，所述信号复位连接线1082一端通过第五连接过孔与所述信号复位线VI连接，所述复位连接线1082的另一端通过第六连接过孔连接相邻子像素的信号复位线VI。所述信号复位连接线1082与所述信号复位线VI平行。
所述信号复位连接线1082的宽度大于所述信号复位线VI的宽度，以减小电阻，降低电压降。
在一种实施例中，所述信号复位转接线1084的一端通过第七连接过孔与所述信号复位线VI连接，所述信号复位转接线1084的另一端通过第八连接过孔与所述有源层104连接。
所述信号复位转接线1084与所述信号复位连接线1082的夹角是锐角。
在一种实施例中，所述电源线VDD与所述储存电容第二电极板1081一体。所述电源线VDD的线宽与所述储存电容第二电极板1081的宽度和等于所述储存电容第一电极板1061的宽度。
在一种实施例中，参照图7至图10，在本申请提供的阵列基板中：
所述栅极层106位于所述有源层104上。
在本实施例中，所述栅极层106包括栅极、信号复位线VI、扫描线Scan（N）、Scan（N-1）、使能信号线Em和储存电容第一电极板1061，所述栅极、信号复位线VI、扫描线Scan（N）、Scan（N-1）、使能信号线Em和所述储存电容第一电极板1061在同一道光罩工艺中形成。
在一种实施例中，所述栅极层106形成的所述储存电容第一电极板1061上有突出部，所述层间绝缘层107在所述突出部对应区域内设置有第三连接过孔。所述突出部的形状为矩形、梯形、圆环形、三角形中的至少一种。在本实施例中，所述突出部的形状为矩形。
所述源漏极层108位于所述栅极层106上。
在本实施例中，所述源漏极层108包括源极、漏极、数据信号线Vdata、电源线VDD、储存电容第二电极板1081、信号复位连接线1082、第二连接线1083、信号复位转接线1084和电源连接线1085，所述源极、所述漏极、所述数据信号线Vdata、所述电源线VDD、所述储存电容第二电极板1081、所述信号复位连接线1082、所述第二连接线1083、所述信号复位转接线1084和所述电源连接线1085在同一道光罩工艺中形成。
在一种实施例中，所述第二连接线1083的一端通过所述第三连接过孔与所述第一电极板1061连接；所述第二连接线1083的另一端通过第四过孔连接有源层104。
在一种实施例中，所述信号复位连接线1082一端通过第五连接过孔与所述信号复位线VI连接，所述复位连接线1082的另一端通过第六连接过孔连接相邻子像素的信号复位线VI。所述信号复位连接线1082与所述信号复位线VI平行。
所述信号复位连接线1082的宽度大于所述信号复位线VI的宽度，以减小电阻，降低电压降。
在一种实施例中，所述信号复位转接线1084的一端通过第七连接过孔与所述信号复位线VI连接，所述信号复位转接线1084的另一端通过第八连接过孔与所述有源层104连接。
所述信号复位转接线1084与所述信号复位连接线1082的夹角是锐角。
在一种实施例中，所述第二电极板1081通过所述电源连接线1085与所述电源线VDD连接。所述电源连接线1085垂直于所述电源线VDD、且垂直于所述述第二电极板1081的一侧边。所述电源连接线1085的数量大于两个。
所述电源连接线1085为镂空的网状结构，以形成并联电路进行数据信号的传输，降低了传输数据信号的金属线的电阻，减小了电压降；另外网状结构设计方式可以降低因金属线断线造成的断路异常。
同时，本申请还提供一种显示面板，所述显示面板包括阵列基板，所述阵列基板包括：
衬底；
缓冲层，形成于所述衬底上；
有源层，形成于所述缓冲层上，图案化形成薄膜晶体管的有源区，所述有源区包括掺杂区和沟道区；
栅极绝缘层，形成于所述有源层及所述缓冲层上；
栅极层，形成于所述栅极绝缘层上，图案化形成储存电容的第一电极板、栅极、扫描线；
层间绝缘层，形成于所述栅极层及所述栅极绝缘层上；
源漏极层，形成于所述层间绝缘层上，图案化形成所述储存电容的第二电极板、源极、漏极；
钝化层，形成于所述源漏极层以及所述层间绝缘层上。
本申请实施例提供一种显示面板，该显示面板包括阵列基板，其阵列基板包括层叠设置的衬底、缓冲层、有源层、栅极绝缘层、栅极层、层间绝缘层、源漏极层和钝化层；采用单栅极层设计，在栅极层内形成存储电容的第一电极板，在源漏极层内形成存储电容的第二电极板和各种功能连接线，通过各功能连接线实现不同膜层间的电流通路，从而省去了一层栅极结构，节省了一道光罩，降低了生产成本，缓解了现有显示装置存在生产成本高的问题。
在一种实施例中，所述第二电极板设置有缺口，所述缺口对应区域内设置有第一连接过孔；所述源漏极层还图案化形成有第一连接线，所述第一连接线的一端通过所述第一连接过孔，连接所述第一电极板，另一端通过第二连接过孔连接目标薄膜晶体管的掺杂区。
在一种实施例中，所述第一电极板形成有突出部，所述突出部对应区域内设置有第三连接过孔；所述源漏极层还图案化形成有第二连接线，所述第二连接线的一端通过所述第三连接过孔，连接所述第一电极板，另一端通过第四连接过孔连接目标薄膜晶体管的掺杂区。
在一种实施例中，所述源漏极层还图案化形成电源线以及电源连接线，所述第二电极板通过所述电源连接线与所述电源线连接。
在一种实施例中，所述源漏极层还图案化形成电源线，所述第二电极板的一侧边与所述电源线一体。
在一种实施例中，所述栅极层还图案化形成信号复位线，所述信号复位线在所述有源区对应区域内中断；所述源漏极层还图案化形成复位连接线，所述信号复位线通过第五连接过孔连接所述复位连接线的一端，所述复位连接线的另一端通过第六连接过孔连接相邻子像素的信号复位线。
在一种实施例中，所述源漏极层还图案化形成复位转接线，信号复位线通过第七连接过孔连接所述复位转接线的一端，所述复位转接线的另一端通过第八连接过孔连接目标薄膜晶体管的掺杂区。
在一种实施例中，所述显示面板为LCD显示面板，所述LCD显示面板还包括：
彩膜基板；
填充于所述彩膜基板和所述阵列基板之间的液晶。
在另一种实施例中，所述显示面板为OLED显示面板，所述OLED显示面板还包括：
像素定义层，形成于所述钝化层上，图案化形成发光定义区；
发光材料层，形成于所述发光定义区内；
公共电极层，形成于所述发光材料层以及所述像素定义层上；
封装层，形成于所述公共电极层上。
同时，本申请还提供一种阵列基板的制备方法，包括：
S1、提供衬底基板；
S2、在所述衬底基板上制备缓冲层；
S3、在所述缓冲层上制备有源层，并图案化形成薄膜晶体管的有源区，所述有源区包括掺杂区和沟道区；
S4、在所述有源层和所述缓冲层上制备栅极绝缘层；
S5、在所述栅极绝缘层上制备栅极层，并图案化形成储存电容的第一电极板、栅极、扫描线；
S6、在所述栅极层和栅极绝缘层上制备层间绝缘层；
S7、在所述层间绝缘层上制备源漏极层，并图案化形成所述储存电容的第二电极板、源极、漏极；
S8、在所述源漏极层和所述层间绝缘层上制备钝化层。
本申请实施例提供一种阵列基板的制备方法，该制备方法为依次在衬底基板上制备缓冲层、有源层、栅极绝缘层、栅极层、层间绝缘层、源漏极层和钝化层。采用单栅极层设计，在栅极层内形成存储电容的第一电极板，在源漏极层内形成存储电容的第二电极板和各种功能连接线，通过各功能连接线实现不同膜层间的电流通路，从而省去了一层栅极结构，节省了一道光罩，降低了生产成本，缓解了现有显示装置存在生产成本高的问题。
根据上述实施例可知，
本申请实施例提供一种阵列基板、显示面板及阵列基板的制备方法，其阵列基板包括依次设置的衬底、缓冲层、有源层、栅极绝缘层、栅极层、层间绝缘层、源漏极层和钝化层。采用单栅极层设计，在栅极层内形成存储电容的第一电极板，在源漏极层内形成存储电容的第二电极板和各种功能连接线，通过各功能连接线实现不同膜层间的电流通路，从而省去了一层栅极结构，节省了一道光罩，降低了生产成本，缓解了现有显示装置存在生产成本高的问题。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板，其包括：
    衬底；
    缓冲层，形成于所述衬底上；
    有源层，形成于所述缓冲层上，图案化形成薄膜晶体管的有源区，所述有源区包括掺杂区和沟道区；
    栅极绝缘层，形成于所述有源层及所述缓冲层上；
    栅极层，形成于所述栅极绝缘层上，图案化形成储存电容的第一电极板、栅极、扫描线；
    层间绝缘层，形成于所述栅极层及所述栅极绝缘层上；
    源漏极层，形成于所述层间绝缘层上，图案化形成所述储存电容的第二电极板、源极、漏极；
    钝化层，形成于所述源漏极层以及所述层间绝缘层上。
  2. 根据权利要求1所述的阵列基板，其中，所述第二电极板设置有缺口，所述缺口对应区域内设置有第一连接过孔；所述源漏极层还图案化形成有第一连接线，所述第一连接线的一端通过所述第一连接过孔，连接所述第一电极板，另一端通过第二连接过孔连接目标薄膜晶体管的掺杂区。
  3. 根据权利要求1所述的阵列基板，其中，所述第一电极板形成有突出部，所述突出部对应区域内设置有第三连接过孔；所述源漏极层还图案化形成有第二连接线，所述第二连接线的一端通过所述第三连接过孔，连接所述第一电极板，另一端通过第四连接过孔连接目标薄膜晶体管的掺杂区。
  4. 根据权利要求1所述的阵列基板，其中，所述源漏极层还图案化形成电源线以及电源连接线，所述第二电极板通过所述电源连接线与所述电源线连接。
  5. 根据权利要求4所述的阵列基板，其中，所述电源连接线为镂空的网状结构。
  6. 根据权利要求1所述的阵列基板，其中，所述源漏极层还图案化形成电源线，所述第二电极板的一侧边与所述电源线一体。
  7. 根据权利要求1所述的阵列基板，其中，所述栅极层还图案化形成信号复位线，所述信号复位线在所述有源区对应区域内中断；所述源漏极层还图案化形成复位连接线，所述信号复位线通过第五连接过孔连接所述复位连接线的一端，所述复位连接线的另一端通过第六连接过孔连接相邻子像素的信号复位线。
  8. 根据权利要求7所述的阵列基板，其中，所述源漏极层还图案化形成复位转接线，信号复位线通过第七连接过孔连接所述复位转接线的一端，所述复位转接线的另一端通过第八连接过孔连接目标薄膜晶体管的掺杂区。
  9. 根据权利要求1所述的阵列基板，其中，所述源漏极层的材料为钼、铝、铝镍合金、钼钨合金、铬、铜或钛铝合金中的至少一种。
  10. 根据权利要求1所述的阵列基板，其中，所述层间绝缘层的材料为氮化硅或氧化硅。
  11. 根据权利要求1所述的阵列基板，其中，所述栅极层的材料为钼、铝、铝镍合金、钼钨合金、铬、铜或钛铝合金中的至少一种。
  12. 根据权利要求1所述的阵列基板，其中，所述栅极绝缘层的材料为氮化硅、氧化硅或氮氧化硅中的至少一种。
  13. 根据权利要求1所述的阵列基板，其中，所述缓冲层的材料为氮化硅或氧化硅中的至少一种。
  14. 根据权利要求1所述的阵列基板，其中，所述阻挡层的材料为氧化硅。
  15. 根据权利要求1所述的阵列基板，其中，所述衬底为玻璃基板、石英基板、树脂基板中的一种。
  16. 根据权利要求1所述的阵列基板，其中，所述衬底为柔性基板。
  17. 根据权利要求16所述的阵列基板，其中，所述衬底为柔性基板的材料包括聚酰亚胺。
  18. 一种显示面板，其包括如权利要求1所述的阵列基板。
  19. 根据权利要求18所述的显示面板，其中，所述显示面板为LCD显示面板，所述LCD显示面板还包括：
    彩膜基板；
    填充于所述彩膜基板和所述阵列基板之间的液晶。
  20. 根据权利要求18所述的显示面板，其中，所述显示面板为OLED显示面板，所述OLED显示面板还包括：
    像素定义层，形成于所述钝化层上，图案化形成发光定义区；
    发光材料层，形成于所述发光定义区内；
    公共电极层，形成于所述发光材料层以及所述像素定义层上；
    封装层，形成于所述公共电极层上。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110571242B (zh) * 2019-08-12 2021-12-28 武汉华星光电半导体显示技术有限公司 阵列基板及显示面板
CN111129093A (zh) * 2019-12-23 2020-05-08 武汉华星光电半导体显示技术有限公司 阵列基板和显示面板
CN111415974B (zh) * 2020-04-29 2022-10-04 武汉华星光电半导体显示技术有限公司 Oled显示面板及其制备方法
CN114530473B (zh) 2020-10-30 2026-02-10 京东方科技集团股份有限公司 显示面板及其制作方法和显示装置
WO2023044679A1 (zh) * 2021-09-23 2023-03-30 京东方科技集团股份有限公司 显示基板和显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140098077A1 (en) * 2012-10-04 2014-04-10 Samsung Display Co., Ltd. Organic light emitting diode display
CN107274829A (zh) * 2017-07-10 2017-10-20 上海天马有机发光显示技术有限公司 一种有机电致发光显示面板及显示设备
CN108831906A (zh) * 2018-05-31 2018-11-16 武汉华星光电半导体显示技术有限公司 Oled显示面板及oled显示器
CN109064977A (zh) * 2018-07-20 2018-12-21 武汉华星光电半导体显示技术有限公司 Amoled显示面板及其像素结构的暗点化修复方法
CN109148480A (zh) * 2018-08-21 2019-01-04 武汉华星光电半导体显示技术有限公司 阵列基板
CN110190073A (zh) * 2019-07-25 2019-08-30 武汉华星光电半导体显示技术有限公司 阵列基板
CN110571242A (zh) * 2019-08-12 2019-12-13 武汉华星光电半导体显示技术有限公司 阵列基板及显示面板

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100426031B1 (ko) * 2001-12-29 2004-04-03 엘지.필립스 엘시디 주식회사 능동행렬 유기전기발광소자 및 그의 제조 방법

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140098077A1 (en) * 2012-10-04 2014-04-10 Samsung Display Co., Ltd. Organic light emitting diode display
CN107274829A (zh) * 2017-07-10 2017-10-20 上海天马有机发光显示技术有限公司 一种有机电致发光显示面板及显示设备
CN108831906A (zh) * 2018-05-31 2018-11-16 武汉华星光电半导体显示技术有限公司 Oled显示面板及oled显示器
CN109064977A (zh) * 2018-07-20 2018-12-21 武汉华星光电半导体显示技术有限公司 Amoled显示面板及其像素结构的暗点化修复方法
CN109148480A (zh) * 2018-08-21 2019-01-04 武汉华星光电半导体显示技术有限公司 阵列基板
CN110190073A (zh) * 2019-07-25 2019-08-30 武汉华星光电半导体显示技术有限公司 阵列基板
CN110571242A (zh) * 2019-08-12 2019-12-13 武汉华星光电半导体显示技术有限公司 阵列基板及显示面板

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