WO2021027191A1 - 显示面板的侧面绑定结构 - Google Patents

显示面板的侧面绑定结构 Download PDF

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Publication number
WO2021027191A1
WO2021027191A1 PCT/CN2019/123162 CN2019123162W WO2021027191A1 WO 2021027191 A1 WO2021027191 A1 WO 2021027191A1 CN 2019123162 W CN2019123162 W CN 2019123162W WO 2021027191 A1 WO2021027191 A1 WO 2021027191A1
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Prior art keywords
layer
metal layer
metal
hole
width
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Ceased
Application number
PCT/CN2019/123162
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English (en)
French (fr)
Inventor
叶岩溪
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US16/624,322 priority Critical patent/US11282862B2/en
Publication of WO2021027191A1 publication Critical patent/WO2021027191A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/482—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes for individual devices provided for in groups H10D8/00 - H10D48/00, e.g. for power transistors
    • H10W20/484—Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/0102—Constructional details, not otherwise provided for in this subclass
    • G02F1/0105—Illuminating devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/431—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
    • H10H29/14—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 comprising multiple light-emitting semiconductor components
    • H10H29/142—Two-dimensional arrangements, e.g. asymmetric LED layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H10K59/179—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/42—Arrangements for providing conduction through an insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0338—Layered conductor, e.g. layered metal substrate, layered finish layer or layered thin film adhesion layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09145—Edge details
    • H05K2201/0919—Exposing inner circuit layers or metal planes at the side edge of the printed circuit board [PCB] or at the walls of large holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10128—Display
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present invention relates to the display field, in particular to a side binding structure of a display panel.
  • Side Bonding Technology refers to the technology of bonding COF (Chip on Film) to the cross section of the glass boundary.
  • an in-plane circuit uses two layers of metal, namely the first metal layer 11 and the second metal layer 12, and the two layers of metal are connected through through holes.
  • a first through hole 13 and a second through hole 14 are opened on the passivation layer 15.
  • the first through hole 13 penetrates to the surface of the second metal layer 12, and the second through hole 14 penetrates to the surface of the first metal layer 12,
  • a transparent electrode 16 is disposed on the first through hole 13, the second through hole 14 and the passivation layer 15, and the first metal layer 11 and the second metal layer 12 are connected through the transparent electrode 15.
  • the object of the present invention is to provide a side binding structure of a display panel, by opening a through hole on the gate insulating layer, so that the second metal layer is directly connected to the first metal layer, reducing the side The film layer falls off during edge grinding; at the same time, a passivation layer is provided between the in-plane circuit and the transparent electrode of the color film substrate.
  • the metal ball and the conductive layer can be effectively blocked, thereby solving the problem The problem of a short circuit.
  • the present invention provides a side binding structure of a display panel, which includes: an array substrate and a color filter substrate arranged oppositely; an in-plane circuit arranged on the array substrate; a side circuit perpendicular to the The array substrate is connected to the in-plane circuit; wherein the in-plane circuit includes a first metal layer and a second metal layer, the second metal layer is disposed on the first metal layer, and the second metal layer It is directly connected to the first metal layer.
  • the in-plane circuit further includes: a passivation layer and a gate insulating layer; the gate insulating layer is provided on the first metal layer and the array substrate, and the gate insulating layer has a through hole , The through hole exposes the first metal layer; the second metal layer is connected to the first metal layer through the through hole; the passivation layer covers the gate insulating layer and the second metal layer Two metal layers.
  • the width of the through hole is greater than the width of the first metal layer; the width of the through hole is greater than the width of the second metal layer.
  • the second metal layer includes at least one dam and a second metal body layer; the second metal body layer is provided on the first metal layer; the dam is provided in the through hole and attached The side surface of the first metal layer.
  • the width of the through hole is larger than the width of the first metal layer; the width of the through hole is smaller than the width of the second metal layer.
  • the first metal layer has a gap from the sidewall of the through hole; the second metal layer is provided on the gate insulating layer and the first metal layer, and the second metal layer is filled with The gap; the second metal layer has at least one groove, and the groove corresponds to the gap.
  • the width of the through hole is smaller than the width of the first metal layer; the width of the through hole is smaller than the width of the second metal layer.
  • the second metal layer includes at least one protrusion and a second metal body layer; the second metal body layer is disposed on the first metal layer and attached to the side surface of the through hole; the protrusion It is set on the gate insulating layer.
  • the side circuit includes: a metal printing layer arranged on the side surface of the array substrate; a conductive adhesive layer attached to the metal printing layer; a flip chip film attached to the conductive adhesive layer away from the One side of the metal printing layer.
  • the metal printed layer is a metal silver wire printed circuit;
  • the conductive adhesive layer includes conductive particles and a resin adhesive.
  • the present invention provides a side binding structure of a display panel.
  • the second metal layer is directly connected to the first metal layer, thereby reducing the side edge edging film
  • the layer pair is peeled off; and the size of the through hole is adjusted so that the second metal layer can cover the first metal layer, and the first metal layer can be protected when the second metal layer is etched; the last inner circuit and color
  • a passivation layer is provided between the transparent electrodes of the film substrate.
  • Figure 1 is a schematic plan view of a prior art in-plane circuit
  • Figure 2 is a schematic cross-sectional structure diagram of Figure 1 along the Y1-Y2 direction;
  • Fig. 3 is a schematic cross-sectional structure view along the X1-X2 direction of Fig. 1;
  • Figure 4 is a schematic structural diagram of the side binding structure of the present invention.
  • FIG. 5 is a schematic plan view of the in-plane circuit of Embodiment 1 of the present invention.
  • FIG. 6 is a longitudinal cross-sectional view of the in-plane circuit of the embodiment 1 of the present invention along the Y1-Y1 direction shown in FIG. 5;
  • FIG. 7 is a transverse cross-sectional view of the in-plane circuit of Embodiment 1 of the present invention along the X1-X1 direction shown in FIG. 5;
  • FIG. 8 is a longitudinal cross-sectional view of the in-plane circuit of Embodiment 2 of the present invention.
  • Figure 9 is a longitudinal cross-sectional view of the in-plane circuit of Embodiment 3 of the present invention.
  • Gate insulating layer 102 through holes 1021, 1021a, 1021b;
  • Dam 1032 second metal body layer 1031, 1031a, 1031b;
  • Metal printing layer 201 conductive adhesive layer 202; chip on film 203;
  • the side binding structure 30 of the display panel provided by the present invention includes: an array substrate 21, a color filter substrate 22, an in-plane circuit 100 and a side circuit 200.
  • the array substrate 21 and the color filter substrate 22 are disposed oppositely; the color filter substrate 22 is provided with a transparent electrode on the side close to the array substrate 21.
  • the in-plane circuit 100 is provided on the array substrate 21; the in-plane circuit 100 includes: a first metal layer 101, a second The metal layer 103, the passivation layer 104, and the gate insulating layer 102.
  • the second metal layer 103 is disposed on the first metal layer 101, and the second metal layer 103 is directly connected to the first metal layer 101.
  • the first metal layer 101 is disposed on the array substrate 21.
  • the gate insulating layer 102 is disposed on the array substrate 21 and the first metal layer 101; the gate insulating layer 102 is disposed on the first metal layer 101, and the gate insulating layer 102 has a through hole 1021, the through hole 1021 penetrates to the surface of the first metal layer 101; the second metal layer 103 is directly connected to the first metal layer 101 through the through hole 1021.
  • the width of the through hole 1021 is greater than the width of the first metal layer 101; the width of the through hole 1021 is greater than the width of the second metal layer 103.
  • the second metal layer 103 includes at least one dam 1032 and a second metal body layer 1031, and the dam 1032 is connected to the second metal body layer 1031.
  • the second metal body layer 1031 is provided on the first metal layer 101; the dam 1032 is provided in the through hole 1021 and is attached to the side surface of the first metal layer 101.
  • the second metal layer 103 is covered with the first metal layer 101 through the second metal body layer 1031 and the dam 1032, which can protect the second metal layer 103 when the second metal layer 103 is etched.
  • the protective effect of a metal layer 101 prevents the first metal layer 101 from being etched away.
  • the passivation layer 104 is provided on the gate insulating layer 102 and the second metal layer 103.
  • the side circuit 200 is perpendicular to the array substrate 21 and connected to the in-plane circuit 100; the side circuit 200 includes a metal printing layer 201, a conductive adhesive layer 202 and a chip on film 203.
  • the metal printing layer 201 is provided on the side surface of the array substrate 21; the metal printing layer 201 is attached to the side surface of the array substrate 21, the in-plane circuit 100 and the color filter substrate 22; the metal printing layer 201 is Metal silver wire printed circuit.
  • the conductive adhesive layer 202 is attached to the metal printing layer 201; the conductive adhesive layer 202 includes conductive particles 2021 and a resin adhesive 2022.
  • the chip on film 203 is attached to a side of the conductive adhesive layer 202 away from the metal printing layer 201.
  • the side circuit 200 can transmit the IC signal of the chip on film 203 to the in-plane circuit 100, so as to realize a panel display.
  • the present invention directly connects the first metal layer 101 and the second metal layer 103 without using a transparent electrode to connect the first metal layer 101 and the second metal layer 103; when making a narrow frame, the display panel of the present invention is side-grinded At this time, the metal ball in the metal ball frame glue is overwhelmed in the in-plane circuit, and the passivation layer isolates the metal ball from the metal layer, and is not directly connected to the metal layer, thereby solving the problem of circuit short circuit.
  • the film structure of the present invention does not have many uneven structures.
  • the first metal layer 101 is connected to the second metal layer 103, so that the film can be reduced during the side edging process. Peeling of layers.
  • the present invention provides a side binding structure 100 of a display panel.
  • the second metal layer 103 is directly connected to the first metal layer 101, reducing The side edge edging film layer pair falls off; and the size of the through hole 1021 is adjusted so that the second metal layer 103 can cover the first metal layer 101, so that the second metal layer 103 can be protected when the second metal layer 103 is etched
  • a metal layer 101; the last in-plane circuit 100 is separated from the transparent electrode of the color filter substrate 22 by a passivation layer 104.
  • the present invention also provides a side binding structure 30a of the display panel of Embodiment 2.
  • the difference from Embodiment 1 is that the width of the through hole 1021a in Embodiment 2 is greater than the width of the first metal layer 101a; The width of the through hole 1021a is smaller than the width of the second metal layer 103a.
  • the first metal layer 101a has a gap 1022a from the sidewall of the through hole 1021a; the second metal layer 103a is provided on the gate insulating layer 102a and the first metal layer 101a, and the second metal layer The layer 103a fills the gap 1022a.
  • the second metal layer 103a has at least one groove 1033a, and the groove 1033a corresponds to the gap 1022a.
  • Example 2 increases the contact area between the second metal layer 103a and the gate insulating layer 102a by increasing the contact area between the second metal layer 103a and the film layer.
  • the peeling of the film layer can be reduced during the side edging process.
  • the present invention also provides the side binding structure 30b of the display panel of Embodiment 3.
  • the difference from Embodiment 1 is that the width of the through hole 1021b is smaller than the width of the first metal layer 101b; therefore, the gate is insulated
  • the layer 102b is partially disposed on the first metal layer 101b, and the width of the through hole 1021b is smaller than the width of the second metal layer 103b, which also causes the second metal layer 103b to have at least one protrusion 1034b disposed on the On the gate insulating layer 102b.
  • the second metal layer 103b includes at least one protrusion 1034b and a second metal body layer 1031b, and the protrusion 1034b is connected to the second metal body layer 1031b.
  • the second metal body layer 1031b is disposed on the first metal layer 101b and attached to the side surface of the through hole 1021b; the protrusion 1034b is disposed on the gate insulating layer 102b.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本发明提供一种显示面板的侧面绑定结构，包括阵列基板、彩膜基板、面内电路以及侧面电路。通过在所述栅极绝缘层上开设通孔，使得所述第二金属层与所述第一金属层直接相连，减小侧边磨边膜层对的脱落。

Description

显示面板的侧面绑定结构
本申请要求于2019年08月14日提交中国专利局、申请号为201910746908.X、发明名称为“显示面板的侧面绑定结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示领域，尤其是涉及一种显示面板的侧面绑定结构。
 背景技术
侧面绑定技术(Side Bonding Technology)是指把COF（Chip on film，覆晶薄膜）绑定在玻璃边界截面处的技术。
为了实现侧面绑定技术，需要在玻璃截面印刷电路，实现玻璃面内线路和COF线路之间的衔接。所以面内电路(OLB电路)在和侧面电路（COF线路）的衔接处的设计就变得非常重要。
在面内电路和侧面电路衔接处的设计，普通设计的架构如图1和2所示。一般面内电路使用两层金属，分别是第一金属层11和第二金属层12，两层金属通过通孔进行连接。在所述钝化层15上开设第一通孔13以及第二通孔14，第一通孔13贯穿至第二金属层12的表面，第二通孔14贯穿直至第一金属层12表面，最后设置一透明电极16在第一通孔13、第二通孔14以及钝化层15上，通过透明电极15连接第一金属层11与第二金属层12。
 技术问题
在实现侧面绑定技术的时候，为了使得侧面电路能够印刷上去，需要保证侧面绑定技术的品质，所以需要进行侧面磨边工艺（图1中沿Y1-Y2方向的侧边）。如图3所示，当进行侧面磨边制程的时候，由于面内电路结构有很多凹凸不平的地形，很容易导致各个膜层的剥落。另外因为侧面绑定技术一般用于窄边框技术，而窄边框技术一般使用金属球框胶（Au in seal）技术。继续参照图2，当窄边框搭配金属球框胶后，很容易使得金属17压到面内电路区域，使得透明电极和彩膜基板的透明电极相互连接进而短路。
因此，有必要提出一种新的显示面板的侧面绑定结构，提高面内电路的安全性，解决了现有技术中面内电路容易短路的问题。
 技术解决方案
本发明的目的在于，提供一种显示面板的侧面绑定结构，通过在所述栅极绝缘层上开设通孔，使得所述第二金属层与所述第一金属层直接相连，减小侧边磨边时膜层的脱落；同时面内电路与彩膜基板的透明电极间设有一钝化层，在使用窄边框技术时，可以有效阻隔金属球与所述导电层，进而解决了面内电路短路的问题。
为了可以达到上述目的，本发明提供一种显示面板的侧面绑定结构，包括：阵列基板以及相对设置的彩膜基板；面内电路，设于所述阵列基板上；侧面电路，垂直于所述阵列基板并连接所述面内电路；其中，所述面内电路包括第一金属层与第二金属层，所述第二金属层设于所述第一金属层上，所述第二金属层与所述第一金属层直接相连。
进一步地，所述面内电路还包括：钝化层以及栅极绝缘层；所述栅极绝缘层设于所述第一金属层以及所述阵列基板上，所述栅极绝缘层具有一通孔，所述通孔暴露所述第一金属层；所述第二金属层通过所述通孔与所述第一金属层相连接；所述钝化层覆盖所述栅极绝缘层以及所述第二金属层上。
进一步地，所述通孔的宽度大于所述第一金属层的宽度；所述通孔的宽度大于所述第二金属层的宽度。
进一步地，所述第二金属层包括至少一堤坝以及第二金属主体层；所述第二金属主体层设于所述第一金属层上；所述堤坝设于所述通孔中且贴附所述第一金属层的侧面。
进一步地，所述通孔的宽度大于所述第一金属层的宽度；所述通孔的宽度小于所述第二金属层的宽度。
进一步地，所述第一金属层距离所述通孔的侧壁具有一间隙；所述第二金属层设于所述栅极绝缘层和第一金属层上，所述第二金属层填充所述间隙；所述第二金属层具有至少一凹槽，所述凹槽对应所述间隙。
进一步地，所述通孔的宽度小于所述第一金属层的宽度；所述通孔的宽度小于所述第二金属层的宽度。
进一步地，所述第二金属层包括至少一凸起以及第二金属主体层；所述第二金属主体层设于所述第一金属层上且贴附所述通孔的侧面；所述凸起设于所述栅极绝缘层上。
进一步地，所述侧面电路包括：金属印刷层，设于所述阵列基板的侧面；导电胶层，贴附于所述金属印刷层；覆晶薄膜，贴附于所述导电胶层远离所述金属印刷层的一侧。
进一步地，所述金属印刷层为金属银线印刷电路；所述导电胶层包括导电粒子以及树脂黏着剂。
 有益效果
本发明提供一种显示面板的侧面绑定结构，通过在所述栅极绝缘层上开设通孔，使得所述第二金属层与所述第一金属层直接相连，减小侧边磨边膜层对的脱落；并且调整通孔的大小，使得第二金属层可以包覆所述第一金属层，在刻蚀第二金属层的时候可以保护到第一金属层；最后面内电路与彩膜基板的透明电极间设有一钝化层，在使用窄边框技术时，金属球不会与金属层直接接触，解决了面内电路短路的问题。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术面内电路的平面示意图；
图2为图1沿Y1-Y2方向的剖面结构示意图；
图3为图1沿X1-X2方向的剖面结构示意图；
图4为本发明的侧面绑定结构的结构示意图；
图5为本发明实施例1的的面内电路的平面示意图；
图6为本发明实施例1的面内电路沿图5所示Y1-Y1方向的纵向剖面图；
图7为本发明实施例1的面内电路沿图5所示X1-X1方向的横向剖面图；
图8为本发明实施例2的面内电路的纵向剖面图；
图9为本发明实施例3的面内电路的纵向剖面图；
显示面板的侧面绑定结构30、30a、30b；
阵列基板21；彩膜基板22；面内电路100；
侧面电路200；第一金属层101、101a、101b；
第二金属层103、103a、103b；钝化层104；
栅极绝缘层102；通孔1021、1021a、1021b；
堤坝1032；第二金属主体层1031、1031a、1031b；
金属印刷层201；导电胶层202；覆晶薄膜203；
导电粒子2021；树脂黏着剂2022；间隙1022a；
凹槽1033a；凸起1034b。
 本发明的实施方式
以下是各实施例的说明是参考附加的图式，用以例示本发明可以用实施的特定实施例。本发明所提到的方向用语，例如上、下、前、后、左、右、内、外、侧等，仅是参考附图式的方向。本发明提到的元件名称，例如第一、第二等，仅是区分不同的元部件，可以更好的表达。在图中，结构相似的单元以相同标号表示。
本文将参照附图来详细描述本发明的实施例。本发明可以表现为许多不同形式，本发明不应仅被解释为本文阐述的具体实施例。本发明提供实施例是为了解释本发明的实际应用，从而使本领域其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改方案。
如图4所示，本发明提供的显示面板的侧面绑定结构30，包括：阵列基板21、彩膜基板22、面内电路100以及侧面电路200。
所述阵列基板21与所述彩膜基板22相对设置；所述彩膜基板22靠近所述阵列基板21一侧设有一透明电极。
同时参照图5以及图6所示的实施例1的面内电路100，所述面内电路100设于所述阵列基板21上；所述面内电路100包括：第一金属层101、第二金属层103、钝化层104以及栅极绝缘层102。所述第二金属层103设于所述第一金属层101上，所述第二金属层103与所述第一金属层101直接相连接。
所述第一金属层101设于所述阵列基板21上。
所述栅极绝缘层102设于所述阵列基板21以及第一金属层101上；所述栅极绝缘层102设于所述第一金属层101上，所述栅极绝缘层102具有一通孔1021，所述通孔1021贯穿至所述第一金属层101表面；所述第二金属层103通过所述通孔1021与所述第一金属层101直接相连接。
所述通孔1021的宽度大于所述第一金属层101的宽度；所述通孔1021的宽度大于所述第二金属层103的宽度。
所述第二金属层103包括至少一堤坝1032以及第二金属主体层1031，所述堤坝1032连接所述第二金属主体层1031。
所述第二金属主体层1031设于所述第一金属层101上；所述堤坝1032设于所述通孔1021中且贴附所述第一金属层101的侧面。
这样所述第二金属层103通过所述第二金属主体层1031以及所述堤坝1032包覆所述第一金属层101，可以在第二金属层103刻蚀时，能够起到对所述第一金属层101保护的作用，避免第一金属层101被刻蚀掉。
所述钝化层104设于所述栅极绝缘层102以及所述第二金属层103上。
所述侧面电路200垂直于所述阵列基板21并连接所述面内电路100；所述侧面电路200包括：金属印刷层201、导电胶层202以及覆晶薄膜203。
所述金属印刷层201设于所述阵列基板21的侧面；所述金属印刷层201贴附在所述阵列基板21、面内电路100以及彩膜基板22的侧面；所述金属印刷层201为金属银线印刷电路。
所述导电胶层202贴附于所述金属印刷层201；所述导电胶层202包括导电粒子2021以及树脂黏着剂2022。
所述覆晶薄膜203贴附于所述导电胶层202远离所述金属印刷层201的一侧。所述侧面电路200可以将所述覆晶薄膜203的IC信号传递给面内电路100，进而可以实现面板显示。
本发明通过将第一金属层101与第二金属层103直接相连，而没有采用透明电极连接第一金属层101与第二金属层103；在制作窄边框时，对本发明显示面板进行侧磨边时，金属球框胶中的金属球被压倒面内电路内，通过钝化层隔绝金属球与金属层，并不会直接与所述金属层相连接，进而解决了电路短路的问题。
如图7所示，本发明的膜层结构没有很多凹凸不平的结构，所述第一金属层101与所述第二金属层103相连接，这样在进行侧面磨边工艺的时候，可以减少膜层的剥落。
本发明提供一种显示面板的侧面绑定结构100，通过在所述栅极绝缘层102上开设通孔1021，使得所述第二金属层103与所述第一金属层101直接相连，减小侧边磨边膜层对的脱落；并且调整通孔1021的大小，使得第二金属层103可以包覆所述第一金属层101，这样在刻蚀第二金属层103的时候可以保护到第一金属层101；最后面内电路100通过一钝化层104与彩膜基板22的透明电极间隔开，在使用窄边框技术时，金属球框胶中的金属球被压倒面内电路内，并不会与金属层直接接触，解决了面内电路短路的问题。
如图8所示，本发明还提供实施例2的显示面板的侧面绑定结构30a，与实施例1不同之处在于，实施例2中通孔1021a的宽度大于第一金属层101a的宽度；所述通孔1021a的宽度小于第二金属层103a的宽度。
所述第一金属层101a距离所述通孔1021a的侧壁具有一间隙1022a；所述第二金属层103a设于所述栅极绝缘层102a和第一金属层101a上，所述第二金属层103a填充所述间隙1022a。所述第二金属层103a具有至少一凹槽1033a，所述凹槽1033a对应所述间隙1022a。
实施例2较实施例1相比较，通过增加了所述第二金属层103a与所述栅极绝缘层102a接触的部分，从而增加了所述第二金属层103a与膜层的接触面积，进而可以在进行侧面磨边工艺的时候，可以减少膜层的剥落。
如图9所示，本发明还提供实施例3的显示面板的侧面绑定结构30b，与实施例1不同之处在于，通孔1021b的宽度小于第一金属层101b的宽度；因此栅极绝缘层102b有部分设在所述第一金属层101b上，所述通孔1021b的宽度小于第二金属层103b的宽度，这也导致所述第二金属层103b至少有一凸起1034b设置在所述栅极绝缘层102b上。
所述第二金属层103b包括至少一凸起1034b以及第二金属主体层1031b，所述凸起1034b连接所述第二金属主体层1031b。
所述第二金属主体层1031b设于所述第一金属层101b上且贴附所述通孔1021b的侧面；所述凸起1034b设于所述栅极绝缘层102b上。
本发明的技术范围不仅仅局限于所述说明中的内容，本领域技术人员可以在不脱离本发明技术思想的前提下，对所述实施例进行多种变形和修改，而这些变形和修改均应当属于本发明的范围内。

Claims (11)

  1.   一种显示面板的侧面绑定结构，其中，包括：
    阵列基板以及相对设置的彩膜基板；
    面内电路，设于所述阵列基板上；
    侧面电路，垂直于所述阵列基板并连接所述面内电路；
    其中，所述面内电路包括第一金属层与第二金属层，所述第二金属层设于所述第一金属层上，所述第二金属层与所述第一金属层直接相连。
  2.   根据权利要求1所述的显示面板的侧面绑定结构，其中，
    所述面内电路还包括：钝化层以及栅极绝缘层；
    所述栅极绝缘层设于所述第一金属层以及所述阵列基板上，所述栅极绝缘层具有一通孔，所述通孔暴露所述第一金属层；
    所述第二金属层通过所述通孔与所述第一金属层相连接；
    所述钝化层覆盖所述栅极绝缘层以及所述第二金属层。
  3.   根据权利要求2所述的显示面板的侧面绑定结构，其中，
    所述通孔的宽度大于所述第一金属层的宽度；
    所述通孔的宽度大于所述第二金属层的宽度。
  4.   根据权利要求3所述的显示面板的侧面绑定结构，其中，
    所述第二金属层包括至少一堤坝以及第二金属主体层；
    所述第二金属主体层设于所述第一金属层上；
    所述堤坝设于所述通孔中且贴附所述第一金属层的侧面。
  5.   根据权利要求2所述的显示面板的侧面绑定结构，其中，
    所述通孔的宽度大于所述第一金属层的宽度；
    所述通孔的宽度小于所述第二金属层的宽度。
  6.   根据权利要求5所述的显示面板的侧面绑定结构，其中，
    所述第一金属层距离所述通孔的侧壁具有一间隙；
    所述第二金属层设于所述栅极绝缘层和第一金属层上，所述第二金属层填充所述间隙；
    所述第二金属层具有至少一凹槽，所述凹槽对应所述间隙。
  7.   根据权利要求2所述的显示面板的侧面绑定结构，其中，
    所述通孔的宽度小于所述第一金属层的宽度；
    所述通孔的宽度小于所述第二金属层的宽度。
  8.   根据权利要求7所述的显示面板的侧面绑定结构，其中，
    所述第二金属层包括至少一凸起以及第二金属主体层；
    所述第二金属主体层设于所述第一金属层上且贴附所述通孔的侧面；
    所述凸起设于所述栅极绝缘层上。
  9.   根据权利要求1所述的显示面板的侧面绑定结构，其中，
    所述侧面电路包括：
    金属印刷层，设于所述阵列基板的侧面；
    导电胶层，贴附于所述金属印刷层；
    覆晶薄膜，贴附于所述导电胶层远离所述金属印刷层的一侧。
  10. 根据权利要求1所述的显示面板的侧面绑定结构，其中，
    所述金属印刷层为金属银线印刷电路。
  11. 根据权利要求1所述的显示面板的侧面绑定结构，其中，
    所述导电胶层包括导电粒子以及树脂黏着剂。
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