WO2021027068A1

WO2021027068A1 - Array substrate and display panel

Info

Publication number: WO2021027068A1
Application number: PCT/CN2019/113087
Authority: WO
Inventors: 薛炎; 韩佰祥
Original assignee: 深圳市华星光电半导体显示技术有限公司
Priority date: 2019-08-14
Filing date: 2019-10-24
Publication date: 2021-02-18
Also published as: CN110517642A

Abstract

An array substrate and a display panel. A pixel circuit, a first scan driving circuit (111) and a second scan driving circuit (112) are manufactured on the array substrate. A voltage maintaining circuit (21) is provided in the pixel circuit so as to cause a low-potential scan signal (WR(n)) output by the first scan driving circuit (111) to remain at the low potential, thereby eliminating oscillations of the scan signal (WR(n)), and accordingly reducing current and brightness oscillations of a light-emitting element (23).

Description

Array substrate and display panel

Technical field

This application relates to the field of display technology, and in particular to an array substrate and a display panel.

Background technique

At present, the horizontal scan line of AMOLED display panel is driven by an external integrated circuit. The external integrated circuit can control the step-by-step turn-on of the row scan lines at all levels, and the GOA (Gate The Driver on Array method can integrate the line scan driving circuit on the display panel substrate, which can reduce the number of external ICs, thereby reducing the production cost of the display panel, and can realize the narrow frame of the display device.

As shown in Figures 1 and 2, when the panel is driven by the GOA method, since the size of the thin film transistor T3 at the output end of the GOA circuit is large, the source of the thin film transistor T3 is connected to the clock signal CK, and when the clock signal CK is When the potential rises from a low potential to a high potential, the potential at point Q will rise, causing the thin film transistor T3 to turn on by mistake, and the scanning signal WR(n) output by the GOA circuit rises to a high potential by mistake, so that the scanning signal WR( n) Generate voltage oscillations. Since the scan signal WR(n) is connected to the switching thin film transistor T1 of the pixel circuit, the voltage oscillation of the scan signal WR(n) will cause the gate of the driving thin film transistor T2 of the pixel circuit to be connected. Through) effect, which causes crosstalk to the voltage at point G, so the current of the driving thin film transistor T2 will oscillate instantaneously. Since the light emitting element E is driven by the current source generated by the driving thin film transistor T2, the light emitting element E The current and brightness will also oscillate, as shown in the X area in Figure 2.

Therefore, the existing technology has shortcomings and is in urgent need of improvement.

technical problem

The present application provides an array substrate and a display panel, which can alleviate or even eliminate the current and brightness oscillation problems of light-emitting elements caused by clock signals.

Technical solutions

To solve the above problems, the technical solutions provided by this application are as follows:

The present application provides an array substrate including a pixel circuit corresponding to a display area, and a first scan driving circuit and a second scan driving circuit provided corresponding to the periphery of the display area. The pixel circuit includes a switch circuit, a voltage maintaining circuit, and a driving element And light-emitting elements;

The first scan driving circuit includes an output circuit coupled to a first node and connected to a clock signal for outputting a scan signal according to the first node control signal output by the first node and the clock signal ; The second scan driving circuit is used to output a light-emitting control signal;

The switch circuit is connected to a data signal, and is connected to the output circuit of the first scan driving circuit, for controlling the input of the data signal according to the scan signal;

The driving element is connected to the switch circuit and is connected to a high voltage signal for driving the light emitting element to emit light according to the scan signal and the data signal;

Wherein, the voltage maintaining circuit is connected to a constant voltage and low potential, and the switching circuit and the first scan driving circuit are connected in parallel, and the input terminal of the voltage maintaining circuit is connected to the output terminal of the second scan driving circuit The voltage maintaining circuit is used to maintain the low level of the scan signal unchanged when the scan signal output by the output circuit is at a low level.

In the array substrate of the present application, the switch circuit includes a first thin film transistor, the gate of the first thin film transistor is connected to the output terminal of the output circuit, and the source of the first thin film transistor is connected to the For a data signal, the drain of the first thin film transistor is connected to the driving element.

In the array substrate of the present application, the driving element includes a second thin film transistor, the gate of the second thin film transistor is connected to the drain of the first thin film transistor, and the source of the second thin film transistor is connected to For the high voltage signal, the drain of the second thin film transistor is connected to the first electrode of the light emitting element, and the second electrode of the light emitting element is connected to a common ground signal.

In the array substrate of the present application, the pixel circuit further includes a storage capacitor, and the first plate of the storage capacitor is connected in parallel with the gate of the second thin film transistor to the drain of the first thin film transistor, so The second plate of the storage capacitor and the drain of the second thin film transistor are connected in parallel to the first electrode of the light-emitting element.

In the array substrate of the present application, the voltage maintaining circuit includes a third thin film transistor, the gate of the third thin film transistor is connected to the output terminal of the second scan driving circuit, and the source of the third thin film transistor is connected to Into the constant voltage low potential, the drain of the third thin film transistor is connected in parallel to the output terminal of the output circuit and the gate of the first thin film transistor.

In the array substrate of the present application, the output circuit includes a fourth thin film transistor, the gate of the fourth thin film transistor is coupled to the first node, and the source of the fourth thin film transistor is electrically connected to the For the clock signal, the drain of the fourth thin film transistor is connected to the output terminal of the output circuit.

In the array substrate of the present application, when the scan signal output by the output circuit is at a high potential, the light emission control signal output by the second scan driving circuit is at a low potential, the voltage sustaining circuit is turned off, and The switch circuit is turned on, and the data signal is input to the driving element;

When the scan signal output by the output circuit is at a low level, the light emission control signal output by the second scan drive circuit rises to a high level, the voltage maintenance circuit is turned on, the switch circuit is turned off, and the The voltage maintaining circuit is used to maintain the low potential of the scan signal unchanged.

In the array substrate of the present application, the pulse width of the light emission control signal is greater than the pulse width of the scan signal.

The present application also provides a display panel, including the above-mentioned array substrate, and an organic light-emitting layer prepared on the array substrate.

In order to solve the above problems, the present application also provides an array substrate including a pixel circuit corresponding to a display area, and a first scan driving circuit and a second scan driving circuit arranged corresponding to the periphery of the display area. The pixel circuit includes a switch circuit, Voltage maintenance circuit, compensation circuit, driving element and light emitting element;

The input terminal of the compensation circuit is connected to the output terminal of the second scan driving circuit, the output terminal of the compensation circuit is connected to the driving element, and the light emission control signal is used to control the compensation circuit;

Beneficial effect

The beneficial effects of the present application are: compared with the existing display panel, the array substrate and the display panel provided by the present application provide a voltage maintaining circuit in the pixel circuit, thereby alleviating or even eliminating the current and brightness of the light emitting element caused by the clock signal. Oscillation problem. That is, when the potential of the clock signal rises from a low potential to a high potential, it will cause the potential of the Q point to rise, and cause the thin film transistor T4 of the output circuit to turn on by mistake. At this time, the scan signal output by the gate drive circuit needs to be maintained at a low potential. In the present application, the voltage maintaining circuit and the constant voltage low-potential signal connected to it can ensure that the scan signal output by the gate drive circuit is at a low potential and does not oscillate, thus avoiding crosstalk of the pixel circuit G point caused by the clock signal.

Description of the drawings

In order to explain the embodiments or the technical solutions in the prior art more clearly, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only for application. For some embodiments, those of ordinary skill in the art can obtain other drawings based on these drawings without creative work.

FIG. 1 is a partial circuit diagram of a scan driving circuit and a pixel circuit of an array substrate in the prior art;

2 is a timing diagram of a scan driving circuit and a pixel circuit of an array substrate in the prior art;

3 is a schematic diagram of the structure of an array substrate provided by an embodiment of the application;

4 is a partial circuit diagram of a scan driving circuit and a pixel circuit of an array substrate provided by an embodiment of the application;

FIG. 5 is a timing diagram of a scan driving circuit and a pixel circuit of an array substrate provided by an embodiment of the application.

Embodiments of the invention

The description of the following embodiments refers to the attached drawings to illustrate specific embodiments that can be implemented in this application. The directional terms mentioned in this application, such as [Up], [Down], [Front], [Back], [Left], [Right], [Inner], [Outer], [Side], etc., are for reference only The direction of the additional schema. Therefore, the directional terms used are used to illustrate and understand the application, rather than to limit the application. In the figure, units with similar structures are indicated by the same reference numerals.

The present application is directed to the technical problem of the current and brightness of the light-emitting element oscillating due to the clock signal in the existing display panel, and this embodiment can solve this defect.

The pixel circuit in the OLED display device generally adopts a matrix driving mode, and is divided into active matrix (Active Matrix) driving and passive matrix (Passive Matrix) driving according to whether switching elements are introduced in each pixel unit. AMOLED integrates a set of thin film transistors and storage capacitors in the pixel circuit of each pixel. By driving and controlling the thin film transistors and storage capacitors, the current flowing through the OLED is controlled, so that the OLED emits light as needed.

As shown in FIG. 3, it is a schematic diagram of the structure of the array substrate provided by the embodiment of this application. The array substrate includes a pixel circuit corresponding to the display area 10 and a scan driving circuit 11 corresponding to the periphery of the display area 10. A plurality of binding terminals 12 are provided on one side of the display area 10. The scan driving The circuit 11 is connected to the binding terminal 12. The array substrate further includes a plurality of scan lines 13 for connecting the pixel circuit and the scan driving circuit 11. The display area 10 includes pixel areas 101 distributed in an array, and each pixel area 101 corresponds to one pixel circuit.

In this embodiment, the scan driving circuit 11 includes a first scan driving circuit 111 and a second scan driving circuit 112, and the first scan driving circuit 111 and the second scan driving circuit 112 are respectively disposed in the On both sides of the display area 10, the pixel circuit further includes a compensation circuit (not shown), the first scan driving circuit 111 is used to provide scan signals, and the second scan driving circuit 112 is used to provide all The lighting control signal required by the compensation circuit.

As shown in FIG. 4, a partial circuit diagram of the scan driving circuit and the pixel circuit of the array substrate provided by the embodiment of the application. Among them, the n-th stage gate driving circuit is taken as an example for description. The first scan driving circuit 111 includes an output circuit 30, which is coupled to the first node Q and connected to the clock signal CK, and is used to output the first node control signal according to the first node Q and the output circuit 30. The clock signal CK outputs the scan signal WR(n); the first scan driving circuit 111 also includes other conventional circuits, which will not be repeated here.

The pixel circuit P includes a switch circuit 20, a voltage maintaining circuit 21, a driving element 22, and a light emitting element 23. The switch circuit 20 is connected to the data signal D, and the switch circuit 20 is connected to the output terminal M of the output circuit 30 of the first scan driving circuit 111 for controlling according to the scan signal WR(n) The input of the data signal D.

Specifically, the switch circuit 20 includes a first thin film transistor T1, the gate of the first thin film transistor T1 is connected to the output terminal M of the output circuit 30, and the source of the first thin film transistor T1 is connected to the output terminal M of the output circuit 30. For the data signal D, the drain of the first thin film transistor T1 is connected to the driving element 22.

The driving element 22 is connected to the switch circuit 20 and is connected to a high voltage signal VDD for driving the light emitting element 23 to emit light according to the scan signal WR(n) and the data signal D.

Specifically, the driving element 22 includes a second thin film transistor T2, the gate of the second thin film transistor T2 is connected to the drain of the first thin film transistor T1, and the source of the second thin film transistor T2 is connected to For the high voltage signal VDD, the drain of the second thin film transistor T2 is connected to the first electrode of the light emitting element 23, and the second electrode of the light emitting element 23 is connected to a common ground signal VSS. The light-emitting element 23 may be an organic light-emitting diode E, the first electrode may be an anode, and the second electrode may be a cathode.

The voltage maintaining circuit 21 is connected to the constant voltage low potential VGL, and the switch circuit 20 and the first scan driving circuit 111 are connected in parallel, and the input terminal of the voltage maintaining circuit 21 is connected to the second scan driving circuit 112 at the output terminal M', the second scan driving circuit 112 is used to output a light emission control signal EM(n), and the voltage maintaining circuit 21 is used to output the scan signal WR(n) in the output circuit 30 When it is a low potential, the low potential of the scan signal WR(n) is maintained unchanged.

Specifically, the voltage maintenance circuit 21 includes a third thin film transistor T3, the gate of the third thin film transistor T3 is connected to the output terminal M'of the second scan driving circuit 112, and the source of the third thin film transistor T3 The electrode is connected to the constant voltage low potential VGL, and the drain of the third thin film transistor T3 is connected in parallel to the output terminal M of the output circuit 30 and the gate of the first thin film transistor T1.

The pixel circuit P further includes a storage capacitor C. The first plate of the storage capacitor C is connected in parallel with the gate of the second thin film transistor T2 to the drain of the first thin film transistor T1. The second plate of C is connected to the first electrode of the light-emitting element 23 in parallel with the drain of the second thin film transistor T2.

The output circuit 30 includes a fourth thin film transistor T4, the gate of the fourth thin film transistor T4 is coupled to the first node Q, and the source of the fourth thin film transistor T4 is electrically connected to the clock signal CK, the drain of the fourth thin film transistor T4 is connected to the output terminal M of the output circuit 30.

Wherein, the scan signal WR(n) is generated by the first scan driving circuit 111, the light emission control signal EM(n) is generated by the second scan driving circuit 112, and the present application The pixel circuit provided is also applicable to an array substrate provided with a compensation circuit. The input terminal of the compensation circuit (not shown) is connected to the output terminal M'of the second scan driving circuit 112. The output terminal is connected to the driving element 22, the light emission control signal EM(n) is also a signal required by the compensation circuit, and the light emission control signal EM(n) is used to control the compensation circuit.

As shown in conjunction with FIG. 5, a timing diagram of the scan driving circuit and the pixel circuit of the array substrate provided by this embodiment of the application. When the scan signal WR(n) output by the output circuit 30 is at a high potential VGH, the light emission control signal EM(n) output by the second scan driving circuit 112 is at a low potential VGL, and the voltage is maintained The circuit 21 is turned off, the switch circuit 20 is turned on, and the data signal D is input to the driving element 22; when the scan signal WR(n) output by the output circuit 30 is at a low potential VGL, the first The light emission control signal EM(n) output by the second scan driving circuit 112 rises to a high potential VGH, the voltage maintenance circuit 21 is turned on, the switch circuit 20 is turned off, and the constant voltage that the voltage maintenance circuit 21 is connected to The low potential VGL is used to maintain the low potential of the scan signal WR(n) unchanged, so that the next time the clock signal CK rises from the low potential VGL to the high potential VGH, the current and brightness of the organic light emitting diode E No vibration occurs, as shown in the X area in Figure 5.

Specifically, taking a single pixel area 101 as an example for description, in the S1 stage, when the fourth thin film transistor T4 in the output circuit 30 is in the on state, the clock signal CK is at the high potential VGH, and the output The scanning signal WR(n) is a high potential VGH, the light emission control signal EM(n) is a low potential VGL, the third thin film transistor T3 is turned off, and the second thin film transistor T2 is turned on at this time, and the data signal D is written so that the organic light emitting diode E forms a current.

In the S2 stage, the clock signal CK drops to a low potential VGL, and the output scan signal WR(n) also drops to a low potential VGL, the second thin film transistor T2 is turned off, and the light emission control signal EM (n) Still at the low potential VGL, the third thin film transistor T3 is also turned off, and the organic light emitting diode E emits light.

In the S3 stage, the fourth thin film transistor T4 is turned off, the clock signal CK is still at the low potential VGL, the scan signal WR(n) remains at the low potential VGL, and the light emission control signal EM(n) rises to At a high potential VGH, the third thin film transistor T3 is turned on, and the constant voltage low potential VGL accessed by the voltage maintaining circuit 21 is used to maintain the low potential of the scan signal WR(n) unchanged. That is to say, when the clock signal CK rises from the low potential VGL to the high potential VGH, the potential of the first node Q will rise, and the fourth thin film transistor T4 will be turned on by mistake, thereby causing the scan signal The potential of WR(n) rises instantaneously, thereby causing crosstalk to point G. With this circuit design, the scanning signal WR(n) is maintained at a low potential through the third thin film transistor T3 of each pixel circuit, thereby Crosstalk will not be generated to the G point, reducing or even eliminating the voltage oscillation of the scanning signal WR(n), thereby reducing or even eliminating the current and brightness oscillation of the organic light emitting diode E.

Wherein, the pulse width of the light emission control signal EM(n) is greater than the pulse width of the scan signal WR(n). Assuming that the panel resolution is FHD, the refresh rate is 60HZ, the pulse width of the scan signal WR(n) is 15 us within one frame, and the pulse width of the light emission control signal EM(n) is greater than 16 ms. When the data signal D is written, the light emission control signal EM(n) is at a low potential, the third thin film transistor T3 is turned off, the scan signal WR(n) is at a high potential, and the third thin film transistor T3 does not affect the writing of the data signal D. When the light emission control signal EM(n) is at a high potential, the third thin film transistor T3 is in an on state, and within one frame time, the stability of the scanning signal WR(n) can be maintained for a time greater than 16ms , Eliminating the oscillation of the scanning signal WR(n), thereby reducing or even eliminating the current and brightness oscillation of the organic light emitting diode E.

In addition, the first scan driving circuit 111 and the second scan driving circuit 112 both include the constant voltage low potential VGL signal, and the constant voltage low potential VGL connected by the voltage maintenance circuit 21 can be controlled by the The first scan driving circuit 111 or the second scan driving circuit 112 is provided by itself.

In summary, the array substrate and the display panel provided by the present application have a voltage maintaining circuit in the pixel circuit, thereby alleviating or even eliminating the problem of the current and brightness oscillation of the light emitting element caused by the clock signal. That is, when the potential of the clock signal rises from a low potential to a high potential, it will cause the potential of the Q point to rise, and cause the thin film transistor T4 of the output circuit to turn on by mistake. At this time, the scan signal output by the gate drive circuit needs to be maintained at a low potential. In the present application, the voltage maintaining circuit and the constant voltage low-potential signal connected to it can ensure that the scan signal output by the gate drive circuit is at a low potential and does not oscillate, thus avoiding crosstalk of the pixel circuit G point caused by the clock signal.

In summary, although the application has been disclosed as above in preferred embodiments, the above-mentioned preferred embodiments are not intended to limit the application, and those of ordinary skill in the art can make various decisions without departing from the spirit and scope of the application. Such changes and modifications, so the protection scope of this application is subject to the scope defined by the claims.

Claims

An array substrate includes a pixel circuit corresponding to a display area, and a first scan driving circuit and a second scan driving circuit provided corresponding to the periphery of the display area. The pixel circuit includes a switch circuit, a voltage maintaining circuit, a driving element, and a light emitting element;

The first scan driving circuit includes an output circuit coupled to a first node and connected to a clock signal for outputting a scan signal according to the first node control signal output by the first node and the clock signal ; The second scan driving circuit is used to output a light-emitting control signal;

The switch circuit is connected to a data signal, and is connected to the output circuit of the first scan driving circuit, for controlling the input of the data signal according to the scan signal;

The driving element is connected to the switch circuit and is connected to a high voltage signal for driving the light emitting element to emit light according to the scan signal and the data signal;

Wherein, the voltage maintaining circuit is connected to a constant voltage and low potential, and the switching circuit and the first scan driving circuit are connected in parallel, and the input terminal of the voltage maintaining circuit is connected to the output terminal of the second scan driving circuit The voltage maintaining circuit is used to maintain the low level of the scan signal unchanged when the scan signal output by the output circuit is at a low level.
The array substrate according to claim 1, wherein the switch circuit comprises a first thin film transistor, a gate of the first thin film transistor is connected to an output terminal of the output circuit, and a source of the first thin film transistor The data signal is connected, and the drain of the first thin film transistor is connected to the driving element.
4. The array substrate according to claim 2, wherein the driving element comprises a second thin film transistor, the gate of the second thin film transistor is connected to the drain of the first thin film transistor, and the second thin film transistor The source is connected to the high voltage signal, the drain of the second thin film transistor is connected to the first electrode of the light emitting element, and the second electrode of the light emitting element is connected to a common ground signal.
The array substrate according to claim 3, wherein the pixel circuit further comprises a storage capacitor, the first plate of the storage capacitor and the gate of the second thin film transistor are connected in parallel to the first thin film transistor The drain, the second plate of the storage capacitor and the drain of the second thin film transistor are connected in parallel to the first electrode of the light-emitting element.
3. The array substrate according to claim 2, wherein the voltage maintaining circuit comprises a third thin film transistor, a gate of the third thin film transistor is connected to an output terminal of the second scan driving circuit, and the third thin film transistor The source of is connected to the constant voltage low potential, and the drain of the third thin film transistor is connected in parallel to the output terminal of the output circuit and the gate of the first thin film transistor.
The array substrate according to claim 1, wherein the output circuit comprises a fourth thin film transistor, the gate of the fourth thin film transistor is coupled to the first node, and the source of the fourth thin film transistor is electrically connected Is electrically connected to the clock signal, and the drain of the fourth thin film transistor is connected to the output terminal of the output circuit.
The array substrate according to claim 1, wherein when the scan signal output by the output circuit is at a high level, the light emission control signal output by the second scan driving circuit is at a low level, and the voltage is maintained The circuit is turned off, the switch circuit is turned on, and the data signal is input to the driving element;

When the scan signal output by the output circuit is at a low level, the light emission control signal output by the second scan drive circuit rises to a high level, the voltage maintenance circuit is turned on, the switch circuit is turned off, and the The voltage maintaining circuit is used to maintain the low potential of the scan signal unchanged.
8. The array substrate according to claim 7, wherein the pulse width of the light emission control signal is greater than the pulse width of the scan signal.
A display panel, comprising the array substrate according to claim 1, and an organic light-emitting layer prepared on the array substrate.
An array substrate includes a pixel circuit corresponding to a display area, and a first scan driving circuit and a second scan driving circuit arranged corresponding to the periphery of the display area. The pixel circuit includes a switch circuit, a voltage maintaining circuit, a compensation circuit, and a driver Components and light-emitting components;

The first scan driving circuit includes an output circuit coupled to a first node and connected to a clock signal for outputting a scan signal according to the first node control signal output by the first node and the clock signal ; The second scan driving circuit is used to output a light-emitting control signal;

The switch circuit is connected to a data signal, and is connected to the output circuit of the first scan driving circuit, for controlling the input of the data signal according to the scan signal;

The input terminal of the compensation circuit is connected to the output terminal of the second scan driving circuit, the output terminal of the compensation circuit is connected to the driving element, and the light emission control signal is used to control the compensation circuit;

The driving element is connected to the switch circuit and is connected to a high voltage signal for driving the light emitting element to emit light according to the scan signal and the data signal;

Wherein, the voltage maintaining circuit is connected to a constant voltage and low potential, and the switching circuit and the first scan driving circuit are connected in parallel, and the input terminal of the voltage maintaining circuit is connected to the output terminal of the second scan driving circuit The voltage maintaining circuit is used to maintain the low level of the scan signal unchanged when the scan signal output by the output circuit is at a low level.
11. The array substrate of claim 10, wherein the switch circuit comprises a first thin film transistor, a gate of the first thin film transistor is connected to an output terminal of the output circuit, and a source of the first thin film transistor The data signal is connected, and the drain of the first thin film transistor is connected to the driving element.
11. The array substrate according to claim 11, wherein the driving element comprises a second thin film transistor, the gate of the second thin film transistor is connected to the drain of the first thin film transistor, and the second thin film transistor The source is connected to the high voltage signal, the drain of the second thin film transistor is connected to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is connected to a common ground signal.
The array substrate according to claim 12, wherein the pixel circuit further comprises a storage capacitor, the first plate of the storage capacitor and the gate of the second thin film transistor are connected in parallel to the first thin film transistor The drain, the second plate of the storage capacitor and the drain of the second thin film transistor are connected in parallel to the first electrode of the light-emitting element.
11. The array substrate of claim 11, wherein the voltage maintaining circuit comprises a third thin film transistor, a gate of the third thin film transistor is connected to an output terminal of the second scan driving circuit, and the third thin film transistor The source of is connected to the constant voltage low potential, and the drain of the third thin film transistor is connected in parallel to the output terminal of the output circuit and the gate of the first thin film transistor.
9. The array substrate of claim 10, wherein the output circuit comprises a fourth thin film transistor, a gate of the fourth thin film transistor is coupled to the first node, and a source of the fourth thin film transistor Is electrically connected to the clock signal, and the drain of the fourth thin film transistor is connected to the output terminal of the output circuit.
10. The array substrate according to claim 10, wherein when the scan signal output by the output circuit is at a high level, the light emission control signal output by the second scan driving circuit is at a low level, and the voltage is maintained The circuit is turned off, the switch circuit is turned on, and the data signal is input to the driving element;

When the scan signal output by the output circuit is at a low level, the light emission control signal output by the second scan drive circuit rises to a high level, the voltage maintenance circuit is turned on, the switch circuit is turned off, and the The voltage maintaining circuit is used to maintain the low level of the scanning signal unchanged.
15. The array substrate of claim 16, wherein the pulse width of the light emission control signal is greater than the pulse width of the scan signal.