WO2021023107A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

Info

Publication number
WO2021023107A1
WO2021023107A1 PCT/CN2020/106204 CN2020106204W WO2021023107A1 WO 2021023107 A1 WO2021023107 A1 WO 2021023107A1 CN 2020106204 W CN2020106204 W CN 2020106204W WO 2021023107 A1 WO2021023107 A1 WO 2021023107A1
Authority
WO
WIPO (PCT)
Prior art keywords
pole
pole piece
transistor
pixel
display substrate
Prior art date
Application number
PCT/CN2020/106204
Other languages
English (en)
French (fr)
Inventor
马永达
郝学光
乔勇
吴新银
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP20850140.3A priority Critical patent/EP4012773A4/en
Priority to JP2021537179A priority patent/JP2022543714A/ja
Priority to US17/276,282 priority patent/US11991906B2/en
Publication of WO2021023107A1 publication Critical patent/WO2021023107A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure belongs to the field of display technology, and specifically relates to a display substrate, a manufacturing method thereof, and a display device.
  • the present disclosure provides a display substrate including a plurality of pixel regions, each pixel region includes a display region provided with a light emitting device and a driving region provided with a pixel circuit, the pixel circuit including at least one pixel transistor, The first electrode and the second electrode of the at least one pixel transistor are respectively connected to its active layer through a connection via hole, wherein a first electrode piece of a storage capacitor is further provided in the driving area, and the first electrode piece is connected to The first pole and the second pole of the at least one pixel transistor are insulated and overlapped in a direction perpendicular to the display substrate, and the first pole piece has an opening corresponding to at least a part of the connection via.
  • the first pole piece is connected to the first electrode of the light emitting device, and the second electrode of the light emitting device is connected to a second power line;
  • the at least one pixel transistor includes A switching transistor and a driving transistor; wherein the gate of the switching transistor is connected to the gate line, the first electrode is connected to the data line, and the second electrode is electrically connected to the gate of the driving transistor; the first electrode of the driving transistor is connected to the first power line , The second electrode is connected to the pixel electrode.
  • the first pole piece has an opening corresponding to at least one of the following connection vias: a connection via for the first pole of the switching transistor; a connection via for the second pole of the switching transistor; A connection via for the first pole of the driving transistor.
  • connection vias of the first pole piece and the second pole of the drive transistor are insulated and overlapped in a direction perpendicular to the display substrate, and the first pole piece is located on the first pole of the corresponding drive transistor.
  • the connecting via hole of the two poles has an opening.
  • connection vias of the first pole piece and the second pole of the drive transistor are insulated and overlapped in a direction perpendicular to the display substrate, and the first pole piece is connected to the second pole of the corresponding drive transistor. There is no opening at the connecting via of the two poles.
  • the storage capacitor further includes: a second pole piece electrically connected to the second pole of the switching transistor; the second pole piece and the first pole piece are in a direction perpendicular to the display substrate The upper insulation overlaps to form a first sub-capacitor.
  • the second pole piece and the active layer of the pixel transistor are arranged in the same layer.
  • the storage capacitor further includes: a third pole piece electrically connected to the first pole piece, and the third pole piece is arranged in the same layer as the first electrode and the second electrode of the pixel transistor, and It is insulated and overlapped with the second pole piece to form a second sub-capacitor.
  • the light emitting device is an organic light emitting diode.
  • the display substrate further includes a base: the first electrode and the second electrode of the pixel transistor are located on a side of the active layer of the pixel transistor away from the base; the first electrode piece is located on the pixel transistor The active layer is close to the side of the substrate.
  • the orthographic projection of the opening on the substrate covers the orthographic projection of the corresponding connecting via on the substrate.
  • the area of the orthographic projection of the opening on the substrate is greater than or equal to the area of the orthographic projection of the corresponding connecting via on the substrate.
  • the slope angle of the connection via hole corresponding to the opening is an acute angle
  • the slope angle is an included angle between the sidewall of the connection via hole and the plane where the display substrate is located.
  • the slope angle of the connecting via hole corresponding to the opening is between 45 degrees and 75 degrees.
  • the boundary angle of the active layer at the connection via hole corresponding to the opening is an acute angle
  • the boundary angle is the angle between the sidewall of the active layer and the plane where the display substrate is located.
  • the slope angle of the connecting via hole corresponding to the opening is an acute angle; and ( ⁇ + ⁇ )/2>min( ⁇ , ⁇ )>1/4 ⁇ , where ⁇ is the slope of any connecting via hole corresponding to the opening Angle, ⁇ is the boundary angle of the active layer at the connection via, the slope angle is the angle between the sidewall of the connection via and the plane where the display substrate is located, and the boundary angle is the The angle between the sidewall of the active layer and the plane where the display substrate is located.
  • the opening includes: a notch located at the edge of the first pole piece; and/or a through hole located inside the first pole piece.
  • a display device including: the above-mentioned display substrate.
  • a method for manufacturing a display substrate including: providing a base; forming a storage capacitor and at least one pixel transistor on the base, wherein the display substrate includes a plurality of pixel regions, each The pixel area includes a display area provided with a pixel electrode and a driving area provided with a pixel circuit.
  • the pixel circuit includes the at least one pixel transistor.
  • the first electrode and the second electrode of the pixel transistor are connected to each other through connection vias.
  • the source layer is connected, wherein the first pole piece of the storage capacitor is located in the driving area, and the first pole piece and the first pole and the second pole of the pixel transistor are in a direction perpendicular to the display substrate
  • the upper insulation overlaps, and the first pole piece has an opening at least part of the connection via hole.
  • forming a storage capacitor and at least one pixel transistor on the substrate includes: forming a first pole piece of the storage capacitor on the substrate; forming a first insulating layer on the first pole piece; The gate and the gate line of the switching transistor are formed on an insulating layer; the second insulating layer is formed on the gate of the switching transistor and the gate line; the active layer of the switching transistor is formed on the second insulating layer Layer, the active layer of the driving transistor and the second pole piece of the storage capacitor, wherein the second pole piece and the first pole piece are insulated and overlapped in a direction perpendicular to the substrate to form a first sub-capacitor; A third insulating layer is formed on the active layer of the switching transistor, the active layer of the driving transistor, and the second pole piece of the storage capacitor; and the first pole of the switching transistor and the second pole piece of the switching transistor are formed on the third insulating layer.
  • the pole piece is connected with the second pole of the driving transistor through a connection via, and the second pole piece and the third pole piece are insulated and overlapped in a direction perpendicular to the substrate to form a second sub-capacitor .
  • FIG. 1 is a schematic structural diagram of a display substrate according to an embodiment of the disclosure
  • FIG. 2 is a circuit diagram of a pixel circuit in a display substrate according to an embodiment of the disclosure
  • FIG. 3 is a schematic structural diagram of a pixel area in a display substrate according to an embodiment of the disclosure.
  • FIG. 4 is a schematic diagram of the structure of the first pole piece in FIG. 3;
  • Fig. 5 is a schematic cross-sectional structure view along AA' in Fig. 3;
  • Fig. 6 is a schematic cross-sectional structure view along BB' in Fig. 3;
  • Fig. 7 is a schematic cross-sectional structure view along DD' in Fig. 3;
  • FIG. 8 is a schematic structural diagram of a pixel area in a display substrate according to an embodiment of the disclosure.
  • FIG. 9 is a flowchart of manufacturing a display substrate according to an embodiment of the disclosure.
  • each unit and module involved in the embodiments of the present disclosure may correspond to only one physical structure, or may be composed of multiple physical structures, or multiple units and modules may also be integrated into one physical structure.
  • the “same layer arrangement” of multiple structures means that multiple structures are formed by the same material layer, so they are in the same layer in the stacking relationship, but it does not mean that the distance between them and the substrate is equal, nor does it mean that they are in the same layer.
  • the other layer structures between the substrates are exactly the same.
  • the structure of "different layer arrangement” refers to multiple layers of different materials that do not meet the above conditions of "same layer arrangement".
  • the "patterning process” refers to a step of forming a structure with a specific pattern, which may be a photolithography process.
  • the photolithography process includes one or more steps of forming a material layer, coating photoresist, exposing, developing, etching, and photoresist stripping.
  • the patterning process can also be an imprinting process, an inkjet printing process and other processes.
  • Opening means that the first pole piece originally has a relatively complete regular shape (such as a rectangle), but has missing parts (such as gaps or holes) in some positions, so the positions where these regular shapes are missing are “openings”.
  • the first electrode and the second electrode (ie source and drain) of the pixel transistor are generally connected to its active layer through connection vias, and most of the voltages of the first and second electrodes are different from the voltages of the electrodes of the storage capacitor , Resulting in a voltage difference between the overlapping layers. Therefore, at the position where the via hole is connected above, it is easy to cause a short circuit between the storage capacitor and the pixel transistor (specifically, the electrode of the storage capacitor and the first electrode and the second electrode of the pixel transistor), which reduces the product quality.
  • a display substrate including a plurality of pixel regions, each pixel region including a display region provided with a pixel electrode and a driving region provided with a pixel circuit.
  • the pixel circuit includes at least one pixel transistor, and the first electrode and the second electrode of the pixel transistor are respectively connected to its active layer through a connection via.
  • the first pole piece of the storage capacitor is also provided in the driving area, and the first pole piece is insulated and overlapped with the first pole and the second pole of the pixel transistor in the direction perpendicular to the display substrate, and is connected to at least part of at least part of the pixel transistor There is an opening at the via hole.
  • the storage capacitor is located in the driving area and overlaps the pixel transistor, so its area is large and the storage effect is good.
  • the first pole piece of the storage capacitor has openings at the corresponding connection vias, that is, the first pole piece does not overlap with these connection vias or the overlap is small, thereby reducing the occurrence of the first pole piece at the connection vias. Defective risks such as short circuits improve product quality.
  • the display substrate of the embodiment of the present disclosure includes a plurality of pixel areas 9, and each pixel area 9 includes a display area 92 provided with a pixel electrode 921 and a driving area 91 provided with a pixel circuit.
  • the pixel circuit includes at least one pixel transistor, and the first electrode and the second electrode of the pixel transistor are respectively connected to its active layer through the connection via 2.
  • the display substrate of the embodiment of the present disclosure includes a plurality of pixel regions 9, and each pixel region 9 is a minimum unit capable of independently performing display, that is, a sub-pixel.
  • a plurality of gate lines GATE and a plurality of data lines DATA may also be provided on the display substrate.
  • the gate lines GATE and the data lines DATA are insulated from each other and have crosses, and each pixel region 9 is one by two adjacent The area enclosed by the gate line GATE and two adjacent data lines DATA.
  • each pixel area 9 may be located in the effective area (AA area) of the display substrate, and the display substrate may also include a fan-out area (Fanout area, that is, the top area in FIG. 1) for drawing the leads, etc. Describe in detail.
  • the display substrate may also include structures such as a first power line VDD and a second power line VSS for supplying power to each pixel area 9.
  • a first power line VDD and a second power line VSS for supplying power to each pixel area 9.
  • the first power supply line VDD and the second power supply line VSS are not shown.
  • each pixel area 9 includes a display area 92 and a driving area 91.
  • the display area 92 is provided with a pixel electrode 921. By driving the pixel electrode 921 with a data voltage (gray-scale voltage), the display area 92 can display desired content.
  • the driving area 91 is provided with a pixel circuit for driving the display area 92 for display.
  • the pixel circuit includes at least one transistor (pixel transistor), and the source and drain of these pixel transistors (that is, the first electrode and the second electrode) are connected to their corresponding active layer through a via (connection via 2).
  • a first pole piece C1 of the storage capacitor C is also provided, and the first pole piece C1 is insulated and overlapped with the first pole and the second pole of the pixel transistor in a direction perpendicular to the display substrate, and at least At least part of the pixel transistors has an opening C11 at the connection via 2.
  • a storage capacitor C is also provided in the pixel area 9, and one pole piece (first pole piece C1) of the storage capacitor C is at least partially located in the driving area 91 and is connected to the first pole and the second pole of the pixel transistor.
  • first pole piece C1 covers the entire driving area 91.
  • the first pole piece C1 has an opening C11, so that the first pole piece C1 does not overlap with these connection vias 2 or the overlapping area is small Therefore, the probability that the first pole piece C1 is short-circuited at the connection via 2 can be reduced, and the product quality can be improved.
  • the display substrate further includes a base 5.
  • the orthographic projection of the opening C11 on the substrate 5 covers the orthographic projection of the corresponding connection via 2 on the substrate 5. Further, the area of the orthographic projection of the opening C11 on the substrate 5 is greater than the area of the orthographic projection of the corresponding connecting via 2 on the substrate 5, and further makes the area of the orthographic projection of the opening C11 on the substrate 5 larger than that of the connecting via 2 The contact area between the data line or power line and the active layer.
  • the opening C11 preferably completely covers its corresponding connection via 2 to ensure that the first pole piece C1 and the connection via 2 do not overlap at all. Further, the opening C11 is more preferably beyond its corresponding connection via 2 to better avoid short circuits.
  • the opening C11 includes: a notch located at the edge of the first pole piece C1; and/or a through hole located inside the first pole piece C1.
  • the specific form of the opening C11 is also different.
  • the opening C11 When it is located at the edge of the first pole piece C1, the opening C11 is a recess that is recessed from the edge of the first pole piece C1 (as shown in the left side of 4 in the figure). Three openings C11); and when the opening C11 is located inside the first pole piece C1, it is a through hole that penetrates the first pole piece C1 (the opening C11 near the right in 4 in the figure).
  • the slope angle ⁇ of the connection via 2 corresponding to the opening C11 is an acute angle. Further, the slope angle ⁇ of the connecting via 2 corresponding to the opening C11 is between 45 degrees and 75 degrees.
  • the slope angle ⁇ of the connecting via 2 is the angle between its sidewall and the plane where the substrate 5 is located.
  • at least the connection via 2 corresponding to the opening C11 has an acute angle ⁇ , and further an acute angle between 45 degrees and 75 degrees.
  • the slope angle ⁇ of the via is related to the process parameters when the via is formed.
  • the slope angle ⁇ of the via hole is larger, it is more likely to cause over-etching, and therefore it is more likely to cause a wire contact layer to be formed at the via hole position, which increases the possibility of a short circuit between the via hole position and the conductive layer of a different layer.
  • the first electrode and the second electrode of the pixel transistor are arranged in the same layer, and are located on the side of the active layer of the pixel transistor away from the substrate 5; the first pole piece C1 is located on the side of the active layer of the pixel transistor close to the substrate 5.
  • the first electrode and the second electrode of the pixel transistor can be located above the active layer, so they are connected to the active layer through the connection via 2 located below itself.
  • the first pole piece C1 is located under the active layer.
  • such a first pole piece C1 and the connection via 2 are more likely to be short-circuited, so it is more suitable to adopt the opening C11 of the embodiment of the present disclosure.
  • the first pole piece C1 is electrically connected to the pixel electrode 921
  • the pixel electrode 921 is the first electrode of the light emitting device L
  • the second electrode of the light emitting device L is connected to the second power line VSS.
  • the pixel transistor includes a switching transistor T1 and a driving transistor T2.
  • the gate T13 of the switching transistor is connected to the gate line GATE
  • the first electrode T11 is connected to the data line DATA
  • the second electrode T12 is electrically connected to the gate T23 of the driving transistor.
  • the first electrode T21 of the driving transistor is connected to the first power line VDD
  • the second electrode is connected to the pixel electrode 921.
  • the light emitting device L is an organic light emitting diode.
  • the pixel circuit may be specifically in the form of controlling the writing of the data voltage by the switching transistor T1, and controlling the light-emitting brightness of the light-emitting device L by controlling the voltage of the gate T23 of the driving transistor.
  • the light-emitting device L It can be an organic light emitting diode (OLED), the first electrode (pixel electrode 921) of which can be one of a cathode or an anode, and the second electrode is the other.
  • FIG. 3 shows the most basic form (2T1C) of the above pixel circuit, that is, the pixel circuit includes at least two pixel transistors, a switching transistor T1 and a driving transistor T2, and a storage capacitor C.
  • the pixel circuit also includes other structures such as pixel transistors, it is also feasible.
  • one of the two electrodes of the storage capacitor should be electrically connected to the pixel electrode 921 (or the second electrode T22 of the driving transistor), and the other electrode should be connected to the second electrode T12 of the switching transistor (or the second electrode of the driving transistor).
  • the gate T23) is electrically connected.
  • the first pole piece C1 of the storage capacitor C belongs to the pole that is electrically connected to the pixel electrode 921.
  • the first pole piece C1 has an opening C11 corresponding to at least one of the following connecting vias 2: the connecting via 2 of the first pole T11 of the switching transistor; the connecting via 2 of the second pole T12 of the switching transistor; driving The first pole T21 of the transistor is connected to the via 2.
  • the first pole piece C1 is not directly connected to the first pole T11 and the second pole T12 of the switching transistor, and the first pole T21 of the driving transistor. Therefore, the voltages of the three poles T11, T12, and T21 are usually the same as those of the first pole T11, T12, and T21.
  • the voltage of one pole piece C1 is different, and it is easier to short-circuit with the first pole piece C1. Therefore, referring to FIG. 3, the first pole piece C1 is preferably provided with an opening C11 at the connection via 2 corresponding to the three poles T11, T12, and T2 (of course, it is most preferred to be at the corresponding three poles T11, T12, T2).
  • An opening C11 is provided at the connection via 2 at the same time.
  • the first pole piece C1 is insulated and overlapped with the connection via 2 of the second pole T22 of the driving transistor.
  • the first pole piece C1 Since the first pole piece C1 is electrically connected to the pixel electrode 921, it is also electrically connected to the second pole T22 of the driving transistor. The voltage of both should be the same at any time in theory, so the probability of a short circuit between the two is small. Therefore, referring to FIGS. 3 and 6, the first pole piece C1 has no opening at the connection via 2 corresponding to the second pole T22 of the driving transistor, but is insulated from the connection via 2 of the second pole T22 of the driving transistor. Stack to increase the area of the first pole piece C1.
  • the first pole piece C1 has an opening C11 at the connection via 2 corresponding to the second pole T22 of the driving transistor.
  • the probability of a short circuit between the first pole piece C1 and the second pole T22 of the driving transistor is relatively small, in order to more completely avoid the short circuit, referring to FIG. 8, the first pole piece C1 is on the first pole of the corresponding driving transistor.
  • the connecting via 2 of the diode T22 may also have an opening C11.
  • the storage capacitor C further includes: a second pole piece C2 electrically connected to the second pole T12 of the switching transistor, the second pole piece C2 and the first pole piece C1 are insulated and overlapped in a direction perpendicular to the display substrate to form The first sub-capacitor.
  • the first pole piece C1 must overlap with other pole pieces to form a capacitor.
  • the first pole piece C1 can overlap the second pole piece C2, and the second pole piece C2 and the switching transistor
  • the second electrode T12 (or the gate T23 of the driving transistor) is electrically connected.
  • the second pole piece C2 is arranged in the same layer as the active layer of the pixel transistor.
  • the storage capacitor C further includes: a third pole piece C3 electrically connected to the first pole piece C1, the third pole piece C3 and the first pole piece C1 are arranged in different layers and are connected to the first pole and the second pole of the pixel transistor. Very same layer setting.
  • the third pole piece C3 and the second pole piece C2 are insulated and overlapped to form a second sub-capacitor.
  • a third pole piece C3 arranged in a different layer from the first pole piece C1 can be added, and the third pole piece C3 is electrically connected to the first pole piece C1, so the first pole piece C1 and the first pole piece C1 are electrically connected to the first pole piece C1.
  • the voltage of the triode C3 is the same.
  • the third pole piece C3 and the first pole piece C1 are respectively located on both sides of the second pole piece C2 and overlap with it, so the storage capacitor C can be increased without increasing In the case of total area, increase its capacitance value.
  • the boundary angle ⁇ of the active layer at the connection via 2 corresponding to the opening C11 is an acute angle.
  • the boundary angle ⁇ of the active layer refers to the angle between the sidewall of the active layer and the plane where the substrate 5 is located.
  • the larger boundary angle ⁇ of the active layer can easily cause over-etching and increase the possibility of short circuits between the conductive layers of different layers. Therefore, the active layer (such as the switch The active layer T14 of the transistor and the active layer T24 of the driving transistor) at least the etching boundary angle ⁇ near the connection via 2 corresponding to the opening C11 is an acute angle (of course, due to process reasons, the same active layer is in each The boundary angle ⁇ of the location is usually the same).
  • the slope angle ⁇ of the connection via 2 corresponding to the opening C11 is an acute angle; and satisfies ( ⁇ + ⁇ )/2>min( ⁇ , ⁇ )>1/4 ⁇ , where the slope angle ⁇ and the boundary angle ⁇ are the same One corresponds to the corresponding angle at the connection via 2 with the opening C11.
  • the slope angle ⁇ of the connection via 2 and the active layer (such as the drive transistor).
  • the boundary angle ⁇ of the active layer T24) is an acute angle, and satisfies the above formula ( ⁇ + ⁇ )/2>min( ⁇ , ⁇ )>1/4 ⁇ , so that the etching rate can be kept fast and the connection is reduced The requirement of the possibility of short circuit between layers at the position of hole 2.
  • the above display substrate may also include other known structures.
  • the light-emitting layer and the second electrode of the light-emitting device L (not shown in the figure), the gate T13 of the switching transistor and the first insulating layer 61 of the first pole piece C1, the gate T13 of the switching transistor and the active
  • the second insulating layer 62 of the layer T14 (also including the active layer T24 of the driving transistor), the third insulating layer 63 that isolates each active layer and each first electrode/each second electrode, isolates each first electrode/each second electrode
  • the gate line GATE can be arranged on the same layer as the gate electrode T13 of the switching transistor
  • the second pole piece C2 can be arranged on the same layer as each active layer (the second pole piece C2 can be conductive)
  • the third pole piece C3 Each first pole/each second pole, data line DATA, first power line VDD, etc. can be arranged in the same layer.
  • the two structures can be electrically connected through vias.
  • the second pole T12 of the switching transistor can be electrically connected to the second pole piece C2 through a via hole, and referring to FIG. 3, the first pole piece C1 may further have an opening C11 at the via hole; for another example, the third pole The sheet C3 can be connected to the first pole piece C1 through a via hole, and the pixel electrode 921 can be connected to the third pole piece C3 through a via hole, thereby realizing the electrical connection of the first pole piece C1, the third pole piece C3, and the pixel electrode 921 .
  • the second pole T12 of the switching transistor can be directly connected to the gate T23 of the driving transistor as a whole; for another example, the second pole T22 of the driving transistor can be directly connected to the third pole piece C3 as a whole, so as to finally realize the driving transistor.
  • the second pole T22, the first pole piece C1, the third pole piece C3, and the pixel electrode 921 are electrically connected to each other.
  • Each pixel area of the display substrate includes a display area provided with pixel electrodes and a driving area provided with pixel circuits.
  • the pixel circuit includes at least one pixel transistor.
  • the first electrode and the second electrode of the pixel transistor are respectively connected to its active layer through a connection via.
  • the first pole piece of the storage capacitor is located in the driving area, the first pole piece and the first pole and the second pole of the pixel transistor are insulated and overlapped in a direction perpendicular to the display substrate, and the first pole piece is at least partially connected to each other There is an opening at the hole.
  • the preparation method thereof may include the following steps.
  • first pole piece C1 on the substrate through a patterning process.
  • the first pole piece C1 and the first pole and the second pole of the pixel transistor to be formed are insulated and overlapped in a direction perpendicular to the display substrate, and the first pole piece has an opening at least part of the connection via hole.
  • the second pole piece C2 and the first pole piece C1 are insulated and overlapped in a direction perpendicular to the substrate to form a first sub-capacitor.
  • the same process can be used to form the second pole piece C2 and the active layer of each transistor, that is, the same material (such as polysilicon) can be used to prepare the second pole piece C2 and the active layer of each transistor, and the second pole piece can be separately applied C2 is ion-doped to increase its conductivity.
  • the third pole piece C3 is connected to the first pole piece C1 through a connection via, and is connected to the second pole T22 of the driving transistor.
  • the second pole piece C2 and the third pole piece C3 are insulated and overlapped in a direction perpendicular to the substrate to form a second sub-capacitor.
  • the second electrode T12 of the switching transistor is connected to the gate T23 of the driving transistor.
  • the first pole T11 of the switching transistor is connected to the data line DATA.
  • the first pole T21 of the driving transistor is connected to the first power line VDD.
  • a fourth insulating layer 64 is formed on a power line VDD, a second power line VSS, and the third pole piece C3.
  • a pixel electrode 921 (first electrode) on the fourth insulating layer 64 through a patterning process.
  • the pixel electrode 921 is connected to the third pole piece C3 through a connection via.
  • the above method is described by taking the switching transistor as a bottom gate type and the driving transistor as a top gate type as an example, but the present disclosure is not limited to this.
  • a display device including the above-mentioned display substrate.
  • the display device can be any liquid crystal display panel (LCD), organic light emitting diode (OLED) display panel, electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc. Products or parts.
  • LCD liquid crystal display panel
  • OLED organic light emitting diode

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本公开提供一种显示基板及其制作方法、显示装置，该显示基板包括多个像素区，每个像素区包括设有像素电极的显示区和设有像素电路的驱动区，所述像素电路包括至少一个像素晶体管，所述像素晶体管的第一极和第二极分别通过连接过孔与有源层相连；所述驱动区中还设有存储电容的第一极片，所述第一极片与所述像素晶体管的第一极和第二极在垂直于所述显示基板的方向上绝缘交叠，且第一极片在对应至少部分连接过孔处具有开口。

Description

显示基板及其制作方法、显示装置
相关申请的交叉引用
本公开要求于2019年8月5日在中国知识产权局提交的No.201921258054.2的中国专利申请的优先权，该中国专利申请的全部内容通过引用合并于此。
技术领域
本公开属于显示技术领域，具体涉及一种显示基板及其制作方法、显示装置。
背景技术
现有显示基板(如有机发光二极管显示基板)中，随着分辨率的提高，每个像素区的面积越来越小。而为扩大存储电容，需要增大存储电容的极片的面积，从而可能导致极片与像素电路中的各像素晶体管有交叠。
发明内容
在一个方面，本公开提供了一种显示基板，包括多个像素区，每个像素区包括设有发光器件的显示区和设有像素电路的驱动区，所述像素电路包括至少一个像素晶体管，所述至少一个像素晶体管的第一极和第二极分别通过连接过孔与其有源层相连，其中，所述驱动区中还设有存储电容的第一极片，所述第一极片与所述至少一个像素晶体管的第一极和第二极在垂直于所述显示基板的方向上绝缘交叠，且所述第一极片在对应至少部分所述连接过孔处具有开口。
可选地，在一个所述像素区中，所述第一极片与所述发光器件的第一电极连接，所述发光器件的第二电极连接第二电源线；所述至少一个像素晶体管包括开关晶体管和驱动晶体管；其中，所述开关晶体管的栅极连接栅线，第一极连接数据线，第二极电 连接驱动晶体管的栅极；所述驱动晶体管的第一极连接第一电源线，第二极连接像素电极。
可选地，所述第一极片在对应以下至少一个连接过孔处具有开口：所述开关晶体管的第一极的连接过孔；所述开关晶体管的第二极的连接过孔；所述驱动晶体管的第一极的连接过孔。
可选地，所述第一极片与所述驱动晶体管的第二极的连接过孔在垂直于所述显示基板的方向上绝缘交叠，并且所述第一极片在对应驱动晶体管的第二极的连接过孔处具有开口。
可选地，所述第一极片与所述驱动晶体管的第二极的连接过孔在垂直于所述显示基板的方向上绝缘交叠，并且所述第一极片与对应驱动晶体管的第二极的连接过孔处不具有开口。
可选地，所述存储电容还包括：与所述开关晶体管的第二极电连接的第二极片；所述第二极片与所述第一极片在垂直于所述显示基板的方向上绝缘交叠以形成第一子电容。
可选地，所述第二极片与所述像素晶体管的有源层同层设置。
可选地，所述存储电容还包括：与所述第一极片电连接的第三极片，所述第三极片与所述像素晶体管的第一极和第二极同层设置，并与所述第二极片绝缘交叠以形成第二子电容。
可选地，所述发光器件为有机发光二极管。
可选地，所述显示基板还包括基底：所述像素晶体管的第一极和第二极位于所述像素晶体管的有源层远离基底的一侧；所述第一极片位于所述像素晶体管的有源层靠近基底的一侧。
可选地，所述开口在所述基底上的正投影覆盖其对应的连接过孔在所述基底上的正投影。
可选地，所述开口在所述基底上的正投影的面积大于或等于其对应的连接过孔在所述基底上的正投影的面积。
可选地，对应有开口的连接过孔的坡度角为锐角，所述坡度角为所述连接过孔的侧壁与所述显示基板所在平面之间的夹角。
可选地，对应有开口的连接过孔的坡度角在45度至75度之间。
可选地，对应有开口的连接过孔处的有源层的边界角为锐角，所述边界角为所述有源层的侧壁与所述显示基板所在平面之间的夹角。
可选地，对应有开口的连接过孔的坡度角为锐角；且(α+β)/2＞min(α，β)＞1/4α，其中α为对应有开口的任意连接过孔的坡度角，β为该连接过孔处的有源层的边界角，所述坡度角为所述连接过孔的侧壁与所述显示基板所在平面之间的夹角，所述边界角为所述有源层的侧壁与所述显示基板所在平面之间的夹角。
可选地，所述开口包括：位于所述第一极片边缘的凹口；和/或，位于所述第一极片内部的通孔。
在另一个方面，提供了一种显示装置，包括：以上所述的显示基板。
在另一个方面，提供了一种用于制作显示基板的方法，包括：提供基底；在所述基底上形成存储电容和至少一个像素晶体管，其中，所述显示基板包括多个像素区，每个像素区包括设有像素电极的显示区和设有像素电路的驱动区，所述像素电路包括所述至少一个像素晶体管，所述像素晶体管的第一极和第二极分别通过连接过孔与其有源层相连，其中，所述存储电容的第一极片位于所述驱动区中，所述第一极片与所述像素晶体管的第一极和第二极在垂直于所述显示基板的方向上绝缘交叠，且所述第一极片在至少部分连接过孔处具有开口。
可选地，在所述基底上形成存储电容和至少一个像素晶体管包括：在所述基底上形成存储电容的第一极片；在所述第一极片上形成第一绝缘层；在所述第一绝缘层上形成开关晶体管的栅极及栅线；在所述开关晶体管的栅极及所述栅线上形成第二绝缘层；在所述第二绝缘层上形成所述开关晶体管的有源层、驱动晶体管的有源层和存储电容的第二极片，其中，所述第二极片与所述第一极片在垂直所述基底的方向上绝缘交叠以形成第一子电容；在所述开关晶体管的有源层、驱动晶体管的有源层和存储电容的第 二极片上形成第三绝缘层；以及在所述第三绝缘层上形成开关晶体管的第一极、开关晶体管的第二极、驱动晶体管的第一极、驱动晶体管的第二极、驱动晶体管的栅极、数据线、第一电极线和第三极片，其中，所述第三极片与所述第一极片通过连接过孔连接并且与所述驱动晶体管的第二极连接，所述第二极片与所述第三极片在垂直于所述基底的方向上绝缘交叠以形成第二子电容。
附图说明
图1为本公开实施例的一种显示基板的结构示意图；
图2为本公开实施例的一种显示基板中的像素电路的电路图；
图3为本公开实施例的一种显示基板中的一个像素区的结构示意图；
图4为图3中第一极片的结构示意图；
图5为图3中沿AA’的剖面结构示意图；
图6为图3中沿BB’的剖面结构示意图；
图7为图3中沿DD’的剖面结构示意图；
图8为本公开实施例的一种显示基板中的一个像素区的结构示意图；
图9为本公开实施例的制作显示基板的流程图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
可以理解的是，此处描述的具体实施例和附图仅仅用于解释本公开，而非对本公开的限定。
可以理解的是，在不冲突的情况下，本公开中的各实施例及实施例中的各特征可相互组合。
可以理解的是，为便于描述，本公开的附图中仅示出了与本公开相关的部分，而与本公开无关的部分未在附图中示出。
可以理解的是，本公开的实施例中所涉及的每个单元、模块可仅对应一个实体结构，也可由多个实体结构组成，或者，多个单元、模块也可集成为一个实体结构。
名词解释
在本公开中，如无特殊说明，以下技术词语应按照下述的解释理解。
多个结构“同层设置”是指多个结构是由同一个材料层形成的，故它们在层叠关系上处于相同层中，但并不代表它们与基底间的距离相等，也不代表它们与基底间的其它层结构完全相同。相对的，结构“不同层设置”则是指多个不符合以上“同层设置”的条件，而是由不同材料层形成的。
“构图工艺”是指形成具有特定的图形的结构的步骤，其可为光刻工艺。光刻工艺包括形成材料层、涂布光刻胶、曝光、显影、刻蚀、光刻胶剥离等步骤中的一步或多步。当然，构图工艺也可为压印工艺、喷墨打印工艺等其它工艺。
“开口”是指，第一极片原本具有相对完整的规则形状(如矩形)，但在部分位置具有缺失(如缺口或孔)，从而这些规则形状缺失的位置即为“开口”。
由于像素晶体管的第一极和第二极(即源极和漏极)一般通过连接过孔与其有源层连接，且多数第一极、第二极的电压都与存储电容的电极的电压不同，从而导致交叠的层之间存在电压差。因此，在以上连接过孔的位置，容易造成存储电容与像素晶体管(具体是存储电容的电极与像素晶体管第一极、第二极)之间发生短路不良，降低产品质量。
因此，根据本公开的一个方面，提供了一种显示基板，其包括多个像素区，每个像素区包括设有像素电极的显示区和设有像素电路的驱动区。像素电路包括至少一个像素晶体管，像素晶体管的第一极和第二极分别通过连接过孔与其有源层相连。驱动区中还设有存储电容的第一极片，第一极片与像素晶体管的第一极和第二极在垂直显示基板的方向上绝缘交叠，且在至少部分像素 晶体管的至少部分连接过孔处具有开口。
本公开实施例的显示基板中，存储电容位于驱动区并与像素晶体管交叠，故其面积较大，存储效果好。同时，存储电容的第一极片在对应连接过孔处具有开口，即第一极片与这些连接过孔不交叠或交叠较小，从而降低了第一极片在连接过孔处产生短路等不良的风险，提高了产品质量。
参照图1至图8，对本公开的显示基板进行详细说明。
本公开实施例的显示基板包括多个像素区9，每个像素区9包括设有像素电极921的显示区92和设有像素电路的驱动区91。像素电路包括至少一个像素晶体管，像素晶体管的第一极和第二极分别通过连接过孔2与其有源层相连。
本公开实施例的显示基板包括多个像素区9，每个像素区9为一个能独立进行显示的最小单元，即为一个子像素。参照图1，显示基板上还可设有多条栅线GATE和多条数据线DATA，栅线GATE与数据线DATA相互绝缘且具有交叉，而每个像素区9即为一个由两条相邻栅线GATE与两条相邻数据线DATA围成的区域。其中，各像素区9均可位于显示基板的有效区(AA区)中，显示基板还可包括用于将引线引出的扇出区(Fanout区，即图1的顶部区域)等，在此不再详细描述。
在显示基板中，还可包括用于为各像素区9供电的第一电源线VDD、第二电源线VSS等结构，但在图1中，为清楚表示像素区9与栅线GATE、数据线DATA的关系，故第一电源线VDD、第二电源线VSS没有示出。
参照图1、图3，每个像素区9包括显示区92和驱动区91。显示区92中设有像素电极921，通过用数据电压(灰阶电压)驱动像素电极921，可使显示区92显示所需内容。而驱动区91中则设有用于驱动显示区92进行显示的像素电路。
像素电路包括至少一个晶体管(像素晶体管)，这些像素晶体管的源极和漏极(即第一极和第二极)是通过过孔(连接过孔2)与其对应的有源层连接的。
在驱动区91中，还设有存储电容C的第一极片C1，第一极片C1与像素晶体管的第一极和第二极在垂直于显示基板的方向上绝缘交叠，且在至少部分像素晶体管的至少部分连接过孔2处具有开口C11。
也就是说，像素区9中还设有存储电容C，且存储电容C的一个极片(第一极片C1)有至少部分位于驱动区91中，且与像素晶体管的第一极和第二极有交叠，从而第一极片C1的面积较大，可提高存储电容C的存储性能。在一个示例中，如图3所示，第一极片C1覆盖整个驱动区91。
同时，在至少部分第一极、第二极对应的连接过孔2处，第一极片C1具有开口C11，从而第一极片C1与这些连接过孔2不交叠或交叠面积较小，故可降低第一极片C1在连接过孔2处发生短路的概率，提高产品质量。
可选的，该显示基板还包括基底5。开口C11在基底5上的正投影覆盖其对应的连接过孔2在基底5上的正投影。进一步的，开口C11在基底5上的正投影的面积大于其对应的连接过孔2在基底5上的正投影的面积，并进一步使得开口C11在基底5上的正投影的面积大于连接过孔2中数据线或电源线等与有源层的接触面积。
参照图3、图5、图6，开口C11优选是完全覆盖其对应的连接过孔2的，从而保证第一极片C1与连接过孔2完全不交叠。进一步的，开口C11更优选超出其对应的连接过孔2，从而更好的避免短路。
可选的，开口C11包括：位于第一极片C1边缘的凹口；和/或，位于第一极片C1内部的通孔。
根据位置的不同，开口C11的具体形式也是不同的，当其位于第一极片C1边缘时，开口C11为从第一极片C1边缘向内凹的凹口(如图中4中左侧的三个开口C11)；而当开口C11位于第一极片C1内部时，其则为贯穿第一极片C1的通孔(如图中4中靠近右侧的开口C11)。
可选的，对应有开口C11的连接过孔2的坡度角α为锐角。进一步的，对应有开口C11的连接过孔2的坡度角α在45度至75度之间。
参照图5，连接过孔2的坡度角α即其侧壁与基底5所在平面间的夹角。其中，至少对应有开口C11的连接过孔2，其坡度角α是锐角，更进一步是45度至75度之间的锐角。
过孔的坡度角α与该过孔形成时的工艺参数有关。当过孔的坡度角α较大时更容易造成过度刻蚀，因此更容易造成在过孔位置形成导线接触层，增加该过孔位置处与不同层的导电层之间发生短路的可能性。
因此，经研究发现，在连接过孔2处使用锐角形式的坡度角α，可进一步降低连接过孔2处发生短路的概率。
可选的，像素晶体管的第一极和第二极同层设置，且位于像素晶体管的有源层远离基底5一侧；第一极片C1位于像素晶体管的有源层靠近基底5一侧。
也就是说，参照图5、图6，像素晶体管的第一极和第二极可位于有源层上方，故它们是通过位于自身下方的连接过孔2与有源层连接的。同时，第一极片C1则位于有源层下方。而这样的第一极片C1与连接过孔2更容易发生短路，故更适于采用本公开实施例的开口C11。
根据本公开实施例的一种方式，第一极片C1与像素电极921电连接，像素电极921为发光器件L的第一电极，发光器件L的第二电极连接第二电源线VSS。像素晶体管包括开关晶体管T1和驱动晶体管T2。其中，开关晶体管的栅极T13连接栅线GATE，第一极T11连接数据线DATA，第二极T12电连接驱动晶体管的栅极T23。驱动晶体管的第一极T21连接第一电源线VDD，第二极连接像素电极921。
可选的，发光器件L为有机发光二极管。
也就是说，参照图3，像素电路具体可为通过开关晶体管T1控制数据电压的写入，并通过控制驱动晶体管的栅极T23的电压 控制发光器件L的发光亮度的形式，此时发光器件L可为有机发光二极管(OLED)，其第一电极(像素电极921)可为阴极或阳极中的一者，第二电极为另一者。
应当理解，图3中示出的是以上像素电路的最基本的形式(2T1C)，即像素电路至少包括开关晶体管T1和驱动晶体管T2这两个像素晶体管，以及一个存储电容C。但如果像素电路中还包括其它的像素晶体管等结构，也是可行的。
根据以上像素电路，存储电容的两极中，应当有一极与像素电极921电连接(或者说驱动晶体管的第二极T22)，另一极则与开关晶体管的第二极T12(或者说驱动晶体管的栅极T23)电连接。此时，存储电容C的第一极片C1属于与像素电极921电连接的那一极。
可选的，第一极片C1在对应以下至少一个连接过孔2处具有开口C11：开关晶体管的第一极T11的连接过孔2；开关晶体管的第二极T12的连接过孔2；驱动晶体管的第一极T21的连接过孔2。
可见，第一极片C1与开关晶体管的第一极T11和第二极T12，以及与驱动晶体管的第一极T21均不直接连接，因此这三个极T11、T12、T21的电压通常与第一极片C1的电压不同，更容易与第一极片C1发生短路。因此，参照图3，第一极片C1优选在对应这三个极T11、T12、T2的连接过孔2处设有开口C11(当然最更优选是在对应这三个极T11、T12、T2的连接过孔2处同时设有开口C11)。
可选的，作为本公开实施例的一种形式，第一极片C1与驱动晶体管的第二极T22的连接过孔2绝缘交叠。
由于第一极片C1与像素电极921电连接，故其与驱动晶体管的第二极T22也是电连接的，二者的电压理论上应当随时相同，故二者间发生短路的概率较小。因此，可参照图3和图6，第一极片C1在对应驱动晶体管的第二极T22的连接过孔2处没有开口，而是与驱动晶体管的第二极T22的连接过孔2绝缘交叠，以增大第一极片C1的面积。
可选的，作为本公开实施例的另一种形式，第一极片C1在对应驱动晶体管的第二极T22的连接过孔2处具有开口C11。
也就是说，虽然第一极片C1与驱动晶体管的第二极T22发生短路的概率相对较小，但为了更彻底的避免短路，故参照图8，第一极片C1在对应驱动晶体管的第二极T22的连接过孔2处也可具有开口C11。
可选的，存储电容C还包括：与开关晶体管的第二极T12电连接的第二极片C2，第二极片C2与第一极片C1在垂直显示基板的方向上绝缘交叠以形成第一子电容。
参照图6，第一极片C1必须与其它极片交叠才能形成电容，根据以上像素电路，第一极片C1可与第二极片C2交叠，而该第二极片C2与开关晶体管的第二极T12(或者说驱动晶体管的栅极T23)电连接。并且，如图6所示，第二极片C2与像素晶体管的有源层同层设置。
可选的，存储电容C还包括：与第一极片C1电连接的第三极片C3，第三极片C3与第一极片C1不同层设置而与像素晶体管的第一极和第二极同层设置。第三极片C3与第二极片C2绝缘交叠形成第二子电容。
在本实施例中，可增设与第一极片C1不同层设置的第三极片C3，该第三极片C3与第一极片C1电连接，故从电学上第一极片C1与第三极片C3的电压相同。同时，参照图7，沿垂直显示基板的方向上，第三极片C3与第一极片C1分别位于第二极片C2电的两侧并与其交叠，故可在不增大存储电容C总面积的情况下，提高其电容值。
可选的，对应有开口C11的连接过孔2处的有源层的边界角β为锐角。
如图6所示，有源层的边界角β是指有源层的侧壁与基底5所在平面间的夹角。
如图6所示，基于同样的原因，有源层的边界角β的角度较大也容易造成过度刻蚀，增加不同层的导电层之间发生短路的可 能性，故有源层(如开关晶体管的有源层T14和驱动晶体管的有源层T24)至少在对应有开口C11的连接过孔2附近的刻蚀边界角β为锐角(当然，基于工艺的原因，同一个有源层在各位置的边界角β通常是相同的)。
进一步的，对应有开口C11的连接过孔2的坡度角α为锐角；且满足(α+β)/2＞min(α，β)＞1/4α，其中坡度角α和边界角β是同一个对应有开口C11的连接过孔2处的相应角度。
参照图6，同一个对应有开口C11的连接过孔2(如驱动晶体管的第一极T21对应的连接过孔2)处，连接过孔2的坡度角α和有源层(如驱动晶体管的有源层T24)的边界角β均为锐角，且满足以上的公式(α+β)/2＞min(α，β)＞1/4α，如此可以保持刻蚀速率较快且满足降低连接过孔2位置处层间短路的可能性的要求。
当然，应当理解，参照图5至图7，以上显示基板中，还可包括其它已知的结构。例如，发光器件L的发光层和第二电极(图中未示出)、隔绝开关晶体管的栅极T13与第一极片C1的第一绝缘层61、隔绝开关晶体管的栅极T13与有源层T14(也包括驱动晶体管的有源层T24)的第二绝缘层62、隔绝各有源层与各第一极/各第二极的第三绝缘层63、隔绝各第一极/各第二极与像素电极921的第四绝缘层64等。
当然，应当理解，参照图5至图7，以上显示基板中的部分不同结构可同层设置。例如，栅线GATE可与开关晶体管的栅极T13同层设置，第二极片C2可与各有源层同层设置(第二极片C2可进行导体化处理)，第三极片C3、各第一极/各第二极、数据线DATA、第一电源线VDD等可同层设置等。
当然，应当理解，以上显示基板中，两个结构若电连接，则可通过不同的方式实现：
第一种方式，参照图5至图7，若两个结构不同层设置，则可通过过孔电连接。例如，开关晶体管的第二极T12可通过过孔与第二极片C2电连接，且参照图3，第一极片C1在该过孔处还 可设有开口C11；再如，第三极片C3可通过过孔连接第一极片C1，像素电极921可通过过孔连接第三极片C3，从而实现第一极片C1、第三极片C3、像素电极921三者的相互电连接。
第二种方式，参照图5至图7，若两个结构同层设置，则它们可直接连为一体。例如，开关晶体管的第二极T12可直接与驱动晶体管的栅极T23连为一体；再如，驱动晶体管的第二极T22可直接与第三极片C3连为一体，从而最终实现驱动晶体管的第二极T22、第一极片C1、第三极片C3、像素电极921四者的相互电连接。
当然，应当理解，虽然以上以一种具体的像素电路(有机发光二极管像素电路)为例进行了介绍，但本公开实施例也适用于其它像素电路，如用于液晶显示(LCD)的像素电路等，在此不再详细描述。
参照图1至图8，根据本公开的一个方面，还提供一种上述显示基板的制备方法。该显示基板的每个像素区包括设有像素电极的显示区和设有像素电路的驱动区。像素电路包括至少一个像素晶体管。像素晶体管的第一极和第二极分别通过连接过孔与其有源层相连。存储电容的第一极片位于驱动区中，第一极片与像素晶体管的第一极和第二极在垂直于显示基板的方向上绝缘交叠，且第一极片在对应至少部分连接过孔处具有开口。
具体的，对参照图3所示的显示基板，如图9所示，其制备方法可包括以下步骤。
S301、通过构图工艺在基底上形成第一极片C1。该第一极片C1与待形成的像素晶体管的第一极和第二极在垂直于显示基板的方向上绝缘交叠，且第一极片在至少部分连接过孔处具有开口。
S302、通过构图工艺第一极片C1和暴露的基底上形成第一绝缘层61。
S303、通过构图工艺在第一绝缘层61上形成开关晶体管的栅极T13和与栅极T13连接的栅线GATE。
S304、通过构图工艺在开关晶体管的栅极T13和栅线GATE 上形成第二绝缘层62。
S305、通过构图工艺在第二绝缘层62上形成开关晶体管的有源层T14、驱动晶体管的有源层T24和第二极片C2。其中，第二极片C2与第一极片C1在垂直基底的方向上绝缘交叠以形成第一子电容。其中，可采用同一工艺形成第二极片C2和各晶体管的有源层，即可采用相同材料(如多晶硅)制备第二极片C2和各晶体管的有源层，并且单独对第二极片C2进行离子掺杂以增加其导电性。
S306、通过构图工艺在开关晶体管的有源层T14、驱动晶体管的有源层T24和第二极片C2上形成第三绝缘层63。
S307、通过构图工艺在第三绝缘层63上形成开关晶体管的第一极T11、开关晶体管的第二极T12、驱动晶体管的第一极T21、驱动晶体管的第二极T22、驱动晶体管的栅极T23、数据线DATA、第一电源线VDD和第三极片C3。其中，第三极片C3与第一极片C1通过连接过孔连接，并且与驱动晶体管的第二极T22连接。第二极片C2与第三极片C3在垂直于基底的方向上绝缘交叠以形成第二子电容。开关晶体管的第二极T12与驱动晶体管的栅极T23连接。开关晶体管的第一极T11与数据线DATA连接。驱动晶体管的第一极T21与第一电源线VDD连接。
S308、通过构图工艺在开关晶体管的第一极T11、开关晶体管的第二极T12、驱动晶体管的第一极T21、驱动晶体管的第二极T22、驱动晶体管的栅极T23、数据线DATA、第一电源线VDD、第二电源线VSS和第三极片C3上形成第四绝缘层64。
S309、通过构图工艺在第四绝缘层64上形成像素电极921(第一电极)。该像素电极921通过连接过孔与第三极片C3连接。
S310、通过构图工艺在像素电极921上形成发光层。
S311、通过构图工艺在发光层上形成第二电极。该第二电极与第二电源线VSS通过连接过孔连接。
上述方法以开关晶体管为底栅型，驱动晶体管为顶栅型为例进行说明，但本公开不限于此。
根据本公开的一个方面，提供了一种显示装置，其包括上述的显示基板。
具体的，该显示装置可为液晶显示面板(LCD)、有机发光二极管(OLED)显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (20)

  1. 一种显示基板，包括多个像素区，每个像素区包括设有发光器件的显示区和设有像素电路的驱动区，所述像素电路包括至少一个像素晶体管，所述至少一个像素晶体管的第一极和第二极分别通过连接过孔与其有源层相连，其中，
    所述驱动区中还设有存储电容的第一极片，所述第一极片与所述至少一个像素晶体管的第一极和第二极在垂直于所述显示基板的方向上绝缘交叠，且所述第一极片在对应至少部分所述连接过孔处具有开口。
  2. 根据权利要求1所述的显示基板，其中，在一个所述像素区中，所述第一极片与所述发光器件的第一电极连接，所述发光器件的第二电极连接第二电源线；
    所述至少一个像素晶体管包括开关晶体管和驱动晶体管；其中，
    所述开关晶体管的栅极连接栅线，第一极连接数据线，第二极电连接驱动晶体管的栅极；
    所述驱动晶体管的第一极连接第一电源线，第二极连接像素电极。
  3. 根据权利要求2所述的显示基板，其中，所述第一极片在对应以下至少一个连接过孔处具有开口：
    所述开关晶体管的第一极的连接过孔；
    所述开关晶体管的第二极的连接过孔；
    所述驱动晶体管的第一极的连接过孔。
  4. 根据权利要求3所述的显示基板，其中，
    所述第一极片与所述驱动晶体管的第二极的连接过孔在垂直于所述显示基板的方向上绝缘交叠，并且
    所述第一极片在对应驱动晶体管的第二极的连接过孔处具有开口。
  5. 根据权利要求3所述的显示基板，其中，
    所述第一极片与所述驱动晶体管的第二极的连接过孔在垂直于所述显示基板的方向上绝缘交叠，并且
    所述第一极片与对应驱动晶体管的第二极的连接过孔处不具有开口。
  6. 根据权利要求1-5中任一项所述的显示基板，其中，所述存储电容还包括：
    与所述开关晶体管的第二极电连接的第二极片；
    所述第二极片与所述第一极片在垂直于所述显示基板的方向上绝缘交叠以形成第一子电容。
  7. 根据权利要求6所述的显示基板，其中，所述第二极片与所述像素晶体管的有源层同层设置。
  8. 根据权利要求7所述的显示基板，其中，所述存储电容还包括：与所述第一极片电连接的第三极片，
    所述第三极片与所述像素晶体管的第一极和第二极同层设置，并与所述第二极片绝缘交叠以形成第二子电容。
  9. 根据权利要求2所述的显示基板，其中，
    所述发光器件为有机发光二极管。
  10. 根据权利要求1至9中任意一项所述的显示基板，还包括基底：
    所述像素晶体管的第一极和第二极位于所述像素晶体管的有源层远离基底的一侧；
    所述第一极片位于所述像素晶体管的有源层靠近基底的一侧。
  11. 根据权利要求10所述的显示基板，其中，
    所述开口在所述基底上的正投影覆盖其对应的连接过孔在所述基底上的正投影。
  12. 根据权利要求11所述的显示基板，其中，
    所述开口在所述基底上的正投影的面积大于或等于其对应的连接过孔在所述基底上的正投影的面积。
  13. 根据权利要求1至12中任意一项所述的显示基板，其中，
    对应有开口的连接过孔的坡度角为锐角，所述坡度角为所述连接过孔的侧壁与所述显示基板所在平面之间的夹角。
  14. 根据权利要求13所述的显示基板，其中，
    对应有开口的连接过孔的坡度角在45度至75度之间。
  15. 根据权利要求1至14中任意一项所述的显示基板，其中，
    对应有开口的连接过孔处的有源层的边界角为锐角，所述边界角为所述有源层的侧壁与所述显示基板所在平面之间的夹角。
  16. 根据权利要求1至12中任意一项所述的显示基板，其中，
    对应有开口的连接过孔的坡度角为锐角；
    且(α+β)/2＞min(α，β)＞1/4α，其中α为对应有开口的任意连接过孔的坡度角，β为该连接过孔处的有源层的边界角，所述坡度角为所述连接过孔的侧壁与所述显示基板所在平面之间的夹角，所述边界角为所述有源层的侧壁与所述显示基板所在平面之间的夹角。
  17. 根据权利要求1至16中任意一项所述的显示基板，其中，所述开口包括：
    位于所述第一极片边缘的凹口；
    和/或，
    位于所述第一极片内部的通孔。
  18. 一种显示装置，包括：
    权利要求1至17中任意一项所述的显示基板。
  19. 一种用于制作显示基板的方法，包括：
    提供基底；
    在所述基底上形成存储电容和至少一个像素晶体管，其中，
    所述显示基板包括多个像素区，每个像素区包括设有像素电极的显示区和设有像素电路的驱动区，所述像素电路包括所述至少一个像素晶体管，所述像素晶体管的第一极和第二极分别通过连接过孔与其有源层相连，其中，
    所述存储电容的第一极片位于所述驱动区中，所述第一极片与所述像素晶体管的第一极和第二极在垂直于所述显示基板的方向上绝缘交叠，且所述第一极片在至少部分连接过孔处具有开口。
  20. 根据权利要求19所述的方法，其中，在所述基底上形成存储电容和至少一个像素晶体管包括：
    在所述基底上形成存储电容的第一极片；
    在所述第一极片上形成第一绝缘层；
    在所述第一绝缘层上形成开关晶体管的栅极及栅线；
    在所述开关晶体管的栅极及所述栅线上形成第二绝缘层；
    在所述第二绝缘层上形成所述开关晶体管的有源层、驱动晶体管的有源层和存储电容的第二极片，其中，所述第二极片与所述第一极片在垂直所述基底的方向上绝缘交叠以形成第一子电容；
    在所述开关晶体管的有源层、驱动晶体管的有源层和存储电容的第二极片上形成第三绝缘层；以及
    在所述第三绝缘层上形成开关晶体管的第一极、开关晶体管的第二极、驱动晶体管的第一极、驱动晶体管的第二极、驱动晶体管的栅极、数据线、第一电极线和第三极片，其中，所述第三极片与所述第一极片通过连接过孔连接并且与所述驱动晶体管的第二极连接，所述第二极片与所述第三极片在垂直于所述基底的方向上绝缘交叠以形成第二子电容。
PCT/CN2020/106204 2019-08-05 2020-07-31 显示基板及其制作方法、显示装置 WO2021023107A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP20850140.3A EP4012773A4 (en) 2019-08-05 2020-07-31 DISPLAY SUBSTRATE AND METHOD FOR MAKING IT AND DISPLAY APPARATUS
JP2021537179A JP2022543714A (ja) 2019-08-05 2020-07-31 表示基板及びその製造方法、表示装置
US17/276,282 US11991906B2 (en) 2019-08-05 2020-07-31 Display substrate and manufacturing method thereof, display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201921258054.2U CN209912874U (zh) 2019-08-05 2019-08-05 显示基板、显示装置
CN201921258054.2 2019-08-05

Publications (1)

Publication Number Publication Date
WO2021023107A1 true WO2021023107A1 (zh) 2021-02-11

Family

ID=69051197

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/106204 WO2021023107A1 (zh) 2019-08-05 2020-07-31 显示基板及其制作方法、显示装置

Country Status (5)

Country Link
US (1) US11991906B2 (zh)
EP (1) EP4012773A4 (zh)
JP (1) JP2022543714A (zh)
CN (1) CN209912874U (zh)
WO (1) WO2021023107A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN209912874U (zh) * 2019-08-05 2020-01-07 北京京东方技术开发有限公司 显示基板、显示装置
CN114556579A (zh) 2020-09-10 2022-05-27 京东方科技集团股份有限公司 显示基板和显示面板
DE112021003516T5 (de) * 2021-01-28 2023-05-17 Boe Technology Group Co., Ltd. Arraysubstrat und anzeigevorrichtung
WO2023283768A1 (zh) * 2021-07-12 2023-01-19 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2214207A2 (en) * 2007-10-17 2010-08-04 Ricoh Company, Ltd. Active matrix substrate and electronic display device
CN101800195A (zh) * 2009-02-10 2010-08-11 索尼公司 显示器件的制造方法和显示器件
CN104733499A (zh) * 2013-12-23 2015-06-24 乐金显示有限公司 有机发光二极管显示装置及其制造方法
CN107680993A (zh) * 2017-10-23 2018-02-09 深圳市华星光电半导体显示技术有限公司 Oled面板及其制作方法
CN107785404A (zh) * 2017-10-31 2018-03-09 京东方科技集团股份有限公司 显示背板及其制作方法、显示面板和显示装置
CN209912874U (zh) * 2019-08-05 2020-01-07 北京京东方技术开发有限公司 显示基板、显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7105999B2 (en) * 2002-07-05 2006-09-12 Lg.Philips Lcd Co., Ltd. Organic electroluminescent display device and method of fabricating the same
KR100500147B1 (ko) * 2002-12-31 2005-07-07 엘지.필립스 엘시디 주식회사 유기전계 발광소자와 그 제조방법
KR101434366B1 (ko) * 2012-08-24 2014-08-26 삼성디스플레이 주식회사 박막 트랜지스터 어레이 기판, 이를 포함하는 표시 장치
KR102038076B1 (ko) 2013-04-04 2019-10-30 삼성디스플레이 주식회사 유기 발광 표시 장치
KR102556020B1 (ko) * 2018-01-31 2023-07-17 삼성디스플레이 주식회사 박막트랜지스터 어레이 기판 및 유기발광표시장치

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2214207A2 (en) * 2007-10-17 2010-08-04 Ricoh Company, Ltd. Active matrix substrate and electronic display device
CN101800195A (zh) * 2009-02-10 2010-08-11 索尼公司 显示器件的制造方法和显示器件
CN104733499A (zh) * 2013-12-23 2015-06-24 乐金显示有限公司 有机发光二极管显示装置及其制造方法
CN107680993A (zh) * 2017-10-23 2018-02-09 深圳市华星光电半导体显示技术有限公司 Oled面板及其制作方法
CN107785404A (zh) * 2017-10-31 2018-03-09 京东方科技集团股份有限公司 显示背板及其制作方法、显示面板和显示装置
CN209912874U (zh) * 2019-08-05 2020-01-07 北京京东方技术开发有限公司 显示基板、显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4012773A4 *

Also Published As

Publication number Publication date
US20220037448A1 (en) 2022-02-03
EP4012773A1 (en) 2022-06-15
US11991906B2 (en) 2024-05-21
JP2022543714A (ja) 2022-10-14
CN209912874U (zh) 2020-01-07
EP4012773A4 (en) 2022-10-12

Similar Documents

Publication Publication Date Title
WO2021023107A1 (zh) 显示基板及其制作方法、显示装置
WO2018205651A1 (zh) Oled触控显示面板及其制作方法、触控显示装置
US20200212153A1 (en) Array substrate, manufacturing method thereof, and display apparatus
WO2021139660A1 (zh) 显示基板、其制作方法及显示面板、显示装置
US11257957B2 (en) Thin film transistor, method of fabricating the same, array substrate and display device
CN106981520B (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
WO2020207466A1 (zh) 阵列基板及其制造方法、显示面板及显示装置
US20170250236A1 (en) Display panel, fabrication method and electronic device
WO2015043268A1 (zh) 阵列基板及其制备方法、和显示装置
JP2014220483A (ja) 薄膜トランジスタアレイ基板及びその製造方法
TWI606283B (zh) 顯示裝置
US11508803B2 (en) Array substrate, display panel and display device
US10355064B2 (en) AMOLED display substrate, method for fabricating the same and display device
US11043545B2 (en) Display substrate, fabricating method thereof, and display device
US9450103B2 (en) Thin film transistor, method for manufacturing the same, display device and electronic product
EP3236499B1 (en) Array substrate and manufacturing method therefor, and display device
US20220037615A1 (en) Display substrate, manufacturing method thereof and display panel
US20240023388A1 (en) Display panel and electronic device
CN103681514B (zh) 阵列基板及其制作方法、显示装置
WO2021114368A1 (zh) 显示面板及其制备方法
US11107413B2 (en) Display substrate and method for manufacturing the same, display device
US20150270297A1 (en) Half tone mask plate, array substrate and method for manufacturing the same, display apparatus
WO2021081814A1 (zh) 阵列基板和显示装置
WO2021027140A1 (zh) 阵列基板及其制作方法
US11705461B2 (en) Display substrate, manufacturing method thereof, display panel and display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20850140

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021537179

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2020850140

Country of ref document: EP

Effective date: 20220307