WO2021018057A1 - 基站多通道相位同步装置、方法及基站 - Google Patents

基站多通道相位同步装置、方法及基站 Download PDF

Info

Publication number
WO2021018057A1
WO2021018057A1 PCT/CN2020/104644 CN2020104644W WO2021018057A1 WO 2021018057 A1 WO2021018057 A1 WO 2021018057A1 CN 2020104644 W CN2020104644 W CN 2020104644W WO 2021018057 A1 WO2021018057 A1 WO 2021018057A1
Authority
WO
WIPO (PCT)
Prior art keywords
channel
phase
base station
phase difference
calibration
Prior art date
Application number
PCT/CN2020/104644
Other languages
English (en)
French (fr)
Inventor
段沛
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Priority to KR1020217043089A priority Critical patent/KR102656996B1/ko
Priority to JP2021578150A priority patent/JP7399196B2/ja
Publication of WO2021018057A1 publication Critical patent/WO2021018057A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H04W56/004—Synchronisation arrangements compensating for timing error of reception due to propagation delay
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/20—Monitoring; Testing of receivers
    • H04B17/21—Monitoring; Testing of receivers for calibration; for correcting measurements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H04W56/0035—Synchronisation arrangements detecting errors in frequency or phase
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
    • H04W88/08—Access point devices

Definitions

  • the present disclosure relates to the field of communication technology, and in particular to a base station multi-channel phase synchronization device, method and base station.
  • MIMO multiple-input multiple-output
  • beamforming technologies require precise control of the phase and amplitude of the array unit.
  • the technical problem to be solved by the present disclosure is to solve the problem of base station multi-channel phase synchronization.
  • the present disclosure provides a base station multi-channel phase synchronization device, method and base station.
  • the base station multi-channel phase synchronization device includes: multiple channels, each of which is provided with a local oscillator circuit for generating a local oscillator signal; a clock circuit, the clock circuit and each of the channels Both are connected to provide a clock signal for each of the channels; a calibration circuit is configured to obtain the phase difference of each channel relative to the reference channel, and perform phase calibration on each of the channels based on the phase difference.
  • each channel is separately provided with a local oscillator circuit, and all channels share a synchronization clock.
  • the phases of each channel are synchronized to a certain extent through a common clock reference.
  • it can make the system wiring more convenient and flexible.
  • the clock signal frequency is low and the insertion loss is small, there is no need to set up an amplifier, and there is no need to consider the influence of stray too much, which effectively simplifies the structure of the base station and solves the problem of base station multi-channel phase synchronization.
  • by performing real-time phase calibration on each channel it can be ensured that the performance of phase synchronization is not affected after the simplified hardware.
  • the base station multi-channel phase synchronization method uses the above-mentioned base station multi-channel phase synchronization device to perform multi-channel phase synchronization, and the method includes: obtaining the relative reference of each channel of the base station Phase difference of the channels; phase calibration is performed on each of the channels based on the phase difference.
  • each channel is separately provided with a local oscillator circuit, and all channels share a synchronization clock.
  • the phases of each channel are synchronized to a certain extent through a common clock reference. Therefore, the system wiring can be more convenient and flexible.
  • the clock signal frequency is low and the insertion loss is small, there is no need to set up an amplifier, and there is no need to consider the influence of stray too much, which effectively simplifies the structure of the base station and solves the problem of base station multi-channel phase synchronization.
  • by performing real-time phase calibration on each channel it can be ensured that the performance of phase synchronization is not affected after the simplified hardware.
  • the base station according to the embodiment of the present disclosure includes a multi-channel phase synchronization device, and the multi-channel phase synchronization device is the aforementioned base station multi-channel phase synchronization device.
  • each channel is provided with a separate local oscillator circuit, and each channel shares a synchronous clock.
  • FIG. 1 is a system schematic diagram of the CCP local oscillator solution in related technologies
  • Figure 2 is a system phase difference analysis diagram of a common local oscillator scheme in related technologies
  • FIG. 3 is a system schematic diagram of a common clock solution according to an embodiment of the present disclosure.
  • FIG. 4 is a system phase difference analysis diagram of a common clock scheme according to an embodiment of the present disclosure.
  • Fig. 5 is a flowchart of a method for base station multi-channel phase synchronization according to an embodiment of the present disclosure
  • FIG. 6 is a flowchart of a method for obtaining the phase difference of each channel of a base station relative to a reference channel according to an embodiment of the present disclosure
  • Fig. 7 is a flowchart of a method for multi-channel phase synchronization of a base station according to an embodiment of the present disclosure
  • FIG. 8 is a flowchart of a method for multi-channel phase synchronization of a base station according to an embodiment of the present disclosure
  • Figure 9 is a schematic diagram of an example of a reference system in related technologies.
  • FIG. 10 is a schematic diagram of a common clock reference example according to an embodiment of the present disclosure.
  • the base station system of the common local oscillator solution is composed of the same clock generator 122, PLL (local oscillator generator) 101, local oscillator distributor 102 and amplifier circuits 103, 109, and 114.
  • the biggest feature of the common local oscillator scheme is that the local oscillator signals of all the transceiver channels of the whole machine come from the same local oscillator generator 101, which can ensure that the phase of reaching the mixer of each channel is the same, as long as the phase of the baseband signal Consistent, in this way, it can be ensured that the transmission phases of the N channels TX1 to N are the same.
  • the common local oscillator solution requires calibration. This is because the printed circuit board (PCB) wiring and connectors of each channel of the local oscillator distributor will introduce a fixed phase difference, which needs to be calibrated in the baseband. make up. Since the phase difference of the common local oscillator scheme changes very little with time, the calibration of the common local oscillator is very simple. After the initial calibration, the calibration can be performed every few hours.
  • PCB printed circuit board
  • the common local oscillator solution requires the same PLL (local oscillator generator) to provide the local oscillator signal to the N-channel transceiver link, so that the level of the local oscillator signal is reduced when it reaches each channel, plus the local oscillator
  • the signal frequency is high, the PCB loss is large, and an amplifying circuit needs to be added. This will add additional chip area to the system, and increase power consumption and cost.
  • the frequency of the local oscillator signal is relatively high, and the local oscillator distribution wiring can easily introduce spurs to the system, which brings uncertain risks to the system. With the continuous increase of the number of system array units and the increase of the number of channels, it is almost difficult to solve the problems of local oscillator distribution and wiring and area of 64-channel or 128-channel complete machines.
  • the base station multi-channel phase synchronization device includes: multiple channels, a clock circuit, and a calibration circuit.
  • the base station has multiple channels, and each channel is provided with a local oscillator circuit for generating a local oscillator signal.
  • the clock circuit is connected to each channel to provide a clock signal for each channel.
  • the calibration circuit is set to obtain the phase difference of each channel relative to the reference channel, and perform phase calibration on each channel based on the phase difference.
  • each channel is separately provided with a local oscillator circuit, and all channels share a synchronization clock.
  • the phases of each channel are synchronized to a certain extent through a common clock reference. Therefore, the system wiring can be more convenient and flexible.
  • the clock signal frequency is low and the insertion loss is small, there is no need to set up an amplifier, and there is no need to consider the influence of stray too much, which effectively simplifies the structure of the base station and solves the problem of base station multi-channel phase synchronization.
  • by performing real-time phase calibration on each channel it can be ensured that the performance of phase synchronization is not affected after the simplified hardware.
  • the calibration circuit includes an acquisition module and a calibration module.
  • the acquiring module is configured to acquire the phase difference of each channel of the base station relative to the reference channel
  • the calibration module is set to perform phase calibration on each channel based on the phase difference
  • each channel is separately provided with a local oscillator circuit, and each channel shares the same clock circuit, which defines this disclosure as a common clock reference solution.
  • the acquiring module is specifically configured as:
  • One of the multiple channels is selected as the reference channel, and the phase difference of the remaining channels compared to the reference channel is calculated based on the calibration signal.
  • the digital baseband processing unit 208 can send a special calibration signal to each channel, and the calibration signal returns from the calibration channel 226 to the digital baseband processing unit 208 through each channel. Select one channel from multiple channels as the reference channel, and use the reference channel as the benchmark to calculate the phase difference of the remaining channels relative to the reference channel.
  • the digital baseband processing unit 208 can perform phase compensation on each channel according to the phase difference, so that the phases of all channels are aligned with the reference channel.
  • the phase difference may include: the local oscillator phase difference and the wiring phase difference of each channel.
  • the local oscillator phase difference may include: voltage-controlled oscillator phase difference, frequency divider phase difference and phase detector phase difference
  • the wiring phase difference may include: local oscillator wiring phase difference and clock wiring phase difference
  • phase fluctuation includes ⁇ pll, ⁇ clkpath, and ⁇ LO_path.
  • ⁇ clkpath and ⁇ LO_path belong to the phase difference introduced by the trace.
  • phase compensation can be performed on each channel based on the phase difference, so that the phases of all channels are aligned with the reference channel.
  • the device further includes a judgment module, and the judgment module is set to:
  • the acquisition module is triggered to acquire the phase difference of each channel of the base station relative to the reference channel.
  • the preset phase calibration condition is: the system temperature change of the base station exceeds the preset temperature; and/or the preset calibration time is reached.
  • phase calibration compensation is performed on each channel.
  • the phase fluctuation includes ⁇ pll, ⁇ clkpath, and ⁇ LO_path. Although these phase differences are fixed, under temperature changes, the phase differences will fluctuate. Therefore, after the calibration of the common reference scheme, although the phases of the channels are aligned, if there is a large temperature change, it is caused by ⁇ clkpath and ⁇ LO_path If the phase difference changes too much, the phase difference between the channels may exceed the corresponding requirements and affect the flow.
  • the length of the local oscillator trace of the local oscillator circuit on each channel is the same. It is understandable that by setting the length of the local oscillator circuit of the local oscillator circuit on each channel to be the same, the phase fluctuation ⁇ pll existing in the different PLL output phases on each channel can be reduced, thereby helping to improve the phase consistency of each channel .
  • the length of the clock trace connected to each of the channels of the clock circuit is the same. It is understandable that by setting the length of the clock traces of the clock circuit connected to each of the channels to be the same, the phase difference ⁇ clkpath of the clock traces introduced by the traces between the clock circuit (CLK) and the PLL can be reduced, thereby helping to improve The phase consistency of each channel.
  • the base station multi-channel phase synchronization method uses the above-mentioned base station multi-channel phase synchronization device to perform multi-channel phase synchronization.
  • the method includes:
  • each channel is separately provided with a local oscillator circuit, and all channels share a synchronization clock.
  • the phases of each channel are synchronized to a certain extent through a common clock reference. Therefore, the system wiring can be more convenient and flexible.
  • the clock signal frequency is low and the insertion loss is small, there is no need to set up an amplifier, and there is no need to consider the influence of stray too much, which effectively simplifies the structure of the base station and solves the problem of base station multi-channel phase synchronization.
  • by performing real-time phase calibration on each channel it can be ensured that the performance of phase synchronization is not affected after the simplified hardware.
  • acquiring the phase difference of each channel of the base station relative to the reference channel includes:
  • the digital baseband processing unit 208 can send a special calibration signal to each channel, and the calibration signal returns from the calibration channel 226 to the digital baseband processing unit 208 through each channel.
  • S202 Select one of the multiple channels as a reference channel, and calculate the phase difference of the remaining channels relative to the reference channel based on the calibration signal.
  • one channel is selected from multiple channels as the reference channel, and the reference channel is used as a reference to calculate the phase difference of the remaining channels relative to the reference channel.
  • the digital baseband processing unit 208 can perform phase compensation on each channel according to the phase difference, so that the phases of all channels are aligned with the reference channel.
  • the phase difference may include: the local oscillator phase difference and the wiring phase difference of each channel.
  • the local oscillator phase difference may include: voltage-controlled oscillator phase difference, frequency divider phase difference and phase detector phase difference
  • the wiring phase difference may include: local oscillator wiring phase difference and clock wiring phase difference
  • the PLL local oscillator generator
  • VCO voltage controlled oscillator
  • phase detector phase detector
  • These noise components cause the phase of the PLL (local oscillator generator) to deviate from the phase of the reference clock. Therefore, different PLL output phases will have phase fluctuations ⁇ pll.
  • the trace between the clock circuit (CLK) and the PLL will introduce ⁇ clkpath, and the trace of the local oscillator circuit will introduce ⁇ LO_path. That is to say, in the common reference scheme adopted in the present disclosure, the phase fluctuation includes ⁇ pll, ⁇ clkpath, and ⁇ LO_path.
  • ⁇ clkpath and ⁇ LO_path belong to the phase difference introduced by the trace.
  • the length, thickness, material, and corners of the PCB trace will introduce phase difference, and the adapter, length, and material of the coaxial cable will also be introduced. Phase difference.
  • phase compensation can be performed on each channel based on the phase difference, so that the phases of all channels are aligned with the reference channel.
  • the method further includes:
  • the preset phase calibration condition is: the system temperature change of the base station exceeds the preset temperature; and/or the preset calibration time is reached.
  • phase calibration compensation is performed on each channel.
  • the phase fluctuation includes ⁇ pll, ⁇ clkpath, and ⁇ LO_path. Although these phase differences are fixed, under temperature changes, the phase differences will fluctuate. Therefore, after the calibration of the common reference scheme, although the phases of the channels are aligned, if there is a large temperature change, it is caused by ⁇ clkpath and ⁇ LO_path If the phase difference changes too much, the phase difference between the channels may exceed the corresponding requirements and affect the flow.
  • the factors that trigger the calibration and compensation of each channel are time and temperature. If the temperature change of the whole machine exceeds a certain range or a certain period of time has passed, the phase calibration compensation is started. According to the operator's requirement that the phase error is within 5°, the temperature change of the whole machine can be set to exceed 10°C, and the time change for half an hour is the calibration trigger condition. As shown in Figure 8, the initialization calibration is performed after the system is powered on. When the base station is working, the system CPU will read back the temperature of the whole machine. If the temperature changes more than 10°C, perform a phase calibration. At the same time, if half an hour has passed since the last phase calibration, the system will perform a phase calibration. As a result, it can be ensured that the base station system traffic of the common reference scheme is normal.
  • the signal is coupled from the antenna port into the N-way combiner, and then enters the baseband after the calibration channel.
  • the digital baseband processing unit 208 calculates the phase difference ⁇ PhaseN between the N channel and the reference channel, and then the baseband signal In the phase compensation ⁇ CalN. Make the phase difference between the compensated N channel and the reference channel 0, where,
  • the common clock reference solution of the present disclosure can meet the phase requirements of Massive and beamforming in 5G base stations, while the layout is more flexible, small in size, and can reduce cost and power consumption, and is suitable for multi-channel (64 or 128) beamforming .
  • FIG. 10 shows a circuit example of a transceiver system using a common clock reference scheme.
  • FIG. 9 shows a circuit example of the transceiver system of the N-channel common local oscillator solution (related technical solution).
  • the system in Figure 10 uses a 2T2R transceiver integrated chip, with a total of N transmitting channels and N receiving channels.
  • the same clock chip provides reference for N/2 integrated chips, and the two channels in each integrated chip share the local oscillator.
  • One of the N receiving channels is selected as the transmit phase calibration channel (this can save the number of analog channels), and the N channels enter the calibration channel through the combiner (the N channels can be calibrated at the same time, which can improve the calibration efficiency), thus completing the emission calibration .
  • Select one transmitting channel as the receiving phase calibration channel, and pass the calibration channel to each receiving channel through the combiner to complete the calibration of the receiving channel.
  • the length of the clock wiring, RF wiring, and cables must be as consistent as possible.
  • the common reference scheme adopted by the present disclosure has low risk and fewer strays.
  • the number of chips, cost, power consumption, and area are all smaller than the common local oscillator scheme system adopted in related technologies.
  • at least one PLL chip and N-channel amplifier can be saved And N/4 power dividers. In addition, it can also reduce the waste of the internal PLL of the transceiver and the RF sampling chip.
  • the common reference scheme adopted in this application and the common local oscillator scheme adopted in related technologies will have requirements for wiring. Although the common reference scheme will increase the difficulty of clock wiring, the common local oscillator scheme will increase the complexity of local oscillator wiring. . Since the local oscillator signal has a higher frequency than the clock signal, in general, the common reference has low wiring requirements.
  • the base station includes: a multi-channel phase synchronization device, and the multi-channel phase synchronization device is the aforementioned base station multi-channel phase synchronization device.
  • each channel is provided with a local oscillator circuit for generating a local oscillator signal.
  • the clock circuit is connected to each channel to provide a clock signal for each channel.
  • the calibration circuit is used to obtain the phase difference of each channel relative to the reference channel, and perform phase calibration on each channel based on the phase difference.
  • the base station of the common clock reference scheme adopted by the present disclosure is composed of three parts: a clock generation and distribution circuit, a transceiver circuit, and system phase calibration.
  • the clock generation and distribution circuit mainly includes a clock generator 224, a clock distributor 225, and wirings 204, 211, and 219 from the clock chip to each channel.
  • the main function of this circuit is to distribute the recovered clock to each channel after filtering the spurious. As long as the phase delays on 204, 211, and 219 are consistent, it can be ensured that the clock reaches the same phase of the local oscillator generator of each channel.
  • the transceiver circuit includes frequency synthesizers 201, 209, and 216 for each channel, local oscillator traces 205, 212, 220, and other devices on the radio frequency transceiver link.
  • Frequency synthesizers 1 to 3 use the clock signal as a reference to generate a local oscillator LO signal, which is mixed with the baseband signal and sent out through the radio frequency link.
  • the phase of the local oscillator signal is consistent with the reference, and the trace is the same as the phase delay of other devices, and the phase of each channel to the antenna is the same.
  • the local oscillator circuit of each channel is relatively independent, and all channels share a synchronous clock. Therefore, the system wiring can be more convenient and flexible. Moreover, because the clock signal frequency is low and the insertion loss is small, there is no need to set up an amplifier, and there is no need to consider the influence of spurious too much, which effectively solves the problem of base station multi-channel phase synchronization, which can meet the phase of Massive and beamforming in 5G base stations. The requirements are applicable to multi-channel (64 or 128) beamforming.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Transceivers (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

本公开提出了一种基站多通道相位同步装置、方法及基站，根据本公开的基站多通道相位同步装置，包括：多条通道、时钟电路和校准电路。每条通道上均设有用于产生本振信号的本振电路，时钟电路与各通道均连接，以为各通道提供时钟信号。校准电路设置为获取各通道相对于参考通道的相位差，基于相位差对各通道进行相位校准。根据本公开的基站多通道相位同步装置，各个通道单独设置本振电路，且所有通道共用一个同步时钟。

Description

基站多通道相位同步装置、方法及基站 技术领域
本公开涉及通信技术领域，尤其涉及一种基站多通道相位同步装置、方法及基站。
背景技术
最新的通信技术对信号相位控制提出了更高的要求，Massive多输入多输出(Multiple-Input Multiple-Output，简称为MIMO)、beamforming技术都要求阵列单元的相位和幅度能够被精确控制。
为了保持通道间相位的同步状态，相关技术中，大多数基站采用的是共本振方案。但是，随着系统阵列单元数量的不断增加，通道数的增加，共本振方案中本振分发和走线不便设计，而且占用PCB面积，导致整机体积增大。
发明内容
本公开要解决的技术问题是解决基站多通道相位同步问题，本公开提供一种基站多通道相位同步装置、方法及基站。
根据本公开实施例的基站多通道相位同步装置，包括：多条通道，每条所述通道上均设有用于产生本振信号的本振电路；时钟电路，所述时钟电路与各所述通道均连接，以为各所述通道提供时钟信号；校准电路，设置为获取各通道相对于参考通道的相位差，基于所述相位差对各所述通道进行相位校准。
根据本公开实施例的基站多通道相位同步装置，各个通道单独设置本振电路，且所有通道共用一个同步时钟。由此，通过共同的时钟参考实现各个通道相位在一定程度上的同步。并且，可以使系统走线更加方便、灵 活。而且，因为时钟信号频率较低，插损小，所以不需要设置放大器，也无需过多考虑杂散的影响，有效简化了基站整机结构并解决了基站多通道相位同步的问题。另外，通过对各通道进行实时相位校准，可以保证简化硬件后相位同步的性能不受影响。
根据本公开实施例的基站多通道相位同步方法，所述基站多通道相位同步方法采用上述所述的基站多通道相位同步装置进行多通道相位同步，所述方法包括：获取基站各通道相对于参考通道的相位差；基于所述相位差对各所述通道进行相位校准。
根据本公开的基站多通道相位同步方法，各个通道单独设置本振电路，且所有通道共用一个同步时钟。由此，通过共同的时钟参考实现各个通道相位在一定程度上的同步。由此，可以使系统走线更加方便、灵活。而且，因为时钟信号频率较低，插损小，所以不需要设置放大器，也无需过多考虑杂散的影响，有效简化了基站整机结构并解决了基站多通道相位同步的问题。另外，通过对各通道进行实时相位校准，可以保证简化硬件后相位同步的性能不受影响。
根据本公开实施例的基站，包括多通道相位同步装置，所述多通道相位同步装置为上述所述的基站多通道相位同步装置。
根据本公开实施例的基站，各个通道均设有单独的本振电路，且各个通道共用一个同步时钟。
附图说明
图1是相关技术中共本振方案的系统示意图；
图2是相关技术中共本振方案的系统相位差分析图；
图3是根据本公开实施例的共时钟方案的系统示意图；
图4是根据本公开实施例的共时钟方案的系统相位差分析图；
图5是根据本公开实施例的基站多通道相位同步方法流程图；
图6是根据本公开实施例的获取基站各通道相对于参考通道的相位差的方法流程图；
图7是根据本公开实施例的基站多通道相位同步方法流程图；
图8是根据本公开实施例的基站多通道相位同步方法流程图；
图9是相关技术中供参考系统实例示意图；
图10是根据本公开实施例的共时钟参考实例示意图。
具体实施方式
为更进一步阐述本公开为达成预定目的所采取的技术手段及功效，以下结合附图及较佳实施例，对本公开进行详细说明如后。
相关技术中，为了保持基站各通道间相位的同步状态，大多数基站采用的是共本振方案，如图1所示。共本振方案的基站系统由同一个时钟发生器122、PLL(本振发生器)101、本振分发器102和放大电路103、109、114组成。
共本振方案最大的特点是整机的所有收发信通道的本振信号均来自同一个本振发生器101，由此可以保证到达每个通道混频器的相位是一样的，只要基带信号相位一致，这样就可以保证N个通道TX1～N发射相位相同。
共本振方案需要校准，这是因为本振分发器各个通道的印刷电路板(Printed Circuit Board，简称为PCB)走线和接头等差异会引入一个固定相位差，需要通过校准后在基带中进行补偿。由于共本振方案相位差随时间变化很小，所以共本振的校准很简单，初始化校准后间隔几个小时校准一次即可。
如图1所示，采用共本振方案需要同一个PLL(本振发生器)给N路收发链路提供本振信号，这样本振信号分发到达各路时电平降低，再加上本振信号频率高、PCB损耗大，需要增加放大电路等，这样会给系统需要 增加额外芯片面积，功耗和成本也会增加。同时本振信号频率比较高，本振分发走线很容易给系统引入杂散，给系统带来不确定的风险。随着系统阵列单元数量的不断增加，通道数的增加，64通道或128通道整机本振分发和走线问题和面积的矛盾几乎难以解决。
如图3所示，根据本公开实施例的基站多通道相位同步装置，包括：多条通道、时钟电路和校准电路。
具体而言，如图3所示，基站具有多条通道，每条通道上均设有用于产生本振信号的本振电路。时钟电路与各通道均连接，以为各通道提供时钟信号。校准电路设置为获取各通道相对于参考通道的相位差，基于相位差对各通道进行相位校准。
根据本公开实施例的基站多通道相位同步装置，各个通道单独设置本振电路，且所有通道共用一个同步时钟。并且，通过共同的时钟参考实现各个通道相位在一定程度上的同步。由此，可以使系统走线更加方便、灵活。而且，因为时钟信号频率较低，插损小，所以不需要设置放大器，也无需过多考虑杂散的影响，有效简化了基站整机结构并解决了基站多通道相位同步的问题。另外，通过对各通道进行实时相位校准，可以保证简化硬件后相位同步的性能不受影响。
根据本公开的一些实施例，校准电路包括获取模块和校准模块。
其中，获取模块设置为获取基站各通道相对于参考通道的相位差；
校准模块设置为基于相位差对各通道进行相位校准；
需要说明的是，本公开中，各个通道的单独设置有本振电路，且各个通道共用同一个时钟电路，定义本公开为共时钟参考方案。
如图6所示，根据本公开的一些实施例，获取模块具体设置为：
向各通道发射校准信号；
选取多个通道中的其中一个通道作为参考通道，并基于校准信号计算其余通道相较于参考通道的相位差。
结合图3所示，数字基带处理单元208可以向各通道发送一个特殊校准信号，校准信号经过各通道从校准通道226返回至数字基带处理单元208。从多个通道中选出一个通道作为参考通道，以参考通道为基准，计算其余通道相对于参考通道的相位差。
由此，数字基带处理单元208可以根据相位差对各通道进行相位补偿，使所有通道相位和参考通道对齐。
在本公开的一些实施例中，相位差可以包括：各通道的本振相位差和走线相位差。
其中，本振相位差可以包括：压控振荡器相位差、分频器相位差和鉴相器相位差，走线相位差可以包括：本振走线相位差和时钟走线相位差。
如图4所示，PLL(本振发生器)会引入相噪，相噪存在于VCO(压控振荡器)，分频器和鉴相器中。这些噪声分量导致PLL(本振发生器)的相位偏离参考时钟的相位。因此，不同PLL输出相位会存在相位波动Δpll。时钟电路(CLK)到PLL之间走线会引入Δclkpath，本振电路走线会引入ΔLO_path。也就是说，本公开采用的共参考方案中，相位波动包括Δpll、Δclkpath和ΔLO_path。其中，Δclkpath和ΔLO_path都属于走线引入的相位差，通过实验得出，PCB走线的长度，粗细，材质，拐角都会引入相位差，而同轴线缆的转接头，长度，材质也会引入相位差。
通过计算各通道相对于参考通道的相位差，可以基于该相位差对各通道进行相位补偿，使所有通道相位和参考通道对齐。
在本公开的一些实施例中，装置还包括判断模块，判断模块设置为：
判断是否满足预设相位校准条件；
当满足预设相位校准条件时，触发获取模块获取基站各通道相对于参考通道的相位差。
根据本公开的一些实施例，预设相位校准条件为：基站的系统温度变化超过预设温度；和/或达到预设校准时间。
也就是说，当基站的系统温度变化超过预设温度时，对各通道进行相位校准补偿；或者，当距离上一次校准补偿的时间间隔达到预设校准时间时，对各通道进行相位校准补偿；或者，当基站的系统温度变化超过预设温度，且距离上一次校准补偿的时间间隔达到预设校准时间时，对各通道进行相位校准补偿。
需要说明的是，如上述所述，本公开采用的共时钟参考方案中，相位波动包括Δpll、Δclkpath和ΔLO_path。虽然这些相位差是固定的，但是在温度变化下，相位差会出现波动，所以共参考方案的整机在校准后虽然各通道相位已经对齐，如果出现温度变化较大的情况由于Δclkpath和ΔLO_path引起的相位差变化太大就可能使得各通道间相位差超出相应的要求，影响流量。所以在整机设计中需要控制PCB走线使得Δclkpath和ΔLO_path尽量小，但由于系统的复杂性Δclkpath和ΔLO_path不可能完全消除，需要进行校准补偿。对于pll引起的相位差Δpll也是随着时间和温度随时变化，也需通过校准补偿。
根据本公开的一些实施例，各条通道上的本振电路的本振走线的长度相同。可以理解的是，通过设置各条通道上的本振电路的本振走线的长度相同，可以降低各个通道上不同的PLL输出相位存在的相位波动Δpll，从而有利于提高各通道的相位一致性。
在本公开的一些实施例中，时钟电路连接至各所述通道的时钟走线的长度相同。可以理解的是，通过设置时钟电路连接至各所述通道的时钟走线的长度相同，可以降低时钟电路(CLK)到PLL之间走线会引入的时钟走线相位差Δclkpath，从而有利于提高各通道的相位一致性。
如图3和图5所示，根据本公开的基站多通道相位同步方法，基站多通道相位同步方法采用上述所述的基站多通道相位同步装置进行多通道相位同步，方法包括：
S101：获取基站各通道相对于参考通道的相位差；
S102：基于相位差对各通道进行相位校准；
根据本公开的基站多通道相位同步方法，各个通道单独设置本振电路，且所有通道共用一个同步时钟。并且，通过共同的时钟参考实现各个通道相位在一定程度上的同步。由此，可以使系统走线更加方便、灵活。而且，因为时钟信号频率较低，插损小，所以不需要设置放大器，也无需过多考虑杂散的影响，有效简化了基站整机结构并解决了基站多通道相位同步的问题。另外，通过对各通道进行实时相位校准，可以保证简化硬件后相位同步的性能不受影响。
如图6所示，根据本公开的一些实施例，获取基站各通道相对于参考通道的相位差，包括：
S201：向各通道发射校准信号；
结合图3所示，数字基带处理单元208可以向各通道发送一个特殊校准信号，校准信号经过各通道从校准通道226返回至数字基带处理单元208。
S202：选取多个通道中的其中一个通道作为参考通道，并基于校准信号计算其余通道相对于参考通道的相位差。
结合图3所示，从多个通道中选出一个通道作为参考通道，以参考通道为基准，计算其余通道相对于参考通道的相位差。
由此，数字基带处理单元208可以根据相位差对各通道进行相位补偿，使所有通道相位和参考通道对齐。
在本公开的一些实施例中，相位差可以包括：各通道的本振相位差和走线相位差。
其中，本振相位差可以包括：压控振荡器相位差、分频器相位差和鉴相器相位差，走线相位差可以包括：本振走线相位差和时钟走线相位差。
需要说明的是，如图2所示，相关技术采用的共本振方案中，PLL(本振发生器)到混频器之间的走线差异会引入相位波动ΔLO_path。由此， 可以看出共本振方案的相位波动只有本振电路走线引入的ΔLO_path，这是因为原方案通过复杂的本振方案使得影响相位的因素变少。
本公开采用的共时钟方案中，如图4所示，PLL(本振发生器)会引入相噪，相噪存在于VCO(压控振荡器)，分频器和鉴相器中。这些噪声分量导致PLL(本振发生器)的相位偏离参考时钟的相位。因此，不同PLL输出相位会存在相位波动Δpll。时钟电路(CLK)到PLL之间走线会引入Δclkpath，本振电路走线会引入ΔLO_path。也就是说，本公开采用的共参考方案中，相位波动包括Δpll、Δclkpath和ΔLO_path。其中，Δclkpath和ΔLO_path都属于走线引入的相位差，通过实验得出，PCB走线的长度，粗细，材质，拐角都会引入相位差，而同轴线缆的转接头，长度，材质也会引入相位差。
通过计算各通道相对于参考通道的相位差，可以基于该相位差对各通道进行相位补偿，使所有通道相位和参考通道对齐。
如图7所示，在本公开的一些实施例中，方法还包括：
S301：判断是否满足预设相位校准条件；
S302：当满足预设相位校准条件时，获取基站各通道相对于参考通道的相位差。
根据本公开的一些实施例，预设相位校准条件为：基站的系统温度变化超过预设温度；和/或达到预设校准时间。
也就是说，当基站的系统温度变化超过预设温度时，对各通道进行相位校准补偿；或者，当距离上一次校准补偿的时间间隔达到预设校准时间时，对各通道进行相位校准补偿；或者，当基站的系统温度变化超过预设温度，且距离上一次校准补偿的时间间隔达到预设校准时间时，对各通道进行相位校准补偿。
需要说明的是，如上述所述，本公开采用的共时钟参考方案中，相位波动包括Δpll、Δclkpath和ΔLO_path。虽然这些相位差是固定的，但是在温度变化下，相位差会出现波动，所以共参考方案的整机在校准后虽然 各通道相位已经对齐，如果出现温度变化较大的情况由于Δclkpath和ΔLO_path引起的相位差变化太大就可能使得各通道间相位差超出相应的要求，影响流量。所以在整机设计中需要控制PCB走线使得Δclkpath和ΔLO_path尽量小，但由于系统的复杂性Δclkpath和ΔLO_path不可能完全消除，需要进行校准补偿。对于pll引起的相位差Δpll也是随着时间和温度随时变化，也需通过校准补偿。
如图8所示，触发对各通道进行校准补偿的因素有时间和温度。如果整机温度变化超过一定范围或者经过一定时间，就开始进行相位校准补偿。按照运营商提出的相位误差在5°以内的要求，可以设置整机温度变化超过10℃，时间变化半小时为校准触发条件。如图8所示，首先系统上电后进行初始化校准。基站工作中系统CPU会回读整机温度，如果温度变化超过10℃，进行一次相位校准。同时如果距上一次相位校准半个小时，系统进行一次相位校准。由此，可以保证共参考方案的基站系统流量等业务正常。
结合图3和图4所示，信号从天线口耦合过来进入N路合路器，经校准通道后进入基带，数字基带处理单元208计算出N通道相对参考通道的相位差ΔPhaseN，再在基带信号中进行相位补偿ΔCalN。使得补偿后的N通道和基准通道相位差为0，其中，
ΔPhaseN＝Δpll+Δclkpath+ΔLO_path；
ΔPhaseN+ΔCalN＝0。
本公开的共时钟参考方案可以满足5G基站中Massive和beamforming对相位的要求，同时布局更加灵活、体积小，而且，能够降低成本、功耗，适用于多通道(64或128)的波束赋形。
图10示出了一个将共时钟参考方案整机的收发信系统的电路实例。同时作为对比，图9示出了N通道共本振方案(相关技术方案)整机的收发信系统的电路实例。图10中系统使用2T2R收发集成芯片，共有N个发射通道，N个接收通道。同一个时钟芯片给N/2个集成芯片提供参考， 每个集成芯片中的两路是共本振的。N个接收通道选择一路作为发射相位校准通道(这样可以节省模拟通道数)，N路通过合路器进入校准通道，(N路可以同时校准，这样可以提高校准效率)，这样就完成了发射校准。选择一路发射通道作为接收相位校准通道，通过合路器把校准通道给各个接收通道，完成接收通道的校准。在整机单板走线中要求时钟走线、射频走线和线缆尽量保证长度一致。
通过图9和图10实例的对比，可以看到：
本公开采用的共参考方案系统风险小，杂散更少，芯片数量、成本、功耗、面积均小于相关技术中采用的共本振方案系统，而且，至少可以节省一个PLL芯片，N路放大器和N/4个功分器。另外，还可以减少对transceiver和射频采样芯片内部PLL的浪费。
本申请采用的共参考方案对和相关技术中采用的共本振方案都会对走线有要求，虽然共参考方案会增加时钟走线的难度，但是共本振方案会增加本振走线复杂性。由于本振信号比时钟信号频率高，所以总的来看共参考对走线要求低。
如图3所示，根据本公开实施例的基站，包括：多通道相位同步装置，多通道相位同步装置为上述所述的基站多通道相位同步装置。
其中，每条通道上均设有用于产生本振信号的本振电路。时钟电路与各通道均连接，以为各通道提供时钟信号。校准电路用于获取各通道相对于参考通道的相位差，基于相位差对各通道进行相位校准。
具体而言，如图3所示，本公开采用的共时钟参考方案的基站由3部分组成：时钟产生和分发电路、收发信电路和系统相位校准。
其中，如图3所示，时钟产生和分发电路主要有时钟发生器224，时钟分发器225、时钟芯片到个通道的走线204、211、219。该电路主要作用就是把恢复时钟滤除杂散后分发给各通道。只要204、211、219上的相位延迟一致就可以保证时钟到达各通道本振发生器相位一致。
收发信电路包括收发各通道频率合成器201、209、216，本振走线205、212、220和射频收发链路上的其他器件。频率合成器1～3以时钟信号为参考产生本振LO信号，与基带信号混频后通过射频链路发出去。理想状态下，本振信号相位和参考一致，走线和其他器件相位延迟一致，到天线的各通道相位就是一样的。
根据本公开实施例的基站，各个通道的本振电路是相对独立的，且所有通道共用一个同步时钟。由此，可以使系统走线更加方便、灵活。而且，因为时钟信号频率较低，插损小，所以不需要设置放大器，也无需过多考虑杂散的影响，有效解决了基站多通道相位同步的问题，可以满足5G基站中Massive和beamforming对相位的要求，适用于多通道(64或128)的波束赋形。
通过具体实施方式的说明，应当可对本公开为达成预定目的所采取的技术手段及功效得以更加深入且具体的了解，然而所附图示仅是提供参考与说明之用，并非用来对本公开加以限制。

Claims (16)

  1. 一种基站多通道相位同步装置，包括：
    多条通道，每条所述通道上均设有用于产生本振信号的本振电路；
    时钟电路，所述时钟电路与各所述通道均连接，以为各所述通道提供时钟信号；
    校准电路，设置为获取各通道相对于参考通道的相位差，基于所述相位差对各所述通道进行相位校准。
  2. 根据权利要求1所述的基站多通道相位同步装置，其中，所述校准电路包括：
    获取模块，设置为获取基站各通道相对于参考通道的相位差；
    校准模块，设置为基于所述相位差对各所述通道进行相位校准。
  3. 根据权利要求2所述的基站多通道相位同步装置，其中，所述获取模块具体设置为：
    向各所述通道发射校准信号；
    选取多个所述通道中的其中一个通道作为参考通道，并基于所述校准信号计算其余所述通道相较于所述参考通道的相位差。
  4. 根据权利要求2所述的基站多通道相位同步装置，其中，所述相位差包括：各所述通道的本振相位差和走线相位差。
  5. 根据权利要求4所述的基站多通道相位同步装置，其中，所述本振相位差包括：压控振荡器相位差、分频器相位差和鉴相器相位差，所述走线相位差包括本振走线相位差和时钟走线相位差。
  6. 根据权利要求2所述的基站多通道相位同步装置，其中，所述装 置还包括判断模块，所述判断模块设置为：
    判断是否满足预设相位校准条件；
    当满足所述预设相位校准条件时，触发所述获取模块获取基站各通道相对于参考通道的相位差。
  7. 根据权利要求6所述的基站多通道相位同步装置，其中，所述预设相位校准条件为：
    所述基站的系统温度变化超过预设温度；和/或，
    达到预设校准时间。
  8. 根据权利要求1所述的基站多通道相位同步装置，其中，各条所述通道上的本振电路的本振走线的长度相同。
  9. 根据权利要求1所述的基站多通道相位同步装置，其中，所述时钟电路连接至各所述通道的时钟走线的长度相同。
  10. 一种基站多通道相位同步方法，所述基站多通道相位同步方法采用根据权利要求1至9中任一项所述的基站多通道相位同步装置进行多通道相位同步，所述方法包括：
    获取基站各通道相对于参考通道的相位差；
    基于所述相位差对各所述通道进行相位校准。
  11. 根据权利要求10所述的基站多通道相位同步方法，其中，所述获取基站各通道相对于参考通道的相位差，包括：
    向各所述通道发射校准信号；
    选取多个所述通道中的其中一个通道作为参考通道，并基于所述校准 信号计算其余所述通道相对于所述参考通道的相位差。
  12. 根据权利要求11所述的基站多通道相位同步方法，其中，所述相位差包括：各所述通道的本振相位差和走线相位差。
  13. 根据权利要求12所述的基站多通道相位同步方法，其中，所述本振相位差包括：压控振荡器相位差、分频器相位差和鉴相器相位差，所述走线相位差包括：本振走线相位差和时钟走线相位差。
  14. 根据权利要求10所述的基站多通道相位同步方法，其中，所述方法还包括：
    判断是否满足预设相位校准条件；
    当满足所述预设相位校准条件时，获取基站各通道相对于参考通道的相位差。
  15. 根据权利要求14所述的基站多通道相位同步方法，其中，所述预设相位校准条件为：
    所述基站的系统温度变化超过预设温度；和/或，
    达到预设校准时间。
  16. 一种基站，包括多通道相位同步装置，所述多通道相位同步装置为根据权利要求1-9中任一项所述的基站多通道相位同步装置。
PCT/CN2020/104644 2019-07-31 2020-07-24 基站多通道相位同步装置、方法及基站 WO2021018057A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020217043089A KR102656996B1 (ko) 2019-07-31 2020-07-24 기지국의 다중 채널 위상 동기화 장치, 방법 및 기지국
JP2021578150A JP7399196B2 (ja) 2019-07-31 2020-07-24 基地局マルチチャネル位相同期装置、方法及び基地局

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910698141.8 2019-07-31
CN201910698141.8A CN112312535A (zh) 2019-07-31 2019-07-31 基站多通道相位同步装置、方法及基站

Publications (1)

Publication Number Publication Date
WO2021018057A1 true WO2021018057A1 (zh) 2021-02-04

Family

ID=74230209

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/104644 WO2021018057A1 (zh) 2019-07-31 2020-07-24 基站多通道相位同步装置、方法及基站

Country Status (4)

Country Link
JP (1) JP7399196B2 (zh)
KR (1) KR102656996B1 (zh)
CN (1) CN112312535A (zh)
WO (1) WO2021018057A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113315561B (zh) * 2021-05-25 2022-04-08 之江实验室 一种mimo系统中共参考多通道相位噪声抑制方法
CN114401169A (zh) * 2021-12-09 2022-04-26 普源精电科技股份有限公司 多路信号相干电路和射频信号源
CN115001646B (zh) * 2022-08-01 2022-11-18 杭州加速科技有限公司 一种适用于多板卡的时钟同步校准方法及装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6154641A (en) * 1998-10-27 2000-11-28 Lucent Technologies Inc. Wideband multiple channel frequency converter
CN101424730A (zh) * 2007-11-02 2009-05-06 杰脉通信技术(上海)有限公司 一种多通道定位系统的校准方法
CN108234037A (zh) * 2017-12-29 2018-06-29 鹤壁天海电子信息系统有限公司 一种相位的校准方法和电路
CN109818596A (zh) * 2019-01-29 2019-05-28 中国科学院上海微系统与信息技术研究所 一种多通道射频信号波形和相位精确控制电路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05129980A (ja) * 1991-10-31 1993-05-25 Toshiba Corp 平面状アンテナを備えた無線通信装置
JP3594812B2 (ja) * 1998-09-24 2004-12-02 アルプス電気株式会社 信号受信装置
JP2004312600A (ja) * 2003-04-10 2004-11-04 Hitachi Kokusai Electric Inc 通信機
KR101213473B1 (ko) * 2009-05-07 2012-12-20 한국전자통신연구원 단일 발진기를 이용한 다중 출력 발진기 및 다중 출력 생성 방법
US9979408B2 (en) * 2016-05-05 2018-05-22 Analog Devices, Inc. Apparatus and methods for phase synchronization of phase-locked loops
KR102630181B1 (ko) * 2019-06-10 2024-01-26 삼성전자주식회사 위상차 검출기 및 이를 포함하는 장치

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6154641A (en) * 1998-10-27 2000-11-28 Lucent Technologies Inc. Wideband multiple channel frequency converter
CN101424730A (zh) * 2007-11-02 2009-05-06 杰脉通信技术(上海)有限公司 一种多通道定位系统的校准方法
CN108234037A (zh) * 2017-12-29 2018-06-29 鹤壁天海电子信息系统有限公司 一种相位的校准方法和电路
CN109818596A (zh) * 2019-01-29 2019-05-28 中国科学院上海微系统与信息技术研究所 一种多通道射频信号波形和相位精确控制电路

Also Published As

Publication number Publication date
JP2022538665A (ja) 2022-09-05
KR102656996B1 (ko) 2024-04-15
KR20220016195A (ko) 2022-02-08
JP7399196B2 (ja) 2023-12-15
CN112312535A (zh) 2021-02-02

Similar Documents

Publication Publication Date Title
WO2021018057A1 (zh) 基站多通道相位同步装置、方法及基站
US7499684B2 (en) Master-slave local oscillator porting between radio integrated circuits
US10270583B2 (en) Enabling RX signal path synchronization and alignment signals in a highly integrated TX RFIC
KR20160113016A (ko) 고속 아날로그 빔형성 시스템 및 방법
KR20180107012A (ko) 개별신호발생기를 이용한 무선 전력 송신 장치 및 방법
CN115603763A (zh) 多通道信号合成电路及多通道信号合成方法
CN111245472B (zh) 射频收发芯片、针对射频收发芯片的同步系统及方法
US10687293B2 (en) Wirelessly synchronized clock networks
US11212016B1 (en) Distribution of inter/intra calibration signals for antenna beamforming signals
CN209690498U (zh) 一种s波段测波雷达的信号源
Ji et al. The synchronization design of multi-channel digital TR module for phased array radar
CN215990748U (zh) 一种系统时钟装置及5g全频段射频信号的采集设备
CN203775191U (zh) 一种特高频宽带校正信号源
CN215768986U (zh) 数字雷达中频信号处理单元及数字相控阵雷达
CN113451776A (zh) 一种高集成度数字相控阵系统
CN113328265A (zh) 一种可扩展e波段数字有源阵列
CN112946583A (zh) 中频信号处理单元及具有其的数字相控阵雷达
KR101351589B1 (ko) 다중 안테나 송수신 시스템
US10837819B2 (en) Radar fill level measurement device comprising a synchronizing signal on different layers of a printed circuit board
EP3851869B1 (en) Radar system
Hidvégi et al. Timing and triggering system for the European XFEL project-a double sized AMC board
EP4328706A1 (en) Method and system for clock distribution for multi-device synchronization
EP4312375A1 (en) Frequency synthesizer and method for generating an rf clock signal
CN117640052B (zh) 一种软件无线电设备相位同步校准方法及系统
RU212365U1 (ru) Приемопередающий аппаратный модуль базовой станции

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20848356

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021578150

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 20217043089

Country of ref document: KR

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20848356

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20848356

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 22/09/2022)

122 Ep: pct application non-entry in european phase

Ref document number: 20848356

Country of ref document: EP

Kind code of ref document: A1