WO2021017120A1

WO2021017120A1 - Array substrate

Info

Publication number: WO2021017120A1
Application number: PCT/CN2019/106565
Authority: WO
Inventors: 曹武
Original assignee: 深圳市华星光电半导体显示技术有限公司
Priority date: 2019-07-26
Filing date: 2019-09-19
Publication date: 2021-02-04
Also published as: CN110346995A; CN110346995B

Abstract

Disclosed is an array substrate (100), comprising a plurality of sub-pixels (150) distributed in an array, wherein each sub-pixel (150) is divided into a main area (110) and a secondary area (120); and a first metal layer (10), wherein in the main area (110), the first metal layer (10) is provided with first longitudinal wirings (101) and a first lateral wiring (103), each longitudinal column of sub-pixels corresponds to at least one first longitudinal wiring (101), the first lateral wiring (103) is arranged at a side, facing the secondary area (120), of the main area (110), and all the first longitudinal wirings (101) are perpendicularly connected to the first lateral wiring (103); and in the secondary area (120), the first metal layer (10) is provided with second longitudinal wirings (102) and a second lateral wiring (122), each longitudinal column of sub-pixels corresponds to one second longitudinal wiring (102), the second lateral wiring (122) is arranged at a side, facing the main area (110), of the secondary area (120), and all the second longitudinal wirings (102) are perpendicularly connected to the second lateral wiring (122). By means of reducing the number of lateral wirings of a first common electrode, the number of intersections and turns in a pixel area are reduced, thereby effectively alleviating the problems of light leakage, poor contrast, etc. of pixels in a dark state.

Description

An array substrate

Technical field

The present invention relates to the field of display, in particular to an array substrate.

Background technique

Generally in pixel design and LCD manufacturing process, patterns are made on the first layer. In addition to the TFT gate, a common electrode (first common electrode) component of the array substrate is also added, because the metal is opaque and shields the electric field. Role, so it is also called "shading metal".

In the pixel design of common array substrates, the first common electrode is provided on the first metal layer, and its main structure can shield the lateral electric field of the scan line, which can be used to protect the pixel electrode; and the main area is set as a grid-like first common electrode. The common electrode can also shield the coupling effect of the high-voltage and high-frequency jump electric field of the data line on the pixel electrode, so that the pixel voltage is more stable, and it can prevent crosstalk or deterioration of picture taste or even abnormality. In the middle of the pixel, the first common electrode forms a Mesh network. For a large-size LCD, it can not only reduce the impedance and stabilize the signal, but also play the role of shielding the shared common electrode.

Although the first common electrode has several advantages, it is limited by the limitations of the process itself.

technical problem

As shown in Figure 1, the effect of the metal film forming process on the pixel structure, the actual exposure and etching patterning makes the right-angle design of the side of the metal pattern passivated into a circular arc, and when the metal side profile extends in the direction of the polarizer (POL) polarization When the axis is at an angle of 45°, light leakage occurs in a dark state at the cross of the first common electrode. By rotating the POL 45°, it can be clearly found that the doji has disappeared, but the dark metal edges are all lit up, indicating that it is the main cause of light leakage.

Therefore, it is necessary to improve the pixel structure design of the array substrate to avoid or reduce the intersection or corners of the pixel center area, while maintaining the shielding effect of the first common electrode on the electric field of the data line in a specific area; in addition, the intermittent metal traces extend to In the pixel area, there is also a certain risk of electrostatic discharge (ESD) damage during manufacturing or use.

Technical solutions

The purpose of the present invention is to reduce the horizontal wiring of the first common electrode, thereby reducing the intersections and corners in the pixel area, which can effectively improve the problems of light leakage and poor contrast of the pixels in the dark state.

To solve the above technical problems, the present invention provides an array substrate including a plurality of sub-pixels arranged in an array, each sub-pixel is divided into a main area and a sub-area; the first metal layer has a third lateral wiring, Is set between the main area and the sub-area; in the main area, the first metal layer has a first vertical wiring and a first horizontal wiring; each column of sub-pixels corresponds to at least one first Longitudinal wiring; the first horizontal wiring is close to the secondary area and spaced from the third horizontal wiring, and all the first longitudinal wirings are vertically connected to the first horizontal wiring; in the secondary area , The first metal layer has a second vertical wiring and a second horizontal wiring, each column of sub-pixels corresponds to a second vertical wiring, the second horizontal wiring is close to the main area and spaced from the first Three horizontal traces, and all second vertical traces are vertically connected to the second horizontal traces; and the second metal layer has a third vertical trace extending from the main area to the secondary area, and a second metal layer The three longitudinal wires correspond to a second longitudinal wire and a first longitudinal wire.

Further, there are two adjacent first longitudinal wires in the non-identical main area; a connecting wire is connected to one end of the two first longitudinal wires away from the secondary area, and the connecting wire is parallel to all the first longitudinal wires. The first horizontal routing is described.

Further, the sub-pixel further includes a data line, which is arranged outside the main area and the sub-area, and the data line is located in the second metal layer and is perpendicular to the third lateral wiring; The third lateral trace is a scan line.

Further, it further includes: a black matrix correspondingly arranged above the data line; and/or the black matrix correspondingly arranged above the third lateral wiring.

Further, in the main area, the projection of the black matrix on the first metal layer extends from the data line to a first longitudinal wiring line closest to the data line.

Further, the width of the black matrix in the secondary area is smaller than the width of the black matrix in the main area.

Further, the main region and the sub-region respectively correspond to four domains of liquid crystal molecules.

Further, it also includes a main area thin film transistor, including a first source, a first drain, and a first gate; a first capacitor, a main area storage capacitor, one end of which is connected to the first source of the main area thin film transistor The other end is connected to the first common electrode; the second capacitor is the main area liquid crystal capacitor, one end is connected to the first source or second drain of the main area thin film transistor, and the other end is connected To the second common electrode; the first gate is connected to the third lateral trace; the first drain or the first source is connected to the data line.

Further, in the sub-region, it also includes a sub-region thin film transistor, including a second source, a second drain, and a second gate; a shared thin film transistor, including a third source, a third drain, and a third gate. The third capacitor is a sub-region liquid crystal capacitor, one end of which is connected to the second source or second drain of the sub-region thin film transistor, and the other end is connected to the first common electrode; the fourth capacitor is the sub-region storage A capacitor, one end of which is connected to the second source or the second drain of the thin film transistor in the sub-region; the second drain or the second source is connected to the data line; the third source or the third The drain is connected to the third lateral trace; the third drain or the third source is connected to the data line.

Further, the source and drain of the first thin film transistor, the source and drain of the second thin film transistor, the source and drain of the third thin film transistor, and the data line are arranged on the second metal layer ; The gate of the first thin film transistor, the gate of the second thin film transistor, the gate of the third thin film transistor and the scan line are arranged in the first metal layer.

Beneficial effect

The invention provides an array substrate, which reduces the cross or corners of the electrode wiring between pixels by reducing the horizontal wiring design of the network-shaped first common electrode, thereby avoiding the risk of light leakage; at the same time, by reducing the first common electrode between adjacent pixels The first longitudinal wires of the electrodes are connected to each other to prevent problems caused by the destruction of the network-shaped first common electrode design. Finally, a black matrix is added above the data line, which can cover a large number of low liquid crystal efficiency areas on both sides of the data line and improve the contrast of the liquid crystal panel.

Description of the drawings

In order to more clearly describe the technical solutions in the embodiments of the present invention, the following will briefly introduce the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

FIG. 1 is a schematic diagram of the structure of the arc light leakage on the side of the metal pattern in the prior art;

2 is a schematic diagram of the structure of the sub-pixel of the present invention;

3 is a schematic diagram of the interconnection structure between adjacent sub-pixels of the present invention;

4 is a schematic diagram of the structure of the width of the black matrix in the main area of the present invention;

5 is a schematic diagram of the structure of the width of the black matrix of the sub-region of the present invention;

Fig. 6 is a circuit diagram of a sub-pixel of the present invention;

Array substrate 100

Sub-pixel 150; first metal layer 10; second metal layer 20;

Main area 110; Sub area 120; Black matrix 140;

The first longitudinal wiring 101; the second longitudinal wiring 102; the first horizontal wiring 103;

The second horizontal wiring 122; the third horizontal wiring 111; the third longitudinal wiring 114;

Main area thin film transistor 107; first capacitor 104; second capacitor 105;

Sub-region thin film transistor 121; third capacitor 123; fourth capacitor 124;

Shared thin film transistor 113; data line 112.

Embodiments of the invention

The following is the description of each embodiment with reference to the attached drawings to illustrate specific embodiments in which the present invention can be implemented. The terms of direction mentioned in the present invention, such as up, down, front, back, left, right, inside, outside, side, etc., are only directions with reference to the drawings. The component names mentioned in the present invention, such as first, second, etc., only distinguish different components and can be better expressed. In the figures, units with similar structures are indicated by the same reference numerals.

The embodiments of the present invention will be described in detail herein with reference to the accompanying drawings. The present invention can be manifested in many different forms, and the present invention should not only be interpreted as the specific embodiments set forth herein. The embodiments of the present invention are provided to explain the practical application of the present invention, so that other skilled in the art can understand various embodiments of the present invention and various modifications suitable for specific anticipated applications.

As shown in FIG. 2, the present invention provides an array substrate 100 including a plurality of sub-pixels 150, a first metal layer 10, a second metal layer 20 and a black matrix 140.

The sub-pixels 150 are arranged in an array, the pixel structure is an eight-domain 3T pixel structure, which is a PSVA pixel, and the sub-pixels 150 are divided into a main area 110 and a sub area 120.

The first metal layer 10 has a third lateral wiring 111, which is provided between the main region 110 and the sub-region 120; the third lateral wiring 111 is a scan line in the pixel structure, and is located in the TFT The device functions as a gate switch.

In the main area 110, the first metal layer 10 has a first vertical wiring 101 and a first horizontal wiring 103; each column of sub-pixels 150 corresponds to at least one first vertical wiring 101; The horizontal wiring 103 is close to the sub-area 120 and spaced from the third horizontal wiring 111, and all the first vertical wirings 101 are vertically connected to the first horizontal wiring 103.

The first common electrode wiring of the present invention does not constitute the existing network structure, but excludes the lateral first common electrode wiring away from the sub-region but facing the first common electrode of the sub-region The horizontal wiring means that the first horizontal wiring 103 is reserved.

In the sub-region 120, the first metal layer 10 has a second vertical wiring 102 and a second horizontal wiring 122. Each column of sub-pixels 150 corresponds to a second vertical wiring 102, and the second horizontal The wiring 122 is close to the main area 110 and separated from the third horizontal wiring 111, and all the second vertical wirings 102 are vertically connected to the second horizontal wiring 122.

The second metal layer 20 has a third longitudinal wiring 114, the third longitudinal wiring 114 extends from the main area 110 to the secondary area 120, and the third longitudinal wiring 114 corresponds to a second longitudinal wiring. Wire 102 and a first longitudinal wire 101. The third vertical wiring 114 is the shared common electrode (Sharecom) of the present invention.

There are two adjacent first longitudinal wires 101 in the non-identical main area 110; a connecting wire 12 is connected to one end of the two first longitudinal wires 101 away from the secondary area 120, and the connecting wire 12 Parallel to the first lateral wiring 103.

The interconnection between the left and right adjacent sub-pixels 150 compensates to a certain extent the risk of tip discharge ESD caused by the destruction of the first common electrode mesh trace. So it is feasible.

The sub-pixel 150 further includes a main area thin film transistor 107, a first capacitor 104, a second capacitor 105, a sub area thin film transistor 121, a third capacitor 123, a fourth capacitor 124, a shared thin film transistor 113, and a data line 112;

The data line 112 is perpendicular to the scan line 111, and the data line 112 is disposed in the second metal layer 20.

The first capacitor 104 is the main area storage capacitor Cst, one end of the first capacitor 104 is connected to the first source or the first drain of the main area thin film transistor 107, and the other end is connected to the first common electrode (That is, the common electrode Acom of the array substrate). The second capacitor 105 is the main area liquid crystal capacitor Clc, one end of the second capacitor 105 is connected to the first source or the second drain of the main area thin film transistor 107, and the other end is connected to the second common electrode (Ie, the color filter substrate common electrode CFcom); the first gate is connected to the third lateral wiring 111; the first drain or source is connected to the data line 112.

The third capacitor 123 is a sub-region storage capacitor Cst. One end of the third capacitor 123 is connected to the second source or the second drain of the sub-region thin film transistor 121, and the other end is connected to the first common electrode. (That is, the common electrode Acom of the array substrate); the fourth capacitor 124 is a sub-region liquid crystal capacitor Cst, and one end of the fourth capacitor 124 is connected to the second source or the second drain of the sub-region thin film transistor 121; The second drain or second source is connected to the data line 112; the third source or third drain is connected to the third lateral trace 111; the third drain or third The source electrode is connected to the data line 112.

The main region 110 and the sub region 120 respectively use liquid crystal molecules with four domains. In a general manufacturing process, the source and drain of the thin film transistor 107 in the main region, the source and drain of the thin film transistor 121 in the sub region, the source and drain of the shared thin film transistor 113, and the data line 112 is fabricated on the second metal layer 20; the gate of the thin film transistor 107 in the main region, the gate of the thin film transistor 121 in the sub region, the gate of the shared thin film transistor 113 and the scan line 111 are fabricated on the first metal layer 10.

As shown in FIG. 3, the present invention connects the adjacent sub-pixels 150 through the connecting line 12, which creates the corners of the wiring. In order to prevent the pixel structure from leaking light, a black matrix 140 can be provided above the data line 112 for shielding. .

The black matrix 140 is correspondingly arranged above the data line 112; and/or the black matrix 140 is correspondingly arranged above the third lateral wiring 111. In the main area 110, the projection of the black matrix 140 on the first metal layer 10 extends from the data line 112 to a first longitudinal wiring 101 closest to the data line 112. The width of the black matrix 140 in the secondary area 120 is smaller than the width of the black matrix 140 in the main area 110.

As shown in FIG. 4, the black matrix 140 has a trapezoidal cross-section with an upper base and a lower base. The upper base length of the black matrix 140 corresponding to the data line 112 of the main area 110 is 15-19um, preferably 18um. It can also be 16um or 18um. The distance between the adjacent first longitudinal traces 101 between adjacent sub-pixels 150 is 12~16um, preferably 15um, and can also be 13um or 14um; the width of the DBS electrode is 12.5um; the main area 110 The black matrix 140 can cover a large number of low liquid crystal efficiency areas on both sides of the data line 112, such as gaps, etc., so the contrast is improved significantly.

As shown in FIG. 5, the upper bottom length of the black matrix 140 corresponding to the data line 112 of the sub-area 120 is 12-16um, preferably 14um, or 13um or 15um; the width of the DBS electrode is 7um; The black matrix 140 of the sub-area 120 can cover a large number of low liquid crystal efficiency areas on both sides of the data line 112, such as gaps, etc., so the contrast is improved significantly.

Refer to FIG. 6, which is a schematic circuit diagram of the sub-pixel 150 structure provided by the present invention. The sub-pixels 150 are arranged in an array, and each sub-pixel 150 can be divided into a main area 110 and a sub-area 120, including a main area thin film transistor 107, a main area liquid crystal capacitor, a main area storage capacitor, a sub area thin film transistor 121, and a sub area. Zone liquid crystal capacitor, sub zone storage capacitor and shared thin film transistor 113; the DBS signal line 20 is vertically connected to the data line 112.

The storage capacitor in the main area is also the first capacitor 104, the liquid crystal capacitor in the main area is the second capacitor 105; the storage capacitor in the secondary area is the third capacitor 123, and the liquid crystal capacitor in the sub-area The capacitor is the fourth capacitor 124.

One scan line 111 is provided corresponding to each row of sub-pixels 150. A data line 112 is provided for each column of sub-pixels 150; the gate of the thin film transistor 107 in the main area is connected to the scan line 111, and the source/drain is connected to the data line 112, and the drain/source and common electrode are first common The main area liquid crystal capacitor 105 and the main area storage capacitor 104 are connected in parallel between the electrodes (or CFcom).

The gate of the thin film transistor 121 in the sub-area is connected to the scan line 111, and its source/drain is connected to the data line 112. The storage capacitor and the liquid crystal in the sub-area are connected in parallel between the drain/source and the first common electrode of the common electrode. Capacitance; The gate of the shared thin film transistor 113 is connected to the scan line 111, and its source and drain are respectively connected to the drain/source of the thin film transistor 121 in the sub-region and the third vertical wiring 114.

The core of the present invention is to reduce the intersection of metal traces at the center of the pixel and light leakage at the corners, causing problems such as poor contrast. The design mainly avoids the cross or corners of metal traces, thereby reducing the horizontal first common pixel in the panel. The wiring design of the electrodes, and directly connect the first common electrodes between adjacent pixels (both sides of the data line 112), that is, connect the first vertical wiring 101 of the present invention, thereby reducing the number of The design of the crossing or corner of the line. At the same time, the interconnection of the first vertical traces 101 close to each other between adjacent pixels compensates to a certain extent the risk of removing the first common electrode in the network shape caused by the removal of the horizontal first common electrode, and at the same time avoids The tip discharges ESD. Therefore, the present invention is feasible.

In summary, the array substrate 100 of the present invention reduces the horizontal wiring of the network-shaped first common electrode design, reduces the crossing or corners of the electrode wiring between the pixels, thereby avoiding the risk of light leakage; at the same time, by reducing the first common electrode between adjacent pixels The first longitudinal wires 101 of the electrodes are connected to each other to prevent problems caused by the destruction of the network-shaped first common electrode design. Finally, a black matrix 140 is added above the data line 112, which can cover a large number of low liquid crystal efficiency areas on both sides of the data line 112 and improve the contrast of the liquid crystal panel.

The technical scope of the present invention is not limited to the content in the description. Those skilled in the art can make various deformations and modifications to the embodiments without departing from the technical idea of the present invention, and these deformations and modifications are all It should fall within the scope of the present invention.

Claims

An array substrate, including

A plurality of sub-pixels are arranged in an array, and each sub-pixel is divided into a main area and a sub area;

The first metal layer has a third lateral trace, which is arranged between the main area and the secondary area; in the main area, the first metal layer has a first longitudinal trace and a first lateral Wiring; each column of sub-pixels corresponds to at least one first vertical wiring; the first horizontal wiring is close to the secondary area and spaced from the third horizontal wiring, and all the first vertical wiring is connected vertically to all The first horizontal wiring; in the sub-area, the first metal layer has a second vertical wiring and a second horizontal wiring, each column of sub-pixels corresponds to a second vertical wiring, the second The horizontal wiring is close to the main area and spaced apart from the third horizontal wiring, and all the second vertical wirings are vertically connected to the second horizontal wiring; and

The second metal layer has a third longitudinal wiring extending from the main area to the secondary area. A third longitudinal wiring corresponds to a second longitudinal wiring and a first longitudinal wiring.
The array substrate according to claim 1, wherein:

There are two adjacent first longitudinal wires in the non-identical main area; a connecting wire is connected to the end of the two first longitudinal wires away from the secondary area, and the connecting wire is parallel to the first Horizontal wiring.
The array substrate according to claim 1, wherein the sub-pixels further comprise data lines, which are arranged outside the main area and the sub-area, and the data lines are located in the second metal layer and are vertical Route the third horizontal line;

The third lateral trace is a scan line.
The array substrate according to claim 3, further comprising:

The black matrix is correspondingly set above the data line; and/or

The black matrix is correspondingly arranged above the third lateral wiring.
4. The array substrate according to claim 4, wherein, in the main area, the projection of the black matrix on the first metal layer extends from the data line to the first one closest to the data line One longitudinal trace.
The array substrate according to claim 4, wherein the width of the black matrix in the secondary area is smaller than the width of the black matrix in the main area.
The array substrate according to claim 1, wherein the main area and the sub area respectively correspond to four domains of liquid crystal molecules.
The array substrate according to claim 3, wherein, in the main area, further comprising

The thin film transistor in the main region includes a first source, a first drain, and a first gate;

The first capacitor is a storage capacitor in the main area, one end of which is connected to the first source or the first drain of the main area thin film transistor, and the other end is connected to the first common electrode;

The second capacitor is a main area liquid crystal capacitor, one end of which is connected to the first source or second drain of the main area thin film transistor, and the other end is connected to the second common electrode;

The first gate is connected to the third lateral trace;

The first drain or the first source is connected to the data line.
The array substrate according to claim 8, wherein, in the sub-region, further comprising

The thin film transistor in the sub-region includes a second source, a second drain, and a second gate;

Shared thin film transistor, including a third source, a third drain, and a third gate;

The third capacitor is a sub-region liquid crystal capacitor, one end of which is connected to the second source or second drain of the sub-region thin film transistor, and the other end is connected to the first common electrode;

The fourth capacitor is a storage capacitor in the secondary region, one end of which is connected to the second source or the second drain of the thin film transistor in the secondary region;

The second drain or the second source is connected to the data line;

The third source or the third drain is connected to the third lateral trace;

The third drain or the third source is connected to the data line.
The array substrate according to claim 9, wherein:

The source and drain stages of the first thin film transistor, the source and drain stages of the second thin film transistor, the source and drain stages of the third thin film transistor, and the data line are arranged on the second metal layer;

The gate of the first thin film transistor, the gate of the second thin film transistor, the gate of the third thin film transistor and the scan line are arranged on the first metal layer.