WO2021017003A1 - 电容检测电路、触摸检测装置和电子设备 - Google Patents

电容检测电路、触摸检测装置和电子设备 Download PDF

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Publication number
WO2021017003A1
WO2021017003A1 PCT/CN2019/098922 CN2019098922W WO2021017003A1 WO 2021017003 A1 WO2021017003 A1 WO 2021017003A1 CN 2019098922 W CN2019098922 W CN 2019098922W WO 2021017003 A1 WO2021017003 A1 WO 2021017003A1
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WIPO (PCT)
Prior art keywords
capacitor
under test
switch
charging
discharging
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PCT/CN2019/098922
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English (en)
French (fr)
Inventor
范硕
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2019/098922 priority Critical patent/WO2021017003A1/zh
Priority to CN201980001411.3A priority patent/CN112601966B/zh
Priority to EP19918497.9A priority patent/EP3798645B1/en
Priority to US17/019,573 priority patent/US11481072B2/en
Publication of WO2021017003A1 publication Critical patent/WO2021017003A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated
    • H03K17/96—Touch switches
    • H03K17/962—Capacitive touch switches
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
    • G01D5/12—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means
    • G01D5/14—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage
    • G01D5/24—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying capacitance
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
    • G01R35/005—Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/94—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00 characterised by the way in which the control signal is generated
    • H03K2217/96—Touch switches
    • H03K2217/9607—Capacitive touch switches
    • H03K2217/960705—Safety of capacitive touch and proximity switches, e.g. increasing reliability, fail-safe
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/94—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00 characterised by the way in which the control signal is generated
    • H03K2217/96—Touch switches
    • H03K2217/9607—Capacitive touch switches
    • H03K2217/96071—Capacitive touch switches characterised by the detection principle

Definitions

  • This application relates to the field of integrated circuits, in particular to a capacitance detection circuit, a touch detection device, and electronic equipment.
  • Capacitive sensors are widely used in the field of human-computer interaction of electronic products. Specifically, a capacitance is formed between the detection electrode and the ground. When a conductor (such as a finger) approaches or touches the detection electrode, the capacitance between the detection electrode and the ground Will change, the information about the conductor approaching or touching the detection electrode is obtained by detecting the change of the capacitance, so as to determine the user's operation.
  • the quality of the capacitance detection circuit directly affects the user's operating experience. Therefore, how to improve the detection performance of the capacitance detection circuit becomes an urgent problem to be solved.
  • the embodiments of the present application provide a capacitance detection circuit, a touch detection device, and an electronic device.
  • the capacitance detection circuit has better detection performance.
  • a capacitance detection circuit which includes: a first charging and discharging circuit for charging and discharging a capacitor under test; a second charging and discharging circuit for charging and discharging a calibration capacitor; an analog-to-digital conversion circuit To continuously sample the voltage difference between the capacitor under test and the calibration capacitor during the charging and discharging process to obtain sample data; a digital processing circuit is used to detect the capacitance of the capacitor under test according to the sample data.
  • the digital processing circuit is configured to detect the capacitance of the capacitor under test according to the energy value of the fundamental frequency of the sampled data.
  • the digital processing circuit includes a digital demodulator, where the digital demodulator is used to perform digital quadrature demodulation or Fourier transform on the sampled data to obtain the base Frequency energy value.
  • each charge and discharge cycle includes a charge phase and a discharge phase.
  • the first charging and discharging circuit and the second charging and discharging circuit are respectively used to simultaneously charge the capacitor under test and the calibration capacitor; in the discharging phase, the first charging and discharging circuit and the calibration capacitor The second charging and discharging circuits are respectively used for simultaneously discharging the capacitor under test and the calibration capacitor.
  • the first charging and discharging circuit includes a first current source for charging or discharging the capacitor under test; the second charging and discharging circuit includes a second current source for The calibration capacitor is charged or discharged.
  • the first end of the first current source is connected to a power supply, and the second end of the first current source is connected to the first end of the capacitor under test through a first switch, so The first end of the capacitor under test is also grounded through a second switch, and the second end of the capacitor under test is grounded; the first end of the second current source is connected to a power source, and the second end of the second current source is It is connected to the first terminal of the calibration capacitor through a third switch, the first terminal of the calibration capacitor is also grounded through a fourth switch, and the second terminal of the calibration capacitor is grounded.
  • the first end of the first current source is grounded, the second end of the first current source is connected to the first end of the capacitor under test through a first switch, and the The first end of the capacitor under test is also connected to the power supply through a second switch, the second end of the capacitor under test is grounded; the first end of the second current source is grounded, and the second end of the second current source passes through the
  • the three switches are connected to the first end of the calibration capacitor, the first end of the calibration capacitor is also connected to the power supply through a fourth switch, and the second end of the calibration capacitor is grounded.
  • C C is equal to C X ⁇ I 2 /I 1 , or the difference between C C and C 0 ⁇ I 2 /I 1 is less than a preset value, where C 0 is the The base capacitance of the capacitor to be tested, C C is the capacitance of the calibration capacitor, I 1 is the current value of the first current source, and I 2 is the current value of the second current source.
  • the first charging and discharging circuit includes a first resistor for charging or discharging the capacitor under test; the second charging and discharging circuit includes a second resistor for charging and discharging the capacitor under test.
  • the calibration capacitor is charged or discharged.
  • the first end of the first resistor is connected to a power supply, and the second end of the first resistor is connected to the first end of the capacitor under test through the first switch, so The first end of the capacitor under test is also grounded through the second switch, and the second end of the capacitor under test is grounded; the first end of the second resistor is connected to a power source, and the second end of the second resistor
  • the third switch is connected to the first terminal of the calibration capacitor, the first terminal of the calibration capacitor is also grounded through the fourth switch, and the second terminal of the calibration capacitor is grounded.
  • the first end of the first resistor is grounded, the second end of the first resistor is connected to the first end of the capacitor under test through a first switch, and the capacitor under test is The first end of the second resistor is also connected to the power supply through a second switch, the second end of the capacitor under test is grounded; the first end of the second resistor is grounded, and the second end of the second resistor is connected to the The first end of the calibration capacitor is connected, the first end of the calibration capacitor is also connected to the power supply through a fourth switch, and the second end of the calibration capacitor is grounded.
  • the first charging and discharging circuit includes a first transistor for charging or discharging the capacitor under test;
  • the second charging and discharging circuit includes a second transistor for charging or discharging the capacitor under test;
  • the calibration capacitor is charged or discharged.
  • the first transistor and the second transistor are N-type metal oxide semiconductor MOS transistors, the gate of the first transistor is connected to a fixed level, and the gate of the first transistor is The drain is connected to the power supply, the source of the first transistor is connected to the first terminal of the capacitor under test through a first switch, and the first terminal of the capacitor under test is also grounded through a second switch.
  • the second end of the capacitor is grounded; the gate of the second transistor is connected to a fixed level, the drain of the second transistor is connected to the power supply, and the source of the second transistor is connected to the calibration capacitor through a third switch
  • the first end of the calibration capacitor is connected to the ground through the fourth switch, and the second end of the calibration capacitor is grounded.
  • the first transistor and the second transistor are P-type MOS transistors, the gate of the first transistor is connected to a fixed level, and the drain of the first transistor is grounded, The source of the first transistor is connected to the first terminal of the capacitor under test through a first switch, and the first terminal of the capacitor under test is also connected to a power source through a second switch.
  • the gate of the second transistor is connected to a fixed level, the drain of the second transistor is grounded, and the source of the second transistor is connected to the first terminal of the calibration capacitor through a third switch.
  • the first end of the calibration capacitor is also connected to the power supply through a fourth switch, and the second end of the calibration capacitor is connected to the power supply.
  • the capacitance detection circuit further includes a control circuit, and the control circuit is used for controlling the closing of the second switch and the fourth switch and controlling the The first switch and the third switch are turned off; in the discharging phase, the first switch and the third switch are controlled to be turned on, and the second switch and the fourth switch are controlled to be turned off.
  • T C 2 M ⁇ T S , where T C is the length of N charge and discharge cycles, 2 M is the number of sampling points in N charge and discharge cycles, and T S is adjacent
  • T C 2 M ⁇ T S , where T C is the length of N charge and discharge cycles, 2 M is the number of sampling points in N charge and discharge cycles, and T S is adjacent
  • T C 2 M ⁇ T S , where T C is the length of N charge and discharge cycles, 2 M is the number of sampling points in N charge and discharge cycles, and T S is adjacent
  • T C 2 M ⁇ T S , where T C is the length of N charge and discharge cycles, 2 M is the number of sampling points in N charge and discharge cycles, and T S is adjacent
  • M and N are positive integers.
  • the fundamental frequency is 1/T C.
  • the capacitance detection circuit further includes an operational amplifier, wherein two input terminals of the operational amplifier are respectively connected to the capacitor to be tested and the calibration capacitor.
  • the operational amplifier is a continuity instrumentation operational amplifier.
  • the capacitance detection circuit further includes a filter, wherein the input end of the filter is connected to the output end of the operational amplifier, and the output end of the filter is connected to the analog-to-digital The input terminal of the conversion circuit is connected.
  • the capacitor to be tested is a capacitive sensor arranged on a touch panel, and the capacitive sensor is used to detect touch information of a finger on the touch panel.
  • the energy value of the fundamental frequency when the energy value of the fundamental frequency is less than a threshold value, it means that no finger touches the capacitive sensor; when the energy value of the fundamental frequency is greater than the threshold value, it means that a finger touches the capacitor.
  • Type sensor when the energy value of the fundamental frequency is less than a threshold value, it means that no finger touches the capacitive sensor; when the energy value of the fundamental frequency is greater than the threshold value, it means that a finger touches the capacitor.
  • an embodiment of the present application provides a touch detection device, including the capacitance detection circuit described in the first aspect or any possible implementation of the first aspect.
  • an embodiment of the present application provides an electronic device, including the touch detection device as described in the second aspect.
  • the analog-to-digital conversion circuit continuously samples the voltage difference between the capacitor to be tested and the calibration capacitor during the charging and discharging process to obtain the change of the voltage difference during the charging and discharging process.
  • the digital processing circuit performs continuous sampling of the data Processing to realize the detection of the capacitance change of the capacitor under test. Since the sampling data is obtained by continuously sampling the voltage difference, the sampling data is associated with the voltage difference, so that the capacitance of the capacitor under test can be detected according to the sampling data. Since the capacitance change of the capacitor under test is detected in the digital domain, the interference signal and the useful signal are of different frequencies, so the interference of noise can be reduced and the signal-to-noise ratio of the capacitance detection circuit can be improved.
  • Fig. 1 is a schematic block diagram of a conventional capacitance detection circuit.
  • Fig. 2 is a possible schematic structural diagram of the capacitance detection circuit shown in Fig. 1.
  • Fig. 3 is a possible schematic structural diagram of the capacitance detection circuit shown in Fig. 1.
  • FIG. 4 is a timing diagram corresponding to the capacitance detection circuit shown in FIG. 2.
  • Fig. 5 is another possible schematic structural diagram of the capacitance detection circuit shown in Fig. 1.
  • Fig. 6 is another possible schematic structural diagram of the capacitance detection circuit shown in Fig. 1.
  • Fig. 7 is another possible schematic structural diagram of the capacitance detection circuit shown in Fig. 1.
  • FIG. 8 is a schematic block diagram of a touch detection device 800 according to an embodiment of the present application.
  • FIG. 9 is a schematic block diagram of an electronic device 900 according to an embodiment of the present application.
  • Capacitive sensors are widely used in a variety of electronic systems. They are usually used as input devices of the system to provide the system with information about the input, such as position, movement, force, and duration. Generally, the user generates a capacitive effect with the sensing area through operations, such as approaching, touching, pressing, or sliding one or more sensing areas of the capacitive sensor, and the capacitive effect is quantified to determine the user's operation.
  • FIG. 1 is a schematic structural diagram of a capacitance detection circuit 100 according to an embodiment of the present application. As shown in FIG. 1, the capacitance detection circuit 100 is connected to a capacitor 111 to be tested, and the capacitance detection circuit 100 includes:
  • the first charging and discharging circuit 110 is used to charge and discharge the capacitor 111 under test;
  • the second charging and discharging circuit 120 is used to charge and discharge the calibration capacitor 121;
  • the analog-to-digital conversion circuit 130 is configured to continuously sample the voltage difference between the capacitor under test 111 and the calibration capacitor 121 during the charging and discharging process to obtain sampled data;
  • the digital processing circuit 140 is configured to detect the capacitance of the capacitor 111 under test according to the sampled data.
  • the analog-to-digital conversion circuit 130 continuously samples the voltage difference between the capacitor under test 111 and the calibration capacitor 121 during the charging and discharging process, and can obtain the change of the voltage difference during the charging and discharging process.
  • the continuous sampling data is processed to realize the detection of the capacitance change of the capacitor under test. Since the sampled data is obtained by continuously sampling the voltage difference, the energy value of the fundamental frequency of the sampled data is associated with the voltage difference, so that the capacitance of the capacitor under test can be detected according to the energy value of the fundamental frequency. Since the capacitance change of the capacitor under test is detected in the digital domain, the interference signal and the useful signal are of different frequencies, so the interference of noise can be reduced and the signal-to-noise ratio of the capacitance detection circuit can be improved.
  • the capacitance detection circuit 100 in this embodiment can be applied to, for example, a capacitive sensor, where the capacitor under test 111 is the sensor capacitance of the capacitive sensor.
  • the capacitance C X of the capacitor under test 111 is equal to the base capacitance C 0 .
  • the calibration capacitor 121 may be a variable capacitor array or a fixed capacitor, for example.
  • the first charging and discharging circuit 110 may include, for example, a current source, a resistor, a transistor, and other devices, which are used to charge or discharge the capacitor 111 under test.
  • the second charging and discharging circuit 120 may include, for example, a current source, a resistor, or a transistor, etc., for charging or discharging the calibration capacitor 121.
  • the voltage of the capacitor under test 111 and the voltage of the calibration capacitor 121 change according to a certain rule, so the voltage of the capacitor under test 111 and the voltage of the calibration capacitor 121 are The voltage difference also changes according to a certain rule.
  • the digital processing circuit 140 can obtain the capacitance information of the capacitor 111 to be tested from the sampled data.
  • the digital processing circuit is used to detect the capacitance of the capacitor under test according to the energy value of the fundamental frequency of the sampled data.
  • the energy value of the fundamental frequency of the sampled data reflects the change of the voltage difference.
  • the greater the energy value at the fundamental frequency the greater the voltage difference, and therefore the greater the change in capacitance of the capacitor 111 to be tested.
  • the smaller the energy value at the fundamental frequency the smaller the voltage difference, and therefore the greater the change in the capacitance of the capacitor 111 to be tested.
  • the analog-to-digital conversion circuit 130 can sample the voltage difference between the capacitor under test 111 and the calibration capacitor 121 in N charge and discharge cycles each time, where N is a positive integer.
  • each charge and discharge cycle includes a charge phase and a discharge phase.
  • the first charging and discharging circuit 110 and the second charging and discharging circuit 120 are respectively used to charge the capacitor under test 111 and the calibration capacitor 121 simultaneously; in the discharging phase The first charging and discharging circuit 110 and the second charging and discharging circuit 120 are respectively used to discharge the capacitor under test 111 and the calibration capacitor 121 simultaneously.
  • the N charging and discharging cycles constitute a coding period.
  • the analog-to-digital conversion circuit 130 continuously samples the voltage difference between the capacitor 111 to be measured and the calibration capacitor 121, and transmits the sampled data to the digital processing circuit 140. Since the change rule of the voltage difference in each charge and discharge cycle is the same, the voltage difference should change periodically during the N charge and discharge cycles.
  • the digital processing circuit 140 demodulates the received periodically distributed sampling data, and obtains the energy value of the fundamental frequency of the sampling data, so as to determine the capacitance of the capacitor 111 under test according to the energy value.
  • the charging and discharging circuit to charge the capacitor refers to the process of transferring charge to the capacitor to increase the amount of charge stored in the capacitor, while the charging and discharging circuit to discharge the capacitor means that the charge is transferred from the capacitor to reduce The process of the amount of charge stored in a capacitor.
  • the embodiment of the present application does not make any limitation on the implementation form of the first charge and discharge circuit 110 and the second charge and discharge circuit 120.
  • the present application provides the following three implementation manners.
  • the first charging and discharging circuit 110 includes a first current source 112, and the second charging and discharging circuit 120 includes a second current source 122.
  • the first current source 112 is used to charge the capacitor under test 111
  • the second current source 122 is used to charge the calibration capacitor 121.
  • the first terminal of the first current source 112 is connected to the power supply V DD
  • the second terminal of the first current source 112 is connected to the first terminal of the capacitor under test 111 through the first switch S1.
  • the first end of the capacitor under test 111 is also grounded through the second switch S2, and the second end of the capacitor under test 111 is grounded;
  • the first end of the second current source 122 is connected to the power supply V DD , and the second current
  • the second terminal of the source 122 is connected to the first terminal of the calibration capacitor 121 through a third switch S3, the first terminal of the calibration capacitor 121 is also grounded through a fourth switch S4, and the second terminal of the calibration capacitor 121 is grounded .
  • the first current source 112 is used to discharge the capacitor under test 111
  • the second current source 122 is used to discharge the calibration capacitor 121.
  • the first terminal of the first current source 112 is grounded, and the second terminal of the first current source 112 is connected to the first terminal of the capacitor under test 111 through the first switch S1.
  • the first terminal of the second current source 122 is also connected to the power supply V DD through the second switch S2, the second terminal of the capacitor under test 111 is grounded; the first terminal of the second current source 122 is grounded, and the second terminal of the second current source 122 is grounded.
  • the two terminals are connected to the first terminal of the calibration capacitor 121 through the third switch S3, the first terminal of the calibration capacitor 121 is also connected to the power supply V DD through the fourth switch S4, and the second terminal of the calibration capacitor 121 is grounded. .
  • C C C 0 ⁇ I 2 /I 1 can be set, C 0 is the base capacitance of the capacitor 111 to be tested, C C is the capacitance of the calibration capacitor 121, and I 1 is the first The current value of a current source 112, I 2 is the current value of the second current source 122.
  • the voltage difference between the capacitor under test 111 and the calibration capacitor 121 reflects the change ⁇ C of the capacitance value of the capacitor under test 111 with respect to the base capacitance C 0 , and has nothing to do with C 0. Therefore, the base capacitance is realized in the voltage domain.
  • the cancellation of C 0 prevents the capacitance detection circuit 100 from being affected by the size of the base capacitance C 0 , and improves the detection sensitivity and accuracy of the capacitance detection circuit 100.
  • the capacitance of the calibration capacitor 121 can be reduced by setting C C ⁇ C 0 ⁇ I 2 /I 1 , thereby reducing the volume of the capacitance detection circuit 100 and reducing the cost of the chip .
  • the base capacitance C 0 can be considered as the capacitance of the capacitor 111 to be measured to ground when there is no touch.
  • the capacitance of the capacitor under test 111 increases by ⁇ C relative to the base capacitance C 0 , and the ⁇ C reflects the user's touch information.
  • the first charging and discharging circuit 110 includes a first resistor 113
  • the second charging and discharging circuit 120 includes a second resistor 123.
  • the first resistor 113 is used to charge the capacitor 111 under test, and the second resistor 123 is used to charge the calibration capacitor 121.
  • the first end of the first resistor 113 is connected to the power supply V DD
  • the second end of the first resistor 113 is connected to the first end of the capacitor under test 111 through the first switch S1
  • the first end of the capacitor 111 is also grounded through the second switch S2, and the second end of the capacitor under test 111 is grounded
  • the first end of the second resistor 123 is connected to the power supply V DD
  • the second end of the second resistor 123 The two terminals are connected to the first terminal of the calibration capacitor 121 through the third switch S3, the first terminal of the calibration capacitor 121 is also grounded through the fourth switch S4, and the second terminal of the calibration capacitor 121 is grounded.
  • the first resistor 113 is used to discharge the capacitor under test 111
  • the second resistor 123 is used to discharge the calibration capacitor 121.
  • the first end of the first resistor 113 is grounded, the second end of the first resistor 113 is connected to the first end of the capacitor under test 111 through the first switch S1, and the second end of the capacitor under test 111 is One end is also connected to the power supply V DD through the second switch S2, the second end of the capacitor under test 111 is grounded; the first end of the second resistor 123 is grounded, and the second end of the second resistor 123 passes through the
  • the three switch S3 is connected to the first end of the calibration capacitor 121, the first end of the calibration capacitor 121 is also connected to the power supply V DD through the fourth switch S4, and the second end of the calibration capacitor 121 is grounded.
  • the first charge and discharge circuit 110 includes a first transistor 114
  • the second charge and discharge circuit 120 includes a second transistor 124.
  • the first transistor 114 and the second transistor 124 may be, for example, N-type Metal-Oxide Semiconductor (MOS) transistors or P-type MOS transistors.
  • MOS Metal-Oxide Semiconductor
  • the first transistor 114 is used to charge the capacitor under test 111
  • the second transistor 124 is used to charge the calibration capacitor 121.
  • the gate (Gate, abbreviated as G) of the first transistor 114 is connected to the level V bn , the level V bn makes the first transistor 114 work in the saturation region, and the drain of the first transistor 114 (Drain, abbreviated as D) is connected to the power supply V DD , the source (Source, abbreviated as S) of the first transistor 114 is connected to the first end of the capacitor under test 111 through the first switch S1, and the The first terminal of the measuring capacitor 111 is also grounded through the second switch S2, and the second terminal of the measuring capacitor 111 is grounded; the gate G of the second transistor 124 is connected to the level V bn , the level V bn To make the second transistor 124 work in the saturation region, the drain D of the second transistor 124 is connected to the power supply V DD , and the source S of the second transistor 124 is connected to the first of the calibration capacitor 121 through the third switch S3. The first terminal of the calibration capacitor 121 is also grounded through the fourth switch S
  • the first transistor 114 is used to discharge the capacitor under test 111
  • the second transistor 124 is used to discharge the calibration capacitor 121.
  • the gate G of the first transistor 114 is connected to a fixed level V bn , the level V bn makes the first transistor 114 work in the saturation region, the drain D of the first transistor 114 is grounded, and the The source S of the first transistor 114 is connected to the first end of the capacitor under test 111 through the first switch S1, and the first end of the capacitor under test 111 is also connected to the power supply V DD through the second switch S2.
  • the second end of the capacitor under test 111 is connected to the power supply V DD ;
  • the gate G of the second transistor 124 is connected to a fixed level V bn , and the level V bn makes the second transistor 124 work in the saturation region.
  • the drain D of the second transistor 124 is grounded, the source S of the second transistor 124 is connected to the first end of the calibration capacitor 121 through the third switch S3, and the first end of the calibration capacitor 121 also passes through the fourth
  • the switch S4 is connected to the power source V DD , and the second end of the calibration capacitor 121 is connected to the power source V DD .
  • the capacitance detection circuit 100 further includes a control circuit for controlling the aforementioned switches and related circuits to perform corresponding operations.
  • the control circuit controls the second switch S2 and the fourth switch S4 to close, and controls the first switch S1 and the third switch S3 to close, so that the first charge and discharge circuit 110 and the second charge and discharge circuit 110 are closed.
  • the circuit 120 separately charges the capacitor under test 111 and the calibration capacitor 121 at the same time; in the discharging phase, the control circuit controls the first switch S1 and the third switch S3 to close, and controls the second The switch S2 and the fourth switch S4 are turned off, so that the capacitor under test 111 and the calibration capacitor 121 are discharged at the same time.
  • the capacitance detection circuit 100 further includes an operational amplifier 150. Wherein, two input terminals of the operational amplifier 150 are connected to the capacitor under test 111 and the calibration capacitor 121 respectively.
  • one input terminal of the IA 150 in FIG. 3 may be connected to the first terminal of the capacitor under test 111 in FIG. 2, and the other input terminal of the IA 150 is connected to the first terminal of the calibration capacitor 121 in FIG. 2.
  • the operational amplifier 150 is a continuous operational amplifier, such as an instrumentation operational amplifier (Instrumentation Amplifier, IA or INA), so as to realize continuous voltage Amplification of the signal.
  • IA or INA instrumentation operational amplifier
  • the capacitance detection circuit 100 further includes a filter 160.
  • the input terminal of the filter 160 is connected to the output terminal of the operational amplifier 150, and the output terminal of the filter 160 is connected to the input terminal of the analog-to-digital conversion circuit 130.
  • the filter 160 may be, for example, an anti-aliasing filter for reducing aliasing frequency components in the output level.
  • FIGS. 2 to 4 are intended to help those skilled in the art to better understand the embodiments of the present application, and are not intended to limit the scope of the embodiments of the present application. Various equivalent modifications or changes made based on FIGS. 2 to 4 also fall within the scope of the embodiments of the present application.
  • the capacitance detection circuit 100 includes a first charging and discharging circuit 110, and the first charging and discharging circuit 110 includes a first current source 112, a first switch S1 and a second switch S2.
  • the first terminal of the first current source 112 is connected to the power supply V DD
  • the second terminal of the current source 112 is connected to the first terminal of the capacitor under test 111 through S1
  • the second terminal of the capacitor under test 111 is grounded
  • the capacitor under test 111 The first terminal is also grounded through S2.
  • S1 is used to control the charging process of the first current source 112 to the capacitor 111 under test
  • S2 is used to control the discharge process of the capacitor 111 under test to ground.
  • the capacitance detection circuit 100 further includes a second charging and discharging circuit 120, and the second charging and discharging circuit 120 includes a second current source 122, a third switch S3, and a fourth switch S4.
  • the first end of the second current source 122 is connected to the power supply V DD
  • the second end of the first current source 112 is connected to the first end of the calibration capacitor 121 through S3
  • the second end of the calibration capacitor 121 is grounded
  • the second end of the calibration capacitor 121 is grounded.
  • the first terminal is also grounded through S4.
  • S3 is used to control the charging process of the first current source 112 to the calibration capacitor 121
  • S4 is used to control the discharging process of the calibration capacitor 121 to ground.
  • a first current source 112 and the second current source 122 may be a proportional current source, the ratio between the current value of the first current source 112 is I 1 and a second current source 122 of value I may be fixed or adjustable.
  • FIG. 4 shows the changing law of the voltage V1 of the capacitor 111 under test and the changing law of the voltage V2 of the calibration capacitor 121 during the charging phase.
  • FIG. 4 shows the changing law of the voltage V1 of the capacitor 111 under test and the changing law of the voltage V2 of the calibration capacitor 121 during the discharge phase.
  • the current value of the first current source 112 is I, so C C ⁇ C X ⁇ I 2 / I 1 , where C X is the capacitance of the capacitor 111 to be tested.
  • C X is the capacitance of the capacitor 111 to be tested.
  • the capacitance value of the capacitor 111 to be tested is C X ⁇ C 0 + ⁇ C, and the rising speed of V1 during the charging process will decrease.
  • V1 ⁇ V2 so the voltage between V1 and V2 The difference will also become larger, and the change rule of the voltage difference is shown by the solid line corresponding to V OUT in FIG. 4.
  • C C may not be strictly equal to C 0 ⁇ I 2 /I 1
  • the values of C C and I 2 /I 1 can be set so that the capacitor 111 and the capacitor under test are not touched.
  • the energy value of the fundamental frequency of the voltage difference of the calibration capacitor 121 is as small as possible, for example, less than a predetermined value.
  • the energy value of the fundamental frequency when no touch occurs can be recorded as A1, which can be used as a reference for determining whether the energy value changes in the subsequent.
  • the value of C C can be set so that the difference between C C and C 0 ⁇ I 2 /I 1 is smaller than the preset value, that is, it is considered that the detection requirement can be met.
  • the period t1-t3 is a charging and discharging cycle. Whenever a capacitance test is performed, data in one or more charging and discharging cycles can be collected, that is, the corresponding operation in the period t1-t3 is performed one or more times, and according to The change in the difference between the voltage signals of the capacitor under test 111 and the calibration capacitor 121 in these charge and discharge cycles is to detect the change in the capacitance of the capacitor under test 111.
  • Each time data in multiple charge and discharge cycles is collected the implementation corresponding to V OUT in the last row in Figure 4 can be approximated as a periodic triangular wave.
  • the periodic triangular wave signal is continuously sampled, and the capacitor to be tested can be obtained based on the sampled data.
  • the energy value at the fundamental frequency of the difference between the voltage signal of 111 and the calibration capacitor 121 is a periodic triangular wave.
  • the capacitance detection circuit 100 further includes an instrumentation operational amplifier IA 150, a filter 160, an analog-to-digital conversion circuit 130, and a digital processing circuit 140.
  • the IA 150 In N charge and discharge cycles, after V1 and V2 are input to the IA 150, the IA 150 outputs V OUT to the filter 160 for filtering, and the filtered voltage signal V OUT is input to the ADC 130.
  • the ADC 130 continuously samples the voltage signal V OUT , that is, continuously samples the periodic triangular wave curve in FIG. 4.
  • the sampling frequency of ADC 130 cannot be too small.
  • the sampling frequency may be greater than or equal to 2 times the signal bandwidth.
  • the sampling interval is T S , that is, ADC 130 collects one point every T S.
  • the voltage data of 2 M sampling points sampled by the ADC 130 is transmitted to the digital processing circuit 140, and the digital processing circuit 140 processes these sampling points to obtain the energy value at the fundamental frequency of the sampling data of the periodic triangular wave curve in FIG.
  • the fundamental frequency is, for example, 1/T C
  • the energy value can be understood as the magnitude of the signal amplitude at the fundamental frequency. That is to say, the digital processing circuit 140 judges the magnitude of the amplitude at the 1/T C frequency point on the frequency spectrum according to the data collected by the analog-to-digital conversion circuit 130, thereby determining the capacitance of the capacitor 111 under test.
  • the voltage signal is subjected to analog-to-digital conversion and then digital demodulation, so as to detect the capacitance change of the capacitor under test in the digital domain. Since the interference signal and the useful signal have different frequencies, detecting the capacitance change of the capacitor under test in the digital domain can reduce noise interference, improve the signal-to-noise ratio of the capacitance detection circuit, and improve the detection performance of the capacitance detection circuit.
  • the embodiment of the present application does not limit the structure of the data processing circuit, as long as the energy value at the fundamental frequency of the sampled signal can be obtained.
  • the data processing circuit 140 may include a digital demodulator.
  • the digital demodulator can perform digital quadrature demodulation on the above-mentioned sampled data to obtain the energy value at the fundamental frequency.
  • the digital demodulator can perform Fourier Transform (Fast Fourier Transform, FFT) on the aforementioned sampled data to obtain a spectrogram, and obtain the energy value on the fundamental frequency according to the spectrogram.
  • FFT Fast Fourier Transform
  • the digital demodulator can also obtain the energy value of the fundamental frequency in other ways, which is not limited here.
  • C C ⁇ C X ⁇ I 2 /I 1 , V2 ⁇ V1; when the energy value A2 at the fundamental frequency of the voltage difference is greater than or equal to the threshold, it can be considered that the capacitance on C X has changed. At this time, the differential output V OUT of the IA 150
  • the energy value of the fundamental frequency is A1 when no touch occurs, and the energy value of the fundamental frequency is A2 when a touch occurs, it can be determined whether the capacitance on C X has changed according to the magnitude of A2-A1. For example, when applied to touch detection, when A2-A1 is less than a preset threshold, it can be considered that no touch has occurred; when A2-A1 is greater than or equal to the preset threshold, it can be considered that there is a finger touch.
  • the touch operation here can be understood as including operations such as contact, approach, and press.
  • the capacitor under test 111 and the calibration capacitor 121 in FIG. 2 can also be charged by the power supply, and the capacitor under test 111 and the calibration capacitor 121 are driven to discharge by the first current source 112 and the second current source 122.
  • one end of the capacitor under test 111 and the calibration capacitor 121 is connected to a power source, the other end is connected to a current source, and the other end of the current source is grounded.
  • S1 and S3 are closed, S2 and S4 are disconnected, and the capacitor under test 111 and the calibration capacitor 121 are charged by the power supply V DD ; during the period t2-t3, S2 and S4 are closed, and S1 and S3 are disconnected.
  • the capacitor under test 111 and the calibration capacitor 121 are driven to discharge through the first current source 112 and the second current source 122. In this way, the capacitance detection of the capacitor 111 under test can also be realized.
  • first current source 112 shown in FIG. 2 can be replaced by the first resistor 113 or the first transistor 113
  • second current source 122 can be replaced by the second resistor 123 or the second transistor 124.
  • the first transistor 114 and the second transistor 124 charge the capacitor under test 111 and the calibration capacitor 121, respectively, and in the period t2-t3, the capacitor under test 111 and the calibration capacitor 121 Discharge to the ground, thereby realizing the capacitance detection of the capacitor 111 under test.
  • the first resistor 113 and the second resistor 123 charge the capacitor under test 111 and the calibration capacitor 121, respectively, and during the period t2-t3, the capacitor under test 111 and the calibration capacitor 121 are paired Ground discharge, thereby realizing the capacitance detection of the capacitor 111 under test.
  • the capacitance detection circuit 100 of the embodiment of the present application can be applied to various touch devices.
  • the capacitor under test 111 may be a capacitive sensor arranged on a touch panel, and the capacitive sensor is used to detect the touch information of a finger on the touch panel, such as touch position, touch pressure and other information.
  • FIG. 8 is a schematic block diagram of a touch detection device 800 according to an embodiment of the present application.
  • the touch detection device 800 may include the capacitance detection circuit 100 as shown in FIG. 1.
  • the touch detection device 800 can further determine the user's touch information according to the capacitance of the capacitor 111 to be measured determined by the capacitance detection circuit 100.
  • the touch detection device 800 determines the user's touch information according to the capacitance change ⁇ C of the capacitor 111 to be tested relative to the substrate capacitance C 0 determined by the capacitance detection circuit 100.
  • An embodiment of the present application also provides an electronic device 900.
  • the electronic device 900 includes a touch detection device 800 as shown in FIG. 8.
  • the electronic devices in the embodiments of the present application may be portable or mobile computing devices such as terminal devices, mobile phones, tablet computers, notebook computers, desktop computers, game devices, in-vehicle electronic devices, or wearable smart devices, and Electronic databases, automobiles, bank automated teller machines (Automated Teller Machine, ATM) and other electronic equipment.
  • the wearable smart device includes full-featured, large-sized, complete or partial functions that can be achieved without relying on smart phones, such as smart watches or smart glasses, etc., and only focus on a certain type of application function, and need to cooperate with other devices such as smart phones Use, such as various types of smart bracelets, smart jewelry and other equipment for physical sign monitoring.

Abstract

一种电容检测电路（100），具有更优的检测性能。所述电容检测电路（100）包括：第一充放电电路（110），用于对待测电容器（111）进行充放电；第二充放电电路（120），用于对校准电容器（121）进行充放电；模数转换电路（130），用于对充放电过程中所述待测电容器（111）和所述校准电容器（121）的电压差进行连续采样，得到采样数据；数字处理电路（140），用于根据所述采样数据，检测所述待测电容器（111）的电容。

Description

电容检测电路、触摸检测装置和电子设备 技术领域
本申请涉及集成电路领域，尤其涉及一种电容检测电路、触摸检测装置和电子设备。
背景技术
电容型传感器广泛应用于电子产品的人机交互领域，具体地，在检测电极和大地之间会形成电容，当有导体(例如手指)靠近或触摸检测电极时，检测电极和大地之间的电容会发生变化，通过检测该电容的变化量获取导体靠近或触摸检测电极的信息，从而判断用户的操作。电容检测电路的好坏直接影响用户的操作体验，因此，如何提高电容检测电路的检测性能成为亟待解决的问题。
发明内容
本申请实施例提供了一种电容检测电路、触摸检测装置和电子设备，该电容检测电路具有更优的检测性能。
第一方面，提供了一种电容检测电路，包括：第一充放电电路，用于对待测电容器进行充放电；第二充放电电路，用于对校准电容器进行充放电；模数转换电路，用于对充放电过程中所述待测电容器和所述校准电容器的电压差进行连续采样，得到采样数据；数字处理电路，用于根据所述采样数据，检测所述待测电容器的电容。
在一种可能的实现方式中，所述数字处理电路用于根据所述采样数据的基频的能量值，检测所述待测电容器的电容。
在一种可能的实现方式中，所述数字处理电路包括数字解调器，其中，所述数字解调器用于对所述采样数据进行数字正交解调或者傅里叶变换，得到所述基频的能量值。
在一种可能的实现方式中，每个充放电周期包括充电阶段和放电阶段。在充电阶段，所述第一充放电电路和所述第二充放电电路分别用于对所述待测电容器和所述校准电容器同时进行充电；在放电阶段，所述第一充放电电路和所述第二充放电电路分别用于对所述待测电容器和所述校准电容器同 时进行放电。
在一种可能的实现方式中，所述第一充放电电路包括第一电流源，用于对所述待测电容器进行充电或者放电；所述第二充放电电路包括第二电流源，用于对所述校准电容器进行充电或者放电。
在一种可能的实现方式中，所述第一电流源的第一端连接至电源，所述第一电流源的第二端通过第一开关与所述待测电容器的第一端相连，所述待测电容器的第一端还通过第二开关接地，所述待测电容器的第二端接地；所述第二电流源的第一端连接至电源，所述第二电流源的第二端通过第三开关与所述校准电容器的第一端相连，所述校准电容器的第一端还通过第四开关接地，所述校准电容器的第二端接地。
在一种可能的实现方式中，所述第一电流源的第一端接地，所述第一电流源的第二端通过第一开关与所述待测电容器的第一端相连，所述待测电容器的第一端还通过第二开关与电源相连，所述待测电容器的第二端接地；所述第二电流源的第一端接地，所述第二电流源的第二端通过第三开关与所述校准电容器的第一端相连，所述校准电容器的第一端还通过第四开关与电源相连，所述校准电容器的第二端接地。
在一种可能的实现方式中，C C等于C X×I 2/I 1，或者C C与C 0×I 2/I 1之间的差值小于预设值，其中，C 0为所述待测电容器的基地电容，C C为所述校准电容器的电容，I 1为所述第一电流源的电流值，I 2为所述第二电流源的电流值。
在一种可能的实现方式中，所述第一充放电电路包括第一电阻，用于对所述待测电容器进行充电或者放电；所述第二充放电电路包括第二电阻，用于对所述校准电容器进行充电或者放电。
在一种可能的实现方式中，所述第一电阻的第一端连接至电源，所述第一电阻的第二端通过所述第一开关与所述待测电容器的第一端相连，所述待测电容器的第一端还通过所述第二开关接地，所述待测电容器的第二端接地；所述第二电阻的第一端连接至电源，所述第二电阻的第二端通过所述第三开关与所述校准电容器的第一端相连，所述校准电容器的第一端还通过所述第四开关接地，所述校准电容器的第二端接地。
在一种可能的实现方式中，所述第一电阻的第一端接地，所述第一电阻的第二端通过第一开关与所述待测电容器的第一端相连，所述待测电容器的 第一端还通过第二开关连接至电源，所述待测电容器的第二端接地；所述第二电阻的第一端接地，所述第二电阻的第二端通过第三开关与所述校准电容器的第一端相连，所述校准电容器的第一端还通过第四开关连接至电源，所述校准电容器的第二端接地。
在一种可能的实现方式中，所述第一充放电电路包括第一晶体管，用于对所述待测电容器进行充电或者放电；所述第二充放电电路包括第二晶体管，用于对所述校准电容器进行充电或者放电。
在一种可能的实现方式中，所述第一晶体管和所述第二晶体管为N型金属氧化物半导体MOS管，所述第一晶体管的栅极连接至固定电平，所述第一晶体管的漏极连接至电源，所述第一晶体管的源极通过第一开关与所述待测电容器的第一端相连，所述待测电容器的第一端还通过第二开关接地，所述待测电容器的第二端接地；所述第二晶体管的栅极连接至固定电平，所述第二晶体管的漏极连接至电源，所述第二晶体管的源极通过第三开关与所述校准电容器的第一端相连，所述校准电容器的第一端还通过第四开关接地，所述校准电容器的第二端接地。
在一种可能的实现方式中，所述第一晶体管和所述第二晶体管为P型MOS管，所述第一晶体管的栅极连接至固定电平，所述第一晶体管的漏极接地，所述第一晶体管的源极通过第一开关与所述待测电容器的第一端相连，所述待测电容器的第一端还通过第二开关连接至电源，所述待测电容器的第二端连接至电源；所述第二晶体管的栅极连接至固定电平，所述第二晶体管的漏极接地，所述第二晶体管的源极通过第三开关与所述校准电容器的第一端相连，所述校准电容器的第一端还通过第四开关连接至电源，所述校准电容器的第二端连接至电源。
在一种可能的实现方式中，所述电容检测电路还包括控制电路，所述控制电路用于：在所述充电阶段，控制所述第二开关和所述第四开关闭合，以及控制所述第一开关和所述第三开关断开；在所述放电阶段，控制所述第一开关和所述第三开关闭合，以及控制所述第二开关和所述第四开关断开。
在一种可能的实现方式中，T C＝2 M×T S，其中，T C为N个充放电周期的长度，2 M为N个充放电周期内采样点的数量，T S为相邻两个采样点之间的时间间隔，M和N为正整数。
在一种可能的实现方式中，所述基频为1/T C。
在一种可能的实现方式中，所述电容检测电路还包括运算放大器，其中，所述运算放大器的两个输入端分别与所述待测电容器和所述校准电容器连接。
在一种可能的实现方式中，所述运算放大器为连续性仪表运算放大器。
在一种可能的实现方式中，所述电容检测电路还包括滤波器，其中，所述滤波器的输入端与所述运算放大器的输出端相连，所述滤波器的输出端与所述模数转换电路的输入端相连。
在一种可能的实现方式中，所述待测电容器为设置在触控面板上的电容型传感器，所述电容型传感器用于检测手指在所述触控面板上的触摸信息。
在一种可能的实现方式中，所述基频的能量值小于阈值时，表示没有手指触摸所述电容型传感器；所述基频的能量值大于所述阈值时，表示有手指触摸所述电容型传感器。
第二方面，本申请实施例提供了一种触摸检测装置，包括第一方面或第一方面任一可能的实现方式中所述的电容检测电路。
第三方面，本申请实施例提供了一种电子设备，包括如第二方面所述的触摸检测装置。
基于上述技术方案，模数转换电路通过对充放电过程中待测电容器和校准电容器的电压差进行连续采样，可以得到充放电过程中该电压差的变化情况，数字处理电路通过对连续采样数据进行处理，实现对待测电容器的电容变化量的检测。由于采样数据是对该电压差进行连续采样得到的，因此采样数据与该电压差相关联，从而可以根据该采样数据检测待测电容器的电容。由于是在数字域检测待测电容器的电容变化量，干扰信号与有用信号不同频，因此能够减小噪声的干扰，提高电容检测电路的信噪比。
附图说明
图1是现有的一种电容检测电路的示意性框图。
图2是图1所示的电容检测电路的一种可能的示意性结构图。
图3是图1所示的电容检测电路的一种可能的示意性结构图。
图4是图2所示的电容检测电路对应的时序图。
图5是图1所示的电容检测电路的另一种可能的示意性结构图。
图6是图1所示的电容检测电路的另一种可能的示意性结构图。
图7是图1所示的电容检测电路的另一种可能的示意性结构图。
图8是本申请实施例的触摸检测装置800的示意性框图。
图9是本申请实施例的电子设备900的示意性框图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例进行描述。
电容型传感器被广泛应用于多种电子系统中，通常用作系统的输入设备，为系统提供关于输入的信息，诸如位置、运动、作用力以及持续时间等。一般地，用户通过操作，例如靠近、接触、按压、滑动电容型传感器的一个或者多个传感区域，与传感区域产生电容效应，通过将所述电容效应进行量化，以判断用户的操作。
图1是根据本申请实施例的电容检测电路100的示意性结构图。如图1所示，所述电容检测电路100与待测电容器111相连，所述电容检测电路100包括：
第一充放电电路110，用于对所述待测电容器111进行充放电；
第二充放电电路120，用于对所述校准电容器121进行充放电；
模数转换电路130，用于对充放电过程中所述待测电容器111和所述校准电容器121的电压差进行连续采样，得到采样数据；
数字处理电路140，用于根据所述采样数据，检测所述待测电容器111的电容。
该实施例中，模数转换电路130通过对充放电过程中待测电容器111和校准电容器121的电压差进行连续采样，可以得到充放电过程中该电压差的变化情况，数字处理电路140通过对连续采样数据进行处理，实现对待测电容器的电容变化量的检测。由于采样数据是对该电压差进行连续采样得到的，因此采样数据的基频的能量值与该电压差相关联，从而可以根据该基频的能量值检测待测电容器的电容。由于是在数字域检测待测电容器的电容变化量，干扰信号与有用信号不同频，因此能够减小噪声的干扰，提高电容检测电路的信噪比。
该实施例中的电容检测电路100例如可以应用于电容式传感器，其中，所述待测电容器111为所述电容式传感器的传感器电容。
在无触摸时，所述待测电容器111的电容C X等于基地电容C 0。
在有触摸时，所述待测电容器111的电容C X会增大△C，变为C X＝C 0+△C。
校准电容器121例如可以是可变电容阵列或者是固定电容。
该第一充放电电路110例如可以包括电流源、电阻或者晶体管等器件，用于对待测电容器111进行充电或放电。
该第二充放电电路120例如可以包括电流源、电阻或者晶体管等器件，用于对校准电容器121进行充电或放电。
在对待测电容器111和校准电容器121进行充放电的过程中，待测电容器111的电压和校准电容器121的电压按照一定规律变化，于是，待测电容器111的电压和校准电容器121的电压之间的电压差也按照一定规律变化。模数转换电路130对充放电过程中不断变化的该电压差进行连续采样后，数字处理电路140从该采样数据中，可以获得待测电容器111的电容信息。
例如，所述数字处理电路用于根据所述采样数据的基频的能量值，检测所述待测电容器的电容。其中，该采样数据的基频的能量值反映了该电压差的变化情况。其中，该基频上的能量值越大，表明该电压差越大，因此待测电容器111的电容的变化量越大。相反，该基频上的能量值越小，表明该电压差越小，因此待测电容器111的电容的变化量越大。
模数转换电路130每次可以对N个充放电周期内的待测电容器111和校准电容器121的电压差进行采样，N为正整数。可选地，每个充放电周期包括充电阶段和放电阶段。
其中，在所述充电阶段，所述第一充放电电路110和所述第二充放电电路120分别用于对所述待测电容器111和所述校准电容器121同时进行充电；在所述放电阶段，所述第一充放电电路110和所述第二充放电电路120分别用于使所述待测电容器111和所述校准电容器121同时进行放电。
N个充放电周期组成一个打码周期，在该打码周期内，模数转换电路130对待测电容器111和校准电容器121的电压差进行连续采样，并将采样数据传输至数字处理电路140。由于各个充放电周期内该电压差的变化规律是相同，那么在这N个充放电周期内，电压差应当是周期性变化的。数字处理电路140对接收到的周期性分布的采样数据进行解调，并获得采样数据的基频的能量值，从而根据该能量值确定待测电容器111的电容。
应理解，本申请实施例中，充放电电路对电容器进行充电，指电荷向电 容器转移从而增加电容器存储的电荷量的过程，而充放电电路对电容器进行放电，指电荷由电容器转移走从而减小电容器存储的电荷量的过程。
本申请实施例对所述第一充放电电路110和所述第二充放电电路120的实现形式不做任何限定，作为示例，本申请提供以下三种实现方式。
方式1
所述第一充放电电路110包括第一电流源112，所述第二充放电电路120包括第二电流源122。
可选地，所述第一电流源112用于对所述待测电容器111进行充电，所述第二电流源122用于对所述校准电容器121进行充电。
例如，所述第一电流源112的第一端连接至电源V DD，所述第一电流源112的第二端通过第一开关S1与所述待测电容器111的第一端相连，所述待测电容器111的第一端还通过第二开关S2接地，所述待测电容器111的第二端接地；所述第二电流源122的第一端连接至电源V DD，所述第二电流源122的第二端通过第三开关S3与所述校准电容器121的第一端相连，所述校准电容器121的第一端还通过第四开关S4接地，所述校准电容器121的第二端接地。
可选地，所述第一电流源112用于对所述待测电容器111进行放电，所述第二电流源122用于对所述校准电容器121进行放电。
例如，所述第一电流源112的第一端接地，所述第一电流源112的第二端通过第一开关S1与所述待测电容器111的第一端相连，所述待测电容器111的第一端还通过第二开关S2连接至电源V DD，所述待测电容器111的第二端接地；所述第二电流源122的第一端接地，所述第二电流源122的第二端通过第三开关S3与所述校准电容器121的第一端相连，所述校准电容器121的第一端还通过第四开关S4连接至电源V DD，所述校准电容器121的第二端接地。
其中，可选地，可以设置C C＝C 0×I 2/I 1，C 0为所述待测电容器111的基地电容，C C为所述校准电容器121的电容，I 1为所述第一电流源112的电流值，I 2为所述第二电流源122的电流值。
此时，待测电容器111和校准电容器121的电压差，反映了待测电容器111的电容值相对于基地电容C 0的变化量△C，而与C 0无关，因此在电压域实现了基地电容C 0的抵消，使得电容检测电路100不再受到基地电容C 0的 大小的影响，提高了电容检测电路100的检测灵敏度和准确度。
如果不考虑对基地电容C 0的抵消，则可以通过设置C C＜C 0×I 2/I 1，以减小校准电容器121的电容，从而减小电容检测电路100的体积，降低芯片的成本。
应理解，当该电容检测电路100应用于触摸检测时，该基地电容C 0可以认为是没有任何触摸时，待测电容器111对地的电容。当有触摸时，待测电容器111的电容相对于基地电容C 0增加△C，该△C即反映了用户的触摸信息。
方式2
所述第一充放电电路110包括第一电阻113，所述第二充放电电路120包括第二电阻123。
可选地，所述第一电阻113用于对所述待测电容器111进行充电，所述第二电阻123用于对所述校准电容器121进行充电。
例如，所述第一电阻113的第一端连接至电源V DD，所述第一电阻113的第二端通过第一开关S1与所述待测电容器111的第一端相连，所述待测电容器111的第一端还通过第二开关S2接地，所述待测电容器111的第二端接地；所述第二电阻123的第一端连接至电源V DD，所述第二电阻123的第二端通过第三开关S3与所述校准电容器121的第一端相连，所述校准电容器121的第一端还通过第四开关S4接地，所述校准电容器121的第二端接地。
可选地，所述第一电阻113用于对所述待测电容器111进行放电，所述第二电阻123用于对所述校准电容器121进行放电。
例如，所述第一电阻113的第一端接地，所述第一电阻113的第二端通过第一开关S1与所述待测电容器111的第一端相连，所述待测电容器111的第一端还通过第二开关S2连接至电源V DD，所述待测电容器111的第二端接地；所述第二电阻123的第一端接地，所述第二电阻123的第二端通过第三开关S3与所述校准电容器121的第一端相连，所述校准电容器121的第一端还通过第四开关S4连接至电源V DD，所述校准电容器121的第二端接地。
方式3
所述第一充放电电路110包括第一晶体管114，所述第二充放电电路120 包括第二晶体管124。
所述第一晶体管114和所述第二晶体管124例如可以是N型金属氧化物半导体(Metal-Oxide Semiconductor，MOS)管或P型MOS管。
可选地，所述第一晶体管114用于对所述待测电容器111进行充电，所述第二晶体管124用于对所述校准电容器121进行充电。
例如，所述第一晶体管114的栅极(Gate，简写为G)连接至电平V bn，所述电平V bn使得第一晶体管114工作在饱和区，所述第一晶体管114的漏极(Drain，简写为D)连接至电源V DD，所述第一晶体管114的源极(Source，简写为S)通过第一开关S1与所述待测电容器111的第一端相连，所述待测电容器111的第一端还通过第二开关S2接地，所述待测电容器111的第二端接地；所述第二晶体管124的栅极G连接至电平V bn，所述电平V bn使得第二晶体管124工作在饱和区，所述第二晶体管124的漏极D连接至电源V DD，所述第二晶体管124的源极S通过第三开关S3与所述校准电容器121的第一端相连，所述校准电容器121的第一端还通过第四开关S4接地，所述校准电容器121的第二端接地。
可选地，所述第一晶体管114用于对所述待测电容器111进行放电，所述第二晶体管124用于对所述校准电容器121进行放电。
例如，所述第一晶体管114的栅极G连接至固定电平V bn，所述电平V bn使得第一晶体管114工作在饱和区，所述第一晶体管114的漏极D接地，所述第一晶体管114的源极S通过第一开关S1与所述待测电容器111的第一端相连，所述待测电容器111的第一端还通过第二开关S2连接至电源V DD，所述待测电容器111的第二端连接至电源V DD；所述第二晶体管124的栅极G连接至固定电平V bn，所述电平V bn使得第二晶体管124工作在饱和区，所述第二晶体管124的漏极D接地，所述第二晶体管124的源极S通过第三开关S3与所述校准电容器121的第一端相连，所述校准电容器121的第一端还通过第四开关S4连接至电源V DD，所述校准电容器121的第二端连接至电源V DD。
在一种实现方式中，所述电容检测电路100还包括控制电路，所述控制电路用于控制前述各个开关以及相关电路执行相应操作。
例如，在所述充电阶段，所述控制电路控制第二开关S2和第四开关S4闭合，以及控制第一开关S1和第三开关S3闭合，以使第一充放电电路110 和第二充放电电路120分别向所述待测电容器111和所述校准电容器121同时进行充电；在所述放电阶段，所述控制电路控制第一开关S1和所述第三开关S3闭合，以及控制所述第二开关S2和所述第四开关S4断开，以使所述待测电容器111和所述校准电容器121同时进行放电。
在一种实现方式中，所述电容检测电路100还包括运算放大器150。其中，所述运算放大器150的两个输入端分别与所述待测电容器111和所述校准电容器121连接。
例如，图3中的IA 150的一个输入端可以与图2中的待测电容器111的第一端相连，IA 150的另一个输入端与图2中的校准电容器121的第一端相连。由于所述数字处理单元140需要对连续的电压信号进行采样，因此，优选地，所述运算放大器150为连续型运算放大器，例如仪表运算放大器(Instrumentation Amplifier，IA或INA)，从而实现对连续电压信号的放大。
在一种实现方式中，所述电容检测电路100还包括滤波器160。其中，所述滤波器160的输入端与所述运算放大器150的输出端相连，所述滤波器160的输出端与所述模数转换电路130的输入端相连。
所述滤波器160例如可以是抗混叠滤波器，用于降低输出电平中的混叠频率分量。
下面以第一电流源112和第二电流源122为例，结合图2至图4，详细描述本申请电容检测电路100的工作过程。
应理解，图2至图4所示的例子是为了帮助本领域技术人员更好地理解本申请实施例，而非要限制本申请实施例的范围。基于图2至图4所进行的各种等价的修改或变化，也落入本申请实施例的范围内。
如图2所示，电容检测电路100包括第一充放电电路110，第一充放电电路110包括第一电流源112、第一开关S1和第二开关S2。其中，第一电流源112的第一端接电源V DD，电流源112的第二端通过S1与待测电容器111的第一端相连，待测电容器111的第二端接地，待测电容器111的第一端还通过S2接地。其中，S1用于控制第一电流源112向待测电容器111的充电过程，S2用于控制待测电容器111对地的放电过程。
电容检测电路100还包括第二充放电电路120，第二充放电电路120包括第二电流源122、第三开关S3和第四开关S4。其中，第二电流源122的第一端接电源V DD，第一电流源112的第二端通过S3与校准电容器121的 第一端相连，校准电容器121的第二端接地，校准电容器121的第一端还通过S4接地。其中，S3用于控制第一电流源112向校准电容器121的充电过程，S4用于控制校准电容器121对地的放电过程。
第一电流源112和第二电流源122可以是比例电流源，第一电流源112的电流值I 1与第二电流源122的电流值I 2之间的比例可以固定或者可调的。
如图4所示的时序图，在初始化阶段(t0-t1时段)，S2和S4闭合，S1和S3断开，使得待测电容器111和校准电容器121放电，例如完全放电或者放电至一定程度。在t1时刻，待测电容器111和校准电容器121上存储的电荷量均为0，待测电容器111的电压V1＝0，校准电容器121的电压V2＝0，二者的电压差为0。
在充电阶段(t1-t2时段)，S1和S3闭合，S2和S4断开，从而第一电流源112向待测电容器111充电，例如充满或者充电至一定程度，第二电流源122向校准电容器121充电，例如充满或者充电至一定程度。图4中示出了充电阶段待测电容器111的电压V1的变化规律和校准电容器121的电压V2的变化规律。
在放电阶段(t2-t4时段)，S2和S4闭合，S1和S3断开，使得待测电容器111和校准电容器121放电，例如完全放电或者放电至一定程度。图4中示出了放电阶段待测电容器111的电压V1的变化规律和校准电容器121的电压V2的变化规律。
通过调整第一电流源112的电流值I 1与第二电流源122的电流值I 2之间的比例以及校准电容器121的电容C C的值，以使C C≈C X×I 2/I 1，其中C X为待测电容器111的电容。这时，如果没有触摸，即待测电容器111的电容值为C X≈C 0，则V1≈V2，V1和V2之间的电压差始终接近0，如图4中V OUT对应的虚线所示。当有触摸时，待测电容器111的电容值为C X≈C 0+△C，V1在充电过程中上升的速度会降低，则在充电阶段内V1＜V2，因此V1和V2之间的电压差也会变大，该电压差的变化规律如图4中V OUT对应的实线所示。
在理想情况下，C C＝C 0×I 2/I 1，此时，V1和V2之间的电压差反映了△C的变化，而与C 0无关，因此在电压域实现了对基地电容C 0的抵消。使得电容检测电路100不再受到基地电容C 0的大小的影响，提高了电容检测电路100的检测灵敏度和准确度。这时，图4中V OUT对应的虚线保持为0。
在实际应用中，由于不一定能够使C C严格等于C 0×I 2/I 1，这时，可以设置C C和I 2/I 1的值，使得在未发生触摸时待测电容器111和校准电容器121的电压差的基频的能量值尽可能小，例如小于预定值。这时，可以将未发生触摸时该基频的能量值记为A1，用作后续判断该能量值是否变化的参考。
换句话说，可以设置C C的值，使得C C与C 0×I 2/I 1之间的差值小于预设值，即认为能够满足检测需求。
t1-t3时段为一个充放电周期，每进行一次电容检测时，可以采集一个或多个充放电周期内的数据，也就是说，执行t1-t3时段内的相应操作一次或多次，并根据这些充放电周期内待测电容器111和校准电容器121的电压信号的差值的变化，检测待测电容器111的电容变化。每次采集多个充放电周期内的数据时，图4中最后一行V OUT对应的实现可以近似认为是周期性三角波，对该周期性三角波信号进行连续采样，根据这些采样数据可以获取待测电容器111和校准电容器121的电压信号的差值的基频上的能量值。
如图3所示，电容检测电路100还包括仪表运算放大器IA 150、滤波器160、模数转换电路130和数字处理电路140。IA 150的两个输入端分别接收待测电容器111和校准电容器121的电压信号，放大并输出待测电容器111和校准电容器121的电压信号的差值，其中输出信号V OUT＝|V1-V2|。
N个充放电周期内，V1和V2输入IA 150后，由IA 150输出V OUT至滤波器160进行滤波，滤波后的电压信号V OUT输入至ADC 130。ADC 130对该电压信号V OUT进行连续采样，也就是对图4中的周期性三角波曲线进行连续采样。
ADC 130的采样频率不能过小，优选地，其采样频率可以大于或等于2倍的信号带宽。
例如，采样间隔为T S，即ADC 130每隔T S采集一个点。N个充放电周期的长度为T C，T C内采样点的数量为2 M，M为正整数，T C＝2 M×T S。
ADC 130采样得到的2 M个采样点的电压数据传输至数字处理电路140，数字处理电路140对这些采样点进行处理，得到图4中周期性三角波曲线的采样数据的基频上的能量值。
该基频例如为1/T C，该能量值可理解为基频上的信号幅值的大小。也就是说，数字处理电路140根据模数转换电路130采集到的数据，判断频谱上的1/T C频点处的幅值大小，从而确定待测电容器111的电容。
本申请实施例中，将电压信号进行模数转换后进行数字解调，从而在数字域检测待测电容器的电容变化量。由于干扰信号与有用信号不同频，因此在数字域检测待测电容器的电容变化量，能够减小噪声的干扰，提高电容检测电路的信噪比，提高了电容检测电路的检测性能。
应理解，本申请实施例对数据处理电路的结构不做限定，只要能够获得采样信号的基频上的能量值即可。
可选地，数据处理电路140可以包括数字解调器。
例如，该数字解调器可以对上述采样数据进行数字正交解调，从而获得该基频上的能量值。
又例如，数字解调器可以对上述采样数据进行傅里叶变化(Fast Fourier Transform，FFT)，得到频谱图，并根据该频谱图获得该基频上的能量值。
此外，数字解调器也可以通过其他方式得到该基频上的能量值，在此不做限定。
数字处理单元140根据待测电容器111和校准电容器112在充放电过程中的电压差的基频上的能量值，确定待测电容器111的电容C X的变化。例如，当所述电压差的基频上的能量值A2小于预设的阈值时，可以认为C X上的电容没有发生变化，此时，IA 150的差分输出V OUT＝|V1-V2|很小，C C≈C X×I 2/I 1，V2≈V1；当所述电压差的基频上的能量值A2大于或等于该阈值时，可以认为C X上的电容发生了变化，此时，IA 150的差分输出V OUT＝|V1-V2|较大，C C＜C X×I 2/I 1，V2＞V1。
若未发生触摸时该基频的能量值为A1，发生触摸时该基频的能量值为A2，则可以根据A2-A1的大小判断C X上的电容是否发生变化。例如，对于应用于触摸检测时，A2-A1小于预设的阈值时，可以认为未发生触摸；A2-A1大于或等于预设的阈值时，可以认为有手指触摸。这里的触摸操作可以理解为包括接触、靠近、按压等操作。
图2中的待测电容器111和校准电容器121也可以通过电源进行充电，而通过第一电流源112和第二电流源122驱动待测电容器111和校准电容器121放电。例如图5所示，待测电容器111和校准电容器121的一端接电源，且另一端与电流源相连，电流源的另一端接地。这时，在t1-t2时段，S1和S3闭合，S2和S4断开，由电源V DD向待测电容器111和校准电容器121充电；在t2-t3时段，S2和S4闭合，S1和S3断开，通过第一电流源112和第 二电流源122驱动待测电容器111和校准电容器121放电。这样，同样可以实现对待测电容器111的电容检测。
应理解，除了使用电流源驱动待测电容器111和校准电容器121进行充放电，也可以使用其他器件例如电压源等，实现对待测电容器111和校准电容器121的充放电。并且第一充放电电路110和第二充放电电路120中可以采用相同或不同类型的器件对待测电容器111和校准电容器121进行充放电，本申请均不作限定。例如，图2中所示的第一电流源112可以替换为第一电阻113或者第一晶体管113，第二电流源122可以替换为第二电阻123或者第二晶体管124，替换后，相应的技术特征可以参考前述关于图2至图4的描述，为了简洁，这里不在赘述。
例如，以图6为例，在t1-t2时段，第一晶体管114和第二晶体管124分别向待测电容器111和校准电容器121充电，而在t2-t3时段，待测电容器111和校准电容器121对地放电，从而实现对待测电容器111的电容检测。
又例如图7所示，在t1-t2时段，第一电阻113和第二电阻123分别向待测电容器111和校准电容器121充电，而在t2-t3时段，待测电容器111和校准电容器121对地放电，从而实现对待测电容器111的电容检测。
本申请实施例的电容检测电路100可以应用于各种触控设备。例如，该待测电容器111可以为设置在触控面板上的电容型传感器，所述电容型传感器用于检测手指在所述触控面板上的触摸信息，例如触摸位置、触摸压力等信息。
图8是本申请实施例的触摸检测装置800的示意性框图。如图8所示，该触摸检测装置800可以包括如图1中所示的电容检测电路100。其中，该触摸检测装置800可以根据电容检测电路100确定的待测电容器111的电容，进一步确定用户的触摸信息。具体地，该触摸检测装置800根据电容检测电路100所确定的待测电容器111相对于基底电容C 0的电容变化量△C，确定用户的触摸信息。
本申请实施例还提供了一种电子设备900，如图9所示，所述电子设备900包括如图8所示的触摸检测装置800。
作为示例而非限定，本申请实施例中的电子设备可以为终端设备、手机、平板电脑、笔记本电脑、台式机电脑、游戏设备、车载电子设备或穿戴式智能设备等便携式或移动计算设备，以及电子数据库、汽车、银行自动柜员机 (Automated Teller Machine，ATM)等其他电子设备。该穿戴式智能设备包括功能全、尺寸大、可不依赖智能手机实现完整或部分的功能，例如：智能手表或智能眼镜等，以及只专注于某一类应用功能，需要和其它设备如智能手机配合使用，如各类进行体征监测的智能手环、智能首饰等设备。
需要说明的是，在不冲突的前提下，本申请描述的各个实施例和/或各个实施例中的技术特征可以任意的相互组合，组合之后得到的技术方案也应落入本申请的保护范围。
应理解，本申请实施例中的具体的例子只是为了帮助本领域技术人员更好地理解本申请实施例，而非限制本申请实施例的范围，本领域技术人员可以在上述实施例的基础上进行各种改进和变形，而这些改进或者变形均落在本申请的保护范围内。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (24)

  1. 一种电容检测电路，其特征在于，包括：
    第一充放电电路，用于对待测电容器进行充放电；
    第二充放电电路，用于对校准电容器进行充放电；
    模数转换电路，用于对充放电过程中所述待测电容器和所述校准电容器的电压差进行连续采样，得到采样数据；
    数字处理电路，用于根据所述采样数据，检测所述待测电容器的电容。
  2. 根据权利要求1所述的电容检测电路，其特征在于，所述数字处理电路用于根据所述采样数据的基频的能量值，检测所述待测电容器的电容。
  3. 根据权利要求2所述的电容检测电路，其特征在于，所述数字处理电路包括数字解调器，其中，所述数字解调器用于对所述采样数据进行数字正交解调或者傅里叶变换，得到所述基频的能量值。
  4. 根据权利要求1至3中任一项所述的电容检测电路，其特征在于，每个充放电周期包括充电阶段和放电阶段，
    在充电阶段，所述第一充放电电路和所述第二充放电电路分别用于对所述待测电容器和所述校准电容器同时进行充电；
    在放电阶段，所述第一充放电电路和所述第二充放电电路分别用于对所述待测电容器和所述校准电容器同时进行放电。
  5. 根据权利要求4所述的电容检测电路，其特征在于，
    所述第一充放电电路包括第一电流源，用于对所述待测电容器进行充电或者放电；
    所述第二充放电电路包括第二电流源，用于对所述校准电容器进行充电或者放电。
  6. 根据权利要求5所述的电容检测电路，其特征在于，
    所述第一电流源的第一端连接至电源，所述第一电流源的第二端通过第一开关与所述待测电容器的第一端相连，所述待测电容器的第一端还通过第二开关接地，所述待测电容器的第二端接地；
    所述第二电流源的第一端连接至电源，所述第二电流源的第二端通过第三开关与所述校准电容器的第一端相连，所述校准电容器的第一端还通过第四开关接地，所述校准电容器的第二端接地。
  7. 根据权利要求5所述的电容检测电路，其特征在于，
    所述第一电流源的第一端接地，所述第一电流源的第二端通过第一开关与所述待测电容器的第一端相连，所述待测电容器的第一端还通过第二开关与电源相连，所述待测电容器的第二端接地；
    所述第二电流源的第一端接地，所述第二电流源的第二端通过第三开关与所述校准电容器的第一端相连，所述校准电容器的第一端还通过第四开关与电源相连，所述校准电容器的第二端接地。
  8. 根据权利要求5至7中任一项所述的电容检测电路，其特征在于，
    C C等于C 0×I 2/I 1，或者C C与C 0×I 2/I 1之间的差值小于预设值，其中，C 0为所述待测电容器的基地电容，C C为所述校准电容器的电容，I 1为所述第一电流源的电流值，I 2为所述第二电流源的电流值。
  9. 根据权利要求4所述的电容检测电路，其特征在于，
    所述第一充放电电路包括第一电阻，用于对所述待测电容器进行充电或者放电；
    所述第二充放电电路包括第二电阻，用于对所述校准电容器进行充电或者放电。
  10. 根据权利要求9所述的电容检测电路，其特征在于，
    所述第一电阻的第一端连接至电源，所述第一电阻的第二端通过所述第一开关与所述待测电容器的第一端相连，所述待测电容器的第一端还通过所述第二开关接地，所述待测电容器的第二端接地；
    所述第二电阻的第一端连接至电源，所述第二电阻的第二端通过所述第三开关与所述校准电容器的第一端相连，所述校准电容器的第一端还通过所述第四开关接地，所述校准电容器的第二端接地。
  11. 根据权利要求9所述的电容检测电路，其特征在于，
    所述第一电阻的第一端接地，所述第一电阻的第二端通过第一开关与所述待测电容器的第一端相连，所述待测电容器的第一端还通过第二开关连接至电源，所述待测电容器的第二端接地；
    所述第二电阻的第一端接地，所述第二电阻的第二端通过第三开关与所述校准电容器的第一端相连，所述校准电容器的第一端还通过第四开关连接至电源，所述校准电容器的第二端接地。
  12. 根据权利要求4所述的电容检测电路，其特征在于，
    所述第一充放电电路包括第一晶体管，用于对所述待测电容器进行充电 或者放电；
    所述第二充放电电路包括第二晶体管，用于对所述校准电容器进行充电或者放电。
  13. 根据权利要求12所述的电容检测电路，其特征在于，所述第一晶体管和所述第二晶体管为N型金属氧化物半导体MOS管，
    所述第一晶体管的栅极连接至固定电平，所述第一晶体管的漏极连接至电源，所述第一晶体管的源极通过第一开关与所述待测电容器的第一端相连，所述待测电容器的第一端还通过第二开关接地，所述待测电容器的第二端接地；
    所述第二晶体管的栅极连接至固定电平，所述第二晶体管的漏极连接至电源，所述第二晶体管的源极通过第三开关与所述校准电容器的第一端相连，所述校准电容器的第一端还通过第四开关接地，所述校准电容器的第二端接地。
  14. 根据权利要求12所述的电容检测电路，其特征在于，所述第一晶体管和所述第二晶体管为P型MOS管，
    所述第一晶体管的栅极连接至固定电平，所述第一晶体管的漏极接地，所述第一晶体管的源极通过第一开关与所述待测电容器的第一端相连，所述待测电容器的第一端还通过第二开关连接至电源，所述待测电容器的第二端连接至电源；
    所述第二晶体管的栅极连接至固定电平，所述第二晶体管的漏极接地，所述第二晶体管的源极通过第三开关与所述校准电容器的第一端相连，所述校准电容器的第一端还通过第四开关连接至电源，所述校准电容器的第二端连接至电源。
  15. 根据权利要求6、7、10、11、13、14中任一项所述的电容检测电路，其特征在于，所述电容检测电路还包括控制电路，所述控制电路用于：
    在所述充电阶段，控制所述第二开关和所述第四开关闭合，以及控制所述第一开关和所述第三开关断开；
    在所述放电阶段，控制所述第一开关和所述第三开关闭合，以及控制所述第二开关和所述第四开关断开。
  16. 根据权利要求2至15中任一项所述的电容检测电路，其特征在于，T C＝2 M×T S，其中，T C为N个充放电周期的长度，2 M为N个充放电周期内采 样点的数量，T S为相邻两个采样点之间的时间间隔，M和N为正整数。
  17. 根据权利要求16所述的电容检测电路，其特征在于，所述基频为1/T C。
  18. 根据权利要求1至17中任一项所述的电容检测电路，其特征在于，所述电容检测电路还包括运算放大器，
    其中，所述运算放大器的两个输入端分别与所述待测电容器和所述校准电容器连接。
  19. 根据权利要求18所述的电容检测电路，其特征在于，所述运算放大器为连续性仪表运算放大器IA。
  20. 根据权利要求18或19所述的电容检测电路，其特征在于，所述电容检测电路还包括滤波器，
    其中，所述滤波器的输入端与所述运算放大器的输出端相连，所述滤波器的输出端与所述模数转换电路的输入端相连。
  21. 根据权利要求1至20中任一项所述的电容检测电路，其特征在于，所述待测电容器为设置在触控面板上的电容型传感器，所述电容型传感器用于检测手指在所述触控面板上的触摸信息。
  22. 根据权利要求21所述的电容检测电路，其特征在于，
    所述基频的能量值小于阈值时，表示没有手指触摸所述电容型传感器；
    所述基频的能量值大于所述阈值时，表示有手指触摸所述电容型传感器。
  23. 一种触摸检测装置，其特征在于，包括：如权利要求1至22中任一项所述的电容检测电路。
  24. 一种电子设备，其特征在于，包括：如权利要求23所述的触摸检测装置。
PCT/CN2019/098922 2019-08-01 2019-08-01 电容检测电路、触摸检测装置和电子设备 WO2021017003A1 (zh)

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