WO2021016945A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2021016945A1
WO2021016945A1 PCT/CN2019/098705 CN2019098705W WO2021016945A1 WO 2021016945 A1 WO2021016945 A1 WO 2021016945A1 CN 2019098705 W CN2019098705 W CN 2019098705W WO 2021016945 A1 WO2021016945 A1 WO 2021016945A1
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WO
WIPO (PCT)
Prior art keywords
sub
pixel
spacer
display substrate
anode
Prior art date
Application number
PCT/CN2019/098705
Other languages
English (en)
French (fr)
Inventor
刘利宾
张洁
王红丽
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2019/098705 priority Critical patent/WO2021016945A1/zh
Priority to CN201980001218.XA priority patent/CN112673476A/zh
Priority to EP19933217.2A priority patent/EP4006982A4/en
Priority to US16/957,607 priority patent/US20220384539A1/en
Priority to US16/600,316 priority patent/US11264430B2/en
Publication of WO2021016945A1 publication Critical patent/WO2021016945A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/871—Self-supporting sealing arrangements
    • H10K59/8723—Vertical spacers, e.g. arranged between the sealing arrangement and the OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different

Definitions

  • the embodiment of the present disclosure relates to a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • At least one embodiment of the present disclosure provides a display substrate, which includes: a base substrate; a plurality of sub-pixel groups arranged on the base substrate in a row direction and a column direction; and a first spacer and a second spacer.
  • a spacer and a third spacer, each of the sub-pixel groups includes a first sub-pixel, a second sub-pixel, and a third sub-pixel.
  • the first spacers are located adjacent to each other.
  • the second spacer is located between the adjacent second sub-pixel and the third sub-pixel, the third spacer Is located between the adjacent third sub-pixel and the first sub-pixel, the number of the first spacer, the number of the second spacer, and the number of the third spacer Roughly equal.
  • the first spacer, the second spacer, and the third spacer are arranged in a cycle in sequence.
  • each of the sub-pixel groups includes at most one first spacer, one second spacer, or one third spacer.
  • each of the sub-pixel groups includes one first sub-pixel, one second sub-pixel, and one third sub-pixel pair, and the third sub-pixel
  • the pair includes two third sub-pixels, in a row of the sub-pixel group, the first spacer is located between the adjacent first and second sub-pixels, and the first Two spacers are located between the adjacent second sub-pixel and the third sub-pixel pair, and the third spacer is located between the adjacent third sub-pixel pair and the first sub-pixel between.
  • the first sub-pixel, the second sub-pixel, and the third sub-pixel pair are arranged along the row direction And three sub-pixel columns are formed, and two of the third sub-pixels in the third sub-pixel pair are arranged along the column direction.
  • n is a positive integer greater than or equal to 1.
  • the sub-pixel groups in two adjacent rows are arranged staggered by 1/2 pitch, and the pitch is two adjacent sub-pixels along the row direction. The distance between the centers of the two first sub-pixels in the group.
  • the first sub-pixel is configured to emit light of a first color
  • the second sub-pixel is configured to emit light of a second color
  • the third The sub-pixels are configured to emit light of the third color.
  • the first color is blue
  • the second color is red
  • the third color is green
  • the shape of the first spacer is approximately a long strip, the extending direction of the first spacer is approximately parallel to the column direction, and the first spacer is approximately parallel to the column direction.
  • the shape of the two spacers is roughly elongated, the extending direction of the second spacer is roughly parallel to the row direction, the shape of the third spacer is roughly elongated, and the third spacer
  • the extending direction of the cushion is approximately parallel to the column direction.
  • the size of the first spacer in the column direction is smaller than the size of the first sub-pixel in the column direction
  • the size of the third spacer in the column direction is smaller than the size of the third sub-pixel pair in the column direction, the center of the first spacer and the center of the second spacer
  • the center of the third spacer, the center of the first sub-pixel, the center of the second sub-pixel, and the center of the third sub-pixel pair are approximately located on a straight line substantially parallel to the row direction .
  • the first spacer, the second spacer, and the third spacer have the same size, and the first spacer is
  • the width in the row direction is in the range of 6-15 microns
  • the length of the first spacer in the column direction is 35-45 microns
  • the first spacer is perpendicular to the substrate at the same time.
  • the height range in the direction is 1.5-2.5 microns.
  • the first sub-pixel includes a first anode and a first light-emitting functional layer
  • the second sub-pixel includes a second anode and a second light-emitting functional layer
  • the third The sub-pixel includes a third anode and a third light-emitting functional layer
  • the display substrate further includes: a pixel defining layer located at one of the first anode, the second anode, and the third anode away from the base substrate Side, and includes a first opening, a second opening, and a third opening.
  • the first opening exposes the first anode
  • the second opening exposes the second anode
  • the third opening exposes the third Anode
  • at least a part of the first light-emitting functional layer is located in the first opening and covers the exposed part of the first anode
  • at least a part of the second light-emitting functional layer is located in the second opening and covers the
  • at least a part of the third light-emitting function layer is located in the third opening and covers the exposed part of the third anode
  • the object and the third spacer are located on the surface of the pixel defining layer away from the base substrate.
  • the orthographic projection of the first spacer, the second spacer, and the third spacer on the base substrate and the The orthographic projections of the first opening, the second opening and the third opening on the base substrate do not overlap.
  • the first spacer, the second spacer, and the third spacer are formed by one mask process.
  • At least one embodiment of the present disclosure further provides a display device, including the display substrate described in any one of the above.
  • At least one embodiment of the present disclosure further provides a display substrate, which includes: a base substrate; a plurality of sub-pixel groups arranged on the base substrate in a row direction and a column direction; each of the sub-pixel groups includes a first One sub-pixel, one second sub-pixel, and one third sub-pixel pair, each of the third sub-pixel pairs includes two third sub-pixels, and the first sub-pixel includes a first anode and a first pixel drive circuit,
  • the second sub-pixel includes a second anode and a second pixel drive circuit, the third sub-pixel includes a third anode and a third pixel drive circuit, and the display substrate further includes a first flat layer located on the first Between the anode and the first pixel drive circuit, between the second anode and the second pixel drive circuit, and between the third anode and the third pixel drive circuit, the first sub The pixel includes a first via hole in the first flat layer, the second sub-pixel includes a second via hole in the first flat layer, and
  • the third via hole, the first via hole is used for the connection between the first anode and the first pixel drive circuit, and the second via hole is for the second anode and the second pixel drive circuit
  • the third via is used for the connection between the third anode and the third pixel driving circuit, and the first via, the second via, and the Part of the third via hole is substantially located on the first straight line.
  • the first straight line is substantially parallel to the row direction.
  • the first sub-pixel, the second sub-pixel, and the third sub-pixel pair are arranged along the row direction
  • the two third sub-pixels in the third sub-pixel pair are arranged along the column direction
  • the two third sub-pixels in the third sub-pixel pair are The holes are respectively located on two adjacent first straight lines.
  • the display substrate further includes: a second flat layer located between the first flat layer and the first pixel driving circuit, the second pixel driving circuit and the Between the third pixel driving circuit; a first connecting electrode, a second connecting electrode, and a third connecting electrode are located between the second flat layer and the first flat layer, the first pixel driving circuit includes a first An electrode, the second pixel driving circuit includes a second electrode, the third pixel driving circuit includes a third electrode, the first sub-pixel includes a fourth via located in the second flat layer, the first The two sub-pixels include a fifth via in the second flat layer, the third sub-pixel includes a sixth via in the second flat layer, and the fourth via is for the first electrode Connection with the first connection electrode, the fifth via hole is used for the connection between the second electrode and the second connection electrode, and the sixth via hole is used for the connection between the third electrode and the third connection electrode, The fourth via hole, the fifth via hole and a part of the sixth via hole in the sub-pixel
  • the two sixth via holes of the two third sub-pixels in the third sub-pixel pair are respectively located in the two adjacent second Two on the straight line.
  • the first straight line and the second straight line approximately overlap.
  • the fourth via, the first via, the sixth via, the third via, and the The fifth via, the second via, the sixth via, and the third via are cyclically arranged in sequence.
  • the first via, the second via, the third via, the fourth via, the fifth via, and the The sixth via holes are arranged at intervals.
  • the first via hole, the second via hole, and the third via hole are arranged at equal intervals.
  • the fourth via hole, the fifth via hole and the sixth via hole are arranged at equal intervals.
  • the distance between the first via hole and the fourth via hole is smaller than the distance between the first via hole and the second via hole
  • the distance between the second via hole and the fifth via hole is smaller than the distance between the second via hole and the third via hole
  • the distance between the third via hole and the sixth via hole The distance therebetween is smaller than the distance between the second via hole and the third via hole.
  • the first straight line is located between two adjacent rows of sub-pixel groups.
  • At least one embodiment of the present disclosure further provides a display device, including the display substrate described in any one of the above.
  • FIG. 1 is a schematic diagram of the structure of an OLED display substrate
  • FIG. 2A is a schematic diagram showing the light emission of sub-pixels in a substrate
  • FIG. 2B is a schematic diagram showing the light-emitting condition of sub-pixels in another display substrate
  • FIG. 3 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic plan view of another display substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic plan view of another display substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a sub-pixel in a display substrate according to an embodiment of the present disclosure
  • FIG. 7 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a sub-pixel in a display substrate according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a sub-pixel structure in another display substrate according to an embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of the structure of an OLED display substrate.
  • the OLED display substrate includes: a base substrate 10, a pixel driving circuit 20, a planarization layer 30, an anode 40, a pixel defining layer 50 and a spacer (PS) 60.
  • PS spacer
  • the pixel driving circuit 20 is arranged on the base substrate 10; the flat layer 30 is arranged on the side of the pixel driving circuit 20 away from the base substrate 10; the anode 40 is arranged on the side of the flat layer 30 away from the base substrate 10, and can pass flat
  • the via 35 in the layer 30 is electrically connected to the pixel driving circuit 20;
  • the pixel defining layer 50 is arranged on the side of the anode 40 away from the base substrate 10 and is formed with an opening 52, which can expose the anode 40;
  • a spacer 60 is provided On the side of the pixel defining layer 50 away from the base substrate 10.
  • the orthographic projection of the spacer 60 on the base substrate 10 and the orthographic projection of the opening 52 on the base substrate 10 do not overlap each other.
  • the opening 52 can be provided with a light-emitting layer (not shown in the figure), the light-emitting layer is arranged in contact with the anode 50, and the side of the light-emitting layer away from the anode 50 can also be provided with a cathode (not shown in the figure). It can emit light under the action of the current between the anode and the cathode.
  • the area of the anode 50 is slightly larger than the area of the opening 52, so the opening 52 can define an effective light-emitting area of a sub-pixel.
  • the spacer 60 is usually arranged on the periphery of the sub-pixel, and can play a role of supporting a fine metal mask (FMM) when the light-emitting layer is evaporated.
  • FMM fine metal mask
  • the usual spacer arrangement has the following problems: When the arrangement density of the spacer is high, the FMM placed on the spacer may scratch the spacer, causing the scratched part to be removed from the spacer. Particles fall off to form particles, which will directly bring particle risks and reduce product yield.
  • the spacer when a spacer is provided on the first lateral side of a sub-pixel, the spacer will restrict the sub-pixel
  • the light emitting angle of the first lateral side, and the second lateral side of the spacer (the second lateral side opposite to the first lateral side) of the sub-pixel without spacers does not limit the light emitting angle of the sub-pixel on the second lateral side , Resulting in that when viewed from the first and second lateral sides at the same angle as the normal of the display substrate, the brightness of the sub-pixel viewed from the first lateral side is the same as that observed from the second lateral side.
  • the brightness of the sub-pixels is different, resulting in color shifts under different viewing angles, that is, the color observed from the first lateral side is different from the color observed from the second lateral side; and, due to the separation between the periphery of the sub-pixels of different colors
  • the distribution of the cushions is different, and the sub-pixels of different colors are affected by the spacers to different degrees, which will further cause the display substrate to produce color shifts when viewing images at different viewing angles.
  • FIG. 2A is a schematic diagram showing the light emission of sub-pixels in a substrate.
  • FIG. 2B is a schematic diagram showing the light emission of sub-pixels in another display substrate.
  • 2A and 2B show the blue sub-pixel 71, the red sub-pixel 72, the pixel defining layer 50, and the spacer 60 between the blue sub-pixel 71 and the red sub-pixel 72.
  • the spacer 60 due to the blocking effect of the spacer 60, the light emitted by the blue sub-pixel 71 to the first lateral side (the left side in FIG. 2A) will be blocked by the pixel defining layer 50, and the blue The light emitted from the sub-pixel 71 to the second lateral side (the right side in FIG.
  • the spacer 60 is arranged on the pixel defining layer 50, resulting in a blue sub
  • the light emitted by the pixel 71 to the second lateral side is blocked more severely.
  • the brightness of the light emitted from the blue sub-pixel 71 to the second lateral side is smaller than the light emitted from the blue sub-pixel 71 to the first lateral side.
  • the viewing angle of the blue sub-pixel 71 on the second lateral side is smaller than the viewing angle of the blue sub-pixel 71 on the first lateral side; on the contrary, due to the blocking effect of the spacer 60 , The light emitted from the red sub-pixel 72 to the first lateral side is blocked more severely.
  • the brightness of the light emitted from the red sub-pixel 72 to the first lateral side is less than that of the red sub-pixel 72 to the second lateral side.
  • the brightness of the light also causes the viewing angle of the red sub-pixel 72 on the first lateral side to be smaller than the viewing angle of the red sub-pixel 72 on the second lateral side.
  • the brightness of the blue sub-pixel or the red sub-pixel viewed from the first lateral side is the same as that from the second lateral side.
  • the brightness of the sub-pixels observed on the lateral side is different, resulting in color shift when viewing the picture under different viewing angles, that is, the color observed from the first lateral side is different from the color observed from the second lateral side; in addition, due to blue
  • the distribution of the spacers around the color sub-pixel and the red sub-pixel is different.
  • the brightness of the light emitted by the blue sub-pixel to the second lateral side is less than the brightness of the light emitted by the blue sub-pixel to the first lateral side, while the red sub-pixel
  • the brightness of the light emitted from the pixel to the first lateral side is less than the brightness of the light emitted from the red sub-pixel to the second lateral side, which will further cause the display substrate to produce color shifts when viewing images at different viewing angles.
  • inventions of the present disclosure provide a display substrate and a display device.
  • the display substrate includes a base substrate, a plurality of sub-pixel groups, a first spacer, a second spacer, and a third spacer.
  • a plurality of sub-pixel groups are arranged along a row direction and a column direction on the base substrate, and each sub-pixel group includes a first sub-pixel, a second sub-pixel and a third sub-pixel.
  • the first spacer is located between the adjacent first and second sub-pixels
  • the second spacer is located between the adjacent second and third sub-pixels
  • the first The three spacers are located between the adjacent third sub-pixel and the first sub-pixel, and the number of first spacers, the number of second spacers, and the number of third spacers are approximately equal.
  • the number of first spacers and the number of second spacers is roughly the same as that of the third spacer.
  • the number of spacers on the first lateral side and the number of spacers on the second lateral side of each sub-pixel is also roughly the same, thereby increasing the number of spacers in a row of sub-pixel groups.
  • the brightness of a sub-pixel is roughly the same, which can improve or even eliminate the color shift when viewing the picture under different viewing angles; and, due to the number of first spacers, the number of second spacers, and the number of third spacers
  • the number is roughly the same, and the number of spacers around different sub-pixels in a row of sub-pixel groups is also roughly the same, so that different sub-pixels in a row of sub-pixel groups are blocked by the spacers, which can be further improved. Even eliminate the color cast when viewing the picture under different viewing angles
  • FIG. 3 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • the display substrate 100 includes a base substrate 110, a plurality of sub-pixel groups 120, a first spacer 131, a second spacer 132 and a third spacer 133.
  • a plurality of sub-pixel groups 120 are disposed on the base substrate 110 and arranged along the row direction and the column direction.
  • Each sub-pixel group 120 includes a first sub-pixel 121, a second sub-pixel 122 and a third sub-pixel 123.
  • the first spacer 131 is located between the adjacent first sub-pixel 121 and the second sub-pixel 122, that is, the first spacer 131 is located between the adjacent first and second sub-pixels 121 and 122.
  • the second spacer 132 is located between the adjacent second sub-pixel 122 and the third sub-pixel 123, that is, the second spacer 132 is located in the adjacent second sub-pixel 122
  • the third sub-pixel 123 is located between the adjacent third sub-pixel 123 and the first sub-pixel 121, that is, the third spacer 133 is located in the adjacent third sub-pixel
  • the space between the pixel 123 and the first sub-pixel 121; and the number of first spacers 131, the number of second spacers 132, and the number of third spacers 133 are approximately equal. It should be noted that the first sub-pixel 121 shown in FIG.
  • a pixel in the display field, usually includes multiple sub-pixels that can respectively display a single color (such as red, green, or blue). The ratio of sub-pixels of different colors is controlled to achieve different colors. Therefore, the above-mentioned first A sub-pixel may be a single-color sub-pixel.
  • the display substrate provided by the embodiment of the present disclosure, for one sub-pixel (for example, the first sub-pixel 121, the second sub-pixel 122, or the third sub-pixel 123) in a row of the sub-pixel group 120, due to the first partition
  • the number of spacers 131, the number of second spacers 132, and the number of third spacers 133 are approximately equal, and the number of spacers on the first lateral side and the number of spacers on the second lateral side of each sub-pixel is also Substantially the same, thereby improving the symmetry of the influence of the spacers in a row of sub-pixel groups on the light-emitting conditions of the sub-pixels, so that the first and second lateral sides are at the same angle as the normal of the display substrate
  • the brightness of one sub-pixel in a row of sub-pixel groups observed from the first lateral side and the second lateral side is approximately the same, which can improve or even eliminate the color shift when viewing pictures at different viewing angles.
  • the brightness of the light emitted to the first lateral side from the 100 first sub-pixels 121 provided with the third spacer 133 on the first lateral side is smaller than the brightness of the light emitted to the second lateral side;
  • the brightness of the light emitted to the second lateral side from the 100 first sub-pixels 121 provided with the first spacer 131 on the second lateral side is less than the brightness of the light emitted to the first lateral side;
  • the first sub-pixel 121 as a whole, the brightness of the light emitted by the first sub-pixels 121 to the second lateral side is approximately equal to the brightness of the light emitted by the first sub-pixels 121 to the first lateral side, thereby improving , And even eliminate the color cast when viewing the picture under different viewing angles.
  • the number of first spacers 131, the number of second spacers 132, and the number of third spacers 133 are equal, which can be better improved. Even eliminate the color cast when viewing the picture under different viewing angles.
  • FIG. 4 is a schematic plan view of a display substrate provided according to an embodiment of the present disclosure.
  • the display substrate 100 includes a base substrate 110, a plurality of sub-pixel groups 120, a first spacer 131, a second spacer 132 and a third spacer 133.
  • a plurality of sub-pixel groups 120 are arranged on the base substrate 110 and arranged in the row direction and the column direction.
  • Each sub-pixel group 120 includes a first sub-pixel 121, a second sub-pixel 122, and a third sub-pixel pair 126.
  • the three sub-pixel pairs 126 include two third sub-pixels 123.
  • the first spacer 131 is located between the adjacent first sub-pixel 121 and the second sub-pixel 122, that is, the first spacer 131 is located between the adjacent first and second sub-pixels 121 and 122.
  • the interval area between two sub-pixels 122; the second spacer 132 is located between the adjacent second sub-pixel 122 and the third sub-pixel pair 126, that is, the second spacer 132 is located in the adjacent second sub-pixel 122 and the third sub-pixel pair 126; the third spacer 133 is located between the adjacent third sub-pixel pair 126 and the first sub-pixel 121, that is, the third spacer 133 is located adjacent
  • the spacing area between the third sub-pixel pair 126 and the first sub-pixel 121; and, the number of first spacers 131, the number of second spacers 132, and the number of third spacers 133 are approximately equal. It should be noted that the first sub-pixel 121 shown in FIG.
  • a pixel usually includes multiple sub-pixels that can respectively display a single color (such as red, green, or blue). The ratio of sub-pixels of different colors is controlled to achieve different colors. Therefore, the above-mentioned first A sub-pixel may be a single-color sub-pixel.
  • the display substrate provided by the embodiment of the present disclosure, for one sub-pixel (for example, the first sub-pixel 121, the second sub-pixel 122, or the third sub-pixel 123) in a row of the sub-pixel group 120, due to the first partition
  • the number of spacers 131, the number of second spacers 132, and the number of third spacers 133 are approximately equal, and the number of spacers on the first lateral side and the number of spacers on the second lateral side of each sub-pixel is also Substantially the same, thereby improving the symmetry of the influence of the spacers in a row of sub-pixel groups on the light-emitting conditions of the sub-pixels, so that the first and second lateral sides are at the same angle as the normal of the display substrate
  • the brightness of one sub-pixel in a row of sub-pixel groups observed from the first lateral side and the second lateral side is approximately the same, which can improve or even eliminate the color shift when viewing pictures at different viewing angles.
  • the brightness of the light emitted to the first lateral side from the 100 first sub-pixels 121 provided with the third spacer 133 on the first lateral side is smaller than the brightness of the light emitted to the second lateral side;
  • the brightness of the light emitted to the second lateral side from the 100 first sub-pixels 121 provided with the first spacer 131 on the second lateral side is less than the brightness of the light emitted to the first lateral side;
  • the first sub-pixel 121 as a whole, the brightness of the light emitted by the first sub-pixels 121 to the second lateral side is approximately equal to the brightness of the light emitted by the first sub-pixels 121 to the first lateral side, thereby improving , And even eliminate the color cast when viewing the picture under different viewing angles.
  • the display substrate provided by the embodiment of the present disclosure, for one sub-pixel (for example, the first sub-pixel 121, the second sub-pixel 122, or the third sub-pixel 123) in a row of the sub-pixel group 120, the The number of spacers 131, the number of second spacers 132, and the number of third spacers 133 are approximately the same, and the number of spacers around different sub-pixels in a row of sub-pixel groups 120 is also approximately the same, so that Different sub-pixels in a row of sub-pixel groups 120 are blocked by spacers (for example, the first spacer 131, the second spacer 132, and the third spacer 133) are also substantially the same, that is, a row of sub-pixel groups
  • the conditions of the first sub-pixel 121, the second sub-pixel 122 and the third sub-pixel 123 being blocked by spacers in 120 are also approximately the same, which can further improve or even eliminate the color shift when viewing images under different viewing angles. As a result, the display
  • the number of first spacers, the number of second spacers, and the number of third spacers mentioned above are approximately equal, which may refer to the number of first spacers, the number of second spacers, and the third spacer.
  • the ratio of the number of cushions to the number of first spacers, the number of second spacers, and the average value of the third spacers is in the range of 0.9-1.1.
  • first spacer, second spacer, and third spacer can be made of polyimide.
  • the embodiments of the present disclosure include but are not limited thereto, and the above-mentioned first spacer, second spacer, and third spacer can also be made of other materials such as silicone.
  • first spacer, second spacer, and third spacer can also be made of materials with higher light transmittance, thereby reducing the first spacer, second spacer, and third spacer.
  • the blocking effect of the cushion on the light can also be made of materials with higher light transmittance, thereby reducing the first spacer, second spacer, and third spacer. The blocking effect of the cushion on the light.
  • the first spacer 131, the second spacer 132, and the third spacer 133 are arranged cyclically in sequence.
  • the first spacer 131, the second spacer 132, and the third spacer 133 are repeated as a group. Therefore, in a row of sub-pixel groups 120, in a certain area, it can be ensured that the number of first spacers 131, the number of second spacers 132, and the number of third spacers 133 are approximately equal, so that To further improve, even eliminate the color cast when viewing the picture under different viewing angles.
  • a row of sub-pixel group 120 is divided into N (N is a positive integer greater than or equal to 1) regions arranged in sequence, and each region includes M (M is a positive integer greater than or equal to 1) above-mentioned first spacers. 131, the second spacer 132, and the third spacer 133; at this time, for each region, the spacer on the first lateral side and the spacer on the second lateral side of each sub-pixel.
  • N is a positive integer greater than or equal to 1
  • M is a positive integer greater than or equal to 1 above-mentioned first spacers.
  • M is a positive integer greater than or equal to 1
  • the number of objects is also approximately the same, thereby improving the symmetry of the effect of the spacers in the area on the light-emitting conditions of the sub-pixels, so that the normal line of the display substrate is the same from the first and second lateral sides.
  • the brightness of a sub-pixel in the area observed from the first lateral side and the second lateral side is approximately the same, which can be further improved and even avoided the color shift caused by uneven distribution of spacers .
  • the number of spacers around different sub-pixels in each area is approximately the same, so that different sub-pixels in each area
  • the condition of being blocked by spacers is also roughly the same, which can be further improved, and even eliminate the color cast when viewing the picture under different viewing angles.
  • each sub-pixel group 120 includes at most one first spacer 131, one second spacer 132 or one third spacer 133, thereby reducing the Density, and then control the particle risk.
  • each sub-pixel group 120 the first sub-pixel 121, the second sub-pixel 122, and the third sub-pixel pair 126 are arranged along the row direction and form three sub-pixel columns 128.
  • Two third sub-pixels 123 in one third sub-pixel pair 126 are arranged along the column direction. That is, each sub-pixel group 120 may include three sub-pixel columns 128. Therefore, the pixel arrangement structure of the display substrate can apply pixel borrowing technology, so that the resolution of the display substrate can be improved.
  • the spacer 131 and the second spacer 132 are separated by 1+3n sub-pixel columns 128, and the second spacer 132 and the third spacer 133 are separated by 1+3n sub-pixel rows 128, and the third spacer 133 and the first spacer 131 are separated by 1+3n sub-pixel rows 128, and n is a positive value greater than or equal to 1.
  • the spacer has two functions: one function is to support the FMM for evaporation, and the other function is to support the cover plate during packaging.
  • the display substrate provided in this example can ensure that the number of first spacers 131, the number of second spacers 132, and the number of third spacers 133 in a row of sub-pixel groups 120 are approximately equal.
  • the display substrate provided in this example can further reduce the density of spacers, thereby reducing the risk of particles when supporting the FMM for evaporation, Improve product yield.
  • the value of n can be set according to the needs of supporting FMM and reducing the risk of particles.
  • two adjacent rows of sub-pixel groups 120 are arranged staggered by 1/2 pitch, and the pitch is the first two of the two adjacent sub-pixel groups 120 in the row direction.
  • the pitch may also be the distance between the centers of two second sub-pixels 122 or third sub-pixel pairs 126 in two sub-pixel groups 120 adjacent in the row direction; the above-mentioned center may be a sub-pixel The geometric center of the pixel.
  • the two adjacent rows of sub-pixel groups 120 are arranged shifted by 1/2 pitch in the row direction.
  • the embodiments of the present disclosure include, but are not limited to, two adjacent rows of sub-pixel groups 120 that are arranged at other distances that are offset.
  • the first sub-pixel 121 is configured to emit light of a first color
  • the second sub-pixel 122 is configured to emit light of a second color
  • the third sub-pixel 123 is configured to emit light of the second color.
  • the embodiments of the present disclosure include but are not limited thereto.
  • One third sub-pixel in the third sub-pixel pair may be configured to emit light of a third color
  • the other third sub-pixel in the third sub-pixel pair The sub-pixels may be configured to emit light of the fourth color.
  • the first color is blue
  • the second color is red
  • the third color is green. Therefore, the display substrate adopts a red, green and blue color scheme; of course, the present disclosure includes but is not limited to this, and the display substrate may also adopt other color schemes.
  • the shape of the effective light-emitting area of the first sub-pixel 121 is approximately a hexagon or an ellipse, and the long axis of symmetry of the hexagon or the long axis of the ellipse is approximately parallel to the column direction. .
  • the shape of the effective light-emitting area of the second sub-pixel 122 is also approximately a hexagon or an ellipse, and the long axis of symmetry of the hexagon or the ellipse is approximately equal to the column direction. parallel.
  • the shape of the effective light-emitting area of the third sub-pixel 123 is approximately a pentagon, and the right-angled sides of the pentagon are approximately parallel to the row direction.
  • the above-mentioned effective light-emitting area is generally designed in a regular shape, such as the above-mentioned hexagon, pentagon, or ellipse.
  • the shape of the formed effective light-emitting area generally has a certain deviation from the regular shape designed above.
  • the corners of the aforementioned regular shape may become rounded corners. Therefore, the shape of the effective light-emitting area (for example, the first effective light-emitting area, the second effective light-emitting area, or the third effective light-emitting area) may be a rounded corner pattern.
  • the shape of the actual manufactured effective light-emitting area may also have other changes from the designed shape.
  • the shape of the effective light-emitting area designed as a hexagon may become approximately elliptical in actual manufacturing.
  • the shape of the first spacer 131 is substantially elongated, the extending direction of the first spacer 131 is substantially parallel to the column direction, and the shape of the second spacer 132 It is roughly elongated, the extension direction of the second spacer 132 is roughly parallel to the column direction, the shape of the third spacer 133 is roughly elongated, and the extension direction of the third spacer 133 is roughly parallel to the listed direction . Therefore, since the sub-pixels are usually also elongated (hexagonal or elliptical), the display substrate can make full use of the space or gap between the sub-pixels.
  • the shape of the aforementioned spacer is the shape of the orthographic projection of the spacer on the base substrate.
  • shape of the effective light-emitting area of the aforementioned sub-pixel is the shape of the orthographic projection of the sub-pixel on the base substrate.
  • the elongated shape means that the length in one direction is greater than the length in the other direction, or the size in one direction is greater than the size in other directions.
  • the bar shape is not limited to a rectangle, and may have other shapes, for example, it may be a long hexagon, an oblong, a trapezoid or other shapes.
  • the size of the first spacer 131 in the column direction is smaller than the size of the first sub-pixel 121 in the column direction
  • the second spacer 132 and the third spacer 133 are The size in the column direction is smaller than the size of the third sub-pixel pair 126 in the column direction, the center of the first spacer 131, the center of the second spacer 132, the center of the third spacer 133, and the size of the first sub-pixel 121
  • the center, the center of the second sub-pixel 122, and the center of the third sub-pixel pair 126 are approximately located on a straight line substantially parallel to the row direction.
  • the first spacer 131, the second spacer 132, and the third spacer 133 have the same size, and the width range of the first spacer 131 in the row direction
  • the length of the first spacer 131 along the column direction is in the range of 35-45 ⁇ m
  • the height of the first spacer 131 in the direction perpendicular to the row direction and the column direction is 1.5- 2.5 microns.
  • the height of the first spacer 131 in a direction perpendicular to both the row direction and the column direction is 2 micrometers.
  • the effective light-emitting area of the first sub-pixel 121 has a size range of 15-23 microns in the row direction and a size of 35-45 microns in the column direction;
  • the size range in the row direction is 11-21 microns, and the size in the column direction is 35-45 microns;
  • the effective light-emitting area of the third sub-pixel 123 has a size range of 9-13 microns in the row direction, and the size in the column direction It is 9-13 micrometers; in a third sub-pixel pair 116, the shortest distance between two third sub-pixels 113 ranges from 13-15 micrometers.
  • FIG. 5 is a schematic plan view of another display substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a sub-pixel in a display substrate according to an embodiment of the present disclosure.
  • FIG. 5 only shows one sub-pixel group.
  • the first sub-pixel 121 includes a first anode 1212 and a first light-emitting functional layer 1214
  • the second sub-pixel 122 includes a second anode 1222 and a second light-emitting functional layer 1224.
  • the third sub-pixel 123 includes a third anode 1232 and a third light-emitting function layer 1234. As shown in FIGS.
  • the display substrate further includes: a pixel defining layer 160 located on the side of the first anode 1212, the second anode 1222, and the third anode 1232 away from the base substrate 110, the pixel defining layer 160 includes the first The opening 171, the second opening 172 and the third opening 173, the first opening 171 exposes the first anode 1212, the second opening 172 exposes the second anode 1222, and the third opening 173 exposes the third anode 1232.
  • At least a part of the first light-emitting functional layer 1214 is located in the first opening 171 and covers the exposed part of the first anode 1212
  • at least a part of the second light-emitting functional layer 1224 is located in the second opening 172 and covers the exposed part of the second anode 1222
  • the third At least a part of the light-emitting function layer 1234 is located in the third opening 173 and covers the exposed portion of the third anode 1232.
  • the first spacer 131, the second spacer 132 and the third spacer 133 are located in the pixel defining layer 160 away from the substrate On the surface of the substrate 110.
  • the area of the first anode 1212 may be slightly larger than the area of the first light-emitting function layer 1214.
  • the first light-emitting functional layer 1214 may include the electroluminescent layer itself and other functional layers located on both sides of the electroluminescent layer, such as a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer.
  • the area of the second anode 1222 may be slightly larger than the area of the second light-emitting function layer 1224.
  • the second light-emitting functional layer 1224 may include the electroluminescent layer itself and other functional layers located on both sides of the electroluminescent layer, such as a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer.
  • the area of the third anode 1232 may be slightly larger than the area of the third light-emitting function layer 1234.
  • the third light-emitting functional layer 1234 may include the electroluminescent layer itself and other functional layers located on both sides of the electroluminescent layer, such as a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer.
  • the orthographic projection of the first spacer 131, the second spacer 132, and the third spacer 133 on the base substrate 101 is the same as the first opening 171, the second opening 172, and the third opening.
  • the orthographic projection of 173 on the base substrate 101 does not overlap.
  • the orthographic projection of the first opening 171 on the base substrate 101 is completely within the orthographic projection of the first anode 1212 on the base substrate 101; the orthographic projection of the second opening 172 on the base substrate 101 It is completely located in the orthographic projection of the second anode 1222 on the base substrate 101; the orthographic projection of the third opening 173 on the base substrate 101 is completely located in the orthographic projection of the third anode 1232 on the base substrate 101.
  • the orthographic projection of the first opening 171 on the base substrate 101 is completely within the orthographic projection of the first light-emitting function layer 1214 on the base substrate 101; the second opening 172 is on the base substrate 101.
  • the orthographic projection is completely located within the orthographic projection of the second light-emitting functional layer 1224 on the base substrate 101; the orthographic projection of the third opening 173 on the base substrate 101 is completely located on the front of the third light-emitting functional layer 1234 on the base substrate 101 Within the projection.
  • the edge of the orthographic projection of the first anode 1212 on the base substrate 101, the edge of the orthographic projection of the second anode 1222 on the base substrate 101, and the edge of the third anode 1232 on the base substrate 101 is covered by the orthographic projection of the pixel defining layer 160 on the base substrate 101.
  • the first light-emitting functional layer 1214 may also partially cover the pixel defining layer 160
  • the second light-emitting functional layer 1224 may also partially cover the pixel defining layer 160
  • the third light-emitting functional layer 1234 may partially cover the pixel defining layer 160. Covers the pixel defining layer 160.
  • the first spacer 131, the second spacer 132, and the third spacer 133 are formed by one mask process.
  • a spacer layer may be formed on the surface of the pixel defining layer 160 away from the base substrate 110, and then the spacer layer may be patterned by a patterning process to form the first spacer 131 and the second spacer. 132 and the third spacer 133.
  • the first spacer 131, the second spacer 132, and the third spacer 133 and the pixel defining layer 160 are also formed by a mask process.
  • the first spacer 131, the second spacer 132, the third spacer 133 and the pixel defining layer 160 may be made of the same material.
  • At least one embodiment of the present disclosure further provides a display device including the above-mentioned display substrate. Therefore, the display device can take into account the density of the spacer and improve the color shift. On the one hand, it can improve or even eliminate the color shift when viewing the picture under different viewing angles. On the other hand, it can also reduce the density of the spacer, thereby controlling Particle risk, improve product yield.
  • the display device adopts the display panel with the pixel arrangement structure provided in the embodiments of the present disclosure
  • the resolution of the display device can be further improved, and a display device with real high resolution can be provided.
  • the pixel arrangement structure provided by the embodiments of the present disclosure can have better symmetry, furthermore, the uniformity of pixel distribution can be improved, and the display effect of the display device can be improved.
  • the display device may be any product or component with a display function, such as a smart phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a smart phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • FIG. 7 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a sub-pixel in a display substrate according to an embodiment of the present disclosure.
  • the display substrate includes a base substrate 110 and a plurality of sub-pixel groups 120.
  • a plurality of sub-pixel groups 120 are arranged on the base substrate 110 and arranged in the row direction and the column direction.
  • Each sub-pixel group 120 includes a first sub-pixel 121, a second sub-pixel 122, and a third sub-pixel pair 126.
  • the three sub-pixel pairs 126 include two third sub-pixels 123.
  • FIG. 7 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a sub-pixel in a display substrate according to an embodiment of the present disclosure.
  • the display substrate includes a base substrate 110 and a plurality of sub-pixel groups 120.
  • the first sub-pixel 121 includes a first anode 1212 and a first pixel driving circuit 1216
  • the second sub-pixel 122 includes a second anode 1222 and a second pixel driving circuit 1226
  • the third sub-pixel 123 includes a third The anode 1232 and the third pixel driving circuit 1236.
  • the display substrate further includes a first flat layer 140, which is located between the first anode 1212 and the first pixel driving circuit 1216, between the second anode 1222 and the second pixel driving circuit 1226, and the third anode 1232 And the third pixel drive circuit 1236.
  • the first sub-pixel 121 includes a first via hole 141 in the first flat layer 140
  • the second sub-pixel 122 includes a second via hole 142 in the first flat layer 140
  • the third sub-pixel 123 includes a first via hole 141 in the first flat layer 140.
  • the third via 143 is used to connect the first anode 1212 and the first pixel drive circuit 1216, the second via 142 is used to connect the second anode 1222 and the second pixel drive circuit 1226, the first
  • the three vias 143 are used to connect the third anode 1232 and the third pixel driving circuit 1236; the first vias 141, the second vias 142, and part of the third vias 143 in the sub-pixel group 120 in a row are approximately in the same straight line on.
  • the connection part of the first anode can cover and fill the corresponding first via to connect to the corresponding first pixel driving circuit; the connection part of the second anode can cover and fill the corresponding first via.
  • Two via holes are connected to the corresponding second pixel drive circuit; the connection part of the third anode can cover and fill the corresponding third via hole, thereby being connected to the corresponding third pixel drive circuit.
  • the first via 141, the second via 142, and a part of the third via 143 in a row of sub-pixel groups 120 are approximately located on the first straight line, that is, the first A via 141, a second via 142 and a part of the third via 143 are arranged in a row, and the pitch is one sub-pixel distance. Therefore, when the process margin changes, the first via 141, the second via 142, and a part of the third via 143 can move up and down at the same time, thereby facilitating the control of the process deviation.
  • the first via 141, the second via 142, and part of the third via 143 move up and down at the same time. Process deviations are controlled. It should be noted that when the first via 141, the second via 142, and a part of the third via 143 have defects, these defects are easily detected, so that the process can be adjusted in time.
  • the first via 141 of the first sub-pixel 121 and the first via 141 of the second sub-pixel 122 in any two adjacent sub-pixel groups 120 in a row of sub-pixel groups 120 The second via 142 and the third via 143 of a third sub-pixel 123 in the third pixel pair 126 are approximately located on the same straight line. Therefore, when the process margin changes, the first via 141, the second via 142, and the third via 143 can move up and down at the same time, thereby facilitating the control of the process deviation.
  • the above-mentioned first straight line does not overlap the effective light-emitting area of each sub-pixel (for example, the first sub-pixel, the second sub-pixel, and the third sub-pixel).
  • the aforementioned first straight line is not located in the overlapping area of the organic layer and the anode of each sub-pixel.
  • the aforementioned first straight line is located between adjacent pixel group rows.
  • the first line in which the first via 141, the second via 142 and a part of the third via 143 in the sub-pixel group 120 in a row are located is substantially parallel to the row direction.
  • the first sub-pixel 121, the second sub-pixel 122, and the third sub-pixel pair 126 are arranged in the row direction, and the third sub-pixel pair 126
  • the two third sub-pixels 123 in the pair are arranged along the column direction, and the two third via holes of the two three-sub-pixels in the third sub-pixel pair are respectively located on two adjacent first straight lines.
  • one of the two third via holes 143 of the two third sub-pixels 123 arranged in the column direction in the third sub-pixel pair 126 and the sub-pixel group row to which the third sub-pixel pair 126 belongs may be
  • the first via 141 and the second via 142 in the Nth sub-pixel group row are located on the same straight line, and the other sub-pixel group row is adjacent to the sub-pixel group row to which the third sub-pixel pair 126 belongs
  • the first via 141 and the second via 142 (which can be recorded as the N-1th sub-pixel group row) are located on the same straight line.
  • the first pixel driving circuit 1216 may include a first active layer 12161, a first gate insulating layer 12162, a first gate 12163, a first interlayer insulating layer 12164, and The first source and drain electrode layer 12165;
  • the second pixel driving circuit 1226 may include a second active layer 12261, a second gate insulating layer 12262, a second gate 12263, a second interlayer insulating layer 12264, and a second source and drain electrode Layer 12265;
  • the third pixel driving circuit 1236 may include a third active layer 12361, a third gate insulating layer 12362, a third gate 12363, a third interlayer insulating layer 12364, and a third source and drain electrode layer 12365.
  • the source and drain in the first source and drain electrode layer 12165 pass through the via holes in the first gate insulating layer 12162 and the first interlayer insulating layer 12164 and the source and drain regions of the first active layer 12161 The regions are respectively connected; the orthographic projection of the first gate electrode 12163 on the base substrate 101 and the orthographic projection of the channel region of the first active layer 12161 on the base substrate 101 overlap each other.
  • the source and drain in the second source and drain electrode layer 12265 pass through the via holes in the second gate insulating layer 12262 and the second interlayer insulating layer 12264 and the source and drain regions of the second active layer 12261 respectively Connected; the orthographic projection of the second gate 12263 on the base substrate 101 and the orthographic projection of the channel region of the second active layer 12261 on the base substrate 101 overlap each other.
  • the source and drain in the third source and drain electrode layer 12365 pass through the via holes in the third gate insulating layer 12362 and the third interlayer insulating layer 12364 and the source region and the drain region of the third active layer 12361, respectively.
  • the first active layer 12161, the second active layer 12261, and the third active layer 12361 may be made of the same semiconductor layer; for example, the first active layer 12161, the second active layer 12261, and the The third active layer 12361 may use materials such as polysilicon, single crystal silicon, and oxide semiconductor.
  • the first gate insulating layer 12162, the second gate insulating layer 12262, and the third gate insulating layer 12362 are the same gate insulating layer; for example, the first gate insulating layer 12162, the second gate insulating layer
  • the polar insulating layer 12262 and the third gate insulating layer 12362 can be made of insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride.
  • the first gate 12163, the second gate 12263, and the third gate 12363 may be made of the same conductive layer; for example, the first gate 12163, the second gate 12263, and the third gate 12363 It can be made of conductive materials such as molybdenum, titanium, aluminum, and copper.
  • the first interlayer insulating layer 12164, the second interlayer insulating layer 12264, and the third interlayer insulating layer 12364 are the same interlayer insulating layer; the first interlayer insulating layer 12164, the second interlayer insulating layer
  • the layer 12264 and the third interlayer insulating layer 12364 can be made of insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride.
  • the first source-drain electrode layer 12165, the second source-drain electrode layer 12265, and the third source-drain electrode layer 12365 may be made of the same conductive layer; for example, the first source-drain electrode layer 12165, the second source and drain electrode layer 12165
  • the drain electrode layer 12265 and the third source and drain electrode layer 12365 may be made of materials such as aluminum, titanium, copper, and molybdenum.
  • FIG. 9 is a schematic diagram of a sub-pixel structure in another display substrate according to an embodiment of the present disclosure.
  • the display substrate further includes: a second flat layer 150 located between the first flat layer 140 and the first pixel driving circuit 1216, the second pixel driving electrode 1226, and the third pixel driving circuit 1236.
  • the pixel driving circuit 1216 includes a first electrode 181, the second pixel driving circuit 1226 includes a second electrode 182, and the third pixel driving circuit 1236 includes a third electrode 183; the display substrate also includes a first connection electrode 191 and a second connection electrode 192 And the third connecting electrode 193 are located between the second planar layer 150 and the first planar layer 140, the first sub-pixel 121 further includes a fourth via 151 located in the second planar layer 150, and the second sub-pixel 122 further includes The fifth via 152 located in the second planar layer 150, the third sub-pixel 123 further includes a sixth via 153 located in the second planar layer 150, the fourth via 151 is used for the first electrode 181 and the first connection The connection of the electrode 191, the fifth via 152 is used for the connection of the second electrode 182 and the second connection electrode 192, the sixth via 153 is used for the connection of the third electrode 183 and the third connection electrode 193, a row of sub-pixel groups 120 The fourth via hole 151, the fifth via hole
  • the fourth via 151, the fifth via 152, and a part of the sixth via 153 in the sub-pixel group 120 in a row are approximately located on the second straight line, that is, the fourth The via 151, the fifth via 152, and a part of the sixth via 153 are arranged in a row, and the pitch is one sub-pixel distance. Therefore, when the process margin changes, the fourth via 151, the fifth via 152, and a part of the sixth via 153 can move up and down at the same time, thereby facilitating the control of the process deviation.
  • the fourth via 151, the fifth via 152, and the sixth via 153 move up and down at the same time. Deviations are controlled. It should be noted that when the fourth via 151, the fifth via 152, and the sixth via 153 have defects, these defects are easily detected, so that the process can be adjusted in time.
  • the fourth via 151 of the first sub-pixel 121 and the fourth via 151 of the second sub-pixel 122 in any two adjacent sub-pixel groups 120 in a row of sub-pixel groups 120 The fifth via 152 and the sixth via 153 of one third sub-pixel 123 in the third sub-pixel pair 126 are approximately located on the second straight line. Therefore, when the process margin changes, the fourth via 151, the fifth via 152, and the sixth via 153 can move up and down at the same time, thereby facilitating the control of the process deviation.
  • the two sixth via holes 153 of the two third sub-pixels 123 in the third sub-pixel pair 126 are respectively located on two adjacent second straight lines. That is to say, one of the two sixth via holes 153 of the two third sub-pixels 123 arranged in the column direction in the third sub-pixel pair 126 and the sub-pixel group row to which the third sub-pixel pair 126 belongs (may be The fourth via 151 and the fifth via 152 in the Nth sub-pixel group row are located on the same straight line, and the other sub-pixel group row is adjacent to the sub-pixel group row to which the third sub-pixel pair 126 belongs The fourth via 151 and the fifth via 152 (which can be recorded as the N-1th sub-pixel group row) are located on the same straight line.
  • the first straight line and the second straight line in a row of sub-pixel group 120 approximately overlap, such as the same straight line; that is, the first straight line in a row of sub-pixel group 120
  • the hole 141, the second via 142, a portion of the third via 143, the fourth via 151, the fifth via 152, and a portion of the sixth via 153 are substantially on the same straight line.
  • the first via 141, the second via 142, a part of the third via 143, the fourth via 151, the fifth via 152, and a part of the sixth via 153 can move up and down at the same time , So as to facilitate the control of process deviation.
  • the first via 141, the second via 142, part of the third via 143, the fourth via 151, the fifth via 152 and part of the sixth via The holes 153 move up and down at the same time, and either all have defects or no defects, so as to facilitate the control of the process deviation. It should be noted that when the first via 141, the second via 142, part of the third via 143, the fourth via 151, the fifth via 152, and the part of the sixth via 153 all have defects, these defects It is easy to be detected, so that the process can be adjusted in time.
  • the first via 141 and the fourth via 151 of the first sub-pixel 121 in any two adjacent sub-pixel groups 120 in a row of sub-pixel groups 120 are approximately located on the same straight line. Therefore, when the process margin changes, the first via 141, the second via 142, the third via 143, the fourth via 151, the fifth via 152, and the sixth via 153 It can move up and down at the same time to facilitate the control of process deviation.
  • the first via 141, the second via 142, the third via 143, the fourth via 151, the fifth via 152, and the The orthographic projections of the sixth via 153 on the base substrate 110 do not overlap each other.
  • the first via 141, the second via 142 and the third via 143 in a row of the sub-pixel group 120 are arranged at equal intervals.
  • the fourth via 151, the fifth via 152 and the sixth via 153 in a row of the sub-pixel group 120 are arranged at equal intervals.
  • the distance between the fourth via 151 and the first via 141, the distance between the fifth via 152 and the second via 142, the sixth via 153 and the third via 143 is roughly equal.
  • the aforementioned distance between the fourth via 151 and the first via 141 refers to the shortest distance between the fourth via 151 and the first via 141 in the same first sub-pixel
  • the aforementioned distance between the fifth via 152 and the second via 142 refers to the shortest distance between the fifth via 152 and the second via 142 in the same second sub-pixel
  • the distance between 153 and the third via 143 refers to the shortest distance between the sixth via 153 and the third via 143 in the same third sub-pixel.
  • the distance between the first via 141 and the fourth via 151 is smaller than the distance between the first via 141 and the second via 142, and the second via 142 and the fifth via 152 The distance between is smaller than the distance between the second via 142 and the third via 143, and the distance between the third via 143 and the sixth via 153 is smaller than the distance between the second via 142 and the third via 143 the distance.
  • the arrangement of the first sub-pixel 121, the second sub-pixel 122, and the third sub-pixel 123 in each sub-pixel group 120 may refer to the pixel in the display substrate shown in FIG.
  • the first via 141, the second via 142 and the third via 143 in the sub-pixel group 120 of one row are located between two adjacent rows of the sub-pixel group 120.
  • the first sub-pixel 121, the second sub-pixel 122, and the third sub-pixel pair including two third sub-pixels 123 are along the row direction.
  • the two third sub-pixels 123 in the third sub-pixel pair are arranged along the column direction.
  • the third via 143 and the sixth via 153 located on the same straight line need to provide electrical connections for the anode and the pixel drive circuit in the third sub-pixels in the two rows of pixel groups adjacent to the straight line.
  • the fourth via 151, the first via 141, the sixth via 153, the third via 143, the fifth via 152, the second via 142, the sixth via 153, and the third via 143 Set in turn.
  • the fourth via 151, the first sub-pixel 121 is a blue sub-pixel
  • the second sub-pixel 122 is a red sub-pixel
  • the third sub-pixel 123 is a green sub-pixel
  • the fourth via 151, the first The via 141, the sixth via 153, the third via 143, the fifth via 152, the second via 142, the sixth via 153, and the third via 143 are cyclically arranged in sequence; at this time, the fourth via 151 and the first via 141 provide electrical connection for the pixel driving circuit and the anode of the blue sub-pixel in the first row, and the fifth via 152 and the second via 142 are the pixel driving circuit and the red sub-pixel of the first row.
  • the anode provides electrical connection.
  • the sixth via 153 and the third via 143 of the first group provide electrical connection for the pixel driving circuit of the green sub-pixel in the second row and the anode.
  • the sixth via 153 and the third via of the second group The hole 143 provides electrical connection for the pixel driving circuit of the green sub-pixel in the first row and the anode.
  • the distance between the fourth via 151 and the first via 141 is smaller than the distance between the first via 141 and the second via 142; the fifth via 152
  • the distance from the second via hole 142 is smaller than the distance between the first via hole 141 and the second via hole 142; the distance between the sixth via hole 153 and the third via hole 142 is smaller than the distance between the first via hole 141 and the second via hole 142.
  • the first anode 1212 further includes a first connection electrode block 12125. In the row direction, the first connection electrode block 12125 is located on the side of the first anode 1212 away from the second sub-pixel 122.
  • the first connection electrode The block 12125 is electrically connected to the first pixel driving electrode 1216 through the first via 141; the second anode 1222 further includes a second connecting electrode block 12225, and the second connecting electrode block 12225 is connected to the second pixel driving electrode through the second via 142 1226 is electrically connected, the third anode 1232 further includes a second connecting electrode block 12325, and the second connecting electrode block 12325 is electrically connected to the third pixel driving electrode 1236 through the third via 143.
  • the first via hole 141 and the fourth via hole 151 are located at the main body portion (the portion overlapping the first effective light-emitting area) of the first anode 1212 away from the adjacent second
  • the fourth via hole 151 is located on the side of the first via hole 141 away from the main body portion of the adjacent first anode 1212.
  • the second via 142 is located directly below the main body portion of the second anode 1222, that is, the orthographic projection of the second via 132 in the row direction and the second anode 1222 The orthographic projections of the main body part in the row direction overlap.
  • the fifth via 152 is located on the side of the second via 142 away from the adjacent third sub-pixel pair 126.
  • the two third via holes 143 of the third sub-pixel pair 126 are respectively located on two adjacent first straight lines, and the two third via holes 143 are respectively It is located on the upper and lower sides of the third sub-pixel pair 126, that is, the orthographic projection of the two third via holes 143 in the row direction overlaps the orthographic projection of the third sub-pixel pair 126 in the row direction.
  • the sixth via 153 is located on the side of the corresponding third via 143 away from the adjacent first sub-pixel 121.
  • An embodiment of the present disclosure also provides a display device.
  • the display device includes the above-mentioned display substrate. Since the first via 141, the second via 142, and the third via 143 in a row of the sub-pixel group 120 are substantially on the same straight line, that is, the first via 141, the second via 142, and the third via The via holes 143 are arranged in a row, and the pitch is one sub-pixel distance. Therefore, when the process margin changes, it is convenient to control the process deviation.
  • the display device adopts the display panel with the pixel arrangement structure provided in the embodiments of the present disclosure, the resolution of the display device can be further improved, and a display device with real high resolution can be provided.
  • the display device may be any product or component with a display function, such as a smart phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

Abstract

一种显示基板和显示装置。该显示基板(100)包括衬底基板(110)、多个子像素组(120)，在衬底基板(110)上且沿行方向和列方向排列；以及第一隔垫物(131)、第二隔垫物(132)和第三隔垫物(133)，各子像素组(120)包括第一子像素(121)、第二子像素(122)和第三子像素(123)，在一行子像素组(120)中，第一隔垫物(131)位于相邻的第一子像素(121)和第二子像素(122)之间，第二隔垫物(132)位于相邻的第二子像素(122)和第三子像素(123)之间，第三隔垫物(133)位于相邻的第三子像素(123)与第一子像素(121)之间，第一隔垫物(131)的数量、第二隔垫物(132)的数量和第三隔垫物(133)的数量大致相等。由此，该显示基板(100)可有效地改善，甚至避免因隔垫物分布不均导致的色偏现象。

Description

显示基板和显示装置 技术领域
本公开的实施例涉及一种显示基板和显示装置。
背景技术
随着显示技术的不断发展，有机发光二极管(Organic Light Emitting Diode，OLED)显示面板因其自发光、广视角、高对比度、低功耗、高反应速度等优点已经越来越多地被应用于各种电子设备中。
发明内容
本公开至少一个实施例提供一种显示基板，其包括：衬底基板；多个子像素组，在所述衬底基板上且沿行方向和列方向排列；以及第一隔垫物、第二隔垫物和第三隔垫物，各所述子像素组包括第一子像素、第二子像素和第三子像素，在一行所述子像素组中，所述第一隔垫物位于相邻的所述第一子像素和所述第二子像素之间，所述第二隔垫物位于相邻的所述第二子像素和所述第三子像素之间，所述第三隔垫物位于相邻的所述第三子像素与所述第一子像素之间，所述第一隔垫物的数量、所述第二隔垫物的数量和所述第三隔垫物的数量大致相等。
例如，在本公开一实施例提供的显示基板中，在一行所述子像素组中，所述第一隔垫物、所述第二隔垫物和所述第三隔垫物依次循环设置。
例如，在本公开一实施例提供的显示基板中，各所述子像素组至多包括一个所述第一隔垫物、一个所述第二隔垫物或者一个所述第三隔垫物。
例如，在本公开一实施例提供的显示基板中，各所述子像素组包括一个所述第一子像素、一个所述第二子像素和一个第三子像素对，所述第三子像素对包括两个所述第三子像素，在一行所述子像素组中，所述第一隔垫物位于相邻的所述第一子像素和所述第二子像素之间，所述第二隔垫物位于相邻的所述第二子像素和所述第三子像素对之间，所述第三隔垫物位于相邻的所述第三子像素对与所述第一子像素之间。
例如，在本公开一实施例提供的显示基板中，在各所述子像素组中，所述第一子像素、所述第二子像素和所述第三子像素对沿所述行方向排列并形成三 个子像素列，所述第三子像素对中的两个所述第三子像素沿所述列方向排列。
例如，在本公开一实施例提供的显示基板中，在一行所述子像素组中，所述第一隔垫物和所述第二隔垫物之间间隔1+3n个所述子像素列，所述第二隔垫物和所述第三隔垫物之间间隔1+3n个所述子像素列，所述第三隔垫物和所述第一隔垫物之间间隔1+3n个所述子像素列，n为大于等于1的正整数。
例如，在本公开一实施例提供的显示基板中，相邻的两行所述子像素组错位1/2节距设置，所述节距为沿所述行方向相邻两个所述子像素组中的两个所述第一子像素的中心之间的距离。
例如，在本公开一实施例提供的显示基板中，所述第一子像素被配置为发第一颜色的光，所述第二子像素被配置为发第二颜色的光，所述第三子像素被配置为发第三颜色的光。
例如，在本公开一实施例提供的显示基板中，所述第一颜色为蓝色、所述第二颜色为红色、所述第三颜色为绿色。
例如，在本公开一实施例提供的显示基板中，所述第一隔垫物的形状大致为长条状，所述第一隔垫物的延伸方向与所述列方向大致平行，所述第二隔垫物的形状大致为长条状，所述第二隔垫物的延伸方向与所述列方向大致平行，所述第三隔垫物的形状大致为长条状，所述第三隔垫物的延伸方向与所述列方向大致平行。
例如，在本公开一实施例提供的显示基板中，所述第一隔垫物在所述列方向的尺寸小于所述第一子像素在所述列方向的尺寸，所述第二隔垫物和所述第三隔垫物在所述列方向的尺寸小于所述第三子像素对在所述列方向的尺寸，所述第一隔垫物的中心、所述第二隔垫物的中心、所述第三隔垫物的中心、所述第一子像素的中心、所述第二子像素的中心和所述第三子像素对的中心大致位于大致平行于所述行方向的直线上。
例如，在本公开一实施例提供的显示基板中，所述第一隔垫物、所述第二隔垫物和所述第三隔垫物具有相同的尺寸，所述第一隔垫物沿所述行方向的宽度范围为6-15微米，所述第一隔垫物沿所述列方向的长度为35-45微米，所述第一隔垫物沿同时垂直于所述衬底基板的方向上的高度范围为1.5-2.5微米。
例如，在本公开一实施例提供的显示基板中，第一子像素包括第一阳极和第一发光功能层，所述第二子像素包括第二阳极和第二发光功能层，所述第三 子像素包括第三阳极和第三发光功能层，所述显示基板还包括：像素限定层，位于所述第一阳极、所述第二阳极和所述第三阳极远离所述衬底基板的一侧，且包括第一开口、第二开口和第三开口，所述第一开口暴露所述第一阳极，所述第二开口暴露所述第二阳极，所述第三开口暴露所述第三阳极，所述第一发光功能层的至少一部分位于所述第一开口并覆盖所述第一阳极被暴露的部分，所述第二发光功能层的至少一部分位于所述第二开口并覆盖所述第二阳极被暴露的部分，所述第三发光功能层的至少一部分位于所述第三开口并覆盖所述第三阳极被暴露的部分，所述第一隔垫物、所述第二隔垫物和所述第三隔垫物位于所述像素限定层远离所述衬底基板的表面上。
例如，在本公开一实施例提供的显示基板中，所述第一隔垫物、所述第二隔垫物和所述第三隔垫物在所述衬底基板上的正投影与所述第一开口、所述第二开口和所述第三开口在所述衬底基板上的正投影不交叠。
例如，在本公开一实施例提供的显示基板中，所述第一隔垫物、所述第二隔垫物和所述第三隔垫物通过一次掩膜工艺形成。
本公开至少一个实施例还提供一种显示装置，包括上述任一项所述的显示基板。
本公开至少一个实施例还提供一种显示基板，其包括：衬底基板；多个子像素组，在所述衬底基板上且沿行方向和列方向排列；各所述子像素组包括一个第一子像素、一个第二子像素和一个第三子像素对，各所述第三子像素对包括两个第三子像素，所述第一子像素包括第一阳极和第一像素驱动电路，所述第二子像素包括第二阳极和第二像素驱动电路，所述第三子像素包括第三阳极和第三像素驱动电路，所述显示基板还包括第一平坦层，位于所述第一阳极和所述第一像素驱动电路之间，所述第二阳极和所述第二像素驱动电路之间，和所述第三阳极和所述第三像素驱动电路之间，所述第一子像素包括位于所述第一平坦层的第一过孔，所述第二子像素包括位于所述第一平坦层的第二过孔，所述第三子像素包括位于所述第一平坦层的第三过孔，所述第一过孔用于所述第一阳极与所述第一像素驱动电路的连接，所述第二过孔用于所述第二阳极与所述第二像素驱动电路的连接，所述第三过孔用于所述第三阳极与所述第三像素驱动电路的连接，在一行所述子像素组中的所述第一过孔、所述第二过孔和部分所述第三过孔大致位于第一直线上。
例如，在本公开一实施例提供的显示基板中，所述第一直线大致平行于所 述行方向。
例如，在本公开一实施例提供的显示基板中，在各所述子像素组中，所述第一子像素、所述第二子像素和所述第三子像素对沿所述行方向排列，所述第三子像素对中的两个所述第三子像素沿所述列方向排列，所述第三子像素对中的两个所述第三子像素的两个所述第三过孔分别位于相邻的两条所述第一直线上。
例如，在本公开一实施例提供的显示基板中，该显示基板还包括：第二平坦层，位于所述第一平坦层与所述第一像素驱动电路、所述第二像素驱动电路和所述第三像素驱动电路之间；第一连接电极、第二连接电极和第三连接电极，位于所述第二平坦层与所述第一平坦层之间，所述第一像素驱动电路包括第一电极，所述第二像素驱动电路包括第二电极，所述第三像素驱动电路包括第三电极，所述第一子像素包括位于所述第二平坦层的第四过孔，所述第二子像素包括位于所述第二平坦层的第五过孔，所述第三子像素包括位于所述第二平坦层的第六过孔，所述第四过孔用于所述第一电极和第一连接电极的连接，所述第五过孔用于所述第二电极和第二连接电极的连接，所述第六过孔用于所述第三电极和第三连接电极的连接，一行所述子像素组中的所述第四过孔、所述第五过孔和部分所述第六过孔大致位于第二直线上。
例如，在本公开一实施例提供的显示基板中，所述第三子像素对中的两个所述第三子像素的两个所述第六过孔分别位于相邻的两条所述第二直线上。
例如，在本公开一实施例提供的显示基板中，在一行所述子像素组中，所述第一直线和所述第二直线大致重合。
例如，在本公开一实施例提供的显示基板中，一行所述子像素组中的所述第四过孔、所述第一过孔、所述第六过孔、所述第三过孔、所述第五过孔、所述第二过孔、所述第六过孔、所述第三过孔循环依次设置。
例如，在本公开一实施例提供的显示基板中，所述第一过孔、所述第二过孔、所述第三过孔、所述第四过孔、所述第五过孔和所述第六过孔相互间隔设置。
例如，在本公开一实施例提供的显示基板中，所述第一过孔、所述第二过孔和所述第三过孔等间距设置。
例如，在本公开一实施例提供的显示基板中，所述第四过孔、所述第五过孔和所述第六过孔等间距设置。
例如，在本公开一实施例提供的显示基板中，所述第一过孔与所述第四过孔之间的距离小于所述第一过孔与所述第二过孔之间的距离，所述第二过孔与所述第五过孔之间的距离小于所述第二过孔与所述第三过孔之间的距离，所述第三过孔与所述第六过孔之间的距离小于所述第二过孔与所述第三过孔之间的距离。
例如，在本公开一实施例提供的显示基板中，所述第一直线位于相邻的两行子像素组之间。
本公开至少一个实施例还提供一种显示装置，包括上述任一项所述的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种OLED显示基板的结构示意图；
图2A为一种显示基板中的子像素发光情况的示意图；
图2B为另一种显示基板中的子像素发光情况的示意图；
图3为根据本公开一实施例提供的一种显示基板的平面示意图；
图4为根据本公开一实施例提供的另一种显示基板的平面示意图；
图5为根据本公开一实施例提供的另一种显示基板的平面示意图；
图6为根据本公开一实施例提供的一种显示基板中一个子像素的结构示意图；
图7为根据本公开一实施例提供的一种显示基板的平面示意图；
图8为根据本公开一实施例提供的一种显示基板中子像素的结构示意图；以及
图9为根据本公开一实施例提供的另一种显示基板中子像素的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所 描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
图1为一种OLED显示基板的结构示意图。如图1所示，该OLED显示基板包括：衬底基板10、像素驱动电路20、平坦层30、阳极40、像素限定层50和隔垫物(PS)60。像素驱动电路20设置在衬底基板10上；平坦层30设置在像素驱动电路20远离衬底基板10的一侧；阳极40设置在平坦层30远离衬底基板10的一侧，且可通过平坦层30中的过孔35与像素驱动电路20电性相连；像素限定层50设置在阳极40远离衬底基板10的一侧且形成有开口52，开口52可暴露阳极40；隔垫物60设置在像素限定层50远离衬底基板10的一侧。隔垫物60在衬底基板10上的正投影与开口52在衬底基板10上的正投影互不交叠。
如图1所示，开口52可设置发光层(图中未示出)，发光层与阳极50接触设置，发光层远离阳极50的一侧还可设置阴极(图中未示出)，发光层在阳极和阴极之间的电流的作用下可发光。通常，阳极50的面积略大于开口52的面积，因此开口52可限定一个子像素的有效发光区。隔垫物60通常设置在子像素的周边，并可在蒸镀发光层时起到支撑极细金属掩膜(Fine Metal Mask，FMM)的作用。然而，通常的隔垫物排布存在以下问题：当隔垫物的排布密度较大时，放置在隔垫物上的FMM可能会划伤隔垫物，从而导致被划伤的部分从隔垫物脱落形成颗粒物(Particle)，会直接带来particle风险，降低产品良率；另一方面，当一个子像素的第一横向侧设置有隔垫物时，隔垫物会限制该子像素在第一横向侧的发光角度，而该子像素没有设置的隔垫物的第二横向侧(第二横向侧与第一横向侧相对)不会限制该子像素的在第二横向侧的发光角度，从而导致从第一横向侧和第二横向侧以与该显示基板的法线呈相同角度进 行观察时，从第一横向侧观察到的该子像素的亮度与从第二横向侧观察到的该子像素的亮度不同，从而导致在不同视角下的色偏，即从第一横向侧观察到的颜色与第二横向侧观察到的颜色不同；并且，由于不同颜色的子像素的周边的隔垫物分布不同，不同颜色的子像素受到隔垫物的影响程度不同，从而也会进一步导致该显示基板产生在不同视角下观看画面时的色偏。
图2A为一种显示基板中的子像素发光情况的示意图。图2B为另一种显示基板中的子像素发光情况的示意图。图2A和2B示出了蓝色子像素71、红色子像素72、像素限定层50以及位于蓝色子像素71和红色子像素72之间的隔垫物60。如图2A和2B所示，由于隔垫物60的遮挡作用，蓝色子像素71向第一横向侧(如图2A中的左侧)发出的光线会被像素限定层50遮挡，而蓝色子像素71向第二横向侧(如图2A中的右侧)发出的光线会被像素限定层50和隔垫物60遮挡；隔垫物60设置在像素限定层50上，从而导致蓝色子像素71向第二横向侧发出的光线被遮挡的程度更严重，一方面导致蓝色子像素71向第二横向侧发出的光线的亮度小于该蓝色子像素71向第一横向侧发出的光线的亮度，另一方面还导致蓝色子像素71在第二横向侧的可视角度小于该蓝色子像素71在第一横向侧的可视角度；相反地，由于隔垫物60的遮挡作用，红色子像素72向第一横向侧发出的光线被遮挡的程度更严重，一方面导致红色子像素72向第一横向侧发出的光线的亮度小于该红色子像素72向第二横向侧发出的光线的亮度，另一方面还导致红色子像素72在第一横向侧的可视角度小于该红色子像素72在第二横向侧的可视角度。由此，从第一横向侧和第二横向侧以与该显示基板的法线呈相同角度进行观察时，从第一横向侧观察到的蓝色子像素或红色子像素的亮度与从第二横向侧观察到的该子像素的亮度不同，从而导致在不同视角下观看画面时的色偏，即从第一横向侧观察到的颜色与第二横向侧观察到的颜色不同；另外，由于蓝色子像素和红色子像素的周边的隔垫物分布不同，蓝色子像素向第二横向侧发出的光线的亮度小于该蓝色子像素向第一横向侧发出的光线的亮度，而红色子像素向第一横向侧发出的光线的亮度小于该红色子像素向第二横向侧发出的光线的亮度，从而也会进一步导致该显示基板产生在不同视角下观看画面时的色偏。
对此，本公开实施例提供一种显示基板和显示装置。该显示基板包括衬底基板、多个子像素组、第一隔垫物、第二隔垫物和第三隔垫物。多个子像素组在衬底基板上沿行方向和列方向排列，各子像素组包括第一子像素，第二子像 素和第三子像素。在一行子像素组中，第一隔垫物位于相邻的第一子像素和第二子像素之间，第二隔垫物位于相邻的第二子像素和第三子像素之间，第三隔垫物位于相邻的第三子像素与第一子像素之间，第一隔垫物的数量、第二隔垫物的数量和第三隔垫物的数量大致相等。由此，对于一行子像素组中的一种子像素(例如，第一子像素、第二子像素或第三子像素)而言，由于第一隔垫物的数量、第二隔垫物的数量和第三隔垫物的数量大致相等，每种子像素的第一横向侧的隔垫物和第二横向侧的隔垫物的数量也大致相同，从而提高了一行子像素组中的隔垫物的对称性，使得从第一横向侧和第二横向侧以与该显示基板的法线呈相同的角度观察时，从第一横向侧和第二横向侧所观察到的一行子像素组中的一种子像素的亮度大致相同，从而可改善，甚至消除在不同视角下观看画面时的色偏；并且，由于第一隔垫物的数量、第二隔垫物的数量和第三隔垫物的数量大致相等，一行子像素组中的不同子像素周边的隔垫物的数量也大致相同，使得一行子像素组中的不同子像素被隔垫物遮挡的情况也大致相同，从而可进一步改善，甚至消除在不同视角下观看画面时的色偏。由此，该显示基板可有效地改善，甚至避免因隔垫物分布不均导致的色偏现象。
下面，结合附图对本公开实施例提供的显示基板和显示装置进行说明。
图3为根据本公开一实施例提供的一种显示基板的平面示意图。如图3所示，该显示基板100包括衬底基板110、多个子像素组120、第一隔垫物131、第二隔垫物132和第三隔垫物133。多个子像素组120设置在衬底基板110上且沿行方向和列方向排列，各子像素组120包括第一子像素121、第二子像素122和第三子像素123。在一行子像素组120中，第一隔垫物131位于相邻的第一子像素121和第二子像素122之间，即第一隔垫物131位于相邻的第一子像素121和第二子像素122之间的间隔区域；第二隔垫物132位于相邻的第二子像素122和第三子像素123之间，即第二隔垫物132位于相邻的第二子像素122和第三子像素123之间的间隔区域；第三隔垫物133位于相邻的第三子像素123与第一子像素121之间，即第三隔垫物133位于相邻的第三子像素123和第一子像素121之间的间隔区域；并且，第一隔垫物131的数量、第二隔垫物132的数量和第三隔垫物133的数量大致相等。需要说明的是，图3所示的第一子像素121可为第一子像素121的有效发光区，图3所示的第二子像素122可为第二子像素122的有效发光区，图3所示的第三子像素123可为第三子像素123的有效发光区。另外，在显示领域，一个像素通常包括多个可分别显示 单色(例如红色、绿色或蓝色)的子像素，通过控制不同颜色的子像素的比例以实现显示不同的颜色，因此上述的第一子像素可为单色子像素。
在本公开实施例提供的显示基板中，对于一行子像素组120中的一种子像素(例如，第一子像素121、第二子像素122或第三子像素123)而言，由于第一隔垫物131的数量、第二隔垫物132的数量和第三隔垫物133的数量大致相等，每种子像素的第一横向侧的隔垫物和第二横向侧的隔垫物的数量也大致相同，从而提高了一行子像素组中的隔垫物对于子像素的发光情况的影响的对称性，使得从第一横向侧和第二横向侧以与该显示基板的法线呈相同的角度观察时，从第一横向侧和第二横向侧所观察到的一行子像素组中的一种子像素的亮度大致相同，从而可改善，甚至消除在不同视角下观看画面时的色偏。例如，假设一行子像素组120中有100个第一子像素121的第一横向侧设置有第三隔垫物133，100个第二子像素122的第二横向侧设置有第一隔垫物131，此时，由于第三隔垫物133的遮挡作用，第一横向侧设置有第三隔垫物133的100个第一子像素121向第一横向侧发出的光线会被第三隔垫物133遮挡，从而导致第一横向侧设置有第三隔垫物133的100个第一子像素121向第一横向侧发出的光线的亮度小于向第二横向侧发出的光线的亮度；相反的，第二横向侧设置有第一隔垫物131的100个第一子像素121向第二横向侧发出的光线的亮度小于向第一横向侧发出的光线的亮度；将该行子像素120中第一子像素121作为一个整体而言，这些第一子像素121向第二横向侧发出的光线的亮度与这些第一子像素121向第一横向侧发出的光线的亮度大致相等，从而可改善，甚至消除在不同视角下观看画面时的色偏。例如，在一些示例中，在一行子像素组120中，第一隔垫物131的数量、第二隔垫物132的数量和第三隔垫物133的数量相等，从而可更好地改善，甚至消除在不同视角下观看画面时的色偏。
图4为根据本公开一实施例提供的一种显示基板的平面示意图。如图4所示，该显示基板100包括衬底基板110、多个子像素组120、第一隔垫物131、第二隔垫物132和第三隔垫物133。多个子像素组120设置在衬底基板110上且沿行方向和列方向排列，各子像素组120包括一个第一子像素121、一个第二子像素122和一个第三子像素对126，第三子像素对126包括两个第三子像素123。在一行子像素组120中，第一隔垫物131位于相邻的第一子像素121和第二子像素122之间，即第一隔垫物131位于相邻的第一子像素121和第二子像素122之间的间隔区域；第二隔垫物132位于相邻的第二子像素122和第 三子像素对126之间，即第二隔垫物132位于相邻的第二子像素122和第三子像素对126之间的间隔区域；第三隔垫物133位于相邻的第三子像素对126与第一子像素121之间，即第三隔垫物133位于相邻的第三子像素对126和第一子像素121之间的间隔区域；并且，第一隔垫物131的数量、第二隔垫物132的数量和第三隔垫物133的数量大致相等。需要说明的是，图4所示的第一子像素121可为第一子像素121的有效发光区，图4所示的第二子像素122可为第二子像素122的有效发光区，图4所示的第三子像素123可为第三子像素123的有效发光区。另外，在显示领域，一个像素通常包括多个可分别显示单色(例如红色、绿色或蓝色)的子像素，通过控制不同颜色的子像素的比例以实现显示不同的颜色，因此上述的第一子像素可为单色子像素。
在本公开实施例提供的显示基板中，对于一行子像素组120中的一种子像素(例如，第一子像素121、第二子像素122或第三子像素123)而言，由于第一隔垫物131的数量、第二隔垫物132的数量和第三隔垫物133的数量大致相等，每种子像素的第一横向侧的隔垫物和第二横向侧的隔垫物的数量也大致相同，从而提高了一行子像素组中的隔垫物对于子像素的发光情况的影响的对称性，使得从第一横向侧和第二横向侧以与该显示基板的法线呈相同的角度观察时，从第一横向侧和第二横向侧所观察到的一行子像素组中的一种子像素的亮度大致相同，从而可改善，甚至消除在不同视角下观看画面时的色偏。例如，假设一行子像素组120中有100个第一子像素121的第一横向侧设置有第三隔垫物133，100个第二子像素122的第二横向侧设置有第一隔垫物131，此时，由于第三隔垫物133的遮挡作用，第一横向侧设置有第三隔垫物133的100个第一子像素121向第一横向侧发出的光线会被第三隔垫物133遮挡，从而导致第一横向侧设置有第三隔垫物133的100个第一子像素121向第一横向侧发出的光线的亮度小于向第二横向侧发出的光线的亮度；相反的，第二横向侧设置有第一隔垫物131的100个第一子像素121向第二横向侧发出的光线的亮度小于向第一横向侧发出的光线的亮度；将该行子像素120中第一子像素121作为一个整体而言，这些第一子像素121向第二横向侧发出的光线的亮度与这些第一子像素121向第一横向侧发出的光线的亮度大致相等，从而可改善，甚至消除在不同视角下观看画面时的色偏。
另外，在本公开实施例提供的显示基板中，对于一行子像素组120中的一种子像素(例如，第一子像素121、第二子像素122或第三子像素123)而言， 由于第一隔垫物131的数量、第二隔垫物132的数量和第三隔垫物133的数量大致相等，一行子像素组120中的不同子像素周边的隔垫物的数量也大致相同，使得一行子像素组120中的不同子像素被隔垫物(例如，第一隔垫物131、第二隔垫物132和第三隔垫物133)遮挡的情况也大致相同，即一行子像素组120中第一子像素121，第二子像素122和第三子像素123被隔垫物遮挡的情况也大致相同，从而可进一步改善，甚至消除在不同视角下观看画面时的色偏。由此，该显示基板可有效地改善，甚至避免因隔垫物分布不均导致的色偏现象。
例如，上述的第一隔垫物的数量、第二隔垫物的数量和第三隔垫物的数量大致相等可指第一隔垫物的数量、第二隔垫物的数量和第三隔垫物的数量分别与第一隔垫物的数量、第二隔垫物的数量和第三隔垫物的平均值之比的范围在0.9-1.1。
例如，上述的第一隔垫物、第二隔垫物和第三隔垫物可采用聚酰亚胺制作。当然，本公开实施例包括但不限于此，上述的第一隔垫物、第二隔垫物和第三隔垫物也可选用有机硅等其他材料制作。
例如，上述第一隔垫物、第二隔垫物和第三隔垫物还可采用光透过率较大的材料制作，从而降低第一隔垫物、第二隔垫物和第三隔垫物对光线的遮挡作用。
例如，在一些示例中，如图4所示，在一行子像素组120中，第一隔垫物131、第二隔垫物132和第三隔垫物133依次循环设置。也就是说，在一行子像素组120中，第一隔垫物131、第二隔垫物132和第三隔垫物133作为一个组不断重复。由此，在一行子像素组120中，在一定的区域内，可保证第一隔垫物131的数量、第二隔垫物132的数量和第三隔垫物133的数量大致相等，从而可进一步改善，甚至消除在不同视角下观看画面时的色偏。
例如，将一行子像素组120分为依次设置的N(N为大于等于1的正整数)个区域，每个区域均包括M(M为大于等于1的正整数)个上述的第一隔垫物131、第二隔垫物132和第三隔垫物133构成的组；此时，对于每个区域而言，每种子像素的第一横向侧的隔垫物和第二横向侧的隔垫物的数量也大致相同，从而提高了该区域中的隔垫物对于子像素的发光情况的影响的对称性，使得从第一横向侧和第二横向侧以与该显示基板的法线呈相同的角度观察时，从第一横向侧和第二横向侧所观察到的该区域中的一种子像素的亮度大致相同，从而可进一步改善，甚至避免因隔垫物分布不均导致的色偏现象。同样地，对于每 个区域而言，对于每个区域中的一种子像素而言，每个区域中的不同子像素周边的隔垫物的数量也大致相同，使得每个区域中的不同子像素被隔垫物遮挡的情况也大致相同，从而也可进一步改善，甚至消除在不同视角下观看画面时的色偏。
例如，在一些示例中，如图4所示，各子像素组120至多包括一个第一隔垫物131、一个第二隔垫物132或者一个第三隔垫物133，从而降低隔垫物的密度，进而管控Particle风险。
例如，在一些示例中，如图4所示，在各子像素组120中，第一子像素121、第二子像素122和第三子像素对126沿行方向排列并形成三个子像素列128，一个第三子像素对126中的两个第三子像素123沿列方向排列。也就是说，各子像素组120可包括三个子像素列128。由此，该显示基板的像素排列结构可应用像素借用技术，从而可提高该显示基板的分辨率。
例如，在一些示例中，如图4所示，在一行子像素组120中，第一隔垫物131和第二隔垫物132之间间隔1+3n个子像素列128，第二隔垫物132和第三隔垫物133之间间隔1+3n个子像素列128，第三隔垫物133和第一隔垫物131之间间隔1+3n个子像素列128，n为大于等于1的正整数。对于OLED显示基板，隔垫物有两个作用：一个作用在于支撑蒸镀用的FMM，另一个作用在于封装时支撑盖板。由此，一方面，该示例提供的显示基板可保证在一行子像素组120中，第一隔垫物131的数量、第二隔垫物132的数量和第三隔垫物133的数量大致相等；另一方面，当n的取值较大时，例如n大于等于2时，该示例提供的显示基板可进一步降低隔垫物的密度，从而降低在支撑蒸镀用的FMM时的Particle风险、提高产品良率。当然，当n的取值可根据支撑FMM的需要和降低Particle风险的需要进行设置。
例如，在一些示例中，如图4所示，相邻的两行子像素组120错位1/2节距设置，节距为沿行方向相邻的两个子像素组120中的两个第一子像素121的中心之间的距离。需要说明的是，节距也可为沿行方向相邻的两个子像素组120中的两个第二子像素122或第三子像素对126的中心之间的距离；上述的中心可为子像素的几何中心。另外，相邻的两行子像素组120是沿行方向错位1/2节距设置。当然，本公开实施例包括但不限于此，相邻的两行子像素组120错位其他距离设置。
例如，在一些示例中，如图4所示，第一子像素121被配置为发第一颜色 的光，第二子像素122被配置为发第二颜色的光，第三子像素123被配置为发第三颜色的光。需要说明的是，本公开实施例包括但不限于此，第三子像素对中的一个第三子像素可被配置为发第三颜色的光，而第三子像素对中的另一个第三子像素可被配置为发第四颜色的光。
例如，第一颜色为蓝色、第二颜色为红色、第三颜色为绿色。由此，该显示基板为采用红绿蓝的颜色方案；当然，本公开包括但不限于此，该显示基板还可采用其他颜色的方案。
例如，在一些示例中，如图4所示，第一子像素121的有效发光区的形状大致为六边形或椭圆形，六边形长对称轴或椭圆形的长轴与列方向大致平行。
例如，在一些示例中，如图4所示，第二子像素122的有效发光区的形状也大致为六边形或椭圆形，六边形长对称轴或椭圆形的长轴与列方向大致平行。
例如，在一些示例中，如图4所示，第三子像素123的有效发光区的形状大致为五边形，五边形的直角边与行方向大致平行。
需要说明的是，上述的有效发光区一般会设计为规则的形状，比如上述的六边形、五边形、或椭圆形。然而，在实际制造工艺中，所形成的有效发光区的形状一般会与上述设计的规则形状有一定的偏差。例如，上述规则的形状的各个角可能会变成圆角，因此，有效发光区(例如，第一有效发光区、第二有效发光区或第三有效发光区)的形状可以为圆角图形。此外，实际制造的有效发光区的形状还可能会与设计的形状有其他的变化。例如，设计为六边形的有效发光区的形状在实际制造中可能变成近似椭圆形。
例如，在一些示例中，如图4所示，第一隔垫物131的形状大致为长条状，第一隔垫物131的延伸方向与列方向大致平行，第二隔垫物132的形状大致为长条状，第二隔垫物132的延伸方向与列方向大致平行，第三隔垫物133的形状大致为长条状，第三隔垫物133的延伸方向与所列方向大致平行。由此，由于子像素通常也为长条状(六边形或椭圆形)，该显示基板可充分利用子像素之间的间隔或间隙。例如，上述隔垫物(例如，第一隔垫物、第二隔垫物或第三隔垫物)的形状为隔垫物在衬底基板上的正投影的形状。相似的，上述的子像素(例如，第一子像素、第二子像素或第三子像素)的有效发光区的形状为子像素在衬底基板上的正投影的形状。
例如，本公开的实施例中，长条形是指一个方向的长度大于另一个方向的 长度，或者，在一个方向上尺寸大于其他方向尺寸即可。条形不限于矩形，可以为其他形状，例如，可以为长条六边形，长椭圆形，梯形或其他形状。
例如，在一些示例中，如图4所示，第一隔垫物131在列方向的尺寸小于第一子像素121在列方向的尺寸，第二隔垫物132和第三隔垫物133在列方向的尺寸小于第三子像素对126在列方向的尺寸，第一隔垫物131的中心、第二隔垫物132的中心、第三隔垫物133的中心、第一子像素121的中心、第二子像素122的中心和第三子像素对126的中心大致位于大致平行于行方向的直线上。
例如，在一些示例中，如图4所示，第一隔垫物131、第二隔垫物132和第三隔垫物133具有相同的尺寸，第一隔垫物131沿行方向的宽度范围为6-15微米，第一隔垫物131沿所述列方向的长度范围为35-45微米，第一隔垫物131沿同时垂直于行方向和列方向的方向上的高度范围为1.5-2.5微米。例如，第一隔垫物131沿同时垂直于行方向和列方向的方向上的高度为2微米。
例如，在一些示例中，第一子像素121的有效发光区域在行方向的尺寸范围为15-23微米，在列方向上的尺寸为35-45微米；第二子像素122的有效发光区域在行方向的尺寸范围为11-21微米，在列方向上的尺寸为35-45微米；第三子像素123的有效发光区域在行方向的尺寸范围为9-13微米，在列方向上的尺寸为9-13微米；在一个第三子像素对116中，两个第三子像素113之间的最短距离的范围在13-15微米。
图5为根据本公开一实施例提供的另一种显示基板的平面示意图。图6为根据本公开一实施例提供的一种显示基板中一个子像素的结构示意图。为了清楚地示出该显示基板中子像素组的结构，图5仅示出了一个子像素组。如图6所示，在该子像素组120中，第一子像素121包括第一阳极1212和第一发光功能层1214，第二子像素122包括第二阳极1222和第二发光功能层1224，第三子像素123包括第三阳极1232和第三发光功能层1234。如图5和6所示，该显示基板还包括：像素限定层160，位于第一阳极1212、第二阳极1222和第三阳极1232远离衬底基板110的一侧，像素限定层160包括第一开口171、第二开口172和第三开口173，第一开口171暴露第一阳极1212，第二开口172暴露第二阳极1222，第三开口173暴露第三阳极1232。第一发光功能层1214至少一部分位于第一开口171并覆盖第一阳极1212被暴露的部分，第二发光功能层1224至少一部分位于第二开口172并覆盖第二阳极1222被暴露的部分， 第三发光功能层1234至少一部分位于第三开口173并覆盖第三阳极1232被暴露的部分，第一隔垫物131、第二隔垫物132和第三隔垫物133位于像素限定层160远离衬底基板110的表面上。需要说明的是，第一阳极1212的面积可以稍大于第一发光功能层1214的面积。另外，第一发光功能层1214可以包括电致发光层本身以及位于电致发光层两侧的其他功能层，例如，空穴注入层、空穴传输层、电子注入层以及电子传输层等等。第二阳极1222的面积可以稍大于第二发光功能层1224的面积。另外，第二发光功能层1224可以包括电致发光层本身以及位于电致发光层两侧的其他功能层，例如，空穴注入层、空穴传输层、电子注入层以及电子传输层等等。第三阳极1232的面积可以稍大于第三发光功能层1234的面积。另外，第三发光功能层1234可以包括电致发光层本身以及位于电致发光层两侧的其他功能层，例如，空穴注入层、空穴传输层、电子注入层以及电子传输层等等。例如，在一些示例中，第一隔垫物131、第二隔垫物132和第三隔垫物133在衬底基板101上的正投影与第一开口171、第二开口172和第三开口173在衬底基板101上的正投影不交叠。
例如，在一些示例中，第一开口171在衬底基板101上的正投影完全位于第一阳极1212在衬底基板101上的正投影内；第二开口172在衬底基板101上的正投影完全位于第二阳极1222在衬底基板101上的正投影内；第三开口173在衬底基板101上的正投影完全位于第三阳极1232在衬底基板101上的正投影内。
例如，在一些示例中，第一开口171在衬底基板101上的正投影完全位于第一发光功能层1214在衬底基板101上的正投影内；第二开口172在衬底基板101上的正投影完全位于第二发光功能层1224在衬底基板101上的正投影内；第三开口173在衬底基板101上的正投影完全位于第三发光功能层1234在衬底基板101上的正投影内。
例如，在一些示例中，第一阳极1212在衬底基板101上的正投影的边缘、第二阳极1222在衬底基板101上的正投影的边缘和第三阳极1232在衬底基板101上的正投影的边缘被像素限定层160在衬底基板101上的正投影覆盖。
例如，在一些示例中，第一发光功能层1214还可部分覆盖在像素限定层160上，第二发光功能层1224还可部分覆盖在像素限定层160上，第三发光功能层1234还可部分覆盖在像素限定层160。
例如，在一些示例中，第一隔垫物131、第二隔垫物132和第三隔垫物133 通过一次掩膜工艺形成。例如，可先在像素限定层160远离衬底基板110的表面上形成一层隔垫物层，然后通过图案化工艺图案化隔垫物层以形成第一隔垫物131、第二隔垫物132和第三隔垫物133。
例如，在一些示例中，第一隔垫物131、第二隔垫物132和第三隔垫物133和像素限定层160还通过一次掩膜工艺形成。例如，第一隔垫物131、第二隔垫物132和第三隔垫物133和像素限定层160可采用相同的材料制作。本公开至少一个实施例还提供一种显示装置，包括上述的显示基板。因此，该显示装置可兼顾隔垫物密度和改善色偏的问题，一方面可改善，甚至消除在不同视角下观看画面时的色偏，另一方面还可降低隔垫物的密度，从而管控Particle风险，提高产品良率。在显示装置采用本公开的实施例给出的像素排布结构的显示面板时，还可进一步提高该显示装置的分辨率，进而可提供一种具有真实的高分辨率的显示装置。另外，由于本公开的实施例给出的像素排列结构可具有较好的对称性，进而，可提高像素分布的均匀性，提高显示装置的显示效果。
例如，在一些示例中，该显示装置可以为智能手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开一实施例提供一种显示基板。图7为根据本公开一实施例提供的一种显示基板的平面示意图。图8为根据本公开一实施例提供的一种显示基板中子像素的结构示意图。如图7所示，该显示基板包括衬底基板110、多个子像素组120。多个子像素组120设置在衬底基板110上且沿行方向和列方向排列，各子像素组120包括一个第一子像素121、一个第二子像素122和一个第三子像素对126，第三子像素对126包括两个第三子像素123。图8示出了一个子像素沿图7中AA方向的剖面示意图。如图8所示，第一子像素121包括第一阳极1212和第一像素驱动电路1216，第二子像素122包括第二阳极1222和第二像素驱动电路1226，第三子像素123包括第三阳极1232和第三像素驱动电路1236。该显示基板还包括第一平坦层140，第一平坦层140位于第一阳极1212和第一像素驱动电路1216之间，第二阳极1222和第二像素驱动电路1226之间，以及第三阳极1232和第三像素驱动电路1236之间。第一子像素121包括位于第一平坦层140的第一过孔141，第二子像素122包括位于第一平坦层140的第二过孔142，第三子像素123包括位于第一平坦层140的第三过孔143；第一过孔141用于第一阳极1212和第一像素驱动电路1216的连接，第二过孔142用于第二阳极1222和第二像素驱动电路1226的连接，第三过孔143用于 第三阳极1232和第三像素驱动电路1236的连接；一行子像素组120中的第一过孔141、第二过孔142和部分第三过孔143大致位于同一条直线上。需要说明的是，第一阳极用于连接的部分可以覆盖并填充对应的第一过孔，从而与对应的第一像素驱动电路连接；第二阳极用于连接的部分可以覆盖并填充对应的第二过孔，从而与对应的第二像素驱动电路连接；第三阳极用于连接的部分可以覆盖并填充对应的第三过孔，从而与对应的第三像素驱动电路连接。
在本公开实施例提供的显示基板中，由于一行子像素组120中的第一过孔141、第二过孔142和部分第三过孔143大致位于第一直线上，也就是说，第一过孔141、第二过孔142和部分第三过孔143布局排成一行，并且间距为一个子像素距离。由此，当工艺冗余量(margin)变动时，第一过孔141、第二过孔142和部分第三过孔143可同时上下移动，从而便于对工艺偏差进行管控。例如，当工艺冗余量(margin)变动较大时，第一过孔141、第二过孔142和部分第三过孔143同时上下移动，要么均出现不良，要么均没有不良，从而便于对工艺偏差进行管控。需要说明的是，当第一过孔141、第二过孔142和部分第三过孔143均出现不良时，这些不良容易被检测出来，从而可及时调整工艺。
例如，在一些示例中，如图7所示，一行子像素组120中任意两个相邻的子像素组120中的第一子像素121的第一过孔141、第二子像素122的第二过孔142和第三像素对126中的一个第三子像素123的第三过孔143大致位于同一条直线上。由此，当工艺冗余量(margin)变动时，这些第一过孔141、第二过孔142和第三过孔143可同时上下移动，从而便于对工艺偏差进行管控。
例如，在一些示例中，如图7所示，上述的第一直线与各子像素(例如，第一子像素、第二子像素和第三子像素)的有效发光区不交叠，也就是说，上述的第一直线不位于各子像素的有机层和阳极的重叠区域内。
例如，在一些示例中，如图7所示，上述的第一直线位于相邻的像素组行之间。
例如，在一些示例中，如图7所示，一行子像素组120中的第一过孔141、第二过孔142和部分第三过孔143所在的第一直线大致平行于行方向。例如，在一些示例中，如图7所示，在各子像素组120中，第一子像素121、第二子像素122和第三子像素对126沿行方向排列，第三子像素对126中的两个第三子像素123沿列方向排列，第三子像素对中的两个三子像素的两个第三过孔分 别位于相邻的两条第一直线上。也就是说，第三子像素对126中沿列方向排列的两个第三子像素123的两个第三过孔143中的一个与该第三子像素对126所属的子像素组行(可记作第N子像素组行)中的第一过孔141和第二过孔142位于同一直线，而另一个与该第三子像素对126所属的子像素组行相邻的子像素组行(可记作第N-1子像素组行)的第一过孔141和第二过孔142位于同一直线。
例如，在一些示例中，如图8所示，第一像素驱动电路1216可包括第一有源层12161、第一栅极绝缘层12162、第一栅极12163、第一层间绝缘层12164和第一源漏电极层12165；第二像素驱动电路1226可包括第二有源层12261、第二栅极绝缘层12262、第二栅极12263、第二层间绝缘层12264和第二源漏电极层12265；第三像素驱动电路1236可包括第三有源层12361、第三栅极绝缘层12362、第三栅极12363、第三层间绝缘层12364和第三源漏电极层12365。
例如，第一源漏电极层12165中的源极和漏极通过第一栅极绝缘层12162和第一层间绝缘层12164中的过孔与第一有源层12161的源极区域和漏极区域分别相连；第一栅极12163在衬底基板101上的正投影与第一有源层12161的沟道区在衬底基板101上的正投影相互交叠。第二源漏电极层12265中的源极和漏极通过第二栅极绝缘层12262和第二层间绝缘层12264中的过孔与第二有源层12261的源极区域和漏极区域分别相连；第二栅极12263在衬底基板101上的正投影与第二有源层12261的沟道区在衬底基板101上的正投影相互交叠。第三源漏电极层12365中的源极和漏极通过第三栅极绝缘层12362和第三层间绝缘层12364中的过孔与第三有源层12361的源极区域和漏极区域分别相连；第三栅极12363在衬底基板101上的正投影与第三有源层12361的沟道区在衬底基板101上的正投影相互交叠。例如，在一些示例中，第一有源层12161、第二有源层12261和第三有源层12361可通过同一半导体层制作；例如，第一有源层12161、第二有源层12261和第三有源层12361可采用多晶硅、单晶硅、氧化物半导体等材料。
例如，在一些示例中，第一栅极绝缘层12162、第二栅极绝缘层12262、第三栅极绝缘层12362为同一栅极绝缘层；例如，第一栅极绝缘层12162、第二栅极绝缘层12262、第三栅极绝缘层12362可采用氮化硅、氧化硅、氮氧化硅等绝缘材料制作。
例如，在一些示例中，第一栅极12163、第二栅极12263、第三栅极12363 可通过同一导电层制作；例如，第一栅极12163、第二栅极12263、第三栅极12363可采用钼、钛、铝、铜等导电材料制作。
例如，在一些示例中，第一层间绝缘层12164、第二层间绝缘层12264、第三层间绝缘层12364为同一层间绝缘层；第一层间绝缘层12164、第二层间绝缘层12264、第三层间绝缘层12364可采用氮化硅、氧化硅、氮氧化硅等绝缘材料制作。
例如，在一些示例中，第一源漏电极层12165、第二源漏电极层12265和第三源漏电极层12365可采用同一导电层制作；例如，第一源漏电极层12165、第二源漏电极层12265和第三源漏电极层12365可采用铝、钛、铜、钼等材料制作。
图9为根据本公开一实施例提供的另一种显示基板中子像素的结构示意图。如图9所示，该显示基板还包括：第二平坦层150，位于第一平坦层140与第一像素驱动电路1216、第二像素驱动电极1226和第三像素驱动电路1236之间，第一像素驱动电路1216包括第一电极181，第二像素驱动电路1226包括第二电极182，第三像素驱动电路1236包括第三电极183；该显示基板还包括第一连接电极191、第二连接电极192和第三连接电极193，位于第二平坦层150与第一平坦层140之间，第一子像素121还包括位于第二平坦层150中的第四过孔151，第二子像素122还包括位于第二平坦层150中的第五过孔152，第三子像素123还包括位于第二平坦层150中的第六过孔153，第四过孔151用于第一电极181和第一连接电极191的连接，第五过孔152用于第二电极182和第二连接电极192的连接，第六过孔153用于第三电极183和第三连接电极193的连接，一行子像素组120中的第四过孔151、第五过孔152和部分第六过孔153大致位于第二直线上。需要说明的是，上述第一电极、第二电极和第三电极可为对应的像素驱动电路中源漏电极层中的漏极。
在本公开实施例提供的显示基板中，由于一行子像素组120中的第四过孔151、第五过孔152和部分第六过孔153大致位于第二直线上，也就是说，第四过孔151、第五过孔152和部分第六过孔153布局排成一行，并且间距为一个子像素距离。由此，当工艺margin变动时，第四过孔151、第五过孔152和部分第六过孔153可同时上下移动，从而便于对工艺偏差进行管控。例如，当工艺冗余量(margin)变动较大时，第四过孔151、第五过孔152和第六过孔153同时上下移动，要么均出现不良，要么均没有不良，从而便于对工艺偏差 进行管控。需要说明的是，当第四过孔151、第五过孔152和第六过孔153均出现不良时，这些不良容易被检测出来，从而可及时调整工艺。
例如，在一些示例中，如图7所示，一行子像素组120中任意两个相邻的子像素组120中的第一子像素121的第四过孔151、第二子像素122的第五过孔152和第三子像素对126中的一个第三子像素123的第六过孔153大致位于第二直线上。由此，当工艺冗余量(margin)变动时，这些第四过孔151、第五过孔152和第六过孔153可同时上下移动，从而便于对工艺偏差进行管控。
例如，在一些示例中，如图7所示，第三子像素对126中的两个第三子像素123的两个第六过孔153分别位于相邻的两条第二直线上。也就是说，第三子像素对126中沿列方向排列的两个第三子像素123的两个第六过孔153中的一个与该第三子像素对126所属的子像素组行(可记作第N子像素组行)中的第四过孔151和第五过孔152位于同一直线，而另一个与该第三子像素对126所属的子像素组行相邻的子像素组行(可记作第N-1子像素组行)的第四过孔151和第五过孔152位于同一直线。
例如，在一些示例中，如图7所示，一行子像素组120中的第一直线和第二直线大致重合，例如为同一直线；也就是说，一行子像素组120中的第一过孔141、第二过孔142、部分第三过孔143、第四过孔151、第五过孔152和部分第六过孔153大致位于同一条直线上。由此，当工艺margin变动时，第一过孔141、第二过孔142、部分第三过孔143、第四过孔151、第五过孔152和部分第六过孔153可同时上下移动，从而便于对工艺偏差进行管控。例如，当工艺冗余量(margin)变动较大时，第一过孔141、第二过孔142、部分第三过孔143、第四过孔151、第五过孔152和部分第六过孔153同时上下移动，要么均出现不良，要么均没有不良，从而便于对工艺偏差进行管控。需要说明的是，当第一过孔141、第二过孔142、部分第三过孔143、第四过孔151、第五过孔152和部分第六过孔153均出现不良时，这些不良容易被检测出来，从而可及时调整工艺。
例如，在一些示例中，如图7所示，一行子像素组120中任意两个相邻的子像素组120中的第一子像素121的第一过孔141和第四过孔151、第二子像素122的第二过孔142和第五过孔152、和第三子像素对126中一个第三子像素123的第三过孔143和第六过孔153大致位于同一条直线上。由此，当工艺冗余量(margin)变动时，这些第一过孔141、第二过孔142、第三过孔143、 第四过孔151、第五过孔152和第六过孔153可同时上下移动，从而便于对工艺偏差进行管控。
例如，在一些示例中，如图7所示，一行子像素组120中的第一过孔141、第二过孔142、第三过孔143、第四过孔151、第五过孔152和第六过孔153在衬底基板110上的正投影互不交叠。
例如，在一些示例中，如图7所示，一行子像素组120中的第一过孔141、第二过孔142和第三过孔143等间距设置。
例如，在一些示例中，如图7所示，一行子像素组120中的第四过孔151、第五过孔152和第六过孔153等间距设置。
例如，在一些示例中，第四过孔151和第一过孔141之间的距离，第五过孔152与第二过孔142之间的距离，第六过孔153和第三过孔143之间的距离大致相等。需要说明的是，上述的第四过孔151和第一过孔141之间的距离是指同一第一子像素中的第四过孔151和第一过孔141之间的最短距离，同样地，上述的第五过孔152和第二过孔142之间的距离是指同一第二子像素中的第五过孔152和第二过孔142之间的最短距离，上述的第六过孔153和第三过孔143之间的距离是指同一第三子像素中的第六过孔153和第三过孔143之间的最短距离。例如，在一些示例中，第一过孔141与第四过孔151之间的距离小于第一过孔141与第二过孔142之间的距离，第二过孔142与第五过孔152之间的距离小于第二过孔142与第三过孔143之间的距离，第三过孔143与第六过孔153之间的距离小于第二过孔142与第三过孔143之间的距离。
例如，在一些示例中，如图7所示，各子像素组120中的第一子像素121、第二子像素122和第三子像素123的排列可参见图3所示的显示基板中像素排列结构，即第一子像素121、第二子像素122和第三子像素对126沿行方向排列，两个第三子像素123沿与列方向排列。
例如，在一些示例中，如图7所示，一行子像素组120中的第一过孔141、第二过孔142和143第三过孔位于相邻的两行子像素组120之间。
例如，在一些示例中，如图7所示，在各子像素组120中，第一子像素121、第二子像素122和包括两个第三子像素123的第三子像素对沿行方向排列，第三子像素对中的两个第三子像素123沿列方向排列。在这种像素排列下，位于同一直线上的第三过孔143和第六过孔153需要为该直线相邻的两行像素组中的第三子像素中的阳极和像素驱动电路提供电连接。此时，第四过孔151、第 一过孔141、第六过孔153、第三过孔143、第五过孔152、第二过孔142、第六过孔153、第三过孔143循环依次设置。
例如，在一些示例中，在第一子像素121为蓝色子像素，第二子像素122为红色子像素，第三子像素123为绿色子像素的情形下，第四过孔151、第一过孔141、第六过孔153、第三过孔143、第五过孔152、第二过孔142、第六过孔153、第三过孔143循环依次设置；此时，第四过孔151和第一过孔141为第一行的蓝色子像素的像素驱动电路和阳极提供电连接，第五过孔152、第二过孔142为第一行的红色子像素的像素驱动电路和阳极提供电连接，第一组第六过孔153和第三过孔143为第二行的绿色子像素的像素驱动电路和阳极提供电连接，第二组的第六过孔153和第三过孔143为第一行的绿色子像素的像素驱动电路和阳极提供电连接。
例如，在一些示例中，如图7所示，第四过孔151与第一过孔141之间的距离小于第一过孔141和第二过孔142之间的距离；第五过孔152与第二过孔142之间的距离小于第一过孔141和第二过孔142之间的距离；第六过孔153与第三过孔142之间的距离小于第一过孔141和第二过孔142之间的距离。例如，在一些示例中，第一阳极1212还包括第一连接电极块12125，在行方向上，第一连接电极块12125位于第一阳极1212的远离第二子像素122的一侧，第一连接电极块12125通过第一过孔141与第一像素驱动电极1216电性相连；第二阳极1222还包括第二连接电极块12225，第二连接电极块12225通过第二过孔142与第二像素驱动电极1226电性相连，第三阳极1232还包括第二连接电极块12325，第二连接电极块12325通过第三过孔143与第三像素驱动电极1236电性相连。
例如，在一些示例中，如图7所示，第一过孔141和第四过孔151位于第一阳极1212的主体部(与第一有效发光区交叠的部分)远离相邻的第二阳极1222的主体部(与第二有效发光区交叠的部分)的一侧，第四过孔151位于第一过孔141远离相邻的第一阳极1212的主体部的一侧。
例如，在一些示例中，如图7所示，第二过孔142位于第二阳极1222的主体部的正下方，也就是说，第二过孔132在行方向上的正投影与第二阳极1222的主体部在行方向上的正投影交叠。第五过孔152位于第二过孔142远离相邻的第三子像素对126的一侧。
例如，在一些示例中，如图7所示，第三子像素对126的两个第三过孔143 分别位于相邻的两条第一直线上，并且这两个第三过孔143分别位于第三子像素对126上下两侧，也就是说，两个第三过孔143在行方向上的正投影与第三子像素对126在行方向上的正投影交叠。第六过孔153位于对应的第三过孔143远离相邻的第一子像素121的一侧。
本公开一实施例还提供一种显示装置。该显示装置包括上述的显示基板。由于一行子像素组120中的第一过孔141、第二过孔142和第三过孔143大致位于同一条直线上，也就是说，第一过孔141、第二过孔142和第三过孔143布局排成一行，并且间距为一个子像素距离。由此，当工艺margin变动时，从而便于对工艺偏差进行管控。在显示装置采用本公开的实施例给出的像素排布结构的显示面板时，还可进一步提高该显示装置的分辨率，进而可提供一种具有真实的高分辨率的显示装置。另外，由于本公开的实施例给出的像素排列结构可具有较好的对称性，进而，可提高像素分布的均匀性，提高显示装置的显示效果。例如，在一些示例中，该显示装置可以为智能手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
有以下几点需要说明：
(1)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开同一实施例及不同实施例中的特征可以相互组合。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (29)

  1. 一种显示基板，包括：
    衬底基板；
    多个子像素组，在所述衬底基板上且沿行方向和列方向排列；以及
    第一隔垫物、第二隔垫物和第三隔垫物，
    其中，各所述子像素组包括第一子像素、第二子像素和第三子像素，
    在一行所述子像素组中，所述第一隔垫物位于相邻的所述第一子像素和所述第二子像素之间，所述第二隔垫物位于相邻的所述第二子像素和所述第三子像素之间，所述第三隔垫物位于相邻的所述第三子像素与所述第一子像素之间，所述第一隔垫物的数量、所述第二隔垫物的数量和所述第三隔垫物的数量大致相等。
  2. 根据权利要求1所述的显示基板，其中，在一行所述子像素组中，所述第一隔垫物、所述第二隔垫物和所述第三隔垫物依次循环设置。
  3. 根据权利要求1所述的显示基板，其中，各所述子像素组至多包括一个所述第一隔垫物、一个所述第二隔垫物或者一个所述第三隔垫物。
  4. 根据权利要求1-3中任一项所述的显示基板，其中，各所述子像素组包括一个所述第一子像素、一个所述第二子像素和一个第三子像素对，所述第三子像素对包括两个所述第三子像素，
    在一行所述子像素组中，所述第一隔垫物位于相邻的所述第一子像素和所述第二子像素之间，所述第二隔垫物位于相邻的所述第二子像素和所述第三子像素对之间，所述第三隔垫物位于相邻的所述第三子像素对与所述第一子像素之间。
  5. 根据权利要求4所述的显示基板，其中，在各所述子像素组中，所述第一子像素、所述第二子像素和所述第三子像素对沿所述行方向排列并形成三个子像素列，所述第三子像素对中的两个所述第三子像素沿所述列方向排列。
  6. 根据权利要求5所述的显示基板，其中，在一行所述子像素组中，所述第一隔垫物和所述第二隔垫物之间间隔1+3n个所述子像素列，所述第二隔垫物和所述第三隔垫物之间间隔1+3n个所述子像素列，所述第三隔垫物和所述第一隔垫物之间间隔1+3n个所述子像素列，n为大于等于1的正整数。
  7. 根据权利要求4-6中任一项所述的显示基板，其中，相邻的两行所述 子像素组错位1/2节距设置，所述节距为沿所述行方向相邻两个所述子像素组中的两个所述第一子像素的中心之间的距离。
  8. 根据权利要求1-6中任一项所述的显示基板，其中，所述第一子像素被配置为发第一颜色的光，所述第二子像素被配置为发第二颜色的光，所述第三子像素被配置为发第三颜色的光。
  9. 根据权利要求7所述的显示基板，其中，所述第一颜色为蓝色、所述第二颜色为红色、所述第三颜色为绿色。
  10. 根据权利要求4-9中任一项所述的显示基板，其中，所述第一隔垫物的形状大致为长条状，所述第一隔垫物的延伸方向与所述列方向大致平行，所述第二隔垫物的形状大致为长条状，所述第二隔垫物的延伸方向与所述列方向大致平行，所述第三隔垫物的形状大致为长条状，所述第三隔垫物的延伸方向与所述列方向大致平行。
  11. 根据权利要求10所述的显示基板，其中，所述第一隔垫物在所述列方向的尺寸小于所述第一子像素在所述列方向的尺寸，所述第二隔垫物和所述第三隔垫物在所述列方向的尺寸小于所述第三子像素对在所述列方向的尺寸，所述第一隔垫物的中心、所述第二隔垫物的中心、所述第三隔垫物的中心、所述第一子像素的中心、所述第二子像素的中心和所述第三子像素对的中心大致位于大致平行于所述行方向的直线上。
  12. 根据权利要求1-11中任一项所述的显示基板，其中，所述第一隔垫物、所述第二隔垫物和所述第三隔垫物具有相同的尺寸，所述第一隔垫物沿所述行方向的宽度范围为6-15微米，所述第一隔垫物沿所述列方向的长度为35-45微米，所述第一隔垫物沿同时垂直于所述衬底基板的方向上的高度范围为1.5-2.5微米。
  13. 根据所述权利要求1-12中任一项所述的显示基板，其中，第一子像素包括第一阳极和第一发光功能层，所述第二子像素包括第二阳极和第二发光功能层，所述第三子像素包括第三阳极和第三发光功能层，所述显示基板还包括：
    像素限定层，位于所述第一阳极、所述第二阳极和所述第三阳极远离所述衬底基板的一侧，且包括第一开口、第二开口和第三开口，所述第一开口暴露所述第一阳极，所述第二开口暴露所述第二阳极，所述第三开口暴露所述第三阳极，
    其中，所述第一发光功能层的至少一部分位于所述第一开口并覆盖所述第一阳极被暴露的部分，所述第二发光功能层的至少一部分位于所述第二开口并覆盖所述第二阳极被暴露的部分，所述第三发光功能层的至少一部分位于所述第三开口并覆盖所述第三阳极被暴露的部分，所述第一隔垫物、所述第二隔垫物和所述第三隔垫物位于所述像素限定层远离所述衬底基板的表面上。
  14. 根据权利要求13所述的显示基板，其中，所述第一隔垫物、所述第二隔垫物和所述第三隔垫物在所述衬底基板上的正投影与所述第一开口、所述第二开口和所述第三开口在所述衬底基板上的正投影不交叠。
  15. 根据权利要求13所述的显示基板，其中，所述第一隔垫物、所述第二隔垫物和所述第三隔垫物通过一次掩膜工艺形成。
  16. 一种显示装置，包括根据权利要求1-15中任一项所述的显示基板。
  17. 一种显示基板，包括：
    衬底基板；
    多个子像素组，在所述衬底基板上且沿行方向和列方向排列；
    其中，各所述子像素组包括一个第一子像素、一个第二子像素和一个第三子像素对，各所述第三子像素对包括两个第三子像素，所述第一子像素包括第一阳极和第一像素驱动电路，所述第二子像素包括第二阳极和第二像素驱动电路，所述第三子像素包括第三阳极和第三像素驱动电路，所述显示基板还包括第一平坦层，位于所述第一阳极和所述第一像素驱动电路之间，所述第二阳极和所述第二像素驱动电路之间，和所述第三阳极和所述第三像素驱动电路之间，所述第一子像素包括位于所述第一平坦层的第一过孔，所述第二子像素包括位于所述第一平坦层的第二过孔，所述第三子像素包括位于所述第一平坦层的第三过孔，
    所述第一过孔用于所述第一阳极与所述第一像素驱动电路的连接，所述第二过孔用于所述第二阳极与所述第二像素驱动电路的连接，所述第三过孔用于所述第三阳极与所述第三像素驱动电路的连接，
    在一行所述子像素组中的所述第一过孔、所述第二过孔和部分所述第三过孔大致位于第一直线上。
  18. 根据权利要求17所述的显示基板，其中，所述第一直线大致平行于所述行方向。
  19. 根据权利要求17所述的显示基板，其中，在各所述子像素组中，所 述第一子像素、所述第二子像素和所述第三子像素对沿所述行方向排列，所述第三子像素对中的两个所述第三子像素沿所述列方向排列，
    所述第三子像素对中的两个所述第三子像素的两个所述第三过孔分别位于相邻的两条所述第一直线上。
  20. 根据权利要求17-19中任一项所述的显示基板，还包括：
    第二平坦层，位于所述第一平坦层与所述第一像素驱动电路、所述第二像素驱动电路和所述第三像素驱动电路之间；
    第一连接电极、第二连接电极和第三连接电极，位于所述第二平坦层与所述第一平坦层之间，
    其中，所述第一像素驱动电路包括第一电极，所述第二像素驱动电路包括第二电极，所述第三像素驱动电路包括第三电极，所述第一子像素包括位于所述第二平坦层的第四过孔，所述第二子像素包括位于所述第二平坦层的第五过孔，所述第三子像素包括位于所述第二平坦层的第六过孔，所述第四过孔用于所述第一电极和第一连接电极的连接，所述第五过孔用于所述第二电极和第二连接电极的连接，所述第六过孔用于所述第三电极和第三连接电极的连接，一行所述子像素组中的所述第四过孔、所述第五过孔和部分所述第六过孔大致位于第二直线上。
  21. 根据权利要求20所述的显示基板，其中，所述第三子像素对中的两个所述第三子像素的两个所述第六过孔分别位于相邻的两条所述第二直线上。
  22. 根据权利要求20所述的显示基板，其中，在一行所述子像素组中，所述第一直线和所述第二直线大致重合。
  23. 根据权利要求22所述的显示基板，其中，一行所述子像素组中的所述第四过孔、所述第一过孔、所述第六过孔、所述第三过孔、所述第五过孔、所述第二过孔、所述第六过孔、所述第三过孔循环依次设置。
  24. 根据权利要求22所述的显示基板，其中，所述第一过孔、所述第二过孔、所述第三过孔、所述第四过孔、所述第五过孔和所述第六过孔相互间隔设置。
  25. 根据权利要求17-24中任一项所述的显示基板，其中，所述第一过孔、所述第二过孔和所述第三过孔等间距设置。
  26. 根据权利要求20-24中任一项所述的显示基板，其中，所述第四过孔、所述第五过孔和所述第六过孔等间距设置。
  27. 根据权利要求20-24中任一项所述的显示基板，其中，所述第一过孔与所述第四过孔之间的距离小于所述第一过孔与所述第二过孔之间的距离，所述第二过孔与所述第五过孔之间的距离小于所述第二过孔与所述第三过孔之间的距离，所述第三过孔与所述第六过孔之间的距离小于所述第二过孔与所述第三过孔之间的距离。
  28. 根据权利要求17-27中任一项所述的显示基板，其中，所述第一直线位于相邻的两行子像素组之间。
  29. 一种显示装置，包括根据权利要求17-28中任一项所述的显示基板。
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