WO2019153949A1 - 像素排列结构、显示基板和显示装置 - Google Patents

像素排列结构、显示基板和显示装置 Download PDF

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Publication number
WO2019153949A1
WO2019153949A1 PCT/CN2018/124884 CN2018124884W WO2019153949A1 WO 2019153949 A1 WO2019153949 A1 WO 2019153949A1 CN 2018124884 W CN2018124884 W CN 2018124884W WO 2019153949 A1 WO2019153949 A1 WO 2019153949A1
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WIPO (PCT)
Prior art keywords
pixel
sub
line segment
adjacent
pixels
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PCT/CN2018/124884
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English (en)
French (fr)
Inventor
刘利宾
杨倩
王红丽
皇甫鲁江
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2020535642A priority Critical patent/JP7322031B2/ja
Priority to US16/621,904 priority patent/US20200119107A1/en
Priority to EP18905193.1A priority patent/EP3751612A4/en
Publication of WO2019153949A1 publication Critical patent/WO2019153949A1/zh
Priority to JP2023121809A priority patent/JP2023138574A/ja

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different

Definitions

  • Embodiments of the present disclosure relate to a pixel arrangement structure, a display substrate, and a display device.
  • the resolution of a display device can be improved by reducing the size of pixels and reducing the spacing between pixels.
  • the reduction in the size of the pixel and the pitch between the pixels is also increasingly required for the precision of the manufacturing process, resulting in an increase in the manufacturing process of the display device and an increase in the manufacturing cost.
  • Sup-Pixel Rendering (SPR) technology can use the difference of the resolution of different color sub-pixels by the human eye, and change the conventional red, green and blue sub-pixels to simply define a pixel mode.
  • SPR Sup-Pixel Rendering
  • Embodiments of the present disclosure provide a pixel arrangement structure, a display substrate, and a display device.
  • the pixel arrangement structure can improve the distribution uniformity of the sensitive color sub-pixels by adjusting the pitch of the sensitive color sub-pixels, thereby improving the visual resolution of the pixel arrangement structure and improving the display quality of the pixel arrangement structure.
  • At least one embodiment of the present disclosure provides a pixel arrangement structure including a plurality of pixel groups; each pixel group includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel; in the pixel group a line connecting the center of the second sub-pixel and the center of the third sub-pixel as a first line segment; the first sub-pixel and the fourth sub-pixel being located in the second sub-pixel and the Between the third sub-pixels and the two sides of the first line segment; the connection between the center of the first sub-pixel and the center of the fourth sub-pixel is a second line segment; The length is less than the length of the first line segment.
  • the ratio of the length of the second line segment to the length of the first line segment is less than or equal to 3/4.
  • the second line segment and the first line segment are halved perpendicularly to each other.
  • the ratio of the length of the second line segment to the length of the first line segment is greater than or equal to 3/8.
  • the first sub-pixel and the fourth sub-pixel are both strip-shaped, and the extending direction of the first sub-pixel does not coincide with the extending direction of the fourth sub-pixel.
  • an angle between an extending direction of the first sub-pixel and an extending direction of the fourth sub-pixel is 70°-100°.
  • first sub-pixel and the fourth sub-pixel are symmetrically arranged with respect to the first line segment, and/or the second sub-pixel and the third sub-pixel are opposite to the second line segment Symmetrical arrangement.
  • the first line segment extends in a first direction
  • the second line segment extends in a second direction
  • the plurality of pixel groups are arranged in an array to form a plurality of rows and columns, even rows of pixel groups and odd rows
  • the pixel groups are misaligned; the lengths of the center lines of the adjacent second sub-pixels and the third sub-pixels of the two adjacent pixel groups in the first direction are smaller than the length of the first line segment
  • the length of the center line of the adjacent first sub-pixel and the fourth sub-pixel in the adjacent two adjacent pixel groups in the adjacent odd-numbered rows or adjacent adjacent-numbered rows Greater than the length of the second line segment.
  • the ratio of the length of the center line of the adjacent second sub-pixel and the third sub-pixel of the two adjacent pixel groups in the first direction to the first line segment is less than or equal to 1/ And/or adjacent first and second sub-pixels of two pixel groups adjacent in the second direction in adjacent odd-numbered rows or adjacent adjacent-numbered rows
  • the ratio of the length of the center line to the length of the second line segment is greater than or equal to 1 and less than or equal to 3.
  • an extension of the second line segment of each pixel group passes through a midpoint of a center line of two pixel groups adjacent to the pixel group in the second direction and located in the same row.
  • the center lines of the two third sub-pixels in the adjacent two pixel groups arranged in the second direction are located at the two The intersection of the first line segment in the pixel group between the three sub-pixels is located between the center of the first line segment and the center of the second sub-pixel.
  • the closest distance between the second sub-pixel and the first sub-pixel is L1
  • the closest distance between the second sub-pixel and the fourth sub-pixel is L2.
  • adjacent sub-pixels the opposite sides are approximately parallel or at an angle of less than 45°, and the adjacent sub-pixels include the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel. Any two adjacent.
  • the first sub-pixel and the fourth sub-pixel are sub-pixels of the same color.
  • At least one embodiment of the present disclosure provides a display substrate including a pixel arrangement structure provided by at least one embodiment of the present disclosure.
  • At least one embodiment of the present disclosure provides a display device including a display substrate provided by at least one embodiment of the present disclosure.
  • 1 is a schematic view of a pixel arrangement structure
  • FIG. 2 is a schematic diagram of a pixel arrangement structure according to an embodiment of the present disclosure
  • 3A is a schematic diagram of a pixel arrangement structure according to an embodiment of the present disclosure.
  • 3B is a schematic diagram of a pixel arrangement structure according to another embodiment of the present disclosure.
  • 3C is a schematic diagram of a pixel arrangement structure according to another embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a pixel arrangement structure according to an embodiment of the present disclosure.
  • FIG. 5A is a schematic diagram of a pixel arrangement structure according to another embodiment of the present disclosure.
  • FIG. 5B is a schematic diagram of a pixel arrangement structure according to another embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a pixel arrangement structure according to another embodiment of the present disclosure.
  • FIG. 7A is a schematic diagram of a pixel arrangement structure according to another embodiment of the present disclosure.
  • FIG. 7B is a schematic diagram of a pixel arrangement structure according to another embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a pixel arrangement structure of a display substrate, and a driving line and a data line according to another embodiment of the present disclosure
  • FIG. 9 is a cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 1 shows a schematic diagram of a pixel arrangement structure.
  • the pixel arrangement is a typical penile arrangement, and a minimum repeating unit includes two green sub-pixels 0111, one red sub-pixel 0112 and one blue sub-pixel 0113.
  • the pixels are evenly arranged and are easy to realize.
  • PPI Pigel Per Inch
  • the inventors of the present application have found that in the pixel arrangement structure shown in FIG. 1, the two green sub-pixels 0111 in the minimum repeating unit are far apart, which is disadvantageous for improving the visual resolution, and is easy to appear colored edges and grainy.
  • the center line LS02 of the two green sub-pixels 0111 is substantially the same as the length of the line LS01 of the center of the red sub-pixel 0112 and the center of the blue sub-pixel 0113 in the minimum repeating unit.
  • AMOLED Active Matrix Organic Light-Emitting Diode
  • FMM Fine Metal Mask
  • An active matrix organic light emitting diode (AMOLED) display device having a high resolution for example, greater than 300 pixel density (PPI)
  • PPI pixel density
  • each pixel group 01 includes a first sub-pixel 111, a second sub-pixel 112, a third sub-pixel 113, and a fourth sub-pixel 114.
  • the line connecting the center C2 of the second sub-pixel 112 and the center C3 of the third sub-pixel 113 is the first line segment LS1; the first sub-pixel 111 and the fourth sub-pixel 114 are located at the second sub-pixel 112.
  • the third sub-pixel 113 are disposed on both sides of the first line segment LS1.
  • a line connecting the center C1 of the first sub-pixel 111 and the center C4 of the fourth sub-pixel 114 is the second line segment LS2.
  • the length of the second line segment LS2 is smaller than the length of the first line segment LS1.
  • the ratio of the length of the second line segment LS2 to the length of the first line segment LS1 is less than or equal to 3/4.
  • the pixel arrangement structure reduces the distance between the first sub-pixel and the fourth sub-pixel in the same pixel group.
  • the pixel arrangement is tighter, the color mixing risk is reduced, and the color is improved. Improve the visual graininess.
  • the spacing between the sub-pixels can be widened to facilitate fabrication.
  • the degree of closeness of the pixel arrangement and the spacing between the sub-pixels can be balanced, and a balance is sought between the two, so that the pixels are arranged relatively closely and the spacing between the sub-pixels is increased to some extent (the pixel defines the layer spacing). It is beneficial to reduce the risk of color mixing, improve the color fringing, improve the visual graininess and widen the spacing between sub-pixels.
  • each sub-pixel given in the embodiment of the present disclosure may be defined by a pixel definition layer, but is not limited thereto.
  • each sub-pixel in the drawing is an actual light-emitting area.
  • the specific shape of each sub-pixel can be set according to a preparation process.
  • the actual light emitting region may be determined by the shape of at least one of the electrode, the light emitting layer, and the pixel defining layer.
  • the illuminating layer graphic application of the first sub-pixel and the fourth sub-pixel in the same pixel group may also be applied.
  • the same opening of the mask is formed by evaporation.
  • the first sub-pixel 111 and the fourth sub-pixel 114 may be sub-pixels of a human-sensitive color, and may be, for example, a green sub-pixel, a yellow sub-pixel, a white sub-pixel, or the like.
  • the areas of the first sub-pixel 111 and the fourth sub-pixel 114 are relatively small compared to the second sub-pixel 112 and the third sub-pixel 113.
  • the area of the first sub-pixel 111 is smaller than the second sub-pixel 112, and/or the area of the first sub-pixel 111 is smaller than the area of the third sub-pixel 113.
  • the fourth sub-pixel 114 can refer to the above description for the area of the first sub-pixel 111. That is, the area of the fourth sub-pixel 114 is smaller than the second sub-pixel 112, and/or the area of the fourth sub-pixel 114 is smaller than the area of the third sub-pixel 113.
  • the pixel arrangement structure can improve the distribution uniformity of the sensitive color sub-pixels by adjusting the pitch of the visual position sensitive color sub-pixels, thereby improving the visual resolution of the pixel arrangement structure and improving the display. quality.
  • the second sub-pixel 112 and the third sub-pixel 113 may be sub-pixels of a human-insensitive color.
  • one of the second sub-pixel 112 and the third sub-pixel 113 is a red sub-pixel, and the other is a blue sub-pixel, but is not limited thereto.
  • the second sub-pixel 112 is a red sub-pixel
  • the third sub-pixel 113 is a blue sub-pixel as an example. It should be noted that when the pixel arrangement structure adopts the red, green and blue (RGB) mode, the above-mentioned human eye sensitive color may be green.
  • RGB red, green and blue
  • the first line segment LS1 may extend in the first direction X
  • the second line segment LS2 may extend in the second direction Y.
  • the first direction X is perpendicular to the second direction Y.
  • the first sub-pixel 111 and the fourth sub-pixel 114 are arranged with the first direction X as an axis of symmetry to make the pixel structure arrangement more uniform.
  • the first sub-pixel 111 is evenly arranged with respect to the second sub-pixel 112 and the third sub-pixel 113 to be consistent, so that the pixel structure is arranged more uniformly.
  • the second line segment LS2 is perpendicular to the first line segment LS1.
  • the pixel arrangement can be made more uniform.
  • the second line segment LS2 is located on the vertical line of the first line segment LS1.
  • the widths of the sub-pixels of the respective colors in the first direction X may be the same, but are not limited thereto.
  • the pixel structure distribution can be made more uniform, the picture display quality is higher, and the display graininess problem under the lower PPI is improved.
  • a plurality of square dotted frames are given, each of which has a length of 1/2 L, and four dotted frames can form a square having a side length L.
  • the pixel group 01 can be the smallest repeating unit of the pixel arrangement structure.
  • the pixel arrangement can be obtained by translational replication of the smallest repeating unit.
  • sub-units that are translatable and repeatable to be arranged to form a pixel structure are not included in the minimum repeating unit.
  • the first line segment SL1 is perpendicular to the second line segment SL2 and is equally halved to each other.
  • the first line segment SL1 vertically bisects the second line segment SL2.
  • the second line segment SL2 also vertically bisects the first line segment SL1.
  • the maximum area enclosed by the line connecting the centers of the first sub-pixel 111, the second sub-pixel 112, the fourth sub-pixel 114, and the third sub-pixel 113 is a diamond
  • the first line segment SL1 and the The second line segment SL2 is the diagonal of the diamond shape, respectively.
  • the distance between the center C1 of the first sub-pixel 111 and the center C4 of the fourth sub-pixel 114 may be greater than or equal to 1/2 L, for example, the distance may range from 1 /2L to L.
  • the first sub-pixel 111 and the fourth sub-pixel may adopt sub-pixels of the same color.
  • the setting of the distance can also avoid adjacent neighbors caused by the proximity of the adjacent first sub-pixels.
  • the two first sub-pixels are difficult to distinguish and are visually combined into one by the human eye, so that the resulting graininess can be avoided.
  • the pixel arrangement structure can improve the uniformity of distribution of the first sub-pixels, thereby improving visual resolution and also improving display quality.
  • the distance between the center C3 of the third sub-pixel 113 and the center C2 of the second sub-pixel 112 may be 4/3L.
  • the third sub-pixel 113 and the second sub-pixel 112 in the same pixel group may be enlarged under the condition of the process. The distance, and/or, reduces the distance between the first sub-pixel 111 and the fourth sub-pixel 114.
  • the ratio of the length of the second line segment LS2 to the length of the first line segment LS1 may be greater than or equal to 3/8. .
  • the first sub-pixel 111 and the second sub-pixel 112 are sub-pixels of different colors, and the first sub-pixel 111 and the second sub-pixel 112 form one pixel P, and the third sub-pixel
  • the pixel 113 and the fourth sub-pixel 114 are sub-pixels of different colors, and the third sub-pixel 113 and the fourth sub-pixel 114 form one pixel P.
  • the first sub-pixel 111 and the fourth sub-pixel 114 are green sub-pixels
  • the second sub-pixel 112 is a red sub-pixel
  • the third sub-pixel 113 is a blue sub-pixel.
  • one red sub-pixel and one green sub-pixel form one pixel
  • one blue sub-pixel and one green sub-pixel form one pixel.
  • the pixel P here only includes sub-pixels of two colors, and it is necessary to borrow a sub-pixel of other pixels in the surrounding image for color display when displaying an image. Therefore, the pixel P here may also be referred to as a virtual pixel.
  • the pixel arrangement structure in which the broken line given in Fig. 2 is removed is shown in Fig. 3A.
  • the dotted lines, centers, and the like given in the embodiments of the present disclosure are virtual lines, virtual centers, for convenience of description.
  • the center may be the center of gravity, the intersection of the vertical bisectors of the opposite sides, and the like, but is not limited thereto.
  • FIG. 3B illustrates a pixel arrangement structure provided in accordance with one or more embodiments of the present disclosure.
  • the first sub-pixel 111 and the fourth sub-pixel 114 adopt the same color. For example, they are all the first sub-pixels 111. Since the homochromatic sub-pixels have no color mixing problem, the light-emitting layer patterns of the first sub-pixel 111 and the fourth sub-pixel 114 in the same pixel group 01 can be evaporated by using the same opening of the mask, thereby facilitating the release of the mask. Net, the tension of the net is small, and the quality of the net is improved.
  • the pixel arrangement structure can improve the visual resolution.
  • FIG. 3C illustrates a pixel arrangement structure provided in accordance with one or more embodiments of the present disclosure.
  • the first sub-pixel 111 and the fourth sub-pixel 114 are sub-pixels of the same color, for example, may include two types of pixel groups, the same color in one type of pixel group.
  • the pair of sub-pixels is a first sub-pixel (eg, a green sub-pixel), and the pair of sub-pixels of the same color in another type of pixel group is a fourth sub-pixel (eg, a white sub-pixel or a yellow sub-pixel).
  • FIG. 4 illustrates a pixel arrangement structure according to one or more embodiments of the present disclosure.
  • the first line segment LS1 may extend along the first direction X, and the two adjacent ones in the first direction X.
  • the length D1 of the center line LS3 between the adjacent second sub-pixel 112 and the third sub-pixel 113 in the pixel group 01 is smaller than the length of the first line segment LS1, so that the pixels can be closely arranged.
  • the length of the first line segment LS1 is 4/3 L as an example, but is not limited thereto.
  • the length of the first line segment LS1 may range from 11/9L to 13/9L.
  • the center of the adjacent second sub-pixels 112 and the center of the third sub-pixel 113 in the two pixel groups 01 adjacent in the first direction is less than or equal to 1/2.
  • the length of the distance D1 is 2/3 L as an example, but it is not limited thereto.
  • the distance D1 may range in length from 5/9L-7/9L.
  • a plurality of pixel groups 01 are arranged in an array, including a plurality of rows and columns, for example, may include a plurality of first pixels located in odd rows.
  • pixel groups of even rows and pixel groups of odd rows are misaligned.
  • the second line segment LS2 may extend in the second direction Y.
  • the length D2 of the center line L14 of the pixel 111 and the fourth sub-pixel 114 is greater than the length of the second line segment LS2.
  • the center of adjacent first and second sub-pixels 111, 114 of the two adjacent pixel groups 01 in the second direction Y is greater than or equal to 1 and less than or equal to 3.
  • the center of adjacent first and second sub-pixels 111, 114 of the two adjacent pixel groups 01 in the second direction Y The length D2 of the line L14 is greater than the length of the second line segment LS2.
  • the odd row pixel group and the even row pixel group are misaligned.
  • the length of the half pixel group in the first direction X may be misaligned in the first direction X, for example, the misalignment length is L, but is not limited thereto.
  • the center of adjacent first and second sub-pixels 111, 114 of the two adjacent pixel groups 01 in the second direction Y The ratio of the length D2 of the line L14 to the length of the second line segment LS2 is greater than or equal to 1 and less than or equal to 3.
  • an extension line of the second line segment LS2 of each pixel group 01 is adjacent to the pixel group 01 in the second direction Y and
  • the center of two pixel groups 01 located in the same row is connected to the midpoint C0 of the LSC.
  • the center of each pixel group 01 is C1
  • the line connecting the centers C1 of two adjacent pixel groups 01 is the center line LSC.
  • the center C1 of the pixel group 01 may be the intersection of the first line segment LS1 and the second line segment LS2.
  • an extension line of the second line segment LS2 of each first pixel group 011 passes through the adjacent third sub-pixel 113 of the two second pixel groups 012 adjacent to the first pixel group 011 and located in the same row and
  • the center of the second sub-pixel 112 is connected to the center C5 of the line LS3.
  • center C5 and center C0 can be the same point.
  • a pixel arrangement structure adjacent two pixel groups arranged in a second direction Y in adjacent odd rows or adjacent adjacent rows a center line LS4 of two of the third sub-pixels 113 of the 01 (adjacent two first pixel groups 011 or two adjacent second pixel groups 012) and a pixel between the two third sub-pixels 113
  • the intersection IP1 of the first line segment LS1 in the group 01 is located between the center IP0 of the first line segment LS1 and the center C2 of the second sub-pixel 112.
  • the center IP0 of the first line segment LS1 may be the center C1 of the pixel group 01.
  • the intersection IP1 is located at the midpoint of the line connecting the center IP0 of the first line segment LS1 and the center C2 of the second sub-pixel 112.
  • the center line LS4 of the two third sub-pixels 113 of the adjacent first pixel group 011 in the same column and the second pixel group 012 adjacent to the third sub-pixel 113 The intersection IP1 of the first line segment LS1 is located between the intersection of the first line segment LS1 of the first line segment LS1 of the second pixel group 012 and the intersection point IP0 of the second line segment LS2 and the center C2 of the second sub-pixel 112.
  • the third sub-pixel 113 in the above description may also be replaced with the second sub-pixel 112.
  • adjacent two pixel groups 01 arranged in the second direction Y adjacent two first pixel groups 011 or two adjacent second pixels
  • the intersection of the center line of the two second sub-pixels 112 in the group 012) and the first line segment LS1 in the pixel group 01 between the two second sub-pixels 112 is located at the center of the first line segment LS1
  • the IP0 is between the center C3 of the third sub-pixel 113.
  • the intersection is located at the midpoint of the line connecting the center IP0 of the first line segment LS1 and the center C3 of the third sub-pixel 113.
  • a pixel arrangement structure in which a closest distance between a second sub-pixel 112 and a first sub-pixel 111 is L1 and a second sub-pixel 112 in the same pixel group.
  • the closest distance to the fourth sub-pixel 114 is L2
  • the closest distance between the third sub-pixel 113 and the first sub-pixel 111 is L3
  • the closest distance between the third sub-pixel 113 and the fourth sub-pixel 114 is L4
  • a pixel arrangement structure As shown in FIG. 4, according to one or more embodiments of the present disclosure, a pixel arrangement structure, a first sub-pixel 111 or a fourth sub-pixel 114 and a pixel group adjacent thereto and not in the same row in the second direction are provided.
  • L1, L2, L3, L4, L5, and L6 reference may also be made to the annotation of the minimum process spacing d in FIGS. 7A and 7B. Each nearest distance is the minimum distance between two sub-pixels.
  • L1, L2, L3, L4, L5, and L6 may be made as close as possible to the minimum process pitch d.
  • each of the opposite sides is approximately parallel or at an angle of less than 45°, and the adjacent sub-pixel includes the first sub-pixel 111 . Any two adjacent ones of the second sub-pixel 112, the third sub-pixel 113, and the fourth sub-pixel 114.
  • the first sub-pixel 111 and the fourth sub-pixel 114 are all strip-shaped, and the extending direction A1 and the fourth sub-pixel 111 extend.
  • the extending direction A2 of the pixels 114 does not coincide.
  • the extending direction A1 of the first sub-pixel 111 intersects or has an included angle with the extending direction A2 of the fourth sub-pixel 114.
  • the first sub-pixel 111 and the fourth sub-pixel 114 are arranged in the first direction X as an axis of symmetry, and are inclined at a certain angle.
  • the angle of inclination is in the range of 30° to 50° from the first direction X, and further, for example, the angle is 45°, but is not limited thereto.
  • the extending direction A1 of the first sub-pixel 111 may be the long-axis direction of the first sub-pixel 111, but is not limited thereto.
  • the extending direction A2 of the fourth sub-pixel 114 may be the long-axis direction of the fourth sub-pixel 114, but is not limited thereto.
  • the first sub-pixel 111 and the fourth sub-pixel 114 are symmetrically arranged with respect to the first line segment LS1.
  • the first sub-pixel 111 and the fourth sub-pixel 114 are asymmetrically arranged with respect to the second line segment LS2.
  • the second sub-pixel 112 and the third sub-pixel 113 are symmetrically arranged with respect to the second line segment LS2, but are not limited thereto.
  • the strip shape means that the length in one direction is longer than the length in the other direction, or the size in one direction is larger than the other direction size.
  • the strip shape is not limited to a rectangle, and may be other shapes, for example, may be a long hexagon, a long ellipse, a trapezoid or the like.
  • the shape of each sub-pixel is not limited to a regular shape, and may be an irregular shape.
  • the angle between the extending direction A1 of the first sub-pixel 111 and the extending direction A2 of the fourth sub-pixel 114 is 70°-100°, and further, the angle may be 80°-95°, and further, the angle may be It is 90° (right angle), and thus, the first sub-pixel 111 and the fourth sub-pixel 114 which form a large area can be utilized to increase the light-emitting area, and it is advantageous to fabricate a web at the time of mask production of the light-emitting layer pattern.
  • a right angle deviations of a few degrees above and below may be allowed. For example, it can be offset from the 90° up and down by 5°.
  • FIG. 5B illustrates a pixel arrangement structure according to one or more embodiments of the present disclosure.
  • the angle between the extending direction A1 of the first sub-pixel 111 and the extending direction A2 of the fourth sub-pixel 114 is a right angle, and is in the same pixel.
  • the first sub-pixel 111 and the fourth sub-pixel 114 are the same color sub-pixels.
  • FIG. 6 illustrates a pixel arrangement structure provided according to one or more embodiments of the present disclosure.
  • the second sub-pixel 112 and the third sub-pixel 113 may be in the shape of a diamond or an approximately diamond.
  • the approximate diamond shape includes, for example, a rounded rhombus, a chamfered diamond, or the like, but is not limited thereto.
  • the sub-pixel shape of the shape of a diamond or an approximately diamond shape is more advantageous for pixel arrangement.
  • the first sub-pixel 111 can be symmetrically surrounded around the third sub-pixel 113 and the second sub-pixel 112, and the long sides of the first sub-pixel 111 are all facing the second sub-pixel 112, and the short sides are all facing
  • the three sub-pixels 113 ensure the uniformity of the pixel arrangement to the utmost extent.
  • the arrangement of the first sub-pixels 111 is more uniform, and the color edges can be improved to some extent, which is beneficial to the realization of high PPI, and can increase the pixel aperture ratio as high as possible.
  • each sub-pixel is not limited to the above, and the shape of the sub-pixel can be adjusted as needed.
  • Area maximization is the main principle for determining the shape of a sub-pixel.
  • the sub-pixel spacing of different colors needs to be greater than the minimum process spacing d of the patterning process, and then consider the special symmetry requirements of the special process.
  • the FMM network wants the opening pattern and the distribution symmetry
  • the first sub-pixel and the fourth The shape of the sub-pixels may be a symmetrical pentagon of a right-angled bottom angle (as shown in FIG. 2). It can be seen that the second and third sub-pixel pitches between adjacent groups of pixels using symmetric shaped sub-pixels are significantly larger than the other different color sub-pixel spacings (minimum process spacing d), ie, there is still an available area in the design.
  • the asymmetric sub-pixel shape can be used to achieve the largest sub-pixel area.
  • the shape of the second sub-pixel 112 and the third sub-pixel 113 may be a rectangular trapezoid or a cut according to a minimum pattern pitch d of different patterning processes. Remove the right angle trapezoid of the acute angle to maximize the area.
  • the shapes of the second sub-pixel 112 and the third sub-pixel 113 are both right-angled trapezoids, the shapes of the second sub-pixel 112 and the third sub-pixel 113 are hexagonal (two right-angled bottoms).
  • the acute corners 190 of the second sub-pixel 112 and the third sub-pixel 113 may further increase the areas of the second sub-pixel 112 and the third sub-pixel 113, thereby further increasing the pixel.
  • Space utilization within the group The pixel arrangement structure can improve the space utilization rate within the pixel group.
  • the shapes of the second sub-pixel 112 and the third sub-pixel 113 are all isosceles trapezoids whose acute angles are chamfered. Therefore, in the case where the process precision is constant, that is, in the case where the distance between the first sub-pixel 111 and the second sub-pixel 112 and the third sub-pixel 113 is constant, the second sub-pixel 112 and the third sub-pixel are added. The area of 113, thereby increasing the utilization of space within the pixel group.
  • the shapes of the second sub-pixel 112 and the third sub-pixel 113 include at least one of an isosceles trapezoid, a hexagon, and a diamond, and the second sub-pixel 112 includes five sides. At least one of a shape, a rectangle, and an approximate rectangle.
  • the approximate rectangle includes, for example, a rounded rectangle, but is not limited thereto.
  • At least one embodiment of the present disclosure provides a display substrate including any of the above pixel arrangement structures.
  • FIG. 8 illustrates a display substrate provided in accordance with one or more embodiments of the present disclosure.
  • the third sub-pixel 113 and the first sub-pixel 111 may be driven by the first driving line DL1
  • the second sub-pixel 112 and the fourth sub-pixel 114 may adopt the second driving line.
  • DL2 driver The first driving line DL1 extends in the E1 direction
  • the second driving line DL2 extends in the E1 direction.
  • the E1 direction is parallel to the first direction X.
  • the first sub-pixel 111 and the fourth sub-pixel 114 in the odd-numbered column pixel group may input a data signal by using the first data line DT1, and the second sub-between the two adjacent first data lines DT1.
  • the pixel 112 and the third sub-pixel 113 may input a data signal using the second data line DT2.
  • the data signal includes voltage and/or current.
  • the first data line DT1 extends in the E2 direction
  • the second data line DT2 also extends in the E2 direction
  • the E2 direction is parallel to the second direction Y.
  • one pixel unit group includes two pixel units, for example, the first sub-pixel 111 and the second sub-pixel 112 form one pixel unit, and the third sub-pixel 113 and the fourth sub-pixel 114 form another pixel unit.
  • a third sub-pixel 111 or a fourth sub-pixel 114 adjacent thereto may be shared in each pixel unit to form a virtual pixel.
  • the display is implemented by means of sub-pixel sharing.
  • FIG. 9 is a cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • the structure includes a base substrate 001 and a buffer layer 002 sequentially disposed on the base substrate 001, a first gate insulating layer 003, a second gate insulating layer 004, an interlayer dielectric layer 005, and a flat surface.
  • the thin film transistor structure including a gate 302, an active layer 301, and a drain electrode 303.
  • the thin film transistor may be a thin film transistor in a pixel driving circuit, and the connection relationship with other components may be set according to a specific pixel circuit arrangement, which will not be shown in detail herein.
  • a signal line 304 may be further included at a position in the same layer as the drain electrode 303, and the signal line 304 may also be used as a signal line of a specific function according to a different pixel circuit arrangement, for example, a data line or a gate line or the like.
  • the pixel defining layer 007 can include openings that define sub-pixels.
  • the anode 403 of the sub-pixel and the light-emitting layer 503 of the third sub-pixel are located in the opening of the pixel defining layer 007. It should be noted that the structure of the display substrate is not limited to that shown in FIG.
  • the anode 403 and the light-emitting layer 503 are in contact with each other, so that the light-emitting layer can be driven to emit light at portions contacting each other, and therefore, the portion where the anode 403 and the light-emitting layer 503 are in contact with each other is an effective portion through which the sub-pixel can emit light.
  • the anode 403 functions as a pixel electrode, so that different data voltages can be applied to different sub-pixels.
  • the electrode serving as the pixel electrode of the sub-pixel is not limited to the anode, and the cathode of the light emitting diode may be used as the pixel electrode.
  • the shape of the sub-pixel may refer to a shape of a portion where the pixel electrode and the light-emitting layer are in contact with each other.
  • the area of the pixel electrode may be slightly larger than the area of the light-emitting layer, or the area of the light-emitting layer may be slightly larger than the area of the pixel electrode, which is not particularly limited in the embodiment of the present disclosure.
  • the light-emitting layer herein may include the electroluminescent layer itself and other functional layers on both sides of the electroluminescent layer, for example, a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, and the like.
  • the shape of the pixel can also be defined by a pixel defining layer.
  • a lower electrode (for example, an anode) of the light emitting diode may be disposed under the pixel defining layer, the pixel defining layer including an opening for defining a pixel, the opening exposing a portion of the lower electrode, and the light emitting layer is formed on the pixel defining layer In the middle opening, the light-emitting layer is in contact with the lower electrode, so that the light-emitting layer can be driven to emit light in this portion. Therefore, in this case, the opening of the pixel defining layer defines the shape of the sub-pixel.
  • the pixel circuit includes at least one transistor including a gate, an active layer, and a source and drain.
  • the signal lines are electrically connected to the source or drain of the respective transistor by vias through the insulating layer underneath.
  • the active layer of the transistor is formed of a polysilicon layer, and on both sides of the channel region of the active layer, the polysilicon layer is conductorized to form a source drain.
  • the signal line is electrically connected to the polysilicon source or drain formed by being formed by via holes.
  • the transistor is a top gate transistor, and a via for electrically connecting the signal line to a source or a drain of the corresponding transistor passes through the gate metal layer and the data metal layer, and the gate metal layer and A portion of the metal pattern of the data metal layer may serve as a relay connection for via electrical connection, but embodiments in accordance with the present disclosure are not limited thereto.
  • the shapes of the various sub-pixels described in the embodiments of the present disclosure are all substantially shaped, and when the light-emitting layer or various electrode layers are formed, the edges of the sub-pixels are not guaranteed to be strictly straight and the angle is strict. Horny.
  • the light-emitting layer may be formed by an evaporation process through a mask, and thus, the corner portion thereof may have a rounded shape.
  • the metal etch has a draft angle, and therefore, when the luminescent layer of the sub-pixel is formed by an evaporation process, a corner of the luminescent layer may be removed.
  • the shape of the sub-pixel is the shape of the orthographic projection of the sub-pixel on the substrate.
  • At least one embodiment of the present disclosure provides a display device including any of the above display substrates. Therefore, the resolution of the display device can be improved, and thus a display device having a true high resolution can be provided. In addition, since the symmetry of the pixel arrangement structure is better, the display device has a better display effect.
  • the display device can be any product or component having a display function, such as a smartphone, tablet, television, display, notebook, digital photo frame, navigator, and the like.

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Abstract

一种像素排列结构、显示基板和显示装置。该像素排列结构包括多个像素组(01)；每个像素组(01)包括第一子像素(111)、第二子像素(112)、第三子像素(113)和第四子像素(114)；在像素组(01)中，第二子像素(112)的中心(C2)和第三子像素(113)的中心(C3)的连线为第一线段(LS1)；第一子像素(111)和第四子像素(114)位于第二子像素(112)和第三子像素(113)之间且分设于第一线段(LS1)的两侧；第一子像素(111)的中心(C1)和第四子像素(114)的中心(C4)的连线为第二线段(LS2)，所述第二线段(LS2)的长度小于所述第一线段(LS1)的长度。由此，该像素排列结构可提高分辨率，并且还可提升显示质量。

Description

像素排列结构、显示基板和显示装置
相关申请的交叉引用
本专利申请要求于2018年2月9日递交的中国专利申请第201810137016.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本公开的实施例的一部分。
技术领域
本公开的实施例涉及一种像素排列结构、显示基板和显示装置。
背景技术
随着显示技术的不断发展，人们对于显示装置的分辨率的要求也越来越高。由于具有显示质量高等优点，高分辨率显示装置的应用范围也越来越广。通常，可通过减小像素的尺寸和减小像素间的间距来提高显示装置的分辨率。然而，像素的尺寸和像素间的间距的减少对制作工艺的精度要求也越来越高，从而导致显示装置的制作工艺的难度和制作成本的增加。
另一方面，子像素渲染(Sup-Pixel Rendering，SPR)技术可以利用人眼对不同色彩子像素的分辨率的差异，改变常规的红、绿、蓝三色子像素简单定义一个像素的模式，通过不同的像素间共享某些位置分辨率不敏感颜色的子像素，用相对较少的子像素数，模拟实现相同的像素分辨率表现能力，从而降低制作工艺的难度和制作成本。
发明内容
本公开实施例提供一种像素排列结构、显示基板和显示装置。该像素排列结构可通过调节敏感颜色子像素的间距，改善敏感颜色子像素的分布均匀性，从而可提高该像素排列结构视觉上的分辨率，并且还可提高该像素排列结构的显示质量。
本公开至少一实施例提供一种像素排列结构，包括多个像素组；每个像素组包括第一子像素、第二子像素、第三子像素和第四子像素；在所述像素组中，所述第二子像素的中心和所述第三子像素的中心的连线为第一线段； 所述第一子像素和所述第四子像素位于所述第二子像素和所述第三子像素之间且分设于所述第一线段的两侧；所述第一子像素的中心和所述第四子像素的中心的连线为第二线段；所述第二线段的长度小于所述第一线段的长度。
例如，所述第二线段与所述第一线段的长度之比小于或等于3/4。
例如，所述第二线段和所述第一线段互相垂直平分。
例如，所述第二线段与所述第一线段的长度之比大于或等于3/8。
例如，在所述像素组中，所述第一子像素和所述第四子像素均为条形，所述第一子像素的延伸方向与所述第四子像素的延伸方向不重合。
例如，所述第一子像素的延伸方向与所述第四子像素的延伸方向的夹角为70°-100°。
例如，所述第一子像素和所述第四子像素相对于所述第一线段对称排列，和/或者，所述第二子像素和所述第三子像素相对于所述第二线段对称排列。
例如，所述第一线段沿第一方向延伸，所述第二线段沿第二方向延伸；所述多个像素组呈阵列排列，形成多行和多列，偶数行的像素组和奇数行的像素组错位排布；在所述第一方向上相邻的两个像素组中的相邻的第二子像素和第三子像素的中心连线的长度小于所述第一线段的长度；在相邻的奇数行或者在相邻的偶数行中，在所述第二方向上相邻的两个像素组中的相邻的第一子像素和第四子像素的中心连线的长度大于所述第二线段的长度。
例如，在所述第一方向上相邻的两个像素组中的相邻的第二子像素和第三子像素的中心连线的长度与所述第一线段的比值小于或等于1/2；和/或者，在相邻的奇数行或者在相邻的偶数行中，在所述第二方向上相邻的两个像素组中的相邻的第一子像素和第四子像素的中心连线的长度与所述第二线段的长度的比值大于等于1并且小于等于3。
例如，每个像素组的所述第二线段的延长线穿过在第二方向上与该像素组相邻并且位于同一行的两个像素组的中心连线的中点。
例如，在相邻的奇数行或者在相邻的偶数行中，在所述第二方向上排列的相邻两个像素组中的两个第三子像素的中心连线和位于该两个第三子像素之间的像素组中的第一线段的交点位于该第一线段的中心与第二子像素的中心之间。
例如，同一像素组中，所述第二子像素与所述第一子像素之间的最近距 离为L1，所述第二子像素与所述第四子像素之间的最近距离为L2，所述第三子像素与所述第一子像素之间的最近距离为L3，所述第三子像素与所述第四子像素之间的最近距离为L4，L1＝L2＝L3＝L4。
例如，所述第一子像素或所述第四子像素和在所述第二方向上与其相邻的且与其不在同一行的像素组中的第二子像素和第三子像素的最近距离分别为L5和L6，L5＝L6。
例如，相邻子像素中，各相对的边大概平行或夹角小于45°，所述相邻子像素包括所述第一子像素、第二子像素、第三子像素和第四子像素中任意相邻的两个。
例如，所述第一子像素和所述第四子像素为同一颜色的子像素。
本公开至少一实施例提供一种显示基板，包括本公开至少一实施例提供的像素排列结构。
本公开至少一实施例提供一种显示装置，包括本公开至少一实施例提供的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种像素排列结构的示意图；
图2为本公开一实施例提供的一种像素排列结构的示意图；
图3A为本公开一实施例提供的一种像素排列结构的示意图；
图3B为本公开另一实施例提供的一种像素排列结构的示意图；
图3C为本公开另一实施例提供的一种像素排列结构的示意图；
图4为本公开一实施例提供的一种像素排列结构的示意图；
图5A为本公开另一实施例提供的一种像素排列结构的示意图；
图5B为本公开另一实施例提供的一种像素排列结构的示意图；
图6为本公开另一实施例提供的一种像素排列结构的示意图；
图7A为本公开另一实施例提供的一种像素排列结构的示意图；
图7B为本公开另一实施例提供的一种像素排列结构的示意图；
图8为本公开另一实施例提供的一种显示基板的像素排列结构以及驱动线和数据线的示意图；以及
图9是本公开一实施例提供的显示基板的截面图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
图1示出了一种像素排列结构示意图。如图1所示，该像素排列为典型的pentile排列方式，一个最小重复单元包括两个绿色子像素0111，一个红色子像素0112和一个蓝色子像素0113，该像素排列均匀分布，易实现高PPI(Pixel Per Inch)显示。
本申请的发明人发现，在图1所示的像素排列结构中，最小重复单元中的两个绿色子像素0111距离较远，不利于提高视觉分辨率，容易出现彩边和颗粒感。通常，图1中的最小重复单元中，两个绿色子像素0111的中心连线LS02与该最小重复单元中红色子像素0112的中心和蓝色子像素0113的中心的连线LS01长度大致相同。
即使采用SPR技术后，高分辨率产品仍然需要较高PPI(Pixel Per Inch)子像素图形化工艺来制作，因此仍然受到制作工艺精度的制约。因此，需要从像素排列结构上进行改进以降低制作工艺难度，以使高分辨率产品适于量产。
为了制作具有高分辨率的显示装置，需要减少像素的尺寸和像素间的间距。然而，像素的尺寸和像素间的间距的减少对制作工艺的精度要求也越来越高，从而会导致显示装置的制作工艺的难度和制作成本的增加。例如，在制作具有高分辨率的有源矩阵有机发光二极管(Active Matrix Organic Light-Emitting Diode，AMOLED)显示装置时，由于精细金属掩膜(Fine Metal Mask，FMM)技术的工艺精度的限制，制作具有高分辨率(例如，大于300像素密度(PPI))的有源矩阵有机发光二极管(AMOLED)显示装置的制作工艺难度大、制作成本较高。像素排列的优劣对显示效果具有较大的影响，好的像素排列可以提高画面显示质量，提升开口率，降低混色，降低工艺难度。
如图2所示，本公开至少一实施例提供一种像素排列结构，包括多个像素组01。每个像素组01包括第一子像素111、第二子像素112、第三子像素113和第四子像素114。在像素组01中，第二子像素112的中心C2和第三子像素113的中心C3的连线为第一线段LS1；第一子像素111和第四子像素114位于第二子像素112和第三子像素113之间且分设于第一线段LS1的两侧。第一子像素111的中心C1和第四子像素114的中心C4的连线为第二线段LS2。第二线段LS2的长度小于第一线段LS1的长度。例如，为了获得较好的像素密排效果，第二线段LS2与第一线段LS1的长度之比小于或等于3/4。
根据本公开至少一实施例提供的像素排列结构，缩小了同一像素组中的第一子像素和第四子像素之间的距离，一方面，可使得像素排列更紧密，降低混色风险、改善彩边，改善视觉颗粒感。另一方面，可拉大子像素之间的间距，以利于制作。或者，也可以兼顾像素排列紧密程度和子像素之间的间距，在二者之间寻求一个平衡，使得像素排列相对紧密且一定程度上拉大子像素之间的间距(像素定义层间距)，以利于兼得降低混色风险、改善彩边、改善视觉颗粒感的效果以及拉大子像素之间的间距的效果。
例如，本公开的实施例中给出的各子像素的形状可由像素定义层定义，但不限于此。例如，附图中的各子像素为实际发光区域。各子像素的具体形状可根据制备工艺进行设置。例如，该实际发光区域可由电极、发光层、像素定义层至少之一的形状来确定。例如，当该种像素排列结构应用于OLED 显示基板，第一子像素和第四子像素为相同颜色时，还可以使得同一像素组中的第一子像素和第四子像素的发光层图形应用掩膜版的同一开口蒸镀形成。
例如，第一子像素111和第四子像素114可为人眼敏感颜色的子像素，例如可为绿色子像素、黄色子像素、白色子像素等。例如，相比于第二子像素112和第三子像素113，第一子像素111和第四子像素114的面积相对较小。例如，第一子像素111的面积小于第二子像素112，和/或，第一子像素111的面积小于第三子像素113的面积。类似的，第四子像素114可参照上述对于第一子像素111面积的描述。即，第四子像素114的面积小于第二子像素112，和/或，第四子像素114的面积小于第三子像素113的面积。
根据本公开至少一实施例提供的像素排列结构，可通过调节视觉位置敏感颜色子像素的间距，改善敏感颜色子像素的分布均匀性，从而可提高该像素排列结构视觉上的分辨率，提升显示质量。
第二子像素112和第三子像素113可为人眼不敏感颜色的子像素。例如，第二子像素112和第三子像素113之一为红色子像素，另一个为蓝色子像素，但不限于此。本公开的实施例中，以第二子像素112为红色子像素，第三子像素113为蓝色子像素为例进行说明。需要说明的是，当像素排列结构采用红绿蓝(RGB)模式时，上述的人眼敏感颜色可为绿色。
如图2所示，第一线段LS1可以沿第一方向X延伸，第二线段LS2可以沿第二方向Y延伸。例如，第一方向X垂直于第二方向Y。例如，每个像素组01中，第一子像素111和第四子像素114以第一方向X为对称轴进行排列，以使得像素结构排布更均匀。例如，第一子像素111相对第二子像素112和第三子像素113均匀排列，保持一致，以使得像素结构排布更均匀。
如图2所示，根据本公开一个或多个实施例提供的像素排列结构，第二线段LS2垂直于第一线段LS1。从而，可使得像素排列更均匀。例如，第二线段LS2位于第一线段LS1的中垂线上，此时，各个颜色的子像素在第一方向X上的宽度可均相同，但不限于此。从而，可使得像素结构分布更均匀，画面显示质量更高，改善较低PPI下的显示颗粒感问题。
如图2所示，为了方便描述，给出了多个正方形的虚线框，每个虚线框的长度为1/2L，四个虚线框可形成边长为L的正方形。图2中的深色矩形虚 线框内为一个像素组01。该像素组01可为该像素排列结构的最小重复单元。例如，像素排列结构可通过最小重复单元的平移复制而得。例如，最小重复单元内不包括可平移重复以进行排列以形成像素结构的子单元。
如图2所示，第一线段SL1与第二线段SL2垂直，且互相垂直平分。第一线段SL1垂直平分第二线段SL2。第二线段SL2也垂直平分第一线段SL1。例如，像素组01中，第一子像素111、第二子像素112、第四子像素114和第三子像素113的中心的连线围成的最大区域呈菱形，第一线段SL1和第二线段SL2分别为该菱形的对角线。
如图2所示，在像素组01中，第一子像素111的中心C1和第四子像素114的中心C4之间的距离可大于或等于1/2L，例如，该距离的范围可从1/2L至L。例如，第一子像素111和第四子像素可采用相同颜色的子像素。第一子像素111和第四子像素采用相同颜色的子像素，例如均为第一子像素111时，该距离的设置还可避免因相邻的第一子像素距离较近而导致的相邻的两个第一子像素难以分辨，被人眼视觉上合二为一的情况，从而可避免因此产生的颗粒感。由此，该像素排列结构可改善第一子像素的分布均匀性，从而可提高视觉上的分辨率，并且还可提升显示质量。
如图2所示，第三子像素113的中心C3和第二子像素112的中心C2之间的距离可为4/3L。为了使得第二线段LS2与第一线段LS1的长度之比小于或等于3/4，可在工艺允许的条件下，拉大同一像素组内第三子像素113和第二子像素112之间的距离，和/或者，减小第一子像素111和第四子像素114之间的距离。
如图2所示，根据本公开一个或多个实施例提供的像素排列结构，为了获得紧密排列的像素结构，第二线段LS2与第一线段LS1的长度之比可大于或等于3/8。
例如，如图2所示，一个像素组中，第一子像素111和第二子像素112为不同颜色的子像素，第一子像素111和第二子像素112形成一个像素P，第三子像素113和第四子像素114为不同颜色的子像素，第三子像素113和第四子像素114形成一个像素P，在显示图像时需要借用周围其他像素的子像素进行彩色显示。例如，第一子像素111和第四子像素114为绿色子像素，第二子像素112为红色子像素，第三子像素113为蓝色子像素。例如，一个 红色子像素和一个绿色子像素形成一个像素，一个蓝色子像素和一个绿色子像素形成一个像素。这里的像素P仅包括两种颜色的子像素，在显示图像时需要借用周围其他像素的子像素进行彩色显示。因此，这里的像素P也可以称为虚拟像素。
图3A中给出了去除了图2中给出的虚线的像素排列结构。本公开的实施例中给出的虚线，中心等是为了便于描述给出的虚拟线，虚拟中心。例如，中心可为重心，对边的垂直平分线的交点等，但不限于此。
图3B示出了根据本公开一个或多个实施例提供的像素排列结构。同一像素组01中，第一子像素111和第四子像素114采用同一种颜色。例如，均为第一子像素111。由于同色子像素没有混色问题，同一像素组01中的第一子像素111和第四子像素114的发光层图形可采用掩膜版的同一开口进行蒸镀，从而，可利于掩膜版的张网，张网压力小，提高张网的质量。
如图3B所示，因同一行的第一子像素111的斜率较低，当属于同一行的第一子像素111共同显示直线时，由于斜率较低(图3B中的密集点虚线)，相邻像素组的第一子像素的波动幅度较小，从而可避免因波动幅度较大而导致的与相邻的行所显示的直线相互咬合而产生的两条直线难以分辨，被人眼视觉上合二为一的情况。由此，该像素排列结构可提高视觉上的分辨率。
图3C示出了根据本公开一个或多个实施例提供的像素排列结构。如图3C所示，各像素组01中，第一子像素111和第四子像素114为相同颜色的子像素，例如可包括两种类型的像素组，一种类型的像素组中相同颜色的成对子像素为第一子像素(例如，绿色子像素)，另一种类型的像素组中相同颜色的成对子像素为第四子像素(例如，白色子像素或者黄色子像素)。在每个像素组的对角线方向上相邻的像素组中的位于第二子像素和第三子像素之间的成对设置的两个子像素的颜色与该像素组中位于第二子像素和第三子像素之间的成对设置的子像素的颜色不同。
图4示出了根据本公开一个或多个实施例提供的像素排列结构，如图4所示，第一线段LS1可以沿第一方向X延伸，在第一方向X上相邻的两个像素组01中的相邻的第二子像素112和第三子像素113之间的中心连线LS3的长度D1小于第一线段LS1的长度，以使得像素可以紧密排列。图4中以第一线段LS1的长度为4/3L为例进行说明，但并不限于此。例如，第一线 段LS1的长度范围可为11/9L-13/9L。
例如，为了使得像素尽可能的紧密排列和工艺条件允许相结合，在第一方向上相邻的两个像素组01中的相邻的第二子像素112的中心和第三子像素113的中心之间的中心连线LS3的长度D1与第一线段LS1的比值小于或等于1/2。图4中以距离D1的长度为2/3L为例进行说明，但并不限于此。例如，距离D1的长度范围可为5/9L-7/9L。
如图4所示，根据本公开一个或多个实施例提供的像素排列结构，多个像素组01呈阵列排列，包括多行和多列，例如，可包括位于奇数行的多个第一像素组011和位于偶数行的多个第二像素组012。例如，偶数行的像素组和奇数行的像素组错位排布。第二线段LS2可以沿第二方向Y延伸。例如，为了实现在列方向上的像素密排，在相邻的奇数行或者在相邻的偶数行中，在第二方向Y上相邻的两个像素组01中的相邻的第一子像素111和第四子像素114的中心连线L14的长度D2大于第二线段LS2的长度。例如，在相邻的奇数行或者在相邻的偶数行中，在第二方向Y上相邻的两个像素组01中的相邻的第一子像素111和第四子像素114的中心连线L14的长度D2与第二线段LS2的长度的比值大于等于1并且小于等于3。
例如，在相邻的奇数行或者在相邻的偶数行中，在第二方向Y上相邻的两个像素组01中的相邻的第一子像素111和第四子像素114的中心连线L14的长度D2大于第二线段LS2的长度。从而，可形成一个像素组周围密排6个像素组的像素结构。奇数行像素组和偶数行像素组错位排布。例如，可在第一方向X上错位半个像素组在第一方向X上的长度，例如，错位长度为L，但不限于此。例如，在相邻的奇数行或者在相邻的偶数行中，在第二方向Y上相邻的两个像素组01中的相邻的第一子像素111和第四子像素114的中心连线L14的长度D2与第二线段LS2的长度的比值大于等于1并且小于等于3。
如图4所示，根据本公开一个或多个实施例提供的像素排列结构，每个像素组01的第二线段LS2的延长线穿过在第二方向Y上与该像素组01相邻并且位于同一行的两个像素组01的中心连线LSC的中点C0。每个像素组01的中心为C1，相邻两个像素组01的中心C1的连线为中心连线LSC。例如，像素组01的中心C1可以为第一线段LS1和第二线段LS2的交点。
例如，每个第一像素组011的第二线段LS2的延长线穿过与该第一像素组011相邻并且位于同一行的两个第二像素组012的相邻的第三子像素113和第二子像素112的中心连线LS3的中心C5。例如，中心C5和中心C0可为同一个点。
如图4所示，根据本公开一个或多个实施例提供的像素排列结构，在相邻的奇数行或者在相邻的偶数行中，在第二方向Y上排列的相邻两个像素组01(相邻两个第一像素组011或相邻两个第二像素组012)中的两个第三子像素113的中心连线LS4和位于该两个第三子像素113之间的像素组01中的第一线段LS1的交点IP1位于该第一线段LS1的中心IP0与第二子像素112的中心C2之间。例如，第一线段LS1的中心IP0可以为该像素组01的中心C1。例如，交点IP1位于第一线段LS1的中心IP0与第二子像素112的中心C2连线的中点。
例如，在相邻奇数行中，位于同一列的相邻第一像素组011的两个第三子像素113的中心连线LS4和与该第三子像素113相邻的第二像素组012的第一线段LS1的交点IP1位于该第二像素组012的第一线段LS1的第一线段LS1和第二线段LS2的交点IP0和第二子像素112的中心C2之间的位置。上述描述中的第三子像素113也可替换为第二子像素112。
例如，在相邻的奇数行或者在相邻的偶数行中，在第二方向Y上排列的相邻两个像素组01(相邻两个第一像素组011或相邻两个第二像素组012)中的两个第二子像素112的中心连线和位于该两个第二子像素112之间的像素组01中的第一线段LS1的交点位于该第一线段LS1的中心IP0与第三子像素113的中心C3之间。例如，该交点位于第一线段LS1的中心IP0与第三子像素113的中心C3连线的中点。
如图4所示，根据本公开一个或多个实施例提供的像素排列结构，同一像素组中，第二子像素112与第一子像素111之间的最近距离为L1，第二子像素112与第四子像素114之间的最近距离为L2，第三子像素113与第一子像素111之间的最近距离为L3，第三子像素113与第四子像素114之间的最近距离为L4，L1＝L2＝L3＝L4。
如图4所示，根据本公开一个或多个实施例提供的像素排列结构，第一子像素111或第四子像素114和在第二方向上与其相邻的且与其不在同一行 的像素组中的第二子像素112和第三子像素113的最近距离分别为L5和L6，L5＝L6。
例如，在一个实施例中，L1＝L2＝L3＝L4＝L5＝L6。
例如，有关L1、L2、L3、L4、L5和L6也可参照图7A和7B中有关于最小工艺间距d的标注。各最近距离为两个子像素之间的最小距离。例如，在实际制作时，可使得L1、L2、L3、L4、L5和L6尽量接近于最小工艺间距d。
如图4所示，根据本公开一个或多个实施例提供的像素排列结构，相邻子像素中，各相对的边大概平行或夹角小于45°，相邻子像素包括第一子像素111、第二子像素112、第三子像素113和第四子像素114中任意相邻的两个。
如图5A所示，根据本公开一个或多个实施例提供的像素排列结构，第一子像素111和第四子像素114均为条形，第一子像素111的延伸方向A1与第四子像素114的延伸方向A2不重合。例如，第一子像素111的延伸方向A1与第四子像素114的延伸方向A2相交或者有夹角。例如，每个像素组中，第一子像素111和第四子像素114以第一方向X为对称轴进行排列，并进行一定角度的倾斜。例如，倾斜角度与第一方向X夹角范围为30°-50°，进一步例如，夹角为45°，但不限于此。例如，第一子像素111的延伸方向A1可为第一子像素111的长轴方向，但不限于此。例如，第四子像素114的延伸方向A2可为第四子像素114的长轴方向，但不限于此。
如图5A所示，根据本公开一个或多个实施例提供的像素排列结构，每个像素组01中，第一子像素111和第四子像素114相对于第一线段LS1对称排列。例如，每个像素组01中，第一子像素111和第四子像素114相对于第二线段LS2不对称排列。
例如，第二子像素112和第三子像素113相对于第二线段LS2对称排列，但不限于此。
例如，本公开的实施例中，条形是指一个方向的长度大于另一个方向的长度，或者，在一个方向上尺寸大于其他方向尺寸即可。条形不限于矩形，可以为其他形状，例如，可以为长条六边形，长椭圆形，梯形或其他形状。本公开的实施例中，各子像素的形状不限于规则形状，也可以为不规则形状。
例如，第一子像素111的延伸方向A1与第四子像素114的延伸方向A2的夹角为70°-100°，进一步的，夹角可为80°-95°，更进一步，夹角可为90°(直角)，从而，可利用形成较大面积的第一子像素111和第四子像素114，以提高出光面积，并利于制作发光层图形的掩膜版制作时的张网。例如，为直角的情况下，可以允许有上下几度的偏差。例如，可以与90°上下偏差5°。
图5B示出了根据本公开一个或多个实施例提供的像素排列结构，第一子像素111的延伸方向A1与第四子像素114的延伸方向A2的夹角为直角，并且，在同一像素组01中，第一子像素111和第四子像素114为相同颜色子像素。
图6示出了根据本公开一个或多个实施例提供的像素排列结构，如图6所示，第二子像素112和第三子像素113可为菱形或近似菱形的形状。近似菱形例如包括圆角菱形，切角菱形等，但不限于此。菱形或近似菱形的形状的子像素形状更加利于像素密排。例如，可使得第一子像素111能够比较对称的围绕在第三子像素113和第二子像素112的周围，第一子像素111的长边均朝向第二子像素112，短边均朝向第三子像素113，以最大程度保证像素排列的均一。第一子像素111的排列更加均匀，可以一定程度上改善彩边，有利于高PPI的实现，可以尽可能高的提高像素开口率。
各子像素的形状不限于之前所述，子像素的形状可根据需要进行调整。面积最大化是确定子像素形状的主要原则。
为避免混色，不同颜色子像素间距需大于图形化工艺的最小工艺间距d，再考虑某些特殊工艺对称性要求，例如，FMM张网希望开孔图形和分布对称，第一子像素和第四子像素的形状可分别为直角底角的对称五边形(如图2所示)。可以看到，采用对称形状子像素的相邻像素组间第二、三子像素间距明显地大于其他不同颜色子像素间距(最小工艺间距d)，即，设计上仍存在可利用面积。在FMM张网技术允许或采用其他对对称性不敏感(如CF)工艺情况下，可以采用非对称子像素形状实现子像素面积最大。
图7A和图7B示出了根据本公开一个或多个实施例提供的像素排列结构。如图7A和图7B所示，在允许采用非对称子像素形状的条件下，根据不同的图形化工艺最小工艺间距d，第二子像素112和第三子像素113形状可以为直角梯形或切掉锐角的直角梯形，以使得面积最大化。
如图7A所示，由于第二子像素112和第三子像素113的形状均为直角梯形，相对于第二子像素112和第三子像素113的形状均为六边形(两个直角底角对称五边形联合形成六边形)的情况，第二子像素112和第三子像素113的锐角部190可进一步提高第二子像素112和第三子像素113的面积，从而进一步提高像素组内的空间利用率。该像素排列结构可提高对像素组内的空间利用率。
如图7B所示，第二子像素112和第三子像素113的形状均为锐角被切角的等腰梯形。从而，在工艺精度一定的情况下，也就是说，第一子像素111分别与第二子像素112和第三子像素113的距离一定的情况下，增加第二子像素112和第三子像素113的面积，从而提高对像素组内的空间的利用率。
根据本公开一个或多个实施例提供的像素排列结构，第二子像素112和第三子像素113的形状包括等腰梯形、六边形、菱形至少之一，第二子像素112包括五边形、矩形、近似矩形至少之一。近似矩形例如包括圆角矩形，但不限于此。
本公开至少一实施例提供一种显示基板，包括上述任一像素排列结构。
图8示出了根据本公开一个或多个实施例提供的显示基板。如图8所示，在同一行像素组中，第三子像素113和第一子像素111可采用第一驱动线DL1驱动，第二子像素112和第四子像素114可采用第二驱动线DL2驱动。第一驱动线DL1沿E1方向延伸，第二驱动线DL2沿E1方向延伸。例如，E1方向平行于第一方向X。
如图8所示，奇数列像素组中的第一子像素111和第四子像素114可采用第一数据线DT1输入数据信号，位于相邻两条第一数据线DT1之间的第二子像素112和第三子像素113可采用第二数据线DT2输入数据信号。例如，数据信号包括电压和/或电流。第一数据线DT1沿E2方向延伸，第二数据线DT2也沿E2方向延伸，E2方向平行于第二方向Y。
例如，一个像素单元组包括两个像素单元，例如，第一子像素111和第二子像素112形成一个像素单元，第三子像素113和第四子像素114形成另一个像素单元。每个像素单元中可以共用与其相邻的第三子像素111或第四子像素114以形成虚拟像素。采用子像素共用的方式实现显示。
图9是本公开一实施例提供的显示基板的截面图。如图9所示，该结构 包括衬底基板001以及依次位于衬底基板001上的缓冲层002、第一栅极绝缘层003、第二栅极绝缘层004、层间介电层005、平坦化层006以及像素限定层007。从图9中可以看到，在子像素的下方有一个薄膜晶体管结构，该薄膜晶体管结构包括栅极302、有源层301以及漏电极303。该薄膜晶体管可为像素驱动电路中的一个薄膜晶体管，其与其他部件的连接关系可以根据具体的像素电路布置而设置，这里不再详细示出。此外，在与漏电极303同层的位置处还可以包括信号线304，该信号线304也可以根据不同的像素电路布置而用作特定功能的信号线，例如，数据线或栅线等。从图9可以看到，像素限定层007可以包括限定子像素的开口。子像素的阳极403和第三子像素的发光层503位于像素限定层007的开口中。需要说明的是，显示基板的结构不限于图9所示。
例如，阳极403与发光层503彼此接触，从而在彼此接触的部分能够驱动发光层进行发光，因此，阳极403和发光层503彼此接触的部分为子像素能够发光的有效部分。在这里阳极403用作像素电极，从而能够给不同的子像素施加不同的数据电压。但根据本公开的实施例中，用作子像素的像素电极的电极不限于阳极，也可以将发光二极管的阴极用作像素电极。例如，在本公开的实施例中，子像素的形状可以是指像素电极与发光层彼此接触的部分的形状。例如，对于每个子像素，像素电极的面积可以稍大于发光层的面积，或者也可以是发光层的面积稍大于像素电极的面积，本公开的实施例对此没有特别限定。例如，这里的发光层可以包括电致发光层本身以及位于电致发光层两侧的其他功能层，例如，空穴注入层、空穴传输层、电子注入层以及电子传输层等等。在有些实施例中，像素的形状也可以由像素限定层来定义。例如，对于发光二极管的下电极(例如，阳极)可以设置在像素限定层的下方，像素限定层包括用于限定像素的开口，该开口露出下电极的一部分，当发光层形成在上述像素限定层中的开口中时，发光层与下电极接触，从而在这部分能够驱动发光层进行发光。因此，在这种情况下，像素限定层的开口定义了子像素的形状。
例如，像素电路中包括至少一个晶体管，所述晶体管包括栅极、有源层以及源漏极。在一个示例中，信号线通过贯穿其下方的绝缘层的过孔与相应的晶体管的源极或漏极电连接。在一个示例中，晶体管的有源层由多晶硅层 形成，在有源层的沟道区的两侧，多晶硅层被导体化以形成源漏极。例如，所述信号线通过过孔与被导体化而形成的多晶硅源极或漏极电连接。例如，晶体管为顶栅极晶体管，用于将所述信号线电连接到相应晶体管的源极或漏极的过孔穿过栅极金属层和数据金属层，且与所述栅极金属层和数据金属层的一部分金属图案可以用作过孔电连接的中继连接件，但根据本公开的实施例不限于此。
例如，对于本公开实施例中所描述的各种子像素的形状，均为大致的形状，在形成发光层或各种电极层时，并不能保证子像素的边沿为严格的直线且角为严格的角状。例如，发光层可以通过掩模用蒸镀工艺来形成，因此，其角部可以为圆角形状。在一些情况下，金属刻蚀会有拔模角，因此，在利用蒸镀工艺形成子像素的发光层时，其发光层的一个角可能被去掉。
例如，子像素的形状为子像素在衬底基板上的正投影的形状。
本公开至少一实施例提供一种显示装置，包括上述任一显示基板。因此，可提高该显示装置的分辨率，进而可提供一种具有真实的高分辨率的显示装置。另外，由于该像素排列结构的对称性更好，因此该显示装置的显示效果较好。
例如，在一些示例中，该显示装置可以为智能手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
有以下几点需要说明：
(1)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开同一实施例及不同实施例中的特征可以相互组合。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (17)

  1. 一种像素排列结构，包括多个像素组；
    每个像素组包括第一子像素、第二子像素、第三子像素和第四子像素；
    在所述像素组中，所述第二子像素的中心和所述第三子像素的中心的连线为第一线段；所述第一子像素和所述第四子像素位于所述第二子像素和所述第三子像素之间且分设于所述第一线段的两侧；
    所述第一子像素的中心和所述第四子像素的中心的连线为第二线段；
    所述第二线段的长度小于所述第一线段的长度。
  2. 根据权利要求1所述的像素排列结构，其中，所述第二线段与所述第一线段的长度之比小于或等于3/4。
  3. 根据权利要求1或2所述的像素排列结构，其中，所述第二线段和所述第一线段互相垂直平分。
  4. 根据权利要求1-3任一项所述的像素排列结构，其中，所述第二线段与所述第一线段的长度之比大于或等于3/8。
  5. 根据权利要求1-4任一项所述的像素排列结构，其中，在所述像素组中，所述第一子像素和所述第四子像素均为条形，所述第一子像素的延伸方向与所述第四子像素的延伸方向不重合。
  6. 根据权利要求5所述的像素排列结构，其中，所述第一子像素的延伸方向与所述第四子像素的延伸方向的夹角为70°-100°。
  7. 根据权利要求5所述的像素排列结构，其中，所述第一子像素和所述第四子像素相对于所述第一线段对称排列，和/或者，所述第二子像素和所述第三子像素相对于所述第二线段对称排列。
  8. 根据权利要求1-7任一项所述的像素排列结构，其中，所述第一线段沿第一方向延伸，所述第二线段沿第二方向延伸；
    所述多个像素组呈阵列排列，形成多行和多列，偶数行的像素组和奇数行的像素组错位排布；
    在所述第一方向上相邻的两个像素组中的相邻的第二子像素和第三子像素的中心连线的长度小于所述第一线段的长度；
    在相邻的奇数行或者在相邻的偶数行中，在所述第二方向上相邻的两个像素组中的相邻的第一子像素和第四子像素的中心连线的长度大于所述第二 线段的长度。
  9. 根据权利要求8所述的像素排列结构，其中，在所述第一方向上相邻的两个像素组中的相邻的第二子像素和第三子像素的中心连线的长度与所述第一线段的比值小于或等于1/2；和/或者，
    在相邻的奇数行或者在相邻的偶数行中，在所述第二方向上相邻的两个像素组中的相邻的第一子像素和第四子像素的中心连线的长度与所述第二线段的长度的比值大于等于1并且小于等于3。
  10. 根据权利要求8所述的像素排列结构，其中，每个像素组的所述第二线段的延长线穿过在第二方向上与该像素组相邻并且位于同一行的两个像素组的中心连线的中点。
  11. 根据权利要求10所述的像素排列结构，其中，在相邻的奇数行或者在相邻的偶数行中，在所述第二方向上排列的相邻两个像素组中的两个第三子像素的中心连线和位于该两个第三子像素之间的像素组中的第一线段的交点位于该第一线段的中心与第二子像素的中心之间。
  12. 根据权利要求8所述的像素排列结构，其中，同一像素组中，所述第二子像素与所述第一子像素之间的最近距离为L1，所述第二子像素与所述第四子像素之间的最近距离为L2，所述第三子像素与所述第一子像素之间的最近距离为L3，所述第三子像素与所述第四子像素之间的最近距离为L4，L1＝L2＝L3＝L4。
  13. 根据权利要求12所述的像素排列结构，其中，所述第一子像素或所述第四子像素和在所述第二方向上与其相邻的且与其不在同一行的像素组中的第二子像素和第三子像素的最近距离分别为L5和L6，L5＝L6。
  14. 根据权利要求12或13所述的像素排列结构，其中，相邻子像素中，各相对的边大概平行或夹角小于45°，所述相邻子像素包括所述第一子像素、第二子像素、第三子像素和第四子像素中任意相邻的两个。
  15. 根据权利要求1-14任一项所述的像素排列结构，其中，所述第一子像素和所述第四子像素为同一颜色的子像素。
  16. 一种显示基板，包括权利要求1-15任一项所述的像素排列结构。
  17. 一种显示装置，包括权利要求16所述的显示基板。
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11233096B2 (en) 2016-02-18 2022-01-25 Boe Technology Group Co., Ltd. Pixel arrangement structure and driving method thereof, display substrate and display device
US11264430B2 (en) 2016-02-18 2022-03-01 Chengdu Boe Optoelectronics Technology Co., Ltd. Pixel arrangement structure with misaligned repeating units, display substrate, display apparatus and method of fabrication thereof
US11448807B2 (en) 2016-02-18 2022-09-20 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate, fine metal mask set and manufacturing method thereof
US11462591B2 (en) 2018-02-09 2022-10-04 Boe Technology Group Co., Ltd. Display device comprising a specified arrangement of sub-pixels and spacers
US11462589B2 (en) 2018-02-09 2022-10-04 Beijing Boe Technology Development Co., Ltd. Pixel arrangement structure, display method and preparing method of pixel arrangement structure, and display substrate
US11574960B2 (en) 2018-02-09 2023-02-07 Boe Technology Group Co., Ltd. Pixel arrangement structure, display substrate, display device and mask plate group
EP4068382A4 (en) * 2019-12-03 2023-02-08 Guangdong Oppo Mobile Telecommunications Corp., Ltd. DISPLAY SCREEN ASSEMBLY AND ELECTRONIC DEVICE
US11735108B2 (en) 2019-07-31 2023-08-22 Boe Technology Group Co., Ltd. Display substrate and preparation method thereof, display panel, and display device
US11747531B2 (en) 2016-02-18 2023-09-05 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate, fine metal mask set and manufacturing method thereof

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11328650B2 (en) 2019-09-30 2022-05-10 Beijing Boe Display Technology Co., Ltd. Driver, display device and optical compensation method
KR20210059091A (ko) * 2019-11-13 2021-05-25 삼성디스플레이 주식회사 표시 장치
CN111009566A (zh) * 2019-12-19 2020-04-14 京东方科技集团股份有限公司 显示基板、显示装置及充电座
CN112038375B (zh) * 2020-09-02 2022-11-15 昆山国显光电有限公司 显示面板和显示装置
CN113097277B (zh) * 2021-03-31 2022-07-22 武汉天马微电子有限公司 显示面板和显示装置
CN113593497B (zh) * 2021-07-30 2022-04-19 惠科股份有限公司 显示面板、驱动方法和显示装置
CN114268717A (zh) * 2021-11-30 2022-04-01 维沃移动通信有限公司 图像传感器、摄像模组和电子设备

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104269411A (zh) * 2014-09-11 2015-01-07 京东方科技集团股份有限公司 显示面板、有机发光二极管显示器和显示装置
CN104882464A (zh) * 2015-03-27 2015-09-02 友达光电股份有限公司 显示器的像素排列结构
CN205355055U (zh) * 2016-02-18 2016-06-29 京东方科技集团股份有限公司 一种像素排列结构、显示面板及显示装置
CN107275359A (zh) * 2016-04-08 2017-10-20 乐金显示有限公司 有机发光显示装置
CN207781608U (zh) * 2018-02-09 2018-08-28 京东方科技集团股份有限公司 显示基板和显示装置
CN207781607U (zh) * 2018-02-09 2018-08-28 京东方科技集团股份有限公司 像素排列结构、显示基板和显示装置
CN207883217U (zh) * 2018-02-09 2018-09-18 京东方科技集团股份有限公司 显示基板和显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10832616B2 (en) * 2012-03-06 2020-11-10 Samsung Display Co., Ltd. Pixel arrangement structure for organic light emitting diode display
KR102030799B1 (ko) * 2013-03-11 2019-10-11 삼성디스플레이 주식회사 유기발광표시장치
CN103777393B (zh) * 2013-12-16 2016-03-02 北京京东方光电科技有限公司 显示面板及其显示方法、显示装置
CN103985735A (zh) * 2014-04-25 2014-08-13 友达光电股份有限公司 一种显示面板
CN105552099A (zh) * 2014-10-29 2016-05-04 上海和辉光电有限公司 一种oled像素排列结构
CN104465714B (zh) * 2014-12-30 2017-04-26 京东方科技集团股份有限公司 一种像素结构及其显示方法、显示装置
CN105826349B (zh) * 2015-01-09 2019-04-23 联咏科技股份有限公司 显示面板
CN104835832A (zh) * 2015-05-18 2015-08-12 京东方科技集团股份有限公司 像素排列结构、有机电致发光器件、显示装置、掩模板
CN110133899A (zh) * 2018-02-09 2019-08-16 京东方科技集团股份有限公司 像素排列结构、显示基板、显示装置
CN115542617A (zh) * 2018-02-09 2022-12-30 京东方科技集团股份有限公司 显示基板和显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104269411A (zh) * 2014-09-11 2015-01-07 京东方科技集团股份有限公司 显示面板、有机发光二极管显示器和显示装置
CN104882464A (zh) * 2015-03-27 2015-09-02 友达光电股份有限公司 显示器的像素排列结构
CN205355055U (zh) * 2016-02-18 2016-06-29 京东方科技集团股份有限公司 一种像素排列结构、显示面板及显示装置
CN107275359A (zh) * 2016-04-08 2017-10-20 乐金显示有限公司 有机发光显示装置
CN207781608U (zh) * 2018-02-09 2018-08-28 京东方科技集团股份有限公司 显示基板和显示装置
CN207781607U (zh) * 2018-02-09 2018-08-28 京东方科技集团股份有限公司 像素排列结构、显示基板和显示装置
CN207883217U (zh) * 2018-02-09 2018-09-18 京东方科技集团股份有限公司 显示基板和显示装置

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11233096B2 (en) 2016-02-18 2022-01-25 Boe Technology Group Co., Ltd. Pixel arrangement structure and driving method thereof, display substrate and display device
US11264430B2 (en) 2016-02-18 2022-03-01 Chengdu Boe Optoelectronics Technology Co., Ltd. Pixel arrangement structure with misaligned repeating units, display substrate, display apparatus and method of fabrication thereof
US11448807B2 (en) 2016-02-18 2022-09-20 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate, fine metal mask set and manufacturing method thereof
US11747531B2 (en) 2016-02-18 2023-09-05 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate, fine metal mask set and manufacturing method thereof
US11462591B2 (en) 2018-02-09 2022-10-04 Boe Technology Group Co., Ltd. Display device comprising a specified arrangement of sub-pixels and spacers
US11462589B2 (en) 2018-02-09 2022-10-04 Beijing Boe Technology Development Co., Ltd. Pixel arrangement structure, display method and preparing method of pixel arrangement structure, and display substrate
US11574960B2 (en) 2018-02-09 2023-02-07 Boe Technology Group Co., Ltd. Pixel arrangement structure, display substrate, display device and mask plate group
US11957019B2 (en) 2018-02-09 2024-04-09 Boe Technology Group Co., Ltd. Pixel arrangement structure, display method and preparing method of pixel arrangement structure, and display substrate
US11735108B2 (en) 2019-07-31 2023-08-22 Boe Technology Group Co., Ltd. Display substrate and preparation method thereof, display panel, and display device
US11908410B2 (en) 2019-07-31 2024-02-20 Boe Technology Group Co., Ltd. Display substrate and preparation method thereof, display panel, and display device
EP4068382A4 (en) * 2019-12-03 2023-02-08 Guangdong Oppo Mobile Telecommunications Corp., Ltd. DISPLAY SCREEN ASSEMBLY AND ELECTRONIC DEVICE

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CN110137215A (zh) 2019-08-16
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EP3751612A1 (en) 2020-12-16
JP7322031B2 (ja) 2023-08-07

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