WO2021015008A1 - Substrat à composant électronique intégré - Google Patents

Substrat à composant électronique intégré Download PDF

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Publication number
WO2021015008A1
WO2021015008A1 PCT/JP2020/027045 JP2020027045W WO2021015008A1 WO 2021015008 A1 WO2021015008 A1 WO 2021015008A1 JP 2020027045 W JP2020027045 W JP 2020027045W WO 2021015008 A1 WO2021015008 A1 WO 2021015008A1
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WO
WIPO (PCT)
Prior art keywords
electronic component
region
ground plane
wiring layer
opening
Prior art date
Application number
PCT/JP2020/027045
Other languages
English (en)
Japanese (ja)
Inventor
横山　健
和俊 露谷
Original Assignee
Tdk株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tdk株式会社 filed Critical Tdk株式会社
Publication of WO2021015008A1 publication Critical patent/WO2021015008A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • the present invention relates to a board with built-in electronic components, and more particularly to a board with built-in electronic components having a structure in which electronic components are embedded at a position overlapping a large-area ground plane.
  • electronic components such as semiconductor ICs may be embedded so as to overlap with a large-area ground plane.
  • the signal quality of the signal transmitted in the board containing the electronic components can be improved, and the heat generated by the operation of the electronic components can be efficiently dissipated. ..
  • an object of the present invention is to prevent peeling in a moisture absorption sensitivity level test while ensuring high heat dissipation in an electronic component built-in substrate having a structure in which an electronic component is embedded at a position overlapping the ground plane. To do.
  • the electronic component built-in substrate includes the first, second and third insulating layers, the first wiring layer embedded between the first insulating layer and the second insulating layer, and the second insulation. It comprises an electronic component embedded between the layer and a third insulating layer, the first wiring layer includes a ground plane, the electronic component is arranged at a position overlapping the ground plane in a plan view, and the first wiring layer. Includes a first region surrounded by a circle with a radius of 1/3 of the short side of the electronic component centered on the point that overlaps the corner of the electronic component in plan view, and is a ground plane located in the first region. Is characterized in that an opening is formed.
  • the opening is formed in the ground plane in the first region overlapping the vicinity of the corner portion of the electronic component, the moisture contained in the second and third insulating layers can be easily removed. This makes it possible to improve the adhesion in the vicinity of the corners of the electronic component, which is most likely to be peeled off.
  • the electronic component has first and second edges, the corners are composed of the ends of the first and second edges, and at least one of the first and second edges is a ground plane.
  • the section that overlaps the ground plane may be longer than the section that does not overlap.
  • peeling is likely to occur near the corners of the electronic component, and this can be prevented by providing an opening in the ground plane.
  • at least one of the first and second edges may overlap the ground plane in its entirety. In the case of such a structure, peeling is more likely to occur in the vicinity of the corners of the electronic component, but peeling can be prevented by providing an opening in the ground plane.
  • the first wiring layer further includes a second region that overlaps with the electronic component in a plan view and does not overlap with the first region, and the pattern formation density of the ground plane in the first region is the first. It may be lower than the pattern formation density of the ground plane in the region 2.
  • Such a structure is a structure in which the moisture contained in the second and third insulating layers is more difficult to escape, but the provision of an opening in the ground plane makes it easier for the moisture to escape.
  • the pattern formation density of the ground plane is high in the second region overlapping with the electronic components, it is possible to secure sufficient heat dissipation.
  • the ground plane may exist on the entire surface of the second region. According to this, it becomes possible to obtain higher heat dissipation.
  • the first wiring layer when a rectangular region including the first and second regions is defined as the first wiring layer, the first wiring layer is included in the rectangular region and includes the first and second regions.
  • the pattern formation density of the ground plane in the first region may be lower than the pattern formation density of the ground plane in the third region, further including a third region that does not overlap with any of them. According to this, since a ground plane having a larger area is used, the signal quality of the signal transmitted in the board containing electronic components can be further improved, and even higher heat dissipation can be obtained.
  • the ground plane may exist on the entire surface of the third region. According to this, the signal quality of the signal transmitted in the electronic component built-in substrate can be further improved, and further higher heat dissipation can be obtained.
  • the electronic component built-in substrate according to the present invention further includes a second wiring layer located on the side opposite to the first wiring layer via the first insulating layer, and the second wiring layer includes a ground plane, and the second wiring layer is included.
  • the second wiring layer includes a fourth region overlapping the first region of the first wiring layer, and an opening is formed in the ground plane located in the fourth region. According to this, the ground plane formed in the second wiring layer does not block the water discharge path.
  • the opening formed in the first region and the opening formed in the fourth region have an overlap in a plan view. According to this, it becomes easier for water to escape.
  • the electronic component is a semiconductor IC, which is embedded between the second insulating layer and the third insulating layer so that the back surface located on the side opposite to the main surface on which the terminal electrode is formed faces the ground plane. It doesn't matter if it is. According to this, it is possible to cover almost the entire back surface of the semiconductor IC with the ground plane.
  • the present invention in the electronic component built-in substrate having a structure in which the electronic component is embedded at a position overlapping the ground plane, it is possible to prevent the occurrence of peeling in the moisture absorption sensitivity level test while ensuring high heat dissipation. It becomes possible.
  • FIG. 1 is a schematic cross-sectional view for explaining the structure of the electronic component built-in substrate 1 according to the preferred embodiment of the present invention.
  • FIG. 2 is a schematic view for explaining the positional relationship between the electronic component 40 and the opening H.
  • FIG. 3 is a schematic view for explaining the position of the opening H according to the first example.
  • FIG. 4 is a schematic view for explaining the position of the opening H according to the second example.
  • FIG. 5 is a schematic view for explaining the position of the opening H according to the third example.
  • FIG. 6 is a schematic view for explaining the position of the opening H according to the fourth example.
  • FIG. 7 is a schematic view for explaining the position of the opening H according to the fifth example.
  • FIG. 8 is a schematic view for explaining the position of the opening H according to the sixth example.
  • FIG. 9 is a schematic view for explaining the position of the opening H according to the seventh example.
  • FIG. 10 is a schematic view for explaining the position of the opening H according to the eighth example.
  • FIG. 11 is a schematic view for explaining the position of the opening H according to the ninth example.
  • FIG. 12 is a schematic view for explaining the planar shape of the electronic component 40 according to the tenth example.
  • FIG. 1 is a schematic cross-sectional view for explaining the structure of the electronic component built-in substrate 1 according to the preferred embodiment of the present invention.
  • the electronic component-embedded substrate 1 has four insulating layers 11 to 14, wiring layers L1 to L4 formed on the surfaces of the insulating layers 11 to 14, and wiring layers L2, respectively.
  • An electronic component 40 embedded between the wiring layer L3 and the wiring layer L3 is provided.
  • the insulating layer 11 located at the top layer and the insulating layer 14 located at the bottom layer are core layers in which a core material such as glass fiber is impregnated with a resin material such as glass epoxy. It doesn't matter.
  • the insulating layers 12 and 13 may be made of a resin material that does not contain a core material such as glass cloth.
  • the coefficient of thermal expansion of the insulating layers 11 and 14 is preferably smaller than the coefficient of thermal expansion of the insulating layers 12 and 13.
  • the type of the electronic component 40 is not particularly limited, but may be, for example, a semiconductor IC.
  • the electronic component 40 is embedded in a face-up manner so that the main surface on which the terminal electrode 41 is formed faces upward.
  • the wiring layer L1 is the wiring layer located at the uppermost layer, and most of it is covered with the solder resist 21. A region of the wiring layer L1 that is not covered by the solder resist 21 constitutes an external terminal E1 on which chip components and the like are mounted.
  • the wiring layer L4 is a wiring layer located at the lowest layer, and most of the wiring layer L4 is covered with the solder resist 22. A region of the wiring layer L4 that is not covered by the solder resist 22 constitutes an external terminal E2 that is connected to the motherboard via solder.
  • the wiring layers L2 and L3 are located in the inner layer.
  • the wiring layer L2 is located between the insulating layer 11 and the insulating layer 12, and the wiring layer L3 is located between the insulating layer 13 and the insulating layer 14.
  • the wiring layer L1 and the wiring layer L2 are connected via the via conductor 31, the wiring layer L2 and the terminal electrode 41 of the electronic component 40 are connected via the via conductor 32, and the wiring layer L2 and the wiring layer L3 are connected via the via conductor. It is connected via 33, and the wiring layer L3 and the wiring layer L4 are connected via the via conductor 34.
  • the wiring layer L3 is provided with a ground plane G.
  • the ground plane G is a large-area solid pattern to which a ground potential is given, and is provided at a position where it overlaps with the electronic component 40 in a plan view.
  • the ground plane G plays a role of improving the signal quality of the signal transmitting the signal wiring formed in the other wiring layers L1, L2, and L4, and efficiently dissipating the heat generated by the operation of the electronic component 40.
  • an opening H is provided in a part of the ground plane G, and moisture can be discharged from the opening H.
  • FIG. 2 is a schematic diagram for explaining the positional relationship between the electronic component 40 and the opening H.
  • the electronic component 40 is in contact with the insulating layer 13 on the back surface side.
  • the electronic component 40 is unlikely to be peeled from the insulating layer 13 in the region 42 located at the center of the back surface, but is likely to be peeled off at the edge portion.
  • peeling is likely to occur in the region 44 closer to the corner portion than the region 43 away from the corner portion.
  • the lengths of the regions 43 and 44 are defined as 1/3 of the length of one side of the electronic component 40.
  • the reason why peeling is likely to occur in the region 44 is that when the insulating layer 13 containing water thermally expands, the stress caused by the difference in the coefficient of thermal expansion concentrates on the corners of the electronic component 40. Therefore, in order to prevent the electronic component 40 from peeling off, it is necessary to efficiently release the water remaining in the vicinity of the corner portion before the solder reflow, and in order to realize this, the vicinity of the corner portion of the electronic component 40 in a plan view. Is provided with an opening H.
  • the water contained in the insulating layers 12 and 13 is discharged through the opening H, and the amount of water at least in the vicinity of the corners of the electronic component 40 is significantly reduced. Therefore, even if solder reflow is performed, the electronic component 40 is less likely to be peeled off.
  • FIG. 3 is a schematic diagram for explaining in more detail the position of the opening H formed in the ground plane G.
  • the peeling of the electronic component 40 is likely to occur at the edge portion on the back surface, but is particularly likely to occur at the region 44 near the corner portion. Therefore, it is necessary to determine the position of the opening H so that the water remaining around the region 44 is efficiently released.
  • the electronic component built-in substrate 1 according to the present embodiment is surrounded by a circle having a radius of 1/3 of one side of the electronic component 40 centered on a point C that overlaps the corner portion of the electronic component 40 in a plan view.
  • the region A1 is defined in the wiring layer L3, and the opening H is arranged in this region A1.
  • a region A4 that coincides with the region A1 in a plan view is defined in the wiring layer L4, and an opening is arranged in this region A4. Is preferable. This is because when the ground plane G having a solid pattern exists in the wiring layer L4, the moisture is not efficiently released only by providing the opening H in the wiring layer L3. In this case, as shown in FIG. 1, it is preferable that the opening H provided in the wiring layer L3 and the opening H4 provided in the wiring layer L4 have an overlapping D in a plan view.
  • one opening H is arranged at a position in the region A1 that does not overlap with the electronic component 40 in a plan view.
  • a region that overlaps with the electronic component 40 in a plan view and does not overlap with the region A1 is defined as a region A2, is included in the rectangular region A including the regions A1 and A2, and is included in the regions A1 and A2.
  • the ground plane G exists on the entire surface of the regions A2 and A3.
  • one opening H is arranged at a position in the area A1 that overlaps with the electronic component 40 in a plan view.
  • the ground plane G exists on the entire surface of the areas A2 and A3. In this way, the opening H may be provided at a position where it overlaps with the electronic component 40.
  • one opening H is arranged at a position where it overlaps with the electronic component 40 and one at a position where it does not overlap with the electronic component 40 in a plan view in the area A1.
  • the ground plane G exists on the entire surface of the areas A2 and A3.
  • the opening H may be provided at both a position where it overlaps with the electronic component 40 and a position where it does not overlap.
  • one opening H is arranged at a position in the region A1 that overlaps the corner portion of the electronic component 40 in a plan view.
  • the ground plane G exists on the entire surface of the areas A2 and A3.
  • the opening H may be provided at a position overlapping the corner portion of the electronic component 40.
  • three openings H are arranged along the edge portion at positions in the region A1 that do not overlap with the electronic component 40 in a plan view.
  • the ground plane G exists on the entire surface of the areas A2 and A3.
  • a plurality of openings H may be provided along the edge portion of the electronic component 40.
  • a plurality of openings H are regularly arranged along the edge portion of the electronic component 40 so as not to overlap with the electronic component 40. Most of the openings H are located in region A1, but some openings H are located in region A3.
  • the ground plane G exists on the entire surface of the area A2. As described above, a part of the opening H may be located in the region A3. Even in this case, if the opening H is laid out so that the pattern formation density of the ground plane G in the region A1 is lower than the pattern formation density of the ground plane G in the region A3, the moisture discharge characteristics and the heat dissipation characteristics can be improved. It becomes possible to achieve both.
  • a plurality of openings H are regularly arranged along the edge portion of the electronic component 40 so as to overlap the edge of the electronic component 40. Most of the openings H are located in the area A1, but some of the openings H are located in the areas A2 and A3. As described above, a part of the opening H may be located in the regions A2 and A3. Even in this case, if the opening H is laid out so that the pattern formation density of the ground plane G in the region A1 is lower than the pattern formation density of the ground plane G in the region A2, the moisture discharge characteristics and the heat dissipation characteristics can be improved. It becomes possible to achieve both.
  • the entire sections of the edges 51 and 52 of the electronic component 40 overlap with the ground plane G of the wiring layer L3. overlapping. Only a part of the edges 53 and 54 of the electronic component 40 overlaps with the ground plane G.
  • the corner portion of the electronic component 40 is composed of an end portion of the edge 51 or 52 and an end portion of the edge 53 or 54. Even in such a case, if the ground plane G overlapping the edges 51 and 52 has a solid pattern, peeling may occur in the vicinity of the corner portion. Therefore, as shown in FIG. 10, by providing the opening H in the region A1, it is possible to prevent peeling in the vicinity of the corner portion.
  • the edges 51 and 52 of the electronic component 40 overlap with the ground plane G of the wiring layer L3, unlike the eighth example shown in FIG. 10, the edges 51, The corner portion formed by 54 and the corner portion formed by edges 52 and 53 do not overlap with the ground plane G of the wiring layer L3.
  • the opening H may be provided in the. As described above, in the present invention, it is not necessary to provide the openings H corresponding to all the corners.
  • the radius of the circle defining the region A1 may be 1/3 of the short side of the electronic component 40. ..
  • the electronic component built-in substrate 1 is provided with the ground plane G having a large area at a position overlapping the electronic component 40, so that the heat dissipation characteristics and the signal quality are improved. Moreover, since the opening H is provided in the ground plane G located near the corner of the electronic component 40, it is possible to efficiently discharge the moisture from the hygroscopic insulating layers 12 and 13.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

Le problème décrit par la présente invention est d'empêcher l'apparition de pelage dans un test de niveau de sensibilité à l'absorption d'humidité tout en assurant une dissipation de chaleur élevée, dans un substrat à composant électronique intégré ayant une structure dans laquelle un composant électronique est intégré au niveau d'une position chevauchant un plan de masse. La solution selon l'invention porte sur un substrat à composant électronique intégré 1 qui comprend une couche de câblage L3 intégrée entre des couches d'isolation 13, 14, et un composant électronique 40 intégré entre les couches d'isolation 12, 13. La couche de câblage L3 comprend : une zone A1 qui comprend un plan de masse G chevauchant le composant électronique 40 et est entouré par un cercle ayant un rayon correspondant à un tiers du côté court du composant électronique 40 centré sur un point chevauchant le coin du composant électronique 40 dans une vue en plan ; et une zone A2 qui chevauche le composant électronique 40 dans une vue en plan et ne chevauche pas la zone A1. Une partie d'ouverture H est formée dans la zone A1. Par conséquent, l'humidité contenue dans les couches d'isolation 12, 13 peut être facilement retirée, et une dissipation thermique élevée peut être assurée.
PCT/JP2020/027045 2019-07-24 2020-07-10 Substrat à composant électronique intégré WO2021015008A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019-135917 2019-07-24
JP2019135917A JP7331521B2 (ja) 2019-07-24 2019-07-24 電子部品内蔵基板

Publications (1)

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WO2021015008A1 true WO2021015008A1 (fr) 2021-01-28

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JP (1) JP7331521B2 (fr)
TW (1) TWI756744B (fr)
WO (1) WO2021015008A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001127194A (ja) * 1999-10-28 2001-05-11 Sharp Corp フリップチップ型半導体装置及びその製造方法
JP2008091471A (ja) * 2006-09-29 2008-04-17 Tdk Corp 半導体内蔵基板及びその製造方法
JP2014112641A (ja) * 2012-11-09 2014-06-19 Taiyo Yuden Co Ltd 電子部品内蔵基板
WO2017006391A1 (fr) * 2015-07-03 2017-01-12 ルネサスエレクトロニクス株式会社 Dispositif à semi-conducteur

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102419900B1 (ko) * 2015-09-02 2022-07-13 삼성전자주식회사 인쇄회로기판 장치 및 이를 포함하는 전자 장치
JP6919194B2 (ja) * 2016-12-27 2021-08-18 Tdk株式会社 コイル部品及びこれを備える回路基板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001127194A (ja) * 1999-10-28 2001-05-11 Sharp Corp フリップチップ型半導体装置及びその製造方法
JP2008091471A (ja) * 2006-09-29 2008-04-17 Tdk Corp 半導体内蔵基板及びその製造方法
JP2014112641A (ja) * 2012-11-09 2014-06-19 Taiyo Yuden Co Ltd 電子部品内蔵基板
WO2017006391A1 (fr) * 2015-07-03 2017-01-12 ルネサスエレクトロニクス株式会社 Dispositif à semi-conducteur

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TWI756744B (zh) 2022-03-01
TW202110300A (zh) 2021-03-01
JP7331521B2 (ja) 2023-08-23
JP2021019168A (ja) 2021-02-15

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