WO2021013030A1 - 半导体器件的封装方法、封装组件及电子设备 - Google Patents

半导体器件的封装方法、封装组件及电子设备 Download PDF

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Publication number
WO2021013030A1
WO2021013030A1 PCT/CN2020/102297 CN2020102297W WO2021013030A1 WO 2021013030 A1 WO2021013030 A1 WO 2021013030A1 CN 2020102297 W CN2020102297 W CN 2020102297W WO 2021013030 A1 WO2021013030 A1 WO 2021013030A1
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Prior art keywords
semiconductor device
photoresist layer
polymer film
film
packaging
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Application number
PCT/CN2020/102297
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English (en)
French (fr)
Inventor
戴聿昌
庞长林
Original Assignee
微智医疗器械有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority claimed from CN201921140717.0U external-priority patent/CN209993588U/zh
Priority claimed from CN201910655731.2A external-priority patent/CN110400757A/zh
Application filed by 微智医疗器械有限公司 filed Critical 微智医疗器械有限公司
Publication of WO2021013030A1 publication Critical patent/WO2021013030A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Definitions

  • the present disclosure relates to the field of semiconductor devices, and more specifically, to a packaging method, packaging assembly and electronic equipment of a semiconductor device.
  • semiconductor devices are manufactured by forming a stacked structure in divided regions of a semiconductor substrate such as silicon, and cutting the semiconductor substrate to form individual semiconductor devices.
  • the semiconductor device is electrically connected to an external circuit via a metal pad located on the surface of the semiconductor device.
  • the pad is soldered or adhered to the external circuit via solder or conductive glue to achieve electrical connection.
  • the silicon capacitor in a semiconductor device as an example.
  • the silicon capacitor includes a substrate and two pads located on the bottom surface of the substrate. The two pads are isolated by an insulating layer.
  • the silicon capacitor is connected to other circuits through conductive glue attached to the pad. The components are electrically connected.
  • the soldering material or conductive glue easily adheres to the side surface of the substrate (such as silicon). Due to the semiconductor characteristics of silicon, this may cause the silicon capacitor to fail due to short circuits.
  • the prior art uses a masking process to attach the conductive adhesive, that is, first place a mask on the circuit element, apply the conductive adhesive, then remove the mask, and finally attach the silicon capacitor. This process is complicated and difficult. Product yield is low.
  • the purpose of the present disclosure is to provide a semiconductor device packaging method, packaging assembly and electronic equipment to avoid short circuits due to the adhesion of soldering materials or conductive glue when the semiconductor device is soldered or adhered to other circuit elements .
  • the semiconductor device includes a side surface, a bottom surface, and at least one pad exposed on the bottom surface
  • the packaging method includes: forming a semiconductor device located below the semiconductor device The support structure is in contact with the pad and exposes the peripheral portion of the bottom surface; forming a polymer film covering the semiconductor device, the polymer film being formed at least on the peripheral portion of the bottom surface and On the side; and removing the support structure to expose the pad.
  • the polymer film is also formed on the top surface of the semiconductor device.
  • the step of forming the support structure specifically includes: forming a first photoresist layer on a substrate; and patterning the first photoresist layer, wherein the first photoresist layer
  • the adhesive layer forms a step structure to allow the polymer material to enter the peripheral portion of the bottom surface.
  • the packaging method before forming the first photoresist layer, further includes: forming a second photoresist layer on the substrate; wherein the first photoresist layer A layer is formed on the second photoresist layer, and the second photoresist layer is dissolved in the step of removing the support structure to separate the semiconductor device from the substrate.
  • the step of patterning the first photoresist layer specifically includes: irradiating the first photoresist layer with a light source to expose the first photoresist layer; and A developer is used to remove the photosensitive first photoresist layer to expose the peripheral portion of the bottom surface of the semiconductor device, wherein when the first photoresist layer is irradiated with a light source, it is located on the bottom surface At least part of the first photoresist layer underneath is blocked by the semiconductor device.
  • irradiating the first photoresist layer with a light source specifically includes irradiating the first photoresist layer by vertical irradiation or oblique irradiation.
  • the polymer film is a parylene film, wherein the parylene film is covered by a chemical vapor deposition process to cover the semiconductor device.
  • the polymer film is a polyimide film, a polypropylene film or a polyterephthalic acid film, wherein the polymer film covers the semiconductor device by a spin coating method or an injection molding method.
  • the packaging method further includes: cutting the polymer film to separate the semiconductor device, and the method of cutting the polymer film includes a mechanical cutting process, Micro-Electro-Mechanical Systems (MEMS) process, thermal cutting process or laser cutting process.
  • MEMS Micro-Electro-Mechanical Systems
  • the method for cutting the polymer film using the MEMS process specifically includes: forming a metal film on the polymer film; forming a third photoresist layer on the metal film; The third photoresist layer; removing the exposed metal film and the polymer film; removing the remaining third photoresist layer and the metal film.
  • the method of cutting the polymer film further includes cutting the polymer film to form a clamping end extending outward from the semiconductor device.
  • a semiconductor device package assembly includes: a semiconductor device including a side surface, a bottom surface, and at least one pad exposed on the bottom surface; and a polymer film, the polymer A film covers the semiconductor device, and the polymer film is formed at least on the peripheral portion of the bottom surface and the side surface.
  • the polymer film is also formed on the top surface of the semiconductor device.
  • the polymer film includes a clamping end extending outward from the semiconductor device.
  • the polymer film is parylene film.
  • the polymer film is a polyimide film, a polypropylene film or a polyterephthalate film.
  • An electronic device includes a semiconductor device packaging assembly manufactured by the packaging method according to the embodiment of the first aspect of the present disclosure or the semiconductor device packaging assembly of the embodiment of the second aspect of the present disclosure.
  • the technical solution provided by the present disclosure forms a polymer film covering the semiconductor device, and the polymer film wraps at least the peripheral part and the side surface of the bottom surface of the semiconductor device.
  • the polymer film located at the peripheral portion of the bottom surface in the present disclosure increases the reliability of short-circuit protection and the bonding strength between the polymer film and the semiconductor device, thereby increasing the service life of the semiconductor device package assembly.
  • the polymer film of the present disclosure also serves as a protective layer for preventing mechanical damage, water vapor corrosion, and chemical corrosion of the semiconductor device, thereby increasing the reliability and stability of the semiconductor device.
  • the conventional bonding process can be used instead of the mask process of the prior art, the operation is simple, the yield rate is high, and the semiconductor device is greatly improved.
  • the technical solution provided by the present disclosure can form multiple semiconductor device packaging components at the same time.
  • the solution is simple and easy to implement, and is suitable for industrialized production.
  • FIG. 1 is an exploded view of one or more stages of a packaging method of a semiconductor device according to an embodiment of the present disclosure
  • FIG. 2 is a perspective view of one or more stages of the packaging method according to an embodiment of the present disclosure
  • 3a is a cross-sectional view of a stage of forming a first photoresist layer and a second photoresist layer of the packaging method according to an embodiment of the present disclosure
  • 3b is a cross-sectional view of a stage of placing a semiconductor device on the first photoresist layer of the packaging method according to an embodiment of the present disclosure
  • 3c is a cross-sectional view of a stage of patterning the first photoresist layer of the packaging method according to an embodiment of the present disclosure
  • Figure 3d is an enlarged view of the part circled in Figure 3c;
  • 3e is a cross-sectional view of a stage of forming a polymer film covering a semiconductor device in a packaging method according to an embodiment of the present disclosure
  • 3f is a cross-sectional view of the stage of cutting the polymer film on the surface of the support structure according to the packaging method of the embodiment of the present disclosure
  • 3g is a cross-sectional view of the stage of removing the support structure of the packaging method according to an embodiment of the present disclosure
  • FIG. 4a is a cross-sectional view of a stage of forming a metal film covering the surface of a polymer film according to an embodiment of the present disclosure
  • 4b is a cross-sectional view of a stage of forming a third photoresist layer covering the surface of a metal film according to an embodiment of the present disclosure
  • 4c is a cross-sectional view of a stage of patterning a third photoresist layer according to an embodiment of the present disclosure
  • 4d is a cross-sectional view of a stage of removing the exposed metal film and polymer film according to an embodiment of the present disclosure
  • 4e is a cross-sectional view of a stage of removing a third photoresist layer, a metal film, and a supporting structure according to an embodiment of the present disclosure
  • FIG. 5 is a top view of one or more stages of a packaging method of a semiconductor device according to an embodiment of the present disclosure
  • Fig. 6a is a physical diagram of a semiconductor device packaging assembly according to an embodiment of the present disclosure.
  • Fig. 6b is a physical diagram of a semiconductor device package assembly with conductive glue attached according to an embodiment of the present disclosure.
  • Support structure 100 substrate 101;
  • Second photoresist layer 102 First photoresist layer 103;
  • Wafer 140 Conductive glue 150.
  • semiconductor structure refers to a general term for the entire semiconductor structure formed in each step of the packaging method of a semiconductor device, including all layers or regions that have been formed.
  • semiconductor structure refers to a general term for the entire semiconductor structure formed in each step of the packaging method of a semiconductor device, including all layers or regions that have been formed.
  • a semiconductor structure including a support structure 100, a semiconductor device 110, and a polymer film 120 covering the semiconductor device 110 is formed.
  • the support structure 100 will be removed to form a semiconductor device package assembly.
  • the semiconductor device 110 includes a side surface, a bottom surface, and at least one pad 111 exposed on the bottom surface.
  • the supporting structure 100 at least includes a substrate 101 and a patterned first photoresist layer 103.
  • the support structure 100 may further include a second photoresist layer 102.
  • the substrate 101 is used to provide mechanical support, and the second photoresist layer 102 is used to protect the substrate 101 during the cutting process and dissolve to remove the substrate 101 when the support structure 100 is removed.
  • the patterned first photoresist layer 103 provides a step structure to support the semiconductor device 110, the patterned first photoresist layer 103 is in contact with the pad 111, and the peripheral portion of the bottom surface of the semiconductor device 110 is formed to accommodate the polymer film 120 space.
  • the polymer film 120 is formed at least on the peripheral portion and the side surface of the bottom surface of the semiconductor device 110, and the thickness of the polymer film (as shown in the dashed frame in FIG. 1) located in the peripheral portion is determined by the thickness of the bottom surface of the semiconductor device 110 and the second photoresist layer The distance between the upper surfaces of 102 is controlled, and its width is controlled by the lateral depth of the first photoresist layer 103 being etched. Further, the polymer film 120 may also be formed on the top surface of the semiconductor device 110.
  • the support structure 100 may include a semiconductor substrate, a metal sheet, a plastic sheet, a glass sheet, a ceramic sheet, or any laminated structure, which is used to support the bottom surface of the semiconductor device 110 and is used on the semiconductor device 110.
  • the peripheral portion of the bottom surface of the, forms a space for accommodating the polymer film 120.
  • 3a to 3f show cross-sectional views of various stages of the packaging method of the semiconductor device 110 according to an embodiment of the present disclosure, and these cross-sectional views are taken along the line A-A in FIG. 2.
  • the packaging method starts with a semiconductor structure in which a first photoresist layer 103 and a second photoresist layer 102 have been formed on a substrate 101.
  • the first photoresist layer 103 is a positive photoresist layer.
  • the first photoresist layer 103 can be formed by spin-coating a positive photoresist process, and then the semiconductor device 110 is pressed into the first photoresist layer 103, and the first photoresist layer 103 is soft baked to increase The adhesion of the semiconductor device 110 in the first photoresist layer 103.
  • the second photoresist layer 102 and the first photoresist layer 103 may be photoresist layers with opposite polarities.
  • the second photoresist layer 102 is a negative photoresist layer
  • the first photoresist layer 103 It is a positive photoresist layer.
  • the second photoresist layer 102 is used to protect the substrate 101 during the cutting process and as a sacrificial layer when releasing the semiconductor device.
  • the second photoresist layer 102 can be omitted to simplify the process flow.
  • the substrate 101 may be a wafer or the like.
  • a negative photoresist is spin-coated on the surface of the wafer, and the negative photoresist is soft baked and exposed, for example, The negative photoresist is completely exposed to the light source. Because the negative photoresist can quickly undergo a photocuring reaction in the exposed area, a second photoresist layer 102 that is cured as a whole is formed, so that the second photoresist layer 102 is It is retained in the subsequent development process.
  • At least one semiconductor device 110 is placed on the first photoresist layer 103.
  • the distance can be controlled by controlling the force and time of pressing the semiconductor device 110 into the first photoresist layer 103.
  • the first photoresist layer 103 is patterned to form the supporting structure 100.
  • the first photoresist layer 103 is exposed by a self-aligned process, that is, the semiconductor device 110 is used as a shielding mask, and a light source is used to irradiate the first photoresist layer 103 to perform the first photoresist layer 103
  • the adhesive layer 103 undergoes exposure processing, and the first photoresist layer 103 located under the bottom surface of the semiconductor device 110 is shielded by the semiconductor device 110.
  • the first photoresist layer 103 that is exposed to light is removed by a developer solution to overdevelop the first photoresist layer 103 and form the support structure 100.
  • the surface of the support structure 100 and the semiconductor device The surface of 110 has a gap, and the lateral depth of the gap can be controlled by controlling the development time.
  • the semiconductor device 110 is used as a shielding mask by vertical irradiation and/or oblique irradiation is used to expose the first photoresist layer 103 located on the peripheral portion of the bottom surface of the semiconductor device 110 Processing, by controlling the inclination of the light source during the exposure process, the lateral depth of the gap can be controlled.
  • the pad 111 is located at the edge of the bottom surface of the semiconductor device 110, and the cross-sectional shape of the pad 111 may be rectangular, trapezoidal, or stepped.
  • the shape of the first photoresist layer 103 is complementary to that of the semiconductor device 110, and the first photoresist layer 103 on a part of the surface of the pad 111 is removed (see the enlarged view in FIG. 3c, the chamfered portion and part of the pad 111 A gap is formed between the bottom surface and the upper surface of the second photoresist layer 102 to form a space for accommodating the polymer film 120.
  • the semiconductor structure is cleaned, spin-dried, and hot-plate dried.
  • a polymer film 120 covering the semiconductor device 110 is formed.
  • the polymer film 120 is formed at least on the peripheral portion of the side surface and the bottom surface of the semiconductor device 110.
  • the peripheral portions of the top, side, and bottom surfaces of the semiconductor device 110 are all exposed surfaces, so the peripheral portions of the top, side, and bottom surfaces of the semiconductor device 110 are all deposited with a polymer film 120 Therefore, the polymer film 120 forms a hermetic coating on the semiconductor device 110.
  • a shielding process (such as forming a mask, etc.) may be performed on the top surface of the semiconductor device 110.
  • the semiconductor device 110 When using conductive glue to attach the semiconductor device 110 to other circuit elements, even if the soldering material or conductive glue adheres to the side of the semiconductor device 110, due to the insulating effect of the polymer film 120, the semiconductor device 110 will not fail due to a short circuit. .
  • the polymer film 120 can be formed by a vapor deposition process.
  • the material of the polymer film 120 may be Parylene, and a chemical vapor deposition (Chemical Vapor Deposition, CVD) process is used to form the polymer film 120.
  • CVD Chemical Vapor Deposition
  • a chemical vapor deposition process can be performed at room temperature to form a parylene film, so that the semiconductor device 110 can be protected from damage due to high temperature during the process.
  • Parylene deposition equipment includes a gasification system and a deposition system.
  • the operation of the gasification system is divided into two stages: in the first stage, the powdered parylene is heated in a vacuum and begins to turn into steam; in the second stage, the above-mentioned steam is delivered to the furnace chamber and preset Pyrolysis at temperature to monomer (mono-radical p-xylene).
  • the above monomers are fed into the deposition system, and the monomers are deposited as parylene film when cold.
  • the monomer is deposited on the above-mentioned peripheral part of the surface and the bottom surface of the semiconductor device 110 in molecular size.
  • a plasma cleaning process may be used to clean the semiconductor device 110, for example, oxygen plasma is used to clean the semiconductor device 110 to clean and roughen the surface of the semiconductor device 110
  • a hydrophilic oxygen functional group is formed on the surface of the semiconductor device 110, so as to improve the bonding strength between the polymer film 120 and the semiconductor device 110 to be subsequently deposited.
  • the polymer film 120 is a polyimide (Polyimide) film, a polypropylene (Polypropylene) film, a polyethylene terephthalate (PET, PETE, Polyethylene Terephthalate) film, or other polymer materials.
  • the polymer film 120 may cover the semiconductor device 110 using a spin coating method or an injection molding method.
  • a mechanical cutting process may be used to cut the polymer film 120 on the surface of the support structure 100 to separate the plurality of semiconductor devices 110.
  • a knife mechanical cutting method may be used to simplify the process flow.
  • a MEMS manufacturing process, a thermal cutting process, or a laser cutting process may be used.
  • the polymer film 120 when cutting the polymer film 120, the polymer film 120 is cut along the dotted line in FIG. 3e to form a clamping end 121 extending outward from the semiconductor device 110.
  • Using tools such as tweezers to clamp the clamping end 121 can avoid damage to the semiconductor device 110, and the operation is very convenient.
  • the support structure 100 is removed to expose the pad 111 for electrical connection.
  • the semiconductor structure may be soaked with a remover to remove the support structure 100, and then the semiconductor structure may be rinsed with water and baked to form a semiconductor device package assembly.
  • FIGS. 4a to 4e show cross-sectional views of various stages of a method for cutting the polymer film 120 using a MEMS process according to an embodiment of the present disclosure.
  • the method starts with the semiconductor structure shown in Figure 3d.
  • a metal film 130 covering the surface of the polymer film 120 is formed on the surface of the semiconductor structure.
  • the metal film 130 is, for example, an aluminum film.
  • a third photoresist layer 131 covering the surface of the metal film 130 is formed.
  • the third photoresist layer 131 may be a positive photoresist layer.
  • the third photoresist layer 131 is patterned so that the third photoresist layer 131 at least covers the surface of the semiconductor device 110.
  • the patterned third photoresist layer 131 may also cover the surface of the polymer film 120 for forming the clamping end 121.
  • the third photoresist layer 131 may be patterned by photolithography and development methods.
  • the exposed metal film 130 and the polymer film 120 are removed to separate the plurality of semiconductor devices 110 on the surface of the support structure 100.
  • the polymer film 120 may be etched using an anisotropic etching method (for example, dry etching). For example, by controlling the etching time, the etching stops at the surface of the second photoresist layer 102 in the support structure 100.
  • an anisotropic etching method for example, dry etching
  • the third photoresist layer 131, the metal film 130, and the supporting structure 100 are removed to expose the pad 111.
  • the semiconductor structure is soaked with a remover to dissolve the photoresist, and the remaining metal film 130 is removed by wet etching, and then the semiconductor structure is cleaned, spin-dried and hot-pan dried to form a semiconductor device package assembly .
  • the final semiconductor device packaging assembly (as shown in FIG. 3f and FIG. 4e) includes a semiconductor device 110 and a polymer film 120 covering the surface of the semiconductor device 110.
  • the semiconductor device 110 includes a top surface, a side surface, a bottom surface, and at least one pad 111 exposed on the bottom surface.
  • the polymer film 120 is formed at least on the side surface and the peripheral portion of the bottom surface of the semiconductor device 110.
  • the polymer film 120 may be a parylene film. .
  • each wafer 140 may be divided into multiple regions to form multiple semiconductor device packaging components.
  • the polymer film 120 has a clamping end 121 that extends to one side for easy clamping.
  • the shape of the clamping end 121 may be rectangular.
  • the peripheral portion of the bottom surface of the semiconductor device 110 is covered with a polymer film 120, and the polymer film 120 also has a clamping end 121.
  • a conductive adhesive 150 may be applied to the surface of the pad 111 to electrically connect the semiconductor device 110 to other circuit elements, for example, to provide voltage and/or current. External circuits to form electronic devices. In other optional embodiments, soldering materials may also be used to connect the semiconductor device 110 to other circuit elements.
  • the semiconductor device 110 Even if the soldering material or conductive glue 150 adheres to the sidewall of the semiconductor device 110, due to the insulation protection of the polymer film 120, the semiconductor device 110 will not fail due to a short circuit, thereby reducing the accuracy of the soldering or adhesion process of the semiconductor device 110 Requirements to improve the process yield.
  • the polymer film 120 located at the peripheral portion of the bottom surface of the semiconductor device 110 improves the reliability of short-circuit protection and the bonding strength between the polymer film 120 and the semiconductor device 110, so the polymer film 120 will not easily fall off and extend Improve the service life of semiconductor device packaging components.
  • the polymer film 120 serves as a protective layer against mechanical damage, water vapor corrosion and chemical corrosion of the semiconductor device 110, thereby improving the semiconductor The reliability and stability of the device.
  • the semiconductor device 110 is a chip or an electronic device processed with silicon or other semiconductors as a substrate, and includes, for example, any one of a capacitor, a resistor, a sensor, an inductor, and an application specific integrated circuit.
  • the shape of the semiconductor device 110 may be any of a rectangular parallelepiped (such as a silicon capacitor), a sphere, a hemisphere, a cylinder, a polyhedron, or a cone.
  • the silicon capacitor in the semiconductor device 110 as an example, the silicon capacitor includes two bonding pads, and the two bonding pads are respectively located on two sides of the bottom surface.
  • Silicon capacitors have the advantage of miniaturization. They can also show high stability under the conditions of frequency, temperature and voltage changes, and they are also very resistant to aging. They can be stably used in medical, aerospace, automotive, communication and other industries Electronic equipment. Taking the medical field as an example, the silicon capacitor package component can be used as an implant for a visual prosthesis for retinal implantation or cerebral cortex implantation, as a discrete component, to be electrically connected with ASIC chips and flexible cables .
  • An electronic device includes a semiconductor device packaging assembly manufactured by the above-mentioned packaging method.

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Abstract

一种半导体器件(110)的封装方法、封装组件及电子设备，半导体器件 (110) 包括侧面、底面以及在底面上暴露的至少一个焊盘 (111)，封装方法包括：形成位于半导体器件 (110) 下方的支撑结构 (100)，支撑结构 (100) 与焊盘 (111) 接触并且暴露底面的周边部分；形成覆盖半导体器件 (110) 的聚合物膜 (120)，聚合物膜 (120) 至少形成在底面的周边部分和侧面上；以及去除支撑结构 (100)，以暴露焊盘 (111)。

Description

半导体器件的封装方法、封装组件及电子设备 技术领域
本公开涉及半导体器件领域，更具体地，涉及一种半导体器件的封装方法、封装组件及电子设备。
背景技术
相关技术中，通过在硅等半导体衬底的划分区域中形成堆叠结构来制造半导体器件，并把半导体衬底切割形成单独的各个半导体器件。半导体器件经由位于半导体器件表面的焊盘(metal pad)与外部电路电连接，例如将焊盘经由焊锡或导电胶焊接或粘附至外部电路，从而实现电连接。
以半导体器件中的硅电容器为例，硅电容器包括衬底和位于衬底底面的两个焊盘，两个焊盘之间通过绝缘层隔离，硅电容器通过附着于焊盘的导电胶与其它电路元件电连接。
在进行电连接工序时，焊接材料或导电胶很容易粘附到衬底(例如硅)的侧面，由于硅的半导体特性，这会导致硅电容器因短路而失效。现有技术通过采用一种掩膜工艺来附着导电胶，即先在电路元件上放置掩膜，涂覆导电胶后，再移出掩膜，最后贴附硅电容器，该工艺操作复杂、难度大、产品良率低。
除了硅电容器外，其它半导体器件，也可能存在以上的技术问题。因此，亟需对现有技术的半导体器件封装组件进行进一步改进，以解决上述问题。
发明内容
鉴于上述问题，本公开的目的在于提供一种半导体器件的封装方法、封装组件及电子设备，避免半导体器件在焊接或粘附至其他电路元件时，由于焊接材料或导电胶粘附而出现的短路。
根据本公开的第一方面实施例的半导体器件的封装方法，所述半导体器件包括侧面、底面以及在所述底面上暴露的至少一个焊盘，所述封装方法包括：形成位于所述半导体器件下方的支撑结构，所述支撑结构与所述焊盘接触，并且暴露所述底面的周边部分；形成覆盖所述半导体器件的聚合物膜，所述聚合物膜至少形成在所述底面的周边部分和所述侧面上；以及去除所述支撑结构，以暴露所述焊盘。
根据本公开的一些实施例，所述聚合物膜还形成在所述半导体器件的顶面上。
根据本公开的一些实施例，形成所述支撑结构的步骤具体包括：在衬底上形成第一光刻胶层；以及图案化所述第一光刻胶层，其中，所述第一光刻胶层形成台阶结构以使聚合物材料进入所述底面的周边部分。
根据本公开的一些实施例，在形成所述第一光刻胶层之前，所述封装方法还包括：在所述衬底上形成第二光刻胶层；其中，所述第一光刻胶层形成于所述第二光刻胶层之上，所述第二光刻胶层在去除所述支撑结构的步骤中溶解以使所述半导体器件与所述衬底分离。
根据本公开的一些实施例，所述焊盘与所述第二光刻胶层的上表面之间具有缝隙。
根据本公开的一些实施例，图案化所述第一光刻胶层的步骤具体包括：采用光源照射所述第一光刻胶层，以对所述第一光刻胶层进行曝光处理；以及采用显影液去除被感光的所述第一光刻胶层，以暴露出所述半导体器件的所述底面的周边部分，其中，采用光源照射所述第一光刻胶层时，位于所述底面下方的至少部分所述第一光刻胶层被所述半导体器件遮挡。
根据本公开的一些实施例，采用光源照射所述第一光刻胶层具体包括采用垂直照射的方式或采用倾角照射的方式照射所述第一光刻胶层。
根据本公开的一些实施例，所述聚合物膜为派瑞林膜，其中所述派瑞林膜采用化学气相沉积工艺覆盖所述半导体器件。
根据本公开的一些实施例，所述聚合物膜为聚酰亚胺膜、聚丙烯膜或聚对苯二甲酸膜，其中所述聚合物膜采用旋涂法或注塑法覆盖所述半导体器件。
根据本公开的一些实施例，在形成所述聚合物膜之后，所述封装方法还包括：切割所述聚合物膜以分离所述半导体器件，切割所述聚合物膜的方法包括机械切割工艺、微电子机械系统(Micro-Electro-Mechanical Systems，MEMS)工艺、热切割工艺或激光切割工艺。
根据本公开的一些实施例，采用MEMS工艺切割所述聚合物膜的方法具体包括：在所述聚合物膜上形成金属膜；在所述金属膜上形成第三光刻胶层；图案化所述第三光刻胶层；去除暴露的所述金属膜和所述聚合物膜；去除剩余的所述第三光刻胶层和所述金属膜。
根据本公开的一些实施例，切割所述聚合物膜的方法还包括切割所述聚合物膜以形成从所述半导体器件向外延伸的夹持端。
根据本公开的第二方面实施例的半导体器件封装组件，包括：半导体器件，所述半导体器件包括侧面、底面以及在所述底面上暴露的至少一个焊盘；以及聚合物膜，所述聚合 物膜覆盖所述半导体器件，所述聚合物膜至少形成在所述底面的周边部分和所述侧面上。
根据本公开的一些实施例，所述聚合物膜还形成在所述半导体器件的顶面上。
根据本公开的一些实施例，所述聚合物膜包括从所述半导体器件向外延伸的夹持端。
根据本公开的一些实施例，所述聚合物膜为派瑞林膜。
根据本公开的一些实施例，所述聚合物膜为聚酰亚胺膜、聚丙烯膜或聚对苯二甲酸膜。
根据本公开的第三方面实施例的电子设备，包括采用根据本公开上述第一方面实施例的封装方法制造的半导体器件封装组件或根据本公开上述第二方面实施例的半导体器件封装组件。
本公开提供的技术方案，形成了覆盖半导体器件的聚合物膜，且聚合物膜至少包裹半导体器件底面的周边部分和侧面，在将半导体器件焊接或粘附至其他电路元件时，即使焊接材料或导电胶粘附到了半导体器件的侧壁，由于聚合物膜的绝缘作用，也会避免半导体器件出现短路，进而降低了半导体器件焊接或粘附工艺的精度要求，提高工艺良品率。
进一步地，本公开中位于底面周边部分的聚合物膜增加了短路保护可靠度以及聚合物膜与半导体器件之间的结合强度，从而增加了半导体器件封装组件的使用寿命。
进一步地，本公开的聚合物膜还起到了对半导体器件的防机械损伤，水汽侵蚀及化学腐蚀的保护层的作用，增加了半导体器件的可靠性和稳定性。
进一步地，本公开将半导体器件封装组件与其它电路元件贴合时，采用常规的粘接工艺即可，无需采用现有技术的掩膜工艺，操作简单、良率高，大大提高了半导体器件的使用范围及适用领域。
进一步地，本公开提供的技术方案，可以同时形成多个半导体器件封装组件，该方案简单易行，适合工业化生产。
本公开的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本公开的实践了解到。
附图说明
本公开的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解，其中：
图1是根据本公开实施例的半导体器件的封装方法的一个或多个阶段的爆炸图；
图2是根据本公开实施例的封装方法的一个或多个阶段的立体图；
图3a是根据本公开实施例的封装方法的形成第一光刻胶层和第二光刻胶层的阶段的截面图；
图3b是根据本公开实施例的封装方法的在第一光刻胶层上放置半导体器件的阶段的截面图；
图3c是根据本公开实施例的封装方法的图案化第一光刻胶层的阶段的截面图；
图3d是图3c圈示的部分的放大图；
图3e是根据本公开实施例的封装方法的形成覆盖半导体器件的聚合物膜的阶段的截面图；
图3f是根据本公开实施例的封装方法的切割位于支撑结构的表面的聚合物膜的阶段的截面图；
图3g是根据本公开实施例的封装方法的去除支撑结构的阶段的截面图；
图4a是根据本公开实施例的形成覆盖于聚合物膜的表面的金属膜的阶段的截面图；
图4b是根据本公开实施例的形成覆盖于金属膜的表面的第三光刻胶层的阶段的截面图；
图4c是根据本公开实施例的图案化第三光刻胶层的阶段的截面图；
图4d是根据本公开实施例的去除暴露的金属膜和聚合物膜的阶段的截面图；
图4e是根据本公开实施例的去除第三光刻胶层、金属膜以及支撑结构的阶段的截面图；
图5是根据本公开实施例的半导体器件的封装方法的一个或多个阶段的俯视图；
图6a是根据本公开实施例的半导体器件封装组件的实物图；
图6b是根据本公开实施例的附着有导电胶的半导体器件封装组件的实物图。
附图标记：
支撑结构100；衬底101；
第二光刻胶层102；第一光刻胶层103；
半导体器件110；焊盘111；
聚合物膜120；夹持端121；
金属膜130；第三光刻胶层131；
晶圆140；导电胶150。
具体实施方式
下面结合附图和实施例，对本公开的具体实施方式作进一步详细描述。
在本公开中，术语“半导体结构”指在半导体器件的封装方法的各个步骤中形成的整个半导体结构的统称，包括已经形成的所有层或区域。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但本领域的技术人员能够理解，可以不按照这些特定的细节来实现本公开。
如图1-图2所示，在半导体器件110的封装方法的一个或多个阶段中，形成包括支撑结构100、半导体器件110以及覆盖半导体器件110的聚合物膜120的半导体结构。在后续工艺制程中，将去除支撑结构100，以形成半导体器件封装组件。
半导体器件110包括侧面、底面以及在底面上暴露的至少一个焊盘111。支撑结构100至少包括衬底101和图案化的第一光刻胶层103。在一些可选的实施例中，支撑结构100还可以包括第二光刻胶层102。衬底101用于提供机械支撑，第二光刻胶层102用于在切割工艺中保护衬底101以及在去除支撑结构100时发生溶解以去除衬底101。图案化的第一光刻胶层103提供台阶结构以支撑半导体器件110，图案化的第一光刻胶层103与焊盘111接触，且半导体器件110底面的周边部分形成用于容纳聚合物膜120的空间。
聚合物膜120至少形成于半导体器件110底面的周边部分和侧面，位于该周边部分的聚合物膜(如图1虚线框内所示)的厚度由半导体器件110的底面与第二光刻胶层102的上表面之间的距离控制，其宽度由第一光刻胶层103被蚀刻的横向深度控制。进一步地，聚合物膜120还可以形成于半导体器件110的顶面。
在一些可选的实施例中，支撑结构100可以包括半导体衬底、金属片、塑料片、玻璃片、陶瓷片或者任意的叠层结构，用于支撑半导体器件110的底面，并在半导体器件110的底面的周边部分形成用于容纳聚合物膜120的空间。
图3a-图3f示出了根据本公开实施例的半导体器件110的封装方法的各个阶段的截面图，这些截面图沿着图2中的A-A线截取。
如图3a所示，该封装方法开始于已经在衬底101上形成第一光刻胶层103和第二光刻胶层102的半导体结构。第一光刻胶层103为正光刻胶层。例如可以采用旋涂正光刻胶的工艺制程形成第一光刻胶层103，之后将半导体器件110压入第一光刻胶层103，并对第一光刻胶层103进行软烤，以增大半导体器件110在第一光刻胶层103中的附着力。
第二光刻胶层102和第一光刻胶层103可以分别为极性相反的光刻胶层，例如，第二光刻胶层102为负光刻胶层，第一光刻胶层103为正光刻胶层。第二光刻胶层102用于在切 割工艺中保护衬底101并在释放半导体器件的时候作为牺牲层。可选地，可以省去第二光刻胶层102，以简化工艺流程。
在该步骤中，衬底101可以为晶圆(wafer)等，完成晶圆的清洁后，在晶圆的表面旋涂负光刻胶，并对负光刻胶进行软烤、曝光，例如将负光刻胶全部暴露于光源，由于负光刻胶在曝光区能很快地发生光固化反应，因此形成了整体被固化的第二光刻胶层102，使第二光刻胶层102在后续的显影工艺中得以保留。
进一步地，如图3b所示，在第一光刻胶层103上放置至少一个半导体器件110。在该步骤中，半导体器件110的底面与第二光刻胶层102的上表面之间具有缝隙，即，半导体器件110与第二光刻胶层102的表面不完全贴紧，或隔开预定距离，通过控制半导体器件110压入第一光刻胶层103的作用力和按压时间可以控制该预定距离的大小。
进一步地，如图3c所示，图案化第一光刻胶层103，以形成支撑结构100。在该步骤中，采用自对准工艺对第一光刻胶层103进行曝光处理，即，利用半导体器件110作为遮挡掩膜，采用光源照射第一光刻胶层103，以对第一光刻胶层103进行曝光处理，位于半导体器件110底面下方的第一光刻胶层103被半导体器件110遮挡。曝光处理之后，采用显影液去除被感光的第一光刻胶层103，以对第一光刻胶层103进行过显影(over develop)处理并形成支撑结构100，支撑结构100的表面与半导体器件110的表面具有缝隙，通过控制显影时间可以控制缝隙的横向深度。
在一些可选的实施例中，采用垂直照射的方式利用半导体器件110作为遮挡掩膜和/或采用倾角照射的方式以对位于半导体器件110底面的周边部分的第一光刻胶层103进行曝光处理，通过控制曝光过程中光源照射的倾角大小可以控制缝隙的横向深度。
可选地，焊盘111位于半导体器件110底面的边缘处，焊盘111的截面形状可以为矩形、梯形或台阶形。第一光刻胶层103的形状与半导体器件110互补，焊盘111的一部分表面的第一光刻胶层103被去除(参见图3c中的放大图，焊盘111的倒角处、及部分底面与第二光刻胶层102的上表面之间形成缝隙)，以形成用于容纳聚合物膜120的空间。
可选地，在对第一光刻胶层103进行曝光、显影之后，对半导体结构进行清洗、甩干、热盘烘干。
进一步地，如图3d所示，形成覆盖半导体器件110的聚合物膜120。聚合物膜120至少形成于半导体器件110的侧面和底面的周边部分。
以半导体器件110的形状是长方体为例，半导体器件110的顶面、侧面及底面的周边部分均为暴露表面，因此半导体器件110的顶面、侧面及底面的周边部分均沉积有聚合物膜 120，从而聚合物膜120对半导体器件110形成了密闭的包覆。在一些可选的实施例中，在气相沉积工艺过程中，可以在半导体器件110的顶面进行遮挡处理(如形成掩膜等)。
在使用导电胶将半导体器件110附着于其它电路元件时，即使焊接材料或导电胶粘附到半导体器件110的侧面，由于聚合物膜120的绝缘作用，也不会导致半导体器件110由于短路而失效。
由于半导体器件110底面的周边部分与第二光刻胶层102之间具有缝隙，与液体分子相比，气体分子更容易进入缝隙，因此可以采用气相沉积工艺形成聚合物膜120。
在该步骤中，聚合物膜120的材料可以为派瑞林(Parylene)，并且采用化学气相沉积(Chemical Vapor Deposition,CVD)工艺形成聚合物膜120。其中，可以在室温条件下进行化学气相沉积工艺以形成派瑞林膜，从而可以保护半导体器件110在工艺过程中不会因高温而损坏。
例如，派瑞林沉积设备包括气化系统和沉积系统。气化系统的运行分为两个阶段：在第一阶段，粉末状的派瑞林在真空中被加热，开始变成蒸气；在第二阶段，上述蒸气被输送到炉腔，并在预设温度下热解为单体(单自由基对二甲苯)。将上述单体送入沉积系统，单体遇冷即沉积为派瑞林膜。该阶段中，单体以分子级尺寸沉积在半导体器件110的表面及底面的上述周边部分。
可选地，在沉积聚合物膜120之前，还可以采用等离子体清洗工艺对半导体器件110进行清洗，例如采用氧等离子体对半导体器件110进行清洗，以对半导体器件110进行表面清洁和表面粗糙化并在半导体器件110的表面形成亲水的氧功能团，便于提高后续沉积的聚合物膜120与半导体器件110的结合强度。
可选地，聚合物膜120为聚酰亚胺(Polyimide)膜、聚丙烯(Polypropylene)膜、聚对苯二甲酸(PET，PETE，Polyethylene Terephthalate)膜或其它聚合物材料。聚合物膜120可以采用旋涂法或注塑法覆盖半导体器件110。
进一步地，如图3e所示，切割位于支撑结构100的表面的聚合物膜120。在该实施例中，可以采用机械切割工艺切割位于支撑结构100的表面的聚合物膜120，以将多个半导体器件110分离，例如可以采用刀具机械切割的方式，以简化工艺流程。在一些可选的实施例中，可以采用MEMS制造工艺、热切割工艺或激光切割等工艺。
可选地，在切割聚合物膜120时，沿图3e中的虚线位置切割聚合物膜120，以形成从半导体器件110向外延伸的夹持端121。采用镊子等工具夹取夹持端121，可以避免对半导体器件110的损伤，而且操作十分方便。
进一步地，如图3f所示，去除支撑结构100以将焊盘111暴露出来以用于电连接。在该步骤中，例如可以采用去除剂浸泡半导体结构以去除支撑结构100，之后进行水冲洗和烘烤半导体结构的步骤从而形成半导体器件封装组件。
图4a-图4e示出了根据本公开实施例的采用MEMS工艺切割聚合物膜120的方法的各个阶段的截面图。该方法开始于图3d所示的半导体结构。
如图4a所示，在半导体结构的表面形成覆盖于聚合物膜120的表面的金属膜130。金属膜130例如为铝膜。
进一步地，如图4b所示，形成覆盖于金属膜130的表面的第三光刻胶层131。第三光刻胶层131可以为正光刻胶层。
进一步地，如图4c所示，图案化第三光刻胶层131，以使第三光刻胶层131至少覆盖半导体器件110的表面。在一些可选的实施例中，图案化的第三光刻胶层131还可以覆盖聚合物膜120的用于形成夹持端121的表面。在该步骤中，例如可以采用光刻和显影的方法对第三光刻胶层131进行图案化处理。
进一步地，如图4d所示，去除暴露的金属膜130和聚合物膜120，以将位于支撑结构100的表面的多个半导体器件110分离。
在该步骤中，可以采用各向异性的蚀刻方法(例如采用干法蚀刻)蚀刻聚合物膜120。例如通过控制蚀刻时间，使得蚀刻在支撑结构100中的第二光刻胶层102的表面处停止。
进一步地，如图4e所示，去除第三光刻胶层131、金属膜130以及支撑结构100，以暴露焊盘111。在该步骤中，例如采用去除剂浸泡半导体结构以溶解光刻胶，采用湿法蚀刻去除剩余的金属膜130，之后对半导体结构进行清洗、甩干以及热盘烘干，以形成半导体器件封装组件。
最终形成的半导体器件封装组件(如图3f和图4e所示)，包括半导体器件110以及覆盖于半导体器件110的表面的聚合物膜120。半导体器件110包括顶面、侧面、底面以及在底面上暴露的至少一个焊盘111，聚合物膜120至少形成于半导体器件110的侧面以及底面的周边部分，聚合物膜120可以为派瑞林膜。
为了批量化生产，因此每个晶圆140的表面可以被划分为多个区域，以形成多个半导体器件封装组件。如图5所示，聚合物膜120具有夹持端121，夹持端121向一侧延伸以便于夹取，夹持端121的形状可以为矩形。
从图6a中可见，半导体器件110的底面周边部分覆盖有聚合物膜120，且聚合物膜120还具有夹持端121。如图6b所示，在进行电连接工序时，例如可以将导电胶150涂覆至焊 盘111的表面，以将半导体器件110电连接至其他电路元件，例如以用于提供电压和/或电流的外部电路，以形成电子设备。在另一些可选的实施例中，还可以采用焊接材料将半导体器件110连接至其他电路元件。即使焊接材料或导电胶150粘附至半导体器件110的侧壁，由于聚合物膜120的绝缘保护，半导体器件110也不会因短路而失效，从而降低了半导体器件110焊接或粘附工艺的精度要求，提高了工艺良品率。
进一步地，位于半导体器件110底面的周边部分的聚合物膜120，提高了短路保护可靠度、以及聚合物膜120与半导体器件110之间的结合强度，因此聚合物膜120不会轻易脱落，延长了半导体器件封装组件的使用寿命。
进一步地，由于增加了聚合物膜120在半导体器件110外部层的包裹和覆盖，聚合物膜120起到了对半导体器件110的防机械损伤、水汽侵蚀及化学腐蚀的保护层的作用，提高了半导体器件的可靠性和稳定性。
半导体器件110为用硅或其它半导体作为基底加工的芯片或电子器件，例如包括电容器、电阻器、传感器、电感器、专用集成电路中的任意一种。半导体器件110的形状可以为长方体(如硅电容器)、球体、半球体、圆柱体、多面体、或锥体中的任意一种。以半导体器件110中的硅电容器的为例，硅电容器包括两个焊盘，两个焊盘分别位于底面的两侧边缘。
硅电容器具备尺寸小型化的优势，在频率、温度、电压变化的情况也能表现出较高的稳定性，而且耐老化性能也非常好，能稳定应用于医疗、航空航天、汽车、通信等行业的电子设备。以医疗领域为例，该硅电容器封装组件能用于作为视网膜植入或脑皮层植入的视觉假体的植入件中，作为分立元器件使用，以与专用集成电路芯片及柔性电缆电连接。
根据本公开实施例的电子设备，包括采用上述封装方法所制造的半导体器件封装组件。
尽管已经示出和描述了本公开的实施例，本领域的普通技术人员可以理解：在不脱离本公开的原理和宗旨的情况下可以对这些实施例进行多种变化、修改、替换和变型，本公开的范围由权利要求及其等同物限定。

Claims (18)

  1. 一种半导体器件的封装方法，所述半导体器件包括侧面、底面以及在所述底面上暴露的至少一个焊盘，其特征在于，所述封装方法包括：
    形成位于所述半导体器件下方的支撑结构，所述支撑结构与所述焊盘接触，并且暴露所述底面的周边部分；
    形成覆盖所述半导体器件的聚合物膜，所述聚合物膜至少形成在所述底面的周边部分和所述侧面上；以及
    去除所述支撑结构，以暴露所述焊盘。
  2. 根据权利要求1所述的封装方法，其特征在于，所述聚合物膜还形成在所述半导体器件的顶面上。
  3. 根据权利要求1所述的封装方法，其特征在于，形成所述支撑结构的步骤具体包括：
    在衬底上形成第一光刻胶层；以及
    图案化所述第一光刻胶层；
    其中，所述第一光刻胶层形成台阶结构以使聚合物材料进入所述底面的周边部分。
  4. 根据权利要求3所述的封装方法，其特征在于，在形成所述第一光刻胶层之前，还包括：
    在所述衬底上形成第二光刻胶层；
    其中，所述第一光刻胶层形成于所述第二光刻胶层之上，所述第二光刻胶层在去除所述支撑结构的步骤中溶解以使所述半导体器件与所述衬底分离。
  5. 根据权利要求4所述的封装方法，其特征在于，所述焊盘与所述第二光刻胶层的上表面之间具有缝隙。
  6. 根据权利要求3所述的封装方法，其特征在于，图案化所述第一光刻胶层的步骤具体包括：
    采用光源照射所述第一光刻胶层，以对所述第一光刻胶层进行曝光处理；以及
    采用显影液去除被感光的所述第一光刻胶层，以暴露出所述半导体器件的所述底面的周边部分；
    其中，采用光源照射所述第一光刻胶层时，位于所述底面下方的至少部分所述第一光刻胶层被所述半导体器件遮挡。
  7. 根据权利要求6所述的封装方法，其特征在于，采用光源照射所述第一光刻胶层具体包括：
    采用垂直照射的方式或采用倾角照射的方式照射所述第一光刻胶层。
  8. 根据权利要求1所述的封装方法，其特征在于，所述聚合物膜为派瑞林膜，其中所述派瑞林膜采用化学气相沉积工艺覆盖所述半导体器件。
  9. 根据权利要求1所述的封装方法，其特征在于，所述聚合物膜为聚酰亚胺膜、聚丙烯膜或聚对苯二甲酸膜，其中所述聚合物膜采用旋涂法或注塑法覆盖所述半导体器件。
  10. 根据权利要求1所述的封装方法，其特征在于，在形成所述聚合物膜之后，还包括：
    切割所述聚合物膜以分离所述半导体器件，切割所述聚合物膜的方法包括机械切割工艺、MEMS工艺、热切割工艺或激光切割工艺。
  11. 根据权利要求10所述的封装方法，其特征在于，采用MEMS工艺切割所述聚合物膜的方法具体包括：
    在所述聚合物膜上形成金属膜；
    在所述金属膜上形成第三光刻胶层；
    图案化所述第三光刻胶层；
    去除暴露的所述金属膜和所述聚合物膜；
    去除剩余的所述第三光刻胶层和所述金属膜。
  12. 根据权利要求10所述的封装方法，其特征在于，切割所述聚合物膜的方法还包括：
    切割所述聚合物膜以形成从所述半导体器件向外延伸的夹持端。
  13. 一种半导体器件封装组件，其特征在于，包括：
    半导体器件，所述半导体器件包括侧面、底面以及在所述底面上暴露的至少一个焊盘；以及
    聚合物膜，所述聚合物膜覆盖所述半导体器件，所述聚合物膜至少形成在所述底面的周边部分和所述侧面上。
  14. 根据权利要求13所述的半导体器件封装组件，其特征在于，所述聚合物膜还形成在所述半导体器件的顶面上。
  15. 根据权利要求13所述的半导体器件封装组件，其特征在于，所述聚合物膜包括从所述半导体器件向外延伸的夹持端。
  16. 根据权利要求13所述的半导体器件封装组件，其特征在于，所述聚合物膜为派瑞林膜。
  17. 根据权利要求13所述的半导体器件封装组件，其特征在于，所述聚合物膜为聚酰亚胺膜、聚丙烯膜或聚对苯二甲酸膜。
  18. 一种电子设备，其特征在于，包括采用如权利要求1所述的封装方法制造的半导 体器件封装组件或如权利要求13所述的半导体器件封装组件。
PCT/CN2020/102297 2019-07-19 2020-07-16 半导体器件的封装方法、封装组件及电子设备 WO2021013030A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102132411A (zh) * 2008-08-29 2011-07-20 垂直电路公司 图像传感器
CN102468264A (zh) * 2010-11-17 2012-05-23 三星电子株式会社 凸起结构、半导体封装件及其制造方法
US20120181686A1 (en) * 2011-01-19 2012-07-19 Samsung Electronics Co., Ltd. Method of preparing semiconductor package and semiconductor die for semiconductor package
CN110400757A (zh) * 2019-07-19 2019-11-01 微智医疗器械有限公司 半导体器件的封装方法、封装组件及电子设备

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102132411A (zh) * 2008-08-29 2011-07-20 垂直电路公司 图像传感器
CN102468264A (zh) * 2010-11-17 2012-05-23 三星电子株式会社 凸起结构、半导体封装件及其制造方法
US20120181686A1 (en) * 2011-01-19 2012-07-19 Samsung Electronics Co., Ltd. Method of preparing semiconductor package and semiconductor die for semiconductor package
CN110400757A (zh) * 2019-07-19 2019-11-01 微智医疗器械有限公司 半导体器件的封装方法、封装组件及电子设备

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