WO2021012798A1 - 半导体处理装置及方法 - Google Patents

半导体处理装置及方法 Download PDF

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Publication number
WO2021012798A1
WO2021012798A1 PCT/CN2020/093782 CN2020093782W WO2021012798A1 WO 2021012798 A1 WO2021012798 A1 WO 2021012798A1 CN 2020093782 W CN2020093782 W CN 2020093782W WO 2021012798 A1 WO2021012798 A1 WO 2021012798A1
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Prior art keywords
electrode
radius
radio frequency
disk body
semiconductor processing
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PCT/CN2020/093782
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English (en)
French (fr)
Inventor
王卓
周仁
张赛谦
Original Assignee
沈阳拓荆科技有限公司
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Application filed by 沈阳拓荆科技有限公司 filed Critical 沈阳拓荆科技有限公司
Priority to US17/620,881 priority Critical patent/US20220351942A1/en
Priority to JP2022504556A priority patent/JP2022542264A/ja
Priority to KR1020227005946A priority patent/KR20220038437A/ko
Priority to CN202080045039.9A priority patent/CN113994452A/zh
Publication of WO2021012798A1 publication Critical patent/WO2021012798A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32715—Workpiece holder
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/32174—Circuits specially adapted for controlling the RF discharge
    • H01J37/32183—Matching circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/32137—Radio frequency generated discharge controlling of the discharge by modulation of energy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32532—Electrodes
    • H01J37/32541—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/32091—Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32532—Electrodes
    • H01J37/32568—Relative arrangement or disposition of electrodes; moving means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
    • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
    • H01J2237/332—Coating
    • H01J2237/3321—CVD [Chemical Vapor Deposition]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
    • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
    • H01J2237/334—Etching

Definitions

  • the present application generally relates to semiconductor processing devices, and more specifically, to semiconductor processing devices with adjustable radio frequency loops.
  • Plasma processing is used in the manufacturing of integrated circuits, photomasks, plasma displays, and solar technology.
  • wafers are processed by plasma chambers, such as etching, plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PEPVD).
  • PECVD plasma enhanced chemical vapor deposition
  • PEPVD physical vapor deposition
  • the control of processing parameters needs to be more precise, such as plasma energy spectrum, plasma energy radial distribution, plasma density, and plasma density radial distribution.
  • the plasma density which determines the deposition rate and etching rate of the wafer surface.
  • the radial distribution of plasma density and the radial distribution of plasma energy affect the uniformity of deposition and etching.
  • the known semiconductor processing device is provided with an upper electrode and a lower electrode, which can generate plasma between the two.
  • the known configuration is still not easy to achieve these precise controls, and even limits the freedom of plasma adjustment.
  • the present application provides a disk body for a semiconductor processing device, which includes a first electrode and a second electrode, wherein the first electrode is selectively coupled to a first ground terminal via a first switch The second electrode is selectively coupled to a second ground terminal via a second switch, and the first electrode and the second electrode are electrically isolated from each other.
  • the tray body further includes a carrying surface for carrying a wafer, wherein the first electrode and the second electrode are located below the carrying surface.
  • the first electrode is defined by a first radius
  • the second electrode is defined by a second radius and a third radius
  • the third radius is larger than the first radius and the second radius.
  • the first electrode and the second electrode are located on the same plane or different planes.
  • the first electrode is defined by a first radius
  • the second lower electrode is defined by a second radius
  • the first electrode and the second electrode are located on different planes. According to an embodiment of the present application, the first radius and the second radius are approximately equal.
  • the first electrode and the second electrode are arranged concentrically. In other embodiments, at least one of the first electrode and the second electrode is a block in a circular or ring electrode, and the circular or ring electrode includes a plurality of blocks.
  • At least one of the first electrode and the second electrode includes a mesh structure.
  • the present application provides a semiconductor processing apparatus including a disk body according to an embodiment of the present application.
  • the semiconductor processing device further includes a second disk body including a third electrode electrically coupled to the radio frequency generator and matcher.
  • the semiconductor processing device further includes: a first feedback component configured to provide a first feedback signal to the radio frequency generator and matcher based on a signal received from the first electrode; and a second A feedback component configured to provide a second feedback signal to the radio frequency generator and matcher based on the signal received from the second electrode.
  • the present application provides a method of manufacturing a ground electrode for a semiconductor processing device, which includes: providing a disk body base; and forming a first electrically isolated ground electrode in the disk body base in the following manner. Electrode and second electrode: (1) sintering the first electrode and the second electrode in the base of the disc body respectively; or (2) combining the first electrode and the second electrode by weaving The two electrodes are molded and pressed in the base of the disc body at one time.
  • respectively sintering the first electrode and the second electrode in the disc body base includes sintering the first electrode and the second electrode into the disc body base. At the same plane. In other embodiments, respectively sintering the first electrode and the second electrode in the disk body base includes sintering the first electrode and the second electrode into the disk body base Different planes.
  • the present application provides a method of operating a semiconductor processing device according to an embodiment of the present application, which includes: for a first process, controlling the first switch to couple the first electrode to the The first ground terminal; and for the second process, controlling the second switch to couple the second electrode to the second ground terminal.
  • the method further includes: for the third process, controlling the first switch and the second switch to couple the first electrode and the second electrode to the first electrode, respectively A ground terminal and the second ground terminal.
  • Fig. 1 shows a block diagram of an exemplary radio frequency component according to an embodiment of the present application.
  • Fig. 1A shows a schematic structural diagram of an exemplary feedback/control device according to an embodiment of the present application.
  • Fig. 2 shows a schematic diagram of an exemplary ground electrode configuration according to an embodiment of the present application.
  • Fig. 2A shows a schematic diagram of an exemplary circular electrode according to an embodiment of the present application.
  • Figure 2B shows a schematic diagram of an exemplary ring electrode according to an embodiment of the present application.
  • FIG. 3 shows a schematic diagram of an exemplary semiconductor processing apparatus according to an embodiment of the present application.
  • FIG. 4 shows a schematic diagram of another exemplary semiconductor processing apparatus according to an embodiment of the present application.
  • FIG. 5 shows a flowchart of an exemplary method of manufacturing a ground electrode for a semiconductor processing device according to an embodiment of the present application.
  • FIG. 6 shows a flowchart of an exemplary method of operating a semiconductor processing apparatus according to an embodiment of the present application.
  • FIG. 1 shows a schematic diagram of a radio frequency component 100 according to some embodiments of the present application.
  • the radio frequency component 100 includes a first electrode 101 and a plurality of second electrodes 102 and 103 and a radio frequency generator and matcher 104 in a cavity (such as a processing cavity, not shown in the figure) of a semiconductor processing device.
  • a cavity such as a processing cavity, not shown in the figure
  • the radio frequency assembly 100 may include a greater number of first electrodes and/or a greater number of second electrodes.
  • Figure 1 is only for illustrative purposes, and does not limit the actual size, shape and relative position of each component.
  • the radio frequency generator and matcher 104 are electrically coupled (for example, connected by a coaxial cable) to the first electrode 101 to provide radio frequency signals.
  • the second electrodes 102 and 103 are electrically coupled to the radio frequency generator and matcher 104 via the feedback/control devices 105 and 106 respectively.
  • the feedback/control devices 105, 106 are configured to receive one or more sensing signals from the second electrodes 102, 103, respectively, and generate corresponding multiple feedback signals accordingly, and provide the feedback signals to the radio frequency generator and matcher 104 .
  • the feedback/control device 105, 106 can also be configured as a switch for selectively electrically coupling or disconnecting the second electrode 102, 103 to the corresponding ground terminal.
  • the ground terminals to which the second electrodes 102 and 103 are coupled may be the same ground point or different ground points.
  • the first electrode 101 may also be referred to as “radio frequency electrodes”
  • the second electrodes 102 and 103 may also be referred to as “ground electrodes”.
  • the first electrode 101 may be an upper electrode, and the second electrodes 102 and 103 may be a lower electrode. In other embodiments, the first electrode 101 may be a lower electrode, and the second electrodes 102 and 103 may be an upper electrode.
  • the upper electrode is arranged on the top of the cavity.
  • FIG. 1 does not show the structure of the cavity, a typical cavity has a cavity defined by a top, a bottom, and a wall. The top usually has complicated intake manifolds, gas distributors, gas channels and shower heads. In a typical configuration, the upper electrode is included in the structure of the shower head. The top of the cavity or the shower head is electrically coupled to the radio frequency generator and matcher 104 so that the upper electrode receives the signal from the radio frequency source.
  • the bottom electrode is arranged in the wafer support seat.
  • a typical wafer support base is connected to the bottom of the cavity so that the wafer can be supported at a height in the cavity.
  • a plasma region may be formed between the upper electrode and the wafer support base containing the lower electrode.
  • the wafer support base may include a carrying surface for carrying the wafer, wherein the lower electrode is located below the carrying surface.
  • the radio frequency generator and matcher 104 may include a radio frequency generator and a radio frequency matcher.
  • the RF generator in the RF generator and matcher 104 may include a low-frequency RF source, a high-frequency RF source, or a combination of both, and the RF matcher in the RF generator and matcher 104 may include a low-frequency RF source.
  • the matching network includes one or more capacitors, inductors, and some electronic components, and the detailed composition is not described here. It is known to select low-frequency or high-frequency radio frequency operation according to different processing, and will not be repeated here.
  • the radio frequency generator and matcher 104 is configured to receive one or more feedback signals provided by the feedback/control devices 105, 106 and adjust the output frequency of the low-frequency or high-frequency radio frequency source and/or one of the matching networks accordingly. Or multiple variable electronic components, such as variable capacitors, or other variable components in radio frequency circuit components, to control the characteristics of the plasma in the chamber.
  • the radio frequency generator and matcher 104 may be configured to receive one or more feedback signals from the first electrode 101. In other embodiments, one or more of the feedback/control devices 105, 106 does not provide a feedback signal to the radio frequency generator and matcher 104.
  • the feedback/control device in this application can be used to determine various operations associated with the second electrode, such as determining whether the second electrode is grounded, whether to adjust related variable electronic components or to apply to the second electrode. Power, etc.
  • FIG. 1A shows a schematic structural diagram of an exemplary feedback/control device 115 according to an embodiment of the present application.
  • the feedback/control device 115 may be an example of the feedback/control device 105 or 106 in FIG. 1.
  • the feedback/control device 115 may include a feedback component 116 and a switch 118.
  • the feedback component 116 generates a feedback signal based on the signal received from the ground electrode 112 (such as the second electrode 102 or 103 shown in FIG. 1), and provides the feedback signal to the radio frequency generator 114 (such as the one shown in FIG. 1) Radio frequency generator and matcher 104).
  • the feedback component 116 directly provides the signal received from the ground electrode 112 to the radio frequency generator and matcher 114.
  • the feedback/control device 115 does not include the feedback component 116, that is, the feedback/control device 115 does not provide a feedback signal to the radio frequency generator and matcher 114.
  • Switch 118 under the control of a control signal S C, 112 selectively coupled to ground or disconnected from the ground terminal ground electrode.
  • a control signal S C may be at least partially based on signals received from the ground electrode 112, or at least partially based on signals received from the other or radio frequency electrode is a ground electrode, or at least partially on the ongoing process or processes required to be performed.
  • a control signal S C may be generated by hardware or software. The method of generating a control signal based on certain signals or parameters is well known to those skilled in the art, so it will not be repeated here.
  • an impedance network composed of one or more resistors, one or more capacitors, one or more inductors, etc. may be included between the ground electrode 112 and the ground terminal. Provide fixed impedance or variable impedance in the loop (for example, through variable capacitors, etc.).
  • Fig. 2 shows a schematic diagram of an exemplary ground electrode configuration according to an embodiment of the present application (a feedback/control device is omitted). This schematic diagram shows a top view of the ground electrode. Although a specific number of electrodes is shown in FIG. 2, those skilled in the art will understand that the ground electrode configuration of the present application may include fewer or greater numbers of electrodes.
  • the ground electrode configuration shown in this embodiment has a first electrode 201, a second electrode 202, and a third electrode 203.
  • the first electrode 201, the second electrode 202, and the third electrode 203 are arranged concentrically.
  • the first electrode 201 is a circular electrode, defined by a first radius R 1 .
  • the second electrode 202 is defined by at least a second radius R 2 .
  • the third electrode 203 is defined by at least a third radius R 3 .
  • the second radius R 2 is greater than the first radius R 1 but smaller than the third radius R 3 .
  • the second electrode 202 is a circular electrode; in another embodiment, the second electrode 202 may be a ring electrode defined by a first inner diameter and a second radius R 2 , and the first inner diameter may be greater than , Equal to or less than the first radius R 1 .
  • the third electrode 203 is a circular electrode; in another embodiment, the third electrode 203 may be another ring electrode defined by the second inner diameter and the third radius R 3 , the second inner diameter It can be greater than, equal to or less than the second radius R 2 .
  • the first electrode 201, the second electrode 202, and the third electrode 203 may be located at the same level (ie, located on the same plane).
  • the second electrode 202 and the second electrode 203 are ring electrodes, and the inner diameter of the second electrode 202 is greater than or equal to the first radius R 1 , and the inner diameter of the third electrode 203 is greater than or equal to the second radius R 2 .
  • the first electrode 201, the second electrode 202, and the third electrode 203 may be at different levels (that is, on different planes), as related examples are as follows.
  • the first electrode 201, the second electrode 202, and the third electrode 203 are electrically isolated from each other (for example, by an insulating material between the electrodes, or the electrodes are spaced apart from each other). As shown in the figure, each of the first electrode 201, the second electrode 202, and the third electrode 203 can be selectively connected to a ground terminal (with the feedback/control device omitted).
  • the ground electrode may be a circular electrode or a ring electrode. In other embodiments, the ground electrode may be a circle or a block in a ring electrode.
  • 2A and 2B respectively show schematic diagrams of an exemplary circular electrode 210 and a ring electrode 220 including multiple blocks according to an embodiment of the present application. Although FIGS. 2A and 2B show a specific number of regions divided in a specific manner, those skilled in the art will understand that the circular electrode 210 and the ring electrode 220 may include a smaller or greater number of regions divided in other ways. Piece.
  • the circular electrode 210 includes blocks 212, 214, 216, and 218.
  • the ring electrode 220 includes blocks 222, 224, 226, and 228.
  • the blocks 212, 214, 216, and 218 are electrically isolated from each other by insulating materials, and thus can be grounded independently.
  • the blocks 222, 224, 226, and 228 are electrically isolated from each other by insulating materials, and thus can be grounded independently.
  • the second electrode 202 shown in FIG. 1 may be a block 212
  • the third electrode 203 may be a block 214 or another circular or ring electrode or a block in another circular or ring electrode.
  • FIG. 3 shows a schematic diagram of an exemplary semiconductor processing apparatus according to an embodiment of the present application.
  • the ground electrode is the lower electrode, which is arranged in the wafer support seat.
  • the wafer support seat here includes a tray 300 having a wafer carrying surface 301 for carrying wafers undergoing various processes.
  • the upper electrode 302 is located at the top of the cavity.
  • the upper electrode 302 is contained in a shower head located at the top of the cavity.
  • the upper electrode 302 may be the cover or housing of the shower head.
  • the upper electrode 302 is electrically coupled to the radio frequency generator and matcher 303 to receive the radio frequency source.
  • the circuit composition of the upper electrode 302 is the same as the radio frequency generator and matcher 104 shown in FIG. 1, so the description will not be repeated.
  • the radio frequency generator and matcher 303 may be arranged on the top of the cavity or outside the cavity. Alternatively, the radio frequency generator and matcher 303 is electrically coupled to one or more lower electrodes. Alternatively, in a possible embodiment, the radio frequency generator and matcher 303 may be electrically coupled to the upper electrode and the lower electrode at the same time.
  • the composition and combination of the radio frequency generator and matcher can have various changes and are not limited to the description herein.
  • the tray 300 may further include one or more heating elements.
  • the wafer support base shown in FIG. 3 has a plurality of lower electrodes.
  • the disc body 300 is buried with two lower electrodes, which are the first lower electrode 304 and the second lower electrode 305 respectively.
  • the two are located below the wafer carrying surface 301 and are structurally independent of each other (that is, they are not in contact with each other and do not constitute electrical conduction).
  • the first bottom electrode 304 is located below the wafer carrying surface 301 but above the second bottom electrode 305.
  • the first lower electrode 304 and the second lower electrode 305 have approximately the same diameter and extend to an area equivalent to the wafer carrying surface 301. In other embodiments, the first lower electrode 304 may have a larger or smaller diameter than the second lower electrode 305.
  • the first bottom electrode 304 and the second bottom electrode 305 are arranged concentrically.
  • the first lower electrode 304 and the second lower electrode 305 are mesh electrodes, which can be formed in the disc body 300 by manufacturing means of sintering and pressing.
  • the mesh density of the first lower electrode 304 and the second lower electrode 305 may be the same or different. It should be understood that the first lower electrode 304 and the second lower electrode 305 may also have other structures, and the first lower electrode 304 may have the same or different structure as the second lower electrode 305.
  • the first lower electrode 304 and the second lower electrode 305 are electrically coupled to the first feedback/control device 306 and the second feedback/control device 307, respectively.
  • the first feedback/control device 306 is configured to have an appropriate circuit composition to receive the sensing signal from the first bottom electrode 304 and generate the first feedback signal accordingly.
  • the second feedback/control device 307 is configured to have an appropriate circuit composition to receive the sensing signal from the second bottom electrode 305 and generate a second feedback signal accordingly.
  • the induction signal is related to the radio frequency power received by each lower electrode (304, 305) from the upper electrode 302, so the feedback signal can reflect the characteristics of the plasma in the chamber.
  • the first feedback/control device 306 is in communication with the radio frequency generator and matcher 303 via the first feedback path 308 and thereby provides the first feedback signal to the radio frequency generator and matcher 303.
  • the second feedback/control device 307 is communicatively connected via the second feedback path 309 and provides a second feedback signal to the radio frequency generator and matcher 303.
  • the first feedback/control device 306 and the second feedback/control device 307 are also configured to be able to selectively electrically couple the first lower electrode 304 and the second lower electrode 305 to corresponding ground terminals.
  • the first feedback path 308 and the second feedback path 309 can be respectively electrically connected to the low frequency and high frequency control parts of the radio frequency generator and matcher 303 to realize different processing corresponding to the low frequency and the high frequency.
  • the radio frequency generator and matcher 303 is configured to receive the first feedback signal and/or the second feedback signal, and adjust the plasma based on the feedback signal.
  • the radio frequency generator and matcher 303 may further include a controller for signal processing and output.
  • a radio frequency generator such as a high frequency generator or a low frequency generator
  • the RF matcher such as a high-frequency matcher or a low-frequency matcher
  • the RF generator and matcher 303 can adjust the value of its variable capacitance according to the command of the controller to obtain an appropriate matching impedance.
  • the radio frequency generator and matcher 303 may further include other circuit modules, such as an impedance controller composed of a bandpass filter and/or a notch filter, which may be one or Multiple capacitors, inductors and variable capacitors are connected.
  • the impedance controller may be configured to be included in the feedback/control device (306, 307), the radio frequency generator and matcher 303, the controller, or a circuit independent of these components.
  • One or more impedance controllers may be configured to be electrically coupled to the first lower electrode 304 or the second lower electrode 305 and/or the upper electrode 302. Accordingly, the controller controls the radio frequency generator, the radio frequency matcher and/or the impedance controller based on the first feedback signal or the second feedback signal, thereby achieving the purpose of adjusting the plasma.
  • FIG. 4 shows a schematic diagram of another exemplary semiconductor processing apparatus according to an embodiment of the present application.
  • the difference from the embodiment in FIG. 3 is the configuration of the bottom electrode, and the same components as those in FIG. 3 use the same reference numerals, and will not be repeated here.
  • the example of FIG. 4 includes a first lower electrode 401 and a second lower electrode 402. The two are still structurally independent from each other.
  • the first bottom electrode 401 is located below the wafer carrying surface 301 but above the second bottom electrode 402.
  • the first lower electrode 401 is a circular lower electrode defined by a first radius R 1
  • the second lower electrode 402 is a circular lower electrode defined by a second radius R 2 and a third radius R 3
  • the total area of the two is roughly equivalent to the effective area of the wafer carrying surface 301.
  • the third radius R 3 is greater than the first radius R 1 and the second radius R 2
  • the second radius R 2 may be less than, equal to, or greater than the first radius R 1 .
  • the plasma near the center of the wafer can be adjusted based on at least the first bottom electrode 401
  • the plasma located at the edge of the wafer can be adjusted based on at least the second bottom electrode 402.
  • the positions of the first lower electrode 401 and the second lower electrode 402 may be exchanged.
  • the lower electrode closest to the wafer carrying surface 301 may be configured to have electrostatic adsorption capability.
  • a larger number of lower electrodes is also feasible.
  • the bottom electrodes can also be arranged asymmetrically, which means that multiple bottom electrodes have different shapes and some of the bottom electrodes are non-rotationally symmetric. For example, the bottom electrode has a different sector shape.
  • the semiconductor processing device has a disk body embedded with a plurality of ground electrodes electrically isolated from each other, and each of these ground electrodes is selectively coupled to a corresponding ground terminal via a switch. Therefore, according to the different processes performed by the semiconductor processing device, different combinations of ground electrodes can be selected to be coupled to the ground terminal to form different radio frequency loops, so that the plasma density near different electrode positions can be adjusted, thereby controlling the thickness of the deposited film Or the uniformity of etching.
  • FIG. 5 shows a flowchart of an exemplary method 500 for manufacturing a ground electrode (for example, each ground electrode in the embodiment described in this specification) for a semiconductor processing device according to an embodiment of the present application.
  • a disc body base is provided, for example, formed by pressing aluminum nitride material.
  • a first electrode and a second electrode that are electrically isolated from each other are formed in the disc body base.
  • the first electrode and the second electrode may be respectively formed by means of sintering and pressing.
  • the first electrode and the second electrode may be formed by sintering on the same plane or different planes in the base of the disk body.
  • the first electrode and the second electrode can be molded and pressed into the base of the disk body at one time by a combination of knitting method.
  • FIG. 6 shows a flowchart of an exemplary method 600 of operating a semiconductor processing device (such as the semiconductor processing device shown in FIG. 3 and FIG. 4) according to an embodiment of the present application.
  • the semiconductor processing device includes at least a first ground electrode and a second ground electrode, such as the lower electrodes 304 and 305 shown in FIG. 3 and the lower electrodes 401 and 402 shown in FIG. 4.
  • the first ground electrode is selectively coupled to the first ground terminal through the first switch
  • the second ground electrode is selectively coupled to the second ground terminal through the second switch
  • the first ground electrode is connected to the first ground terminal.
  • the two electrodes are electrically isolated from each other.
  • step 602 for the first processing performed by the semiconductor processing device, the first switch is controlled to couple the first ground electrode to the first ground terminal, that is, the radio frequency loop of the first processing will include at least The first ground electrode.
  • step 604 for the second processing performed by the semiconductor processing device, the second switch is controlled to couple the second ground electrode to the second ground terminal, that is, the radio frequency loop of the second processing will include at least The second ground electrode.
  • the method 600 may further include for the third process, controlling the first switch and the second switch to couple the first ground electrode and the second ground electrode to the first ground terminal and the second ground electrode, respectively.
  • the second ground terminal, that is, the radio frequency loop of the third treatment will at least include both the first ground electrode and the second ground electrode.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Plasma Technology (AREA)
  • Drying Of Semiconductors (AREA)
  • Chemical Vapour Deposition (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

本申请提供一种用于半导体处理装置的盘体，其包含第一电极及第二电极，其中所述第一电极经由第一切换开关选择性地耦接至第一接地端，所述第二电极经由第二切换开关选择性地耦接至第二接地端，所述第一电极与所述第二电极彼此电性隔离。

Description

半导体处理装置及方法 技术领域
本申请大体上涉及半导体处理装置，且更具体来说，涉及具有可调射频回路的半导体处理装置。
背景技术
等离子体处理被使用于如集成电路、光罩、等离子体显示及太阳能科技的制造。在集成电路的制造中，晶圆由等离子体腔体处理，例如蚀刻、等离子体增强型化学气相沉积(PECVD)或物理气相沉积(PEPVD)。针对尺寸更微小的集成电路而言，处理参数的控制需要更精确，像是等离子体能量频谱、等离子体能量径向分布、等离子体密度及等离子体密度径向分布。尤其是等离子体密度，其决定了晶圆表面的沉积率和蚀刻率。而等离子体密度径向分布和等离子体能量径向分布更影响沉积和蚀刻的均匀性。已知的半导体处理装置提供有一上电极和一下电极，其可在两者之间产生等离子体。然而，已知的配置仍不容易达到这些精确的控制，甚至限制了等离子体调整的自由度。
因此，有必要发展一种半导体处理装置或者射频组件，可提供不同的射频控制策略，以满足工艺设计的自由度。
发明内容
在一个方面中，本申请提供一种用于半导体处理装置的盘体，其包含第一电极及第二电极，其中所述第一电极经由第一切换开关选择性地耦接至第一接地端，所述第二电极经由第二切换开关选择性地耦接至第二接地端，所述第一电极与所述第二电极彼此电性隔离。
在一些实施例中，所述盘体进一步包含用于承载晶圆的承载面，其中所述第一电极和所述第二电极位于所述承载面下方。
在一些实施例中，所述第一电极由第一半径定义，所述第二电极由第二半径和第三半径定义，所述第三半径大于所述第一半径和所述第二半径。所述第一电极与所述第二电极位于同一平面或不同平面。
在一些实施例中，所述第一电极由第一半径定义，所述第二下电极由第二半径定义，所述第一电极与所述第二电极位于不同平面。根据本申请的一个实施例，所述第一半径和所述第二半径大致相等。
在一些实施例中，所述第一电极和所述第二电极同心排列。在另一些实施例中，所述第一电极和所述第二电极中的至少一者为圆形或环形电极中的区块，所述圆形或环形电极包含多个区块。
在一些实施例中，所述第一电极和所述第二电极中的至少一者包括网状结构。
在另一方面中，本申请提供一种半导体处理装置，其包含根据本申请的实施例的盘体。所述半导体处理装置还包含第二盘体，其包含第三电极，所述第三电极电性耦接至射频产生和匹配器。
在一些实施例中，所述半导体处理装置还包含：第一反馈组件，其经配置以基于从所述第一电极接收的信号向所述射频产生和匹配器提供第一反馈信号；及第二反馈组件，其经配置以基于从所述第二电极接收的信号向所述射频产生和匹配器提供第二反馈信号。
在另一方面中，本申请提供一种制造用于半导体处理装置的接地电极的方法，其包含：提供盘体基体；及通过以下方式在所述盘体基体中形成彼此电性隔离的第一电极和第二电极：(1)将所述第一电极和所述第二电极分别烧结在所述盘体基体中；或(2)通过编织组合的方法将所述第一电极和所述第二电极一次成型压制在所述盘体基体中。
在一些实施例中，将所述第一电极和所述第二电极分别烧结在所述盘体基体中包括将所述第一电极和所述第二电极烧结形成在所述盘体基体中的同一平面处。在另一些实施例中，将所述第一电极和所述第二电极分别烧结在所述盘体基体中包括将所述第一电极和所述第二电极烧结形成在所述盘体基体中的不同平面处。
在又一方面中，本申请提供一种操作根据本申请的实施例的半导体处理装置的方法，其包含：针对第一处理，控制所述第一切换开关将所述第一电极耦接至所述第一接地端；及针对第二处理，控制所述第二切换开关将所述第二电极耦接至所述第二接地端。在一些实施例中，所述方法还包含：针对第三处理，控制所述第一切换开关和所述第二切换开关将所述第一电极和所述第二电极分别耦接至所述第一接地端和所述第二接地端。
在以下附图及描述中阐述本申请的一或多个实例的细节。其他特征、目标及优势将根据所述描述及附图以及权利要求书而显而易见。
附图说明
本说明书中的公开内容提及且包含以下各图：
图1显示根据本申请的实施例的示例性射频组件的方块示意图。
图1A显示根据本申请的实施例的示例性反馈/控制装置的结构示意图。
图2显示根据本申请的实施例的示例性接地电极配置的示意图。
图2A显示根据本申请的实施例的示例性圆形电极的示意图。
图2B显示根据本申请的实施例的示例性环形电极的示意图。
图3显示根据本申请的实施例的示例性半导体处理装置的示意图。
图4显示根据本申请的实施例的另一示例性半导体处理装置的示意图。
图5显示根据本申请的实施例的制造用于半导体处理装置的接地电极的示例性方法的流程图。
图6显示根据本申请的实施例的操作半导体处理装置的示例性方法的流程图。
根据惯例，图示仅用于说明非限制性与非穷举性实例。图式中的构件并非必须为实际尺寸，图示中所说明的各种特征也可能并非按比例绘制。因此，为了清晰起见，可任意扩大或减小各种特征的尺寸。另外，为了清楚起见，可简化图示中所说明的实施方案。因此，图示可能并未说明给定设备或装置的全部组件。最后，可贯穿说明书和图示使用相同参考标号来表示相同特征。
具体实施方式
以下将参考图式更完整说明本发明，并且藉由例示显示特定范例具体实施例。不过，本主张主题可具体实施于许多不同形式，因此所涵盖或申请主张主题的建构并不受限于本说明书所揭示的任何范例具体实施例；范例具体实施例仅为例示。同样，本发明在于提供合理宽阔的范畴给所申请或涵盖之主张主题。除此之外，例如主张主题可具体实施为方法、装置或系统。因此，具体实施例可采用例如硬件、软件、固件或这些的任意组合(已知并非软件)的形式。
本说明书内使用的词汇“在一实施例”或“根据一实施例”并不必要参照相同具体实施例，也不意味着请求保护的技术方案必须包含实施例所描述的所有特征，且本说明书内使用的“在其他(一些/某些)实施例”或“根据其他(一些/某些)实施例”并不必要参照不同的具体实施例。其目的在于例如主张的主题包括全部或部分范例具体实施例的组合。
本说明书中的术语“包括”和“包含”是以开放式的方式使用的，因此应被解释为意指“包 括，但不限于……”。本说明书所称的“耦接”应理解为涵盖“直接连接”以及“经由一或多个中间部件连接”。本说明书所指“上”和“下”的意义并不限于图式所直接呈现的关系，其应包含具有明确对应关系的描述，例如“左”和“右”，或者是“上”和“下”的相反。本说明书中的词汇“晶圆”应理解为可与术语“晶元”、“晶片”、“基片”、“基板”、“硅片”、“衬底”等术语互换使用。本说明书使用某些术语来指称特定的系统部件，正如本领域技术人员将会理解的，不同的企业可能会用不同的名称来指称这些系统部件。
图1显示根据本申请的一些实施例的射频组件100的示意图。射频组件100包含位于半导体处理装置的一腔体(如处理腔体，图中未示出)中的第一电极101和多个第二电极102、103以及射频产生和匹配器104。尽管图1中示出了一个第一电极和两个第二电极，本领域技术人员将会理解射频组件100可包括更多数量的第一电极和/或更多数量的第二电极。图1仅用于示例性说明，并非限制各组件的实际大小、形状和相对位置。
在图1的示例中，射频产生和匹配器104电性耦接(例如以同轴电缆连接)至第一电极101，以提供射频信号。第二电极102、103则分别经由反馈/控制装置105、106电性耦接至射频产生和匹配器104。所述反馈/控制装置105、106配置成分别从第二电极102、103接收一或多个感应信号并据此产生相应的多个反馈信号，以及提供所述反馈信号至射频产生和匹配器104。反馈/控制装置105、106还可配置成作为切换开关，用于选择性地使第二电极102、103电性耦接至相应的接地端或与相应的接地端断开连接。第二电极102、103耦接的接地端可为相同的接地点或不同的接地点。在本申请中，第一电极101也可称为“射频电极”，第二电极102、103也可称为“接地电极”。
在一些实施例中，第一电极101可为上电极，第二电极102、103可为下电极。在另一些实施例中，第一电极101可为下电极，第二电极102、103可为上电极。一般而言，上电极是配置在腔体的顶部。虽然图1没有显示腔体的结构，但典型的腔体具有一腔室，其由一顶部、一底部及一壁部所定义。顶部通常具有复杂的进气歧管、气体分配器、气体通道及喷淋头。在典型的配置中，上电极包含在喷淋头的结构中。腔体的顶部或喷淋头电性耦接至射频产生和匹配器104使上电极接收来自射频源的信号。
下电极配置在晶圆支撑座中。尽管图1未显示，但典型的晶圆支撑座与所述腔体的底部连接，使晶圆可被支撑在腔室中的一高度。一等离子体区域可被形成在上电极与包含下电极的晶圆支撑座之间。晶圆支撑座可包含用于承载晶圆的承载面，其中下电极位于所述承载面下方。
虽然未显示，射频产生和匹配器104可包含射频产生器和射频匹配器。在一实施例中，射 频产生和匹配器104中的射频产生器可包含一低频射频源、一高频射频源或两者的组合，而射频产生和匹配器104中的射频匹配器可包含低频专用的匹配网络、高频专用的匹配网络或两者的组合。所述匹配网络包含一或多个电容器、电感器及一些电子组件，其详细组成不在此赘述。依据不同处理，选择低频或高频射频操作为已知的，亦不在此赘述。射频产生和匹配器104配置成接收来自反馈/控制装置105、106提供的一或多个反馈信号并据此调整所述低频或高频射频源的输出频率及/或所述匹配网络中的一或多个可变电子组件，如可变电容器，或是射频电路组件中的其他可变组件，以控制腔室中等离子体的特性。在一些实施例中，射频产生和匹配器104可配置成接收来自第一电极101的一或多个反馈信号。在另一些实施例中，反馈/控制装置105、106中的一者或多者不向射频产生和匹配器104提供反馈信号。
此外，根据不同目的，本申请中的反馈/控制装置可用于决定与第二电极关联的各种操作，如决定第二电极是否接地、是否调整相关的可变电子组件或施加于第二电极的功率等。
图1A显示根据本申请的实施例的示例性反馈/控制装置115的结构示意图。反馈/控制装置115可为图1中的反馈/控制装置105或106的实例。反馈/控制装置115可包含反馈组件116和切换开关118。反馈组件116基于从接地电极112(例如图1所示的第二电极102或103)接收的信号产生反馈信号，并将所述反馈信号提供给射频产生和匹配器114(例如图1所示的射频产生和匹配器104)。在一些实施例中，反馈组件116将从接地电极112接收的信号直接提供给射频产生和匹配器114。在一些实施例中，反馈/控制装置115并不包含反馈组件116，即，反馈/控制装置115不向射频产生和匹配器114提供反馈信号。
切换开关118在控制信号S C的控制下，选择性地将接地电极112耦接至接地端或与接地端断开连接。控制信号S C可至少部分基于从接地电极112接收的信号，或者至少部分基于从其他接地电极或射频电极接收的信号，或者至少部分基于正在进行或将要进行的处理的工艺要求。控制信号S C可通过硬件或软件方式生成。基于某些信号或参数来生成一控制信号的方法已为本领域技术人员所熟知，故不在此赘述。在一些实施例中，接地电极112与接地端之间可包含由一或多个电阻器、一或多个电容器、一或多个电感器等元件组成的阻抗网络，所述阻抗网络可在射频回路中提供固定阻抗或可变阻抗(例如，通过可变电容器等)。
图2显示根据本申请的实施例的示例性接地电极配置的示意图(省略反馈/控制装置)。此示意图显示接地电极的俯视图。尽管图2中示出了特定数量的电极，本领域技术人员将会理解本申请的接地电极配置可包括更少或更多数量的电极。
本实施例所示接地电极配置具有第一电极201、第二电极202及第三电极203。在一些实施 例中，第一电极201、第二电极202及第三电极203同心排列。第一电极201为圆形电极，由第一半径R 1定义。第二电极202至少由第二半径R 2定义。第三电极203至少由第三半径R 3定义。其中第二半径R 2大于第一半径R 1但小于第三半径R 3。在一实施例中，第二电极202为圆形电极；在另一实施例中，第二电极202可以是由第一内径和第二半径R 2定义的环形电极，所述第一内径可以大于、等于或小于第一半径R 1。在一实施例中，第三电极203为圆形电极；在另一实施例中，第三电极203可以是由第二内径和第三半径R 3定义的另一环形电极，所述第二内径可以大于、等于或小于第二半径R 2。
在一些实施例中，第一电极201、第二电极202和第三电极203可位于相同的水平高度(即位于同一平面)。在此些实施例中，第二电极202和第二电极203为环形电极，且第二电极202的内径大于或等于第一半径R 1，第三电极203的内径大于或等于第二半径R 2。在另一些实施例中，第一电极201、第二电极202和第三电极203可分别在不同的水平高度(即位于不同平面)，相关举例如后。第一电极201、第二电极202和第三电极203彼此电性隔离(例如，通过各电极间的绝缘材料，或者各电极在空间上彼此间隔开)。如图所示，第一电极201、第二电极202和第三电极203中的每一者分别可选择性地(省略反馈/控制装置)与一接地端连接。
在图2的示例中，接地电极可为圆形电极或环形电极。在其他实施例中，接地电极可为圆形或环形电极中的区块。图2A和2B分别显示根据本申请的实施例的包含多个区块的示例性圆形电极210和环形电极220的示意图。尽管图2A和2B中示出了以特定方式划分的特定数量的区块，本领域技术人员将会理解圆形电极210和环形电极220可包含以其他方式划分的更少或更多数量的区块。
圆形电极210包含区块212、214、216和218。环形电极220包含区块222、224、226和228。在一些实施例中，区块212、214、216和218通过绝缘材料彼此电性隔离，因而可以分别独立接地。类似地，在一些实施例中，区块222、224、226和228通过绝缘材料彼此电性隔离，因而可以分别独立接地。举例来说，图1所示的第二电极202可为区块212，第三电极203可为区块214或者另一圆形或环形电极或者另一圆形或环形电极中的区块。
图3显示根据本申请的实施例的示例性半导体处理装置的示意图。在图3的示例中，接地电极是下电极，配置在晶圆支撑座中。尽管未显示处理腔体，但应了解所述晶圆支撑座是安装于处理腔体中。此处晶圆支撑座包含盘体300，其具有晶圆承载面301用于承载经历各种处理的晶圆。上电极302位于腔体的顶部。在一实施例中，上电极302被包含在位于腔体顶部的喷淋头。例如，上电极302可以是喷淋头的盖子或者壳体。上电极302电性耦接至射频产生和匹配器303 以接收射频源，其电路组成如同前述图1所示的射频产生和匹配器104，故不重复说明。射频产生和匹配器303可配置于腔体的顶部或者腔体的外部。可替代地，所述射频产生和匹配器303电性耦接至一或多个下电极。或者，在可能实施例中，射频产生和匹配器303可同时电性耦接至上电极和下电极。所述射频产生和匹配器的组成和组合可以有多种变化，并不限于本文的描述。在一些实施例中，盘体300还可包含一或多个加热元件。
图3所示的晶圆支撑座具有多个下电极。在本实施例中，盘体300埋设有两个下电极，分别是第一下电极304和第二下电极305。两者位于晶圆承载面301的下方且彼此结构独立(即，彼此不接触也不构成电性导通)。第一下电极304位于晶圆承载面301下方，但位于第二下电极305上方。第一下电极304和第二下电极305具有大致相同的直径，并扩展至与晶圆承载面301相当的面积。在其他实施例中，第一下电极304可具有比第二下电极305更大或更小的直径。第一下电极304与第二下电极305为同心排列。此处第一下电极304和第二下电极305为网状电极，其可经由烧结(sintering)和加压的制造手段成型于盘体300中。第一下电极304和第二下电极305的网格密度可相同或不同。应了解，第一下电极304和第二下电极305也可具有其他结构，第一下电极304可具有与第二下电极305相同或不同的结构。
第一下电极304和第二下电极305分别电性耦接至第一反馈/控制装置306和第二反馈/控制装置307。第一反馈/控制装置306配置成具有适当的电路组成以接收来自第一下电极304的感应信号并据此产生第一反馈信号。相似地，第二反馈/控制装置307配置成具有适当的电路组成以接收来自第二下电极305的感应信号并据此产生第二反馈信号。所述感应信号与各下电极(304、305)自上电极302所接收到的射频功率有关，故所述反馈信号可反应出腔室中等离子体的特性。第一反馈/控制装置306经由第一反馈路径308与射频产生和匹配器303通讯连接并藉此提供第一反馈信号至射频产生和匹配器303。相似地，第二反馈/控制装置307经由第二反馈路径309通讯连接并提供第二反馈信号至射频产生和匹配器303。此外，第一反馈/控制装置306和第二反馈/控制装置307还配置成能够选择性地将第一下电极304和第二下电极305电性耦接至相应的接地端。此外，虽然未显示，第一反馈路径308和第二反馈路径309可分别电性连接于射频产生和匹配器303中的低频和高频控制部分，以实现低频和高频所对应的不同处理。
射频产生和匹配器303被配置成用于接收第一反馈信号及/或第二反馈信号，并基于所述反馈信号调整等离子体。所述射频产生和匹配器303可进一步包括控制器，其用于信号的处理和输出。在可能的实施例中，射频产生和匹配器303中的射频产生器(如高频产生器或低频产生器)可根据控制器的指令调整其射频输出频率。可替代地，射频产生和匹配器303中的射频匹 配器(如高频匹配器或低频匹配器)可根据控制器的指令调整其可变电容的值，以获得一适当的匹配阻抗。
在一些可能的实施例中，射频产生和匹配器303可进一步包含其他的电路模块，例如带通(bandpass)滤波器及/或带阻(notch)滤波器组成的阻抗控制器，其可由一或多个电容器、电感器和可变电容器连接而成。所述阻抗控制器可配置成被包含在所述反馈/控制装置(306、307)、所述射频产生和匹配器303、所述控制器或独立于这些组件的电路中。一或多个阻抗控制器可配置成电性耦接至所述第一下电极304或第二下电极305及/或上电极302。据此，所述控制器基于第一反馈信号或第二反馈信号控制所述射频产生器、射频匹配器及/或所述阻抗控制器，进而达到调整等离子体的目的。
本申请提供的接地电极可具有不同的尺寸、形状、材质、埋入深度或网状密度。图4显示根据本申请的实施例的另一示例性半导体处理装置的示意图。与图3实施例不同的是下电极的配置，与图3相同的组件采用了相同的附图标记，不在此赘述。图4的示例包含第一下电极401和第二下电极402。两者仍是彼此结构独立，其中第一下电极401位于晶圆承载面301的下方但位于第二下电极402的上方。虽然仅显示剖面图，但第一下电极401为由第一半径R 1定义的圆形下电极，第二下电极402为由第二半径R 2和第三半径R 3定义的环形下电极，两者的面积总和大致上相当于晶圆承载面301的有效区域。其中，第三半径R 3大于第一半径R 1和第二半径R 2，第二半径R 2可小于、等于或大于第一半径R 1。根据图4的配置，靠近晶圆中心的等离子体可至少基于第一下电极401调整，而位于晶圆边缘的等离子体可至少基于第二下电极402调整。在其他可能的实施例中，第一下电极401和第二下电极402的位置可被交换。在其他可能的实施例中，最靠近晶圆承载面301的下电极可被配置成具有静电吸附的能力。更多数量的下电极也是可行的。下电极亦可为非对称的安排，意即多个下电极为不同形状且部分下电极为非旋转对称。例如下电极是不同的扇形。
综上所述，本申请提供的半导体处理装置具有埋设了多个彼此电性隔离的接地电极的盘体，且这些接地电极中的每一个经由切换开关选择性地耦接至相应的接地端。因此，依据半导体处理装置所执行的不同处理，可选择不同的接地电极的组合耦接至接地端，构成不同的射频回路，从而可以调节不同电极位置附近的等离子体密度，进而控制沉积的薄膜厚度或刻蚀的均匀性。
图5显示根据本申请的实施例的制造用于半导体处理装置的接地电极(例如，本说明书所描述的实施例中的各接地电极)的示例性方法500的流程图。如图5所示，在步骤502中，提 供盘体基体，例如，通过压制氮化铝材料形成。在步骤504中，在盘体基体中形成彼此电性隔离的第一电极和第二电极。在一些实施例中，第一电极和第二电极可分别通过烧结压制的手段形成。所述第一电极和所述第二电极可烧结形成在所述盘体基体中的同一平面或不同平面处。在另一些实施例中，可通过编织组合的方法将第一电极和第二电极一次成型压制在盘体基体中。
图6显示根据本申请的实施例的操作半导体处理装置(例如图3和图4所示的半导体处理装置)的示例性方法600的流程图。根据本申请的实施例，半导体处理装置至少包含第一接地电极和第二接地电极，例如图3所示的下电极304和305、图4所示的下电极401和402。第一接地电极经由第一切换开关选择性地耦接至第一接地端，第二接地电极经由第二切换开关选择性地耦接至第二接地端，所述第一接地电极与所述第二电极彼此电性隔离。
在步骤602中，针对半导体处理装置所执行的第一处理，控制所述第一切换开关将所述第一接地电极耦接至所述第一接地端，即第一处理的射频回路将至少包含所述第一接地电极。在步骤604中，针对半导体处理装置所执行的第二处理，控制所述第二切换开关将所述第二接地电极耦接至所述第二接地端，即第二处理的射频回路将至少包含所述第二接地电极。方法600还可包含针对第三处理，控制所述第一切换开关和所述第二切换开关将所述第一接地电极和所述第二接地电极分别耦接至所述第一接地端和所述第二接地端，即第三处理的射频回路将至少包含所述第一接地电极和所述第二接地电极两者。
本说明书中的描述经提供以使所述领域的技术人员能够进行或使用本发明。所属领域的技术人员将易于显而易见对本发明的各种修改，且本说明书中所定义的一般原理可应用于其它变化形式而不会脱离本发明的精神或范围。因此，本发明不限于本说明书所述的实例和设计，而是被赋予与本说明书所揭示的原理和新颖特征一致的最宽范围。

Claims (17)

  1. 一种用于半导体处理装置的盘体，其包含：
    第一电极；及
    第二电极；
    其中所述第一电极经由第一切换开关选择性地耦接至第一接地端，所述第二电极经由第二切换开关选择性地耦接至第二接地端，所述第一电极与所述第二电极彼此电性隔离。
  2. 根据权利要求1所述的盘体，其进一步包含用于承载晶圆的承载面，其中所述第一电极和所述第二电极位于所述承载面下方。
  3. 根据权利要求1所述的盘体，其中所述第一电极由第一半径定义，所述第二电极由第二半径和第三半径定义，所述第三半径大于所述第一半径和所述第二半径。
  4. 根据权利要求3所述的盘体，所述第一电极与所述第二电极位于同一平面。
  5. 根据权利要求3所述的盘体，所述第一电极与所述第二电极位于不同平面。
  6. 根据权利要求1所述的盘体，其中所述第一电极由第一半径定义，所述第二下电极由第二半径定义，所述第一电极与所述第二电极位于不同平面。
  7. 根据权利要求6所述的盘体，其中所述第一半径和所述第二半径大致相等。
  8. 根据权利要求1所述的盘体，其中所述第一电极和所述第二电极同心排列。
  9. 根据权利要求1所述的盘体，其中所述第一电极和所述第二电极中的至少一者为圆形或环形电极中的区块，所述圆形或环形电极包含多个区块。
  10. 根据权利要求1所述的盘体，其中所述第一电极和所述第二电极中的至少一者包括网 状结构。
  11. 一种半导体处理装置，其包含：
    根据权利要求1-10中任一权利要求所述的盘体；及
    第二盘体，其包含第三电极，所述第三电极电性耦接至射频产生和匹配器。
  12. 根据权利要求11所述的半导体处理装置，其进一步包含：
    第一反馈组件，其经配置以基于从所述第一电极接收的信号向所述射频产生和匹配器提供第一反馈信号；及
    第二反馈组件，其经配置以基于从所述第二电极接收的信号向所述射频产生和匹配器提供第二反馈信号。
  13. 一种制造用于半导体处理装置的接地电极的方法，其包含：
    提供盘体基体；及
    通过以下方式在所述盘体基体中形成彼此电性隔离的第一电极和第二电极：
    将所述第一电极和所述第二电极分别烧结在所述盘体基体中；或
    通过编织组合的方法将所述第一电极和所述第二电极一次成型压制在所述盘体基体中。
  14. 根据权利要求13所述方法，其中将所述第一电极和所述第二电极分别烧结在所述盘体基体中包括将所述第一电极和所述第二电极烧结形成在所述盘体基体中的同一平面处。
  15. 根据权利要求13所述方法，其中将所述第一电极和所述第二电极分别烧结在所述盘体基体中包括将所述第一电极和所述第二电极烧结形成在所述盘体基体中的不同平面处。
  16. 一种操作根据权利要求11所述的半导体处理装置的方法，其包含：
    针对第一处理，控制所述第一切换开关将所述第一电极耦接至所述第一接地端；及
    针对第二处理，控制所述第二切换开关将所述第二电极耦接至所述第二接地端。
  17. 根据权利要求16所述的方法，其进一步包含：
    针对第三处理，控制所述第一切换开关和所述第二切换开关将所述第一电极和所述第二电极分别耦接至所述第一接地端和所述第二接地端。
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