WO2021012738A1 - 同步信号块的发送、时隙位置确定方法及装置、存储介质、基站、终端 - Google Patents
同步信号块的发送、时隙位置确定方法及装置、存储介质、基站、终端 Download PDFInfo
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- WO2021012738A1 WO2021012738A1 PCT/CN2020/087110 CN2020087110W WO2021012738A1 WO 2021012738 A1 WO2021012738 A1 WO 2021012738A1 CN 2020087110 W CN2020087110 W CN 2020087110W WO 2021012738 A1 WO2021012738 A1 WO 2021012738A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W72/00—Local resource management
- H04W72/04—Wireless resource allocation
- H04W72/044—Wireless resource allocation based on the type of the allocated resource
- H04W72/0446—Resources in time domain, e.g. slots or frames
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2602—Signal structure
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
- H04L27/2657—Carrier synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
- H04W56/001—Synchronization between nodes
Definitions
- the present invention relates to the field of communication technology, in particular to a method and device, storage medium, base station, and terminal for the transmission of synchronization signal blocks and time slot position determination.
- each radio frame is divided into 10 sub-frames of the same size with a length of 1 ms.
- each sub-frame may include multiple time slots.
- each time slot is composed of a certain number of symbols, and the number of symbols is determined by the type of cyclic prefix (Cyclic Prefix, CP for short).
- the NR system supports multi-beam synchronization signal block (Synchronization Signal/Physical Broadcast Channel Block, referred to as SS/PBCH Block, that is, SSB) transmission, where the synchronization signal block includes the primary synchronization signal (Primary Synchronization Signal, referred to as PSS) sequence, Secondary Synchronization Signal (SSS) sequence, Physical Broadcast Channel (PBCH) and its demodulation reference signal (Demodulation Reference Signal, DMRS).
- PSS Primary Synchronization Signal
- SSS Secondary Synchronization Signal
- PBCH Physical Broadcast Channel
- DMRS Demodulation Reference Signal
- the synchronization signal block when the synchronization signal block is mapped to the time slot, it is usually continuous in the time domain.
- the NR system supports flexible uplink (Uplink, UL) time slot and downlink (Downlink, DL) time slot configuration, It is impossible to guarantee that multiple consecutive time slots can be used to transmit synchronization signal blocks, which results in that the existing synchronization signal block transmission method cannot be well adapted to the flexible time slot configuration of the NR system.
- the technical problem solved by the present invention is how to provide a new synchronization signal block mapping pattern to meet the flexible uplink and downlink timeslot configuration in the NR system and facilitate the transmission of the synchronization signal block set.
- an embodiment of the present invention provides a method for sending synchronization signal blocks, including: acquiring a synchronization signal block set to be sent, the synchronization signal block set includes n synchronization signal blocks, and n is a positive integer;
- the i-th synchronization signal block in the synchronization signal block set maps multiple signals or channels included in the i-th synchronization signal block to the same time slot of different frames in the transmission window, and the synchronization signal
- the same signal or channel of different synchronization signal blocks in the block set is located in different time slots of the same frame, where 1 ⁇ i ⁇ n, and the multiple signals or channels are selected from PSS sequence, SSS sequence, PBCH and DMRS;
- the synchronization signal block set is sent according to the mapping pattern obtained by the mapping.
- the same signal or channel of different synchronization signal blocks in the synchronization signal block set in different time slots of the same frame refers to: the PSS sequence of the i-th synchronization signal block and the i+k-th synchronization signal block
- the PSS sequence is located in the i-th time slot and the i+k-th time slot of the same frame;
- the SSS sequence of the i-th synchronization signal block and the SSS sequence of the i+k-th synchronization signal block are respectively located in the same frame
- the multiple signals or channels included in the i-th synchronization signal block are, in chronological order: PSS sequence, PBCH and its DMRS, PBCH and its DMRS, SSS sequence, PBCH and its DMRS, PBCH and its DMRS.
- the value of the preset threshold y is used to ensure that there are no idle frames between frames mapped with adjacent signals or channels.
- the value of the preset threshold y is used to make the frame to which the SSS sequence is mapped is the x/2+1th frame.
- the signals or channels included in the i-th synchronization signal block are: PSS sequence, SSS sequence, PBCH and its DMRS, PBCH and DMRS, PBCH and DMRS, and PBCH and DMRS in chronological order.
- the number of frames included in the transmission window is not less than the number of multiple signals or channels included in the i-th synchronization signal block.
- the number of synchronization signal blocks included in the synchronization signal block set is determined according to the subcarrier spacing and the number of beams.
- an embodiment of the present invention also provides a method for determining the slot position of a synchronization signal block, including: receiving a synchronization signal block set within a transmission window, the synchronization signal block set including n synchronization signal blocks, n Is a positive integer, the synchronization signal block set is sent according to the above method; the first index of the currently received synchronization signal block among the n synchronization signal blocks is determined; according to the first index and the synchronization signal block set The mapping pattern in the transmission window determines the slot position of the currently received synchronization signal block.
- the determining the first index of the currently received synchronization signal block in the n synchronization signal blocks includes: determining the first index according to the received PBCH and its DMRS, and/or the load of the MIB .
- an embodiment of the present invention also provides a synchronization signal block sending device, including: an acquisition module, configured to acquire a synchronization signal block set to be sent, the synchronization signal block set includes n synchronization signal blocks, n is a positive integer; the mapping module, for the i-th synchronization signal block in the synchronization signal block set, maps multiple signals or channels included in the i-th synchronization signal block to the same frame in different frames in the transmission window.
- Time slots, and the same signal or channel of different synchronization signal blocks in the synchronization signal block set is located in different time slots of the same frame, where 1 ⁇ i ⁇ n, and the multiple signals or channels are selected from PSS sequence, SSS Sequence, PBCH and its DMRS; a sending module, used to send the synchronization signal block set according to the mapping pattern obtained by mapping within the transmission window.
- an embodiment of the present invention also provides a device for determining the position of a synchronization signal block in a time slot, including: a receiving module for receiving a synchronization signal block set within a transmission window, the synchronization signal block set including n Synchronization signal block, n is a positive integer, and the set of synchronization signal blocks is sent by the above-mentioned sending device; the first determining module is used to determine the first index of the currently received synchronization signal block among the n synchronization signal blocks; The second determining module is configured to determine the slot position of the currently received synchronization signal block according to the first index and the mapping pattern of the synchronization signal block set in the transmission window.
- an embodiment of the present invention also provides a storage medium on which computer instructions are stored, and the computer instructions execute the steps of the above method when the computer instructions are executed.
- an embodiment of the present invention also provides a base station, including a memory and a processor, the memory stores computer instructions that can run on the processor, and when the processor runs the computer instructions Perform the steps of the above method.
- an embodiment of the present invention also provides a terminal, including a memory and a processor, the memory stores computer instructions that can run on the processor, and when the processor runs the computer instructions Perform the steps of the above method.
- an embodiment of the present invention provides a method for sending synchronization signal blocks, including: acquiring a synchronization signal block set to be transmitted, the synchronization signal block set includes n synchronization signal blocks, and n is a positive integer;
- the i-th synchronization signal block in the synchronization signal block set maps multiple signals or channels included in the i-th synchronization signal block to the same time slot of different frames in the transmission window, and the synchronization signal block set
- the same signal or channel of different synchronization signal blocks is located in different time slots of the same frame, where 1 ⁇ i ⁇ n, and the multiple signals or channels are selected from PSS sequence, SSS sequence, PBCH and DMRS;
- the synchronization signal block set is sent according to the mapping pattern obtained by the mapping.
- a synchronization signal block set suitable for narrowband transmission can be provided to support synchronization signal blocks for multi-beam transmission. Further, by mapping the PSS sequence, SSS sequence, PBCH and DMRS in the same synchronization signal block to the same time slot in different frames, the resulting mapped image can better meet the flexible uplink and downlink time slots in the NR system Configuration to facilitate the transmission of the synchronization signal block set. Specifically, for any kind of uplink and downlink configuration, the base station can easily find the corresponding time-domain transmission position and send the PSS sequence, SSS sequence, PBCH and its DMRS in the synchronization signal block in time and successfully. For example, even if the DL time slot currently configured for the UE in the NR system is not continuous, the solution of this embodiment can still complete the transmission of the synchronization signal block set in time.
- an embodiment of the present invention provides a method for determining the slot position of a synchronization signal block, which includes: receiving a synchronization signal block set within a transmission window, the synchronization signal block set includes n synchronization signal blocks, and n is a positive integer , The synchronization signal block set is sent according to the above method; the first index of the currently received synchronization signal block in the n synchronization signal blocks is determined; according to the first index and the synchronization signal block set in the The mapping pattern in the transmission window determines the slot position of the currently received synchronization signal block.
- the UE can determine the slot position according to the first index of the currently received synchronization signal block in the synchronization signal block set, thereby completing the completion according to the received synchronization signal block Timing for subsequent synchronization operations.
- Fig. 1 is a schematic diagram of a synchronization signal block in the prior art
- Fig. 2 is a schematic diagram of time-domain mapping of synchronization signal blocks at different subcarrier intervals in the prior art
- FIG. 3 is a schematic diagram of the position of a synchronization signal block in a single time slot in the prior art
- FIG. 4 is a flowchart of a method for sending a synchronization signal block according to an embodiment of the present invention
- FIG. 5 is a schematic diagram of a first mapping pattern of a synchronization signal block according to an embodiment of the present invention.
- FIG. 6 is a schematic diagram of a second mapping pattern of synchronization signal blocks according to an embodiment of the present invention.
- FIG. 7 is a schematic diagram of a third mapping pattern of a synchronization signal block according to an embodiment of the present invention.
- FIG. 8 is a schematic diagram of a fourth mapping pattern of synchronization signal blocks according to an embodiment of the present invention.
- FIG. 9 is a schematic diagram of a fifth mapping pattern of a synchronization signal block according to an embodiment of the present invention.
- FIG. 10 is a schematic diagram of a sixth mapping pattern of synchronization signal blocks according to an embodiment of the present invention.
- FIG. 11 is a schematic structural diagram of a device for sending a synchronization signal block according to an embodiment of the present invention.
- FIG. 12 is a flowchart of a method for determining the slot position of a synchronization signal block according to an embodiment of the present invention
- FIG. 13 is a schematic structural diagram of an apparatus for determining the position of a time slot of a synchronization signal block according to an embodiment of the present invention.
- the existing synchronization signal block transmission method cannot well adapt to the flexible time slot configuration of the NR system.
- the existing synchronization signal block is composed of 4 orthogonal frequency division multiplexing (Orthogonal Frequency Division Multiplexing, OFDM for short) symbols.
- OFDM Orthogonal Frequency Division Multiplexing
- the PBCH and its DMRS 13 can occupy multiple slots, and the PSS sequence 11 and the SSS sequence 12 each occupy one slot.
- PSS sequence 11 can occupy 12 physical resource blocks (PRBs)
- SSS sequence 12 can occupy 12 PRBs
- the position of the synchronization signal block within 5 ms is related to the subcarrier spacing (Subcarrier Spacing, SCS for short) and the number of beams L.
- the position of the time slot in which the synchronization signal block can be sent in the 5ms period is shown in the cross-stripe filled area in the figure.
- the slot length is equal to the subframe length.
- the synchronization signal block can be continuously mapped to the first 4 time slots in a period of 5 ms.
- the length of the time slot is equal to 1/2 subframe length.
- the synchronization signal block can be continuously mapped to the first 4 time slots in a period of 5 ms.
- the position of the synchronization signal block in each time slot can have 5 situations, as shown in FIG. 3. Specifically, according to different SCS, the length of the time slot is different, and the number and position of the synchronization signal block that can be sent are also different.
- the area filled with grid lines in FIG. 3 indicates the location of the synchronization signal block.
- multiple synchronization signal blocks may form a synchronization signal block set
- the maximum number of synchronization signal blocks that can be sent in the synchronization signal block set is denoted as Lmax
- the actual number of synchronization signal blocks L may be less than Lmax.
- Case D (Case D), corresponding to the subcarrier spacing of 120kHz: the first time domain symbol of the candidate synchronization signal block is located at ⁇ 4,8,16,20 ⁇ +28*n.
- n 0,1,2,3,5,6,7,8,10,11,12,13,15,16,17,18.
- Case E corresponding to the subcarrier spacing of 240kHz: the first time domain symbol of the candidate synchronization signal block is located at ⁇ 8,12,16,20,32,36,40,44 ⁇ +56*n.
- n 0,1,2,3,5,6,7,8.
- an embodiment of the present invention provides a method for sending synchronization signal blocks, including: acquiring a synchronization signal block set to be sent, the synchronization signal block set includes n synchronization signal blocks, and n is a positive integer;
- the i-th synchronization signal block in the synchronization signal block set maps multiple signals or channels included in the i-th synchronization signal block to the same time slot of different frames in the transmission window, and the synchronization signal
- the same signal or channel of different synchronization signal blocks in the block set is located in different time slots of the same frame, where 1 ⁇ i ⁇ n, and the multiple signals or channels are selected from PSS sequence, SSS sequence, PBCH and DMRS;
- the synchronization signal block set is sent according to the mapping pattern obtained by the mapping.
- a synchronization signal block set suitable for narrowband transmission can be provided to support synchronization signal blocks for multi-beam transmission. Further, by mapping the PSS sequence, SSS sequence, PBCH and DMRS in the same synchronization signal block to the same time slot in different frames, the resulting mapped image can better meet the flexible uplink and downlink time slots in the NR system Configuration to facilitate the transmission of the synchronization signal block set. Specifically, for any kind of uplink and downlink configuration, the base station can easily find the corresponding time-domain transmission position and send the PSS sequence, SSS sequence, PBCH and its DMRS in the synchronization signal block in time and successfully. For example, even if the DL time slots currently configured for the UE in the NR system are not continuous, the solution of this embodiment can still complete the transmission of the synchronization signal block set in time.
- Fig. 4 is a flowchart of a method for sending a synchronization signal block according to an embodiment of the present invention.
- the solution of this embodiment can be applied to the narrowband transmission scenario of the NR system.
- the solution of this embodiment can be applied to the network side, such as executed by a base station (gNB) on the network side.
- gNB base station
- the method for sending a synchronization signal block described in this embodiment may include the following steps:
- Step S101 Obtain a synchronization signal block set to be sent, where the synchronization signal block set includes n synchronization signal blocks, and n is a positive integer;
- Step S102 For the i-th synchronization signal block in the synchronization signal block set, map multiple signals or channels included in the i-th synchronization signal block to the same time slot of different frames in the transmission window, and, The same signal or channel of different synchronization signal blocks in the synchronization signal block set is located in different time slots of the same frame, where 1 ⁇ i ⁇ n, and the multiple signals or channels are selected from PSS sequence, SSS sequence, PBCH and DMRS;
- Step S103 Within the transmission window, send the synchronization signal block set according to the mapping pattern obtained by mapping.
- the PSS sequence, SSS sequence, PBCH and DMRS contained in the synchronization signal block are no longer continuously transmitted in the time domain, but are mapped to the same time in different frames.
- the PSS sequence, SSS sequence, PBCH and DMRS contained in the synchronization signal block are no longer continuously transmitted in the time domain, but are mapped to the same time in different frames.
- the same signal or channel of different synchronization signal blocks in the synchronization signal block set in different time slots of the same frame may refer to: the PSS sequence of the i-th synchronization signal block and the i+k-th synchronization signal block
- the PSS sequence is located in the i-th time slot and the i+k-th time slot of the same frame;
- the SSS sequence of the i-th synchronization signal block and the SSS sequence of the i+k-th synchronization signal block are respectively located in the same frame
- a specific frame within the transmission window may be dedicated to transmitting the same signal or channel of all synchronization signal blocks of the synchronization signal block set.
- mapping conflicts between different synchronization signal blocks can be avoided.
- the length of the transmission window can be determined according to the protocol, the base station needs to complete the synchronization signal block sending operation within the transmission window, and correspondingly, the UE needs to complete the synchronization signal block receiving operation within the transmission window.
- k may be a preset value, for example, it may be specified by an agreement.
- k can be equal to 1.
- the multiple signals or channels included in the i-th synchronization signal block may be in order of time: PSS sequence, PBCH and its DMRS, PBCH and its DMRS, SSS sequence, PBCH and Its DMRS and PBCH and its DMRS. That is, the i-th synchronization signal block may be transmitted in the time domain with the aforementioned structure.
- the PBCH and its DMRS are sequentially mapped into the transmission window except for the mapping Frames other than the frame of the PSS sequence and the SSS sequence.
- the value of the preset threshold y may be used to make no idle frames exist between frames mapped with adjacent signals or channels.
- SSB burst ⁇ SSB0,SSB1,...,SSBn-1 ⁇
- the length of each frame is 10ms
- the first SSB (ie SSB0) is located in the first time slot of each frame
- the second SSB (ie SSB1) is located in the second time slot of each frame
- the nth SSB (ie SSBn-1) is located in the nth time slot of each frame.
- the PSS sequence is fixedly mapped to the first frame in the transmission window, according to the PSS sequence, PBCH and its DMRS, PBCH and its DMRS, SSS sequence, PBCH and its DMRS, and PBCH and its DMRS
- the preset threshold y is preferably 3.
- the PBCH of the SSB0 and its DMRS are respectively located in the first time slot of the second frame, the third frame, the fifth frame and the sixth frame in the transmission window, as shown in the area filled with grid lines.
- the PSS sequence of SSB1 can be located in the second time slot of the first frame in the transmission window (not shown); the SSS sequence of SSB1 can be located in the transmission window The second time slot of the 4th frame (not shown); the PBCH of SSB1 and its DMRS are respectively located in the second time slot of the second frame, the third frame, the fifth frame and the sixth frame within the transmission window Gap (not shown).
- the PSS sequence of SSBn-1 may be located in the nth time slot of the first frame in the transmission window (not shown); the SSS sequence of SSB n-1 may be located in the The nth time slot of the 4th frame in the transmission window (not shown); the PBCH of SSB n-1 and its DMRS are respectively located in the 2nd, 3rd, 5th and 6th frames of the transmission window The nth time slot of the frame (not shown).
- the PBCH of the SSB0 and its DMRS are respectively located in the first time slot of the second frame, the third frame, the fifth frame and the sixth frame within the transmission window, as shown in the area filled with grid lines.
- the PSS sequence of SSB1 is mapped to the second time slot of the first frame
- the SSS sequence is mapped to the second time slot of the fourth frame
- the PBCH and its DMRS are mapped to the second frame, the third frame, and the fifth frame respectively.
- the first index (SSB index) of the synchronization signal block in the synchronization signal block set may be It is not equal to the second index (slot index) of the time slot in a single frame.
- the PSS sequence of SSB0 can be mapped to the first time slot of the first frame
- the PSS sequence of SSB1 can be mapped to the third time slot of the first frame
- the PSS sequence of SSB2 can be mapped to the fourth time slot of the first frame.
- Time slots correspondingly, the SSS sequence of SSB0 can be mapped to the first time slot of the 4th frame
- the SSS sequence of SSB1 can be mapped to the 3rd time slot of the 4th frame
- the SSS sequence of SSB2 can be mapped to the 4th time slot of the 4th frame.
- the PSS sequence of SSB2 can be mapped to the fourth time slot of the first frame.
- the PBCH and DMRS of SSB0 can be mapped to the first time slot of the second frame, the third frame, the fifth frame and the sixth frame, and the PBCH and DMRS of SSB1 can be mapped to the second frame and the third frame.
- the 3rd time slot of the 5th and 6th frames, the PBCH of SSB2 and its DMRS can be mapped to the 4th time slot of the 2nd, 3rd, 5th and 6th frames.
- the value of the preset threshold y may be used to make the frame to which the SSS sequence is mapped is the x/2+1th frame. That is, by rationally designing the specific value of the preset threshold y, the starting position of the PSS sequence and the SSS sequence can equally divide the transmission window. For the UE, such a mapping pattern enables the UE to directly obtain T And T/2 timing, slot length and symbol length.
- the preset threshold y is preferably 4.
- the PBCH and DMRS of SSB0 are located in the second and fourth frames of the transmission window , The first time slot of the 6th frame and the 8th frame, as shown in the grid line filled area.
- the PBCH of SSB0 and its DMRS may also be located in the first time slot of the second frame, the third frame, the sixth frame, and the seventh frame within the transmission window.
- mapping rules from SSB1 to SSBn-1 can refer to the relevant description of SSB0, which will not be repeated here.
- a single subframe includes 2 time slots.
- the PBCH of the SSB0 and its DMRS are respectively located in the first time slot of the second frame, the fourth frame, the sixth frame and the eighth frame in the transmission window, as shown in the area filled with grid lines.
- the PSS sequence of SSB1 is mapped to the second time slot of the first frame
- the SSS sequence is mapped to the second time slot of the fifth frame
- the PBCH and its DMRS are mapped to the second frame, the fourth frame, and the sixth frame respectively.
- the first index (SSB index) of the synchronization signal block in the synchronization signal block set may be It is not equal to the second index (slot index) of the time slot in a single frame.
- the PSS sequence of SSB0 can be mapped to the first time slot of the first frame
- the PSS sequence of SSB1 can be mapped to the second time slot of the first frame
- the PSS sequence of SSB2 can be mapped to the fifth time slot of the first frame.
- Time slots correspond to the SSS sequence of SSB0
- the SSS sequence of SSB1 can be mapped to the second time slot of the fifth frame
- the SSS sequence of SSB2 can be mapped to the fifth time slot of the fifth frame.
- the PBCH and DMRS of SSB0 can be mapped to the first time slot of the second frame, the fourth frame, the sixth frame and the eighth frame, and the PBCH and DMRS of SSB1 can be mapped to the second and fourth frame ,
- the second time slot of the 6th frame and the 8th frame, the PBCH of SSB2 and its DMRS can be mapped to the 5th time slot of the second frame, the 4th frame, the 6th frame and the 8th frame.
- the signals or channels included in the i-th synchronization signal block may be in the order of time: PSS sequence, SSS sequence, PBCH and its DMRS, PBCH and its DMRS, PBCH and its DMRS and PBCH and their DMRS. That is, the mapping position of the SSS sequence can be located before all PBCHs and their DMRS. Therefore, the starting position of the PSS sequence and the SSS sequence can directly define the length of a single frame in the transmission window. For the UE, such a mapping pattern enables the UE to directly obtain the frame timing and time slot according to the SSS sequence and the PSS sequence. Length and symbol length.
- mapping position of the SSS sequence of SSB0 is located before the first PBCH and its DMRS in the time domain.
- the PBCH of the SSB0 and its DMRS may be located in the first time slot of the 3rd, 4th, 5th and 6th frames in the transmission window, as shown in the area filled with grid lines.
- mapping rules from SSB1 to SSBn-1 can refer to the relevant description of SSB0, which will not be repeated here.
- the PBCH of SSB0 and its DMRS may be located in the first time slot of any four frames from the third frame to the eighth frame in the transmission window.
- a single subframe includes 2 time slots.
- the PBCH of the SSB0 and its DMRS may be located in the first time slot of the 3rd, 4th, 5th and 6th frames in the transmission window, as shown in the area filled with grid lines.
- the first index (SSB index) of the synchronization signal block in the synchronization signal block set may be It is not equal to the second index (slot index) of the time slot in a single frame.
- the PSS sequence of SSB0 can be mapped to the first time slot of the first frame, while the PSS sequence of SSB1 can be mapped to the fourth time slot of the first frame, and the PSS sequence of SSB2 can be mapped to the sixth time slot of the first frame.
- Time slots correspond to the SSS sequence of SSB0 can be mapped to the first time slot of the second frame, the SSS sequence of SSB1 can be mapped to the fourth time slot of the second frame, and the SSS sequence of SSB2 can be mapped to the sixth time slot of the second frame. Time slots.
- the PBCH and DMRS of SSB0 can be mapped to the first time slot of the 3rd, 4th, 4th and 6th frames
- the PBCH and DMRS of SSB1 can be mapped to the 3rd and 4th frames , 4th frame and 6th frame 4th time slot
- SSB2 PBCH and its DMRS can be mapped to 3rd frame, 4th frame, 4th frame and 6th frame 6th time slot.
- the number of frames included in the transmission window may not be less than the number of multiple signals or channels included in the i-th synchronization signal block to ensure that each of the i-th synchronization signal block A signal or channel can be mapped to the corresponding frame one by one.
- the number of frames included in the transmission window is not less than 6.
- the number of synchronization signal blocks included in the synchronization signal block set may be determined according to the subcarrier spacing and the number of beams.
- Lmax can take a larger value, because there can be more time slots in a single transmission window, and the mapping image in the transmission window can be referred to the above-mentioned Figure 5 to Figure 10. Show the example to confirm.
- Narrow Band Internet of Things supports a minimum bandwidth of 180 kHz, and the length of the PSS sequence applied to the Narrow Band Internet of Things is 11 bits.
- the 11-bit PSS sequence may be repeated 10 times and mapped onto 11 subcarriers and 10 OFDM symbols of one PRB.
- the length of the SSS sequence applied to the narrowband Internet of Things is 132 bits, and can be mapped to 12 subcarriers and 11 OFDM symbols of one PRB in the step S103.
- this embodiment provides a synchronization signal block and a set thereof that can support narrowband transmission.
- the base station for the base station side, it is possible to provide a synchronization signal block set suitable for narrowband transmission to support synchronization signal blocks for multi-beam transmission. Further, by mapping the PSS sequence, SSS sequence, PBCH and DMRS in the same synchronization signal block to the same time slot in different frames, the resulting mapped image can better meet the flexible uplink and downlink time slots in the NR system Configuration to facilitate the transmission of the synchronization signal block set. Specifically, for any kind of uplink and downlink configuration, the base station can easily find the corresponding time-domain transmission position and send the PSS sequence, SSS sequence, PBCH and its DMRS in the synchronization signal block in time and successfully. For example, even if the DL time slot currently configured for the UE in the NR system is not continuous, the solution of this embodiment can still complete the transmission of the synchronization signal block set in time.
- Fig. 11 is a schematic structural diagram of an apparatus for sending a synchronization signal block according to an embodiment of the present invention.
- the synchronization signal block sending device 2 (hereinafter referred to as the sending device 2) in this embodiment can be used to implement the method and technical solutions described in the embodiments shown in FIGS. 4 to 10.
- the sending device 2 of this embodiment may include: an acquisition module 21, configured to acquire a synchronization signal block set to be transmitted, the synchronization signal block set includes n synchronization signal blocks, n is a positive integer; a mapping module 22 , For the i-th synchronization signal block in the synchronization signal block set, map multiple signals or channels included in the i-th synchronization signal block to the same time slot of different frames in the transmission window, and The same signal or channel of different synchronization signal blocks in the synchronization signal block set is located in different time slots of the same frame, where 1 ⁇ i ⁇ n, and the multiple signals or channels are selected from PSS sequence, SSS sequence, PBCH and DMRS thereof; The sending module 23 is configured to send the synchronization signal block set according to the mapping pattern obtained by the mapping within the transmission window.
- the same signal or channel of different synchronization signal blocks in the synchronization signal block set in different time slots of the same frame may refer to: the PSS sequence of the i-th synchronization signal block and the i-th synchronization signal block.
- the PSS sequences of +k synchronization signal blocks are respectively located in the i-th time slot and the i+k-th time slot of the same frame; the SSS sequence of the i-th synchronization signal block and the SSS of the i+k-th synchronization signal block
- the sequences are respectively located in the i-th slot and i+k-th slot in the same frame, where k is a positive integer.
- the multiple signals or channels included in the i-th synchronization signal block may be in order of time: PSS sequence, PBCH and its DMRS, PBCH and its DMRS, SSS sequence, PBCH and Its DMRS and PBCH and its DMRS.
- a second mapping sub-module 222 configured to map the SSS sequence to a system frame number determined based on the formula SFN
- mapping sub-module 221 When the first mapping sub-module 221, the second mapping sub-module 222, and the third mapping sub-module 223 perform their respective operations, they may be executed synchronously or asynchronously.
- the value of the preset threshold y may be used to make no idle frames exist between frames mapped with adjacent signals or channels.
- the value of the preset threshold y may be used to make the frame to which the SSS sequence is mapped is the x/2+1th frame.
- the signals or channels included in the i-th synchronization signal block may be in the order of time: PSS sequence, SSS sequence, PBCH and its DMRS, PBCH and DMRS, PBCH and DMRS And PBCH and its DMRS.
- mapping sub-module 224 When the fourth mapping sub-module 224, the fifth mapping sub-module 225, and the sixth mapping sub-module 226 perform their respective operations, they may be executed synchronously or asynchronously.
- the number of frames included in the transmission window may not be less than the number of multiple signals or channels included in the i-th synchronization signal block.
- the number of synchronization signal blocks included in the synchronization signal block set may be determined according to the subcarrier spacing and the number of beams.
- Fig. 12 is a flowchart of a method for determining the slot position of a synchronization signal block according to an embodiment of the present invention.
- the solution of this embodiment can be applied to the narrowband transmission scenario of the NR system.
- the solution in this embodiment may be applied to the user equipment side, such as executed by the UE.
- the method for determining the slot position of a synchronization signal block in this embodiment may include the following steps:
- Step S301 Receive a synchronization signal block set in the transmission window.
- the synchronization signal block set includes n synchronization signal blocks, where n is a positive integer.
- the synchronization signal block set is according to the foregoing embodiments shown in FIGS. 4 to 10 Sent by the method;
- Step S302 Determine the first index of the currently received synchronization signal block among the n synchronization signal blocks;
- Step S303 Determine the slot position of the currently received synchronization signal block according to the first index and the mapping pattern of the synchronization signal block set in the transmission window.
- the length T of the transmission window may be predetermined by a protocol.
- mapping image of the synchronization signal block set in the time domain may be predetermined by a protocol, or may be instructed to the UE in advance by the base station that sends the synchronization signal block set.
- the UE may predetermine the first index of the synchronization signal block in the synchronization signal block set and the corresponding slot position. Therefore, by executing the steps S301 to S303, the UE can determine its first index according to the received synchronization signal block, and then determine its slot position, thereby completing the timing.
- the step S302 may include the step of determining the payload according to the received PBCH and its DMRS, and/or the payload of the master information block (Master Information Block, MIB for short) The first index.
- the master information block Master Information Block, MIB for short
- all first indexes can be obtained based on the PBCH and its DMRS blind detection.
- the UE executing the solution described in this embodiment can determine all the PSS sequences after searching for the PSS sequence.
- the boundary of the transmission window such as the starting position; the length of the time slot, as shown in Figure 5, a PSS sequence occupies the length of a time slot; and the length of the symbol, such as can be determined according to the time-frequency domain mapping method of the PSS sequence .
- two PBCHs and their DMRS can be received between the PSS sequence and the SSS sequence, and two PBCHs and their DMRS can be received after the SSS sequence.
- the first index can be determined, and then the slot position of the currently received synchronization signal block can be determined according to the mapping pattern to complete the timing.
- the UE when the synchronization signal block set is transmitted using the above-mentioned mapping pattern shown in FIG. 7 or FIG. 8, since the start position of the SSS sequence and the PSS sequence divides the transmission window equally, After searching for the PSS sequence and the SSS sequence, the UE can realize the timing of the transmission window and half of the transmission window, and determine the slot length and symbol length.
- the UE can complete the timing of the synchronization signal block.
- the UE when the synchronization signal block set is transmitted using the mapping pattern shown in FIG. 9 or FIG. 10, the UE can realize the frame timing after searching for the PSS sequence and the SSS sequence, and determine the time Gap length and symbol length.
- the UE can complete the timing of the synchronization signal block.
- the UE can determine the slot position according to the first index of the currently received synchronization signal block in the synchronization signal block set, thereby The received synchronization signal block completes timing for subsequent synchronization operations.
- FIG. 13 is a schematic structural diagram of an apparatus for determining the position of a time slot of a synchronization signal block according to an embodiment of the present invention.
- the time slot position determining device 4 of the synchronization signal block described in this embodiment is hereinafter referred to as the time slot position determining device 4) can be used to implement the method and technical solution described in the embodiment shown in FIG. 12.
- the time slot position determining device 4 may include: a receiving module 41, configured to receive a synchronization signal block set within a transmission window, the synchronization signal block set including n synchronization signal blocks, n Is a positive integer, the synchronization signal block set is sent by the above-mentioned sending device; the first determining module 42 is used to determine the first index of the currently received synchronization signal block in n synchronization signal blocks; the second determining module 43 , Used to determine the slot position of the currently received synchronization signal block according to the first index and the mapping pattern of the synchronization signal block set in the transmission window.
- the first determining module 42 may include: a determining sub-module 421 configured to determine the first index according to the received PBCH and its DMRS, and/or the load of the MIB.
- the embodiment of the present invention also discloses a storage medium on which computer instructions are stored, and when the computer instructions are run, the method and technical solutions described in the embodiments shown in FIGS. 4 to 10 and 12 are executed.
- the storage medium may include a computer-readable storage medium such as a non-volatile memory or a non-transitory memory.
- the storage medium may include ROM, RAM, magnetic disk or optical disk, etc.
- an embodiment of the present invention also discloses a terminal, including a memory and a processor, the memory stores computer instructions that can run on the processor, and the processor executes the above diagram when the computer instructions are executed. 12 shows the technical solution of the method described in the embodiment.
- the terminal may be a 5G user terminal.
- an embodiment of the present invention also discloses a base station, including a memory and a processor, the memory stores computer instructions that can run on the processor, and the processor executes the above diagram when the computer instructions are executed. 4 to the technical solution of the method described in the embodiment shown in FIG. 10.
- the base station may be a gNB.
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Abstract
Description
Claims (17)
- 一种同步信号块的发送方法,其特征在于,包括:获取待发送的同步信号块集合,所述同步信号块集合包括n个同步信号块,n为正整数;对于所述同步信号块集合中的第i个同步信号块,将所述第i个同步信号块包括的多个信号或信道分别映射至传输窗口内不同帧的同一时隙,并且,所述同步信号块集合中不同同步信号块的同一信号或信道位于相同帧的不同时隙,其中,1≤i≤n,所述多个信号或信道选自PSS序列、SSS序列、PBCH及其DMRS;在所述传输窗口内,根据映射得到的映射图样发送所述同步信号块集合。
- 根据权利要求1所述的发送方法,其特征在于,所述同步信号块集合中不同同步信号块的同一信号或信道位于相同帧的不同时隙是指:所述第i个同步信号块的PSS序列和第i+k个同步信号块的PSS序列分别位于同一帧的第i个时隙和第i+k个时隙;所述第i个同步信号块的SSS序列和第i+k个同步信号块的SSS序列分别位于同一帧的第i个时隙和第i+k个时隙,其中,k为正整数。
- 根据权利要求1所述的发送方法,其特征在于,所述第i个同步信号块包括的多个信号或信道按时间先后顺序依次为:PSS序列、PBCH及其DMRS、PBCH及其DMRS、SSS序列、PBCH及其DMRS和PBCH及其DMRS。
- 根据权利要求3所述的发送方法,其特征在于,所述将所述第i个同步信号块包括的多个信号或信道分别映射至传输窗口内不同帧的同一时隙包括:将所述PSS序列映射至基于公式SFNmodx=0确定的系统帧号,其中,SFN为所述系统帧号,x为所述传输窗口包括的帧数;将所述SSS序列映射至基于公式SFNmodx=y确定的系统帧号,其中,y为预设阈值;将所述PBCH及其DMRS依序映射至传输窗口内除映射有PSS序列和SSS序列的帧之外的其他帧。
- 根据权利要求4所述的发送方法,其特征在于,所述预设阈值y的取值用于使得映射有相邻信号或信道的帧之间不存在空闲帧。
- 根据权利要求4所述的发送方法,其特征在于,所述预设阈值y的取值用于使得映射有SSS序列的帧为第x/2+1个帧。
- 根据权利要求1所述的发送方法,其特征在于,所述第i个同步信号块包括的信号或信道按时间先后顺序依次为:PSS序列、SSS序列、PBCH及其DMRS、PBCH及其DMRS、PBCH及其DMRS和PBCH及其DMRS。
- 根据权利要求7所述的发送方法,其特征在于,所述将所述第i个同步信号块包括的多个信号或信道分别映射至传输窗口内不同帧的同一时隙包括:将所述PSS序列映射至基于公式SFNmodx=0确定的系统帧号,其中,SFN为所述系统帧号,x为所述传输窗口包括的帧数;将所述SSS序列映射至基于公式SFNmodx=1确定的系统帧号;将所述PBCH及其DMRS依序映射至传输窗口内除映射有PSS序列和SSS序列的帧之外的其他帧。
- 根据权利要求1所述的发送方法,其特征在于,所述传输窗口包括的帧数不小于所述第i个同步信号块包括的多个信号或信道的数量。
- 根据权利要求1所述的发送方法,其特征在于,所述同步信号块集合包括的同步信号块的数量是根据子载波间隔和波束数量确定的。
- 一种同步信号块的时隙位置确定方法,其特征在于,包括:在传输窗口内接收同步信号块集合,所述同步信号块集合包括n个同步信号块,n为正整数,所述同步信号块集合是按照上述权利要求1至10中任一项所述方法发送的;确定当前接收到的同步信号块在n个同步信号块中的第一索引;根据所述第一索引以及所述同步信号块集合在所述传输窗口内的映射图样确定所述当前接收到的同步信号块的时隙位置。
- 根据权利要求11所述的时隙位置确定方法,其特征在于,所述确定当前接收到的同步信号块在n个同步信号块中的第一索引包括:根据接收到的所述PBCH及其DMRS,和/或MIB的负荷确定所述第一索引。
- 一种同步信号块的发送装置,其特征在于,包括:获取模块,用于获取待发送的同步信号块集合,所述同步信号块集合包括n个同步信号块,n为正整数;映射模块,对于所述同步信号块集合中的第i个同步信号块,将所述第i个同步信号块包括的多个信号或信道分别映射至传输窗口内不同帧的同一时隙,并且,所述同步信号块集合中不同同步信号块的同一信号或信道位于相同帧的不同时隙,其中,1≤i≤n,所述多个信号或信道选自PSS序列、SSS序列、PBCH及其DMRS;发送模块,用于在所述传输窗口内,根据映射得到的映射图样发送所述同步信号块集合。
- 一种同步信号块的时隙位置确定装置,其特征在于,包括:接收模块,用于在传输窗口内接收同步信号块集合,所述同步信号块集合包括n个同步信号块,n为正整数,所述同步信号块集合是上述权利要求13所述发送装置发送的;第一确定模块,用于确定当前接收到的同步信号块在n个同步信号块中的第一索引;第二确定模块,用于根据所述第一索引以及所述同步信号块集合在所述传输窗口内的映射图样确定所述当前接收到的同步信号块的时隙位置。
- 一种存储介质,其上存储有计算机指令,其特征在于,所述计算机指令运行时执行权利要求1至12任一项所述方法的步骤。
- 一种基站,包括存储器和处理器,所述存储器上存储有能够在所述处理器上运行的计算机指令,其特征在于,所述处理器运行所述计算机指令时执行权利要求1至10任一项所述方法的步骤。
- 一种终端,包括存储器和处理器,所述存储器上存储有能够在所述处理器上运行的计算机指令,其特征在于,所述处理器运行所述计算机指令时执行权利要求11或12所述方法的步骤。
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