WO2021012738A1 - 同步信号块的发送、时隙位置确定方法及装置、存储介质、基站、终端 - Google Patents

同步信号块的发送、时隙位置确定方法及装置、存储介质、基站、终端 Download PDF

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WO2021012738A1
WO2021012738A1 PCT/CN2020/087110 CN2020087110W WO2021012738A1 WO 2021012738 A1 WO2021012738 A1 WO 2021012738A1 CN 2020087110 W CN2020087110 W CN 2020087110W WO 2021012738 A1 WO2021012738 A1 WO 2021012738A1
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Prior art keywords
synchronization signal
signal block
dmrs
transmission window
pbch
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PCT/CN2020/087110
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English (en)
French (fr)
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周欢
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北京紫光展锐通信技术有限公司
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Publication of WO2021012738A1 publication Critical patent/WO2021012738A1/zh

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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04WWIRELESS COMMUNICATION NETWORKS
    • H04W72/00Local resource management
    • H04W72/04Wireless resource allocation
    • H04W72/044Wireless resource allocation based on the type of the allocated resource
    • H04W72/0446Resources in time domain, e.g. slots or frames
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/26Systems using multi-frequency codes
    • H04L27/2601Multicarrier modulation systems
    • H04L27/2602Signal structure
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/26Systems using multi-frequency codes
    • H04L27/2601Multicarrier modulation systems
    • H04L27/2647Arrangements specific to the receiver only
    • H04L27/2655Synchronisation arrangements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/26Systems using multi-frequency codes
    • H04L27/2601Multicarrier modulation systems
    • H04L27/2647Arrangements specific to the receiver only
    • H04L27/2655Synchronisation arrangements
    • H04L27/2657Carrier synchronisation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04WWIRELESS COMMUNICATION NETWORKS
    • H04W56/00Synchronisation arrangements
    • H04W56/001Synchronization between nodes

Definitions

  • the present invention relates to the field of communication technology, in particular to a method and device, storage medium, base station, and terminal for the transmission of synchronization signal blocks and time slot position determination.
  • each radio frame is divided into 10 sub-frames of the same size with a length of 1 ms.
  • each sub-frame may include multiple time slots.
  • each time slot is composed of a certain number of symbols, and the number of symbols is determined by the type of cyclic prefix (Cyclic Prefix, CP for short).
  • the NR system supports multi-beam synchronization signal block (Synchronization Signal/Physical Broadcast Channel Block, referred to as SS/PBCH Block, that is, SSB) transmission, where the synchronization signal block includes the primary synchronization signal (Primary Synchronization Signal, referred to as PSS) sequence, Secondary Synchronization Signal (SSS) sequence, Physical Broadcast Channel (PBCH) and its demodulation reference signal (Demodulation Reference Signal, DMRS).
  • PSS Primary Synchronization Signal
  • SSS Secondary Synchronization Signal
  • PBCH Physical Broadcast Channel
  • DMRS Demodulation Reference Signal
  • the synchronization signal block when the synchronization signal block is mapped to the time slot, it is usually continuous in the time domain.
  • the NR system supports flexible uplink (Uplink, UL) time slot and downlink (Downlink, DL) time slot configuration, It is impossible to guarantee that multiple consecutive time slots can be used to transmit synchronization signal blocks, which results in that the existing synchronization signal block transmission method cannot be well adapted to the flexible time slot configuration of the NR system.
  • the technical problem solved by the present invention is how to provide a new synchronization signal block mapping pattern to meet the flexible uplink and downlink timeslot configuration in the NR system and facilitate the transmission of the synchronization signal block set.
  • an embodiment of the present invention provides a method for sending synchronization signal blocks, including: acquiring a synchronization signal block set to be sent, the synchronization signal block set includes n synchronization signal blocks, and n is a positive integer;
  • the i-th synchronization signal block in the synchronization signal block set maps multiple signals or channels included in the i-th synchronization signal block to the same time slot of different frames in the transmission window, and the synchronization signal
  • the same signal or channel of different synchronization signal blocks in the block set is located in different time slots of the same frame, where 1 ⁇ i ⁇ n, and the multiple signals or channels are selected from PSS sequence, SSS sequence, PBCH and DMRS;
  • the synchronization signal block set is sent according to the mapping pattern obtained by the mapping.
  • the same signal or channel of different synchronization signal blocks in the synchronization signal block set in different time slots of the same frame refers to: the PSS sequence of the i-th synchronization signal block and the i+k-th synchronization signal block
  • the PSS sequence is located in the i-th time slot and the i+k-th time slot of the same frame;
  • the SSS sequence of the i-th synchronization signal block and the SSS sequence of the i+k-th synchronization signal block are respectively located in the same frame
  • the multiple signals or channels included in the i-th synchronization signal block are, in chronological order: PSS sequence, PBCH and its DMRS, PBCH and its DMRS, SSS sequence, PBCH and its DMRS, PBCH and its DMRS.
  • the value of the preset threshold y is used to ensure that there are no idle frames between frames mapped with adjacent signals or channels.
  • the value of the preset threshold y is used to make the frame to which the SSS sequence is mapped is the x/2+1th frame.
  • the signals or channels included in the i-th synchronization signal block are: PSS sequence, SSS sequence, PBCH and its DMRS, PBCH and DMRS, PBCH and DMRS, and PBCH and DMRS in chronological order.
  • the number of frames included in the transmission window is not less than the number of multiple signals or channels included in the i-th synchronization signal block.
  • the number of synchronization signal blocks included in the synchronization signal block set is determined according to the subcarrier spacing and the number of beams.
  • an embodiment of the present invention also provides a method for determining the slot position of a synchronization signal block, including: receiving a synchronization signal block set within a transmission window, the synchronization signal block set including n synchronization signal blocks, n Is a positive integer, the synchronization signal block set is sent according to the above method; the first index of the currently received synchronization signal block among the n synchronization signal blocks is determined; according to the first index and the synchronization signal block set The mapping pattern in the transmission window determines the slot position of the currently received synchronization signal block.
  • the determining the first index of the currently received synchronization signal block in the n synchronization signal blocks includes: determining the first index according to the received PBCH and its DMRS, and/or the load of the MIB .
  • an embodiment of the present invention also provides a synchronization signal block sending device, including: an acquisition module, configured to acquire a synchronization signal block set to be sent, the synchronization signal block set includes n synchronization signal blocks, n is a positive integer; the mapping module, for the i-th synchronization signal block in the synchronization signal block set, maps multiple signals or channels included in the i-th synchronization signal block to the same frame in different frames in the transmission window.
  • Time slots, and the same signal or channel of different synchronization signal blocks in the synchronization signal block set is located in different time slots of the same frame, where 1 ⁇ i ⁇ n, and the multiple signals or channels are selected from PSS sequence, SSS Sequence, PBCH and its DMRS; a sending module, used to send the synchronization signal block set according to the mapping pattern obtained by mapping within the transmission window.
  • an embodiment of the present invention also provides a device for determining the position of a synchronization signal block in a time slot, including: a receiving module for receiving a synchronization signal block set within a transmission window, the synchronization signal block set including n Synchronization signal block, n is a positive integer, and the set of synchronization signal blocks is sent by the above-mentioned sending device; the first determining module is used to determine the first index of the currently received synchronization signal block among the n synchronization signal blocks; The second determining module is configured to determine the slot position of the currently received synchronization signal block according to the first index and the mapping pattern of the synchronization signal block set in the transmission window.
  • an embodiment of the present invention also provides a storage medium on which computer instructions are stored, and the computer instructions execute the steps of the above method when the computer instructions are executed.
  • an embodiment of the present invention also provides a base station, including a memory and a processor, the memory stores computer instructions that can run on the processor, and when the processor runs the computer instructions Perform the steps of the above method.
  • an embodiment of the present invention also provides a terminal, including a memory and a processor, the memory stores computer instructions that can run on the processor, and when the processor runs the computer instructions Perform the steps of the above method.
  • an embodiment of the present invention provides a method for sending synchronization signal blocks, including: acquiring a synchronization signal block set to be transmitted, the synchronization signal block set includes n synchronization signal blocks, and n is a positive integer;
  • the i-th synchronization signal block in the synchronization signal block set maps multiple signals or channels included in the i-th synchronization signal block to the same time slot of different frames in the transmission window, and the synchronization signal block set
  • the same signal or channel of different synchronization signal blocks is located in different time slots of the same frame, where 1 ⁇ i ⁇ n, and the multiple signals or channels are selected from PSS sequence, SSS sequence, PBCH and DMRS;
  • the synchronization signal block set is sent according to the mapping pattern obtained by the mapping.
  • a synchronization signal block set suitable for narrowband transmission can be provided to support synchronization signal blocks for multi-beam transmission. Further, by mapping the PSS sequence, SSS sequence, PBCH and DMRS in the same synchronization signal block to the same time slot in different frames, the resulting mapped image can better meet the flexible uplink and downlink time slots in the NR system Configuration to facilitate the transmission of the synchronization signal block set. Specifically, for any kind of uplink and downlink configuration, the base station can easily find the corresponding time-domain transmission position and send the PSS sequence, SSS sequence, PBCH and its DMRS in the synchronization signal block in time and successfully. For example, even if the DL time slot currently configured for the UE in the NR system is not continuous, the solution of this embodiment can still complete the transmission of the synchronization signal block set in time.
  • an embodiment of the present invention provides a method for determining the slot position of a synchronization signal block, which includes: receiving a synchronization signal block set within a transmission window, the synchronization signal block set includes n synchronization signal blocks, and n is a positive integer , The synchronization signal block set is sent according to the above method; the first index of the currently received synchronization signal block in the n synchronization signal blocks is determined; according to the first index and the synchronization signal block set in the The mapping pattern in the transmission window determines the slot position of the currently received synchronization signal block.
  • the UE can determine the slot position according to the first index of the currently received synchronization signal block in the synchronization signal block set, thereby completing the completion according to the received synchronization signal block Timing for subsequent synchronization operations.
  • Fig. 1 is a schematic diagram of a synchronization signal block in the prior art
  • Fig. 2 is a schematic diagram of time-domain mapping of synchronization signal blocks at different subcarrier intervals in the prior art
  • FIG. 3 is a schematic diagram of the position of a synchronization signal block in a single time slot in the prior art
  • FIG. 4 is a flowchart of a method for sending a synchronization signal block according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of a first mapping pattern of a synchronization signal block according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a second mapping pattern of synchronization signal blocks according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a third mapping pattern of a synchronization signal block according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a fourth mapping pattern of synchronization signal blocks according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a fifth mapping pattern of a synchronization signal block according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a sixth mapping pattern of synchronization signal blocks according to an embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram of a device for sending a synchronization signal block according to an embodiment of the present invention.
  • FIG. 12 is a flowchart of a method for determining the slot position of a synchronization signal block according to an embodiment of the present invention
  • FIG. 13 is a schematic structural diagram of an apparatus for determining the position of a time slot of a synchronization signal block according to an embodiment of the present invention.
  • the existing synchronization signal block transmission method cannot well adapt to the flexible time slot configuration of the NR system.
  • the existing synchronization signal block is composed of 4 orthogonal frequency division multiplexing (Orthogonal Frequency Division Multiplexing, OFDM for short) symbols.
  • OFDM Orthogonal Frequency Division Multiplexing
  • the PBCH and its DMRS 13 can occupy multiple slots, and the PSS sequence 11 and the SSS sequence 12 each occupy one slot.
  • PSS sequence 11 can occupy 12 physical resource blocks (PRBs)
  • SSS sequence 12 can occupy 12 PRBs
  • the position of the synchronization signal block within 5 ms is related to the subcarrier spacing (Subcarrier Spacing, SCS for short) and the number of beams L.
  • the position of the time slot in which the synchronization signal block can be sent in the 5ms period is shown in the cross-stripe filled area in the figure.
  • the slot length is equal to the subframe length.
  • the synchronization signal block can be continuously mapped to the first 4 time slots in a period of 5 ms.
  • the length of the time slot is equal to 1/2 subframe length.
  • the synchronization signal block can be continuously mapped to the first 4 time slots in a period of 5 ms.
  • the position of the synchronization signal block in each time slot can have 5 situations, as shown in FIG. 3. Specifically, according to different SCS, the length of the time slot is different, and the number and position of the synchronization signal block that can be sent are also different.
  • the area filled with grid lines in FIG. 3 indicates the location of the synchronization signal block.
  • multiple synchronization signal blocks may form a synchronization signal block set
  • the maximum number of synchronization signal blocks that can be sent in the synchronization signal block set is denoted as Lmax
  • the actual number of synchronization signal blocks L may be less than Lmax.
  • Case D (Case D), corresponding to the subcarrier spacing of 120kHz: the first time domain symbol of the candidate synchronization signal block is located at ⁇ 4,8,16,20 ⁇ +28*n.
  • n 0,1,2,3,5,6,7,8,10,11,12,13,15,16,17,18.
  • Case E corresponding to the subcarrier spacing of 240kHz: the first time domain symbol of the candidate synchronization signal block is located at ⁇ 8,12,16,20,32,36,40,44 ⁇ +56*n.
  • n 0,1,2,3,5,6,7,8.
  • an embodiment of the present invention provides a method for sending synchronization signal blocks, including: acquiring a synchronization signal block set to be sent, the synchronization signal block set includes n synchronization signal blocks, and n is a positive integer;
  • the i-th synchronization signal block in the synchronization signal block set maps multiple signals or channels included in the i-th synchronization signal block to the same time slot of different frames in the transmission window, and the synchronization signal
  • the same signal or channel of different synchronization signal blocks in the block set is located in different time slots of the same frame, where 1 ⁇ i ⁇ n, and the multiple signals or channels are selected from PSS sequence, SSS sequence, PBCH and DMRS;
  • the synchronization signal block set is sent according to the mapping pattern obtained by the mapping.
  • a synchronization signal block set suitable for narrowband transmission can be provided to support synchronization signal blocks for multi-beam transmission. Further, by mapping the PSS sequence, SSS sequence, PBCH and DMRS in the same synchronization signal block to the same time slot in different frames, the resulting mapped image can better meet the flexible uplink and downlink time slots in the NR system Configuration to facilitate the transmission of the synchronization signal block set. Specifically, for any kind of uplink and downlink configuration, the base station can easily find the corresponding time-domain transmission position and send the PSS sequence, SSS sequence, PBCH and its DMRS in the synchronization signal block in time and successfully. For example, even if the DL time slots currently configured for the UE in the NR system are not continuous, the solution of this embodiment can still complete the transmission of the synchronization signal block set in time.
  • Fig. 4 is a flowchart of a method for sending a synchronization signal block according to an embodiment of the present invention.
  • the solution of this embodiment can be applied to the narrowband transmission scenario of the NR system.
  • the solution of this embodiment can be applied to the network side, such as executed by a base station (gNB) on the network side.
  • gNB base station
  • the method for sending a synchronization signal block described in this embodiment may include the following steps:
  • Step S101 Obtain a synchronization signal block set to be sent, where the synchronization signal block set includes n synchronization signal blocks, and n is a positive integer;
  • Step S102 For the i-th synchronization signal block in the synchronization signal block set, map multiple signals or channels included in the i-th synchronization signal block to the same time slot of different frames in the transmission window, and, The same signal or channel of different synchronization signal blocks in the synchronization signal block set is located in different time slots of the same frame, where 1 ⁇ i ⁇ n, and the multiple signals or channels are selected from PSS sequence, SSS sequence, PBCH and DMRS;
  • Step S103 Within the transmission window, send the synchronization signal block set according to the mapping pattern obtained by mapping.
  • the PSS sequence, SSS sequence, PBCH and DMRS contained in the synchronization signal block are no longer continuously transmitted in the time domain, but are mapped to the same time in different frames.
  • the PSS sequence, SSS sequence, PBCH and DMRS contained in the synchronization signal block are no longer continuously transmitted in the time domain, but are mapped to the same time in different frames.
  • the same signal or channel of different synchronization signal blocks in the synchronization signal block set in different time slots of the same frame may refer to: the PSS sequence of the i-th synchronization signal block and the i+k-th synchronization signal block
  • the PSS sequence is located in the i-th time slot and the i+k-th time slot of the same frame;
  • the SSS sequence of the i-th synchronization signal block and the SSS sequence of the i+k-th synchronization signal block are respectively located in the same frame
  • a specific frame within the transmission window may be dedicated to transmitting the same signal or channel of all synchronization signal blocks of the synchronization signal block set.
  • mapping conflicts between different synchronization signal blocks can be avoided.
  • the length of the transmission window can be determined according to the protocol, the base station needs to complete the synchronization signal block sending operation within the transmission window, and correspondingly, the UE needs to complete the synchronization signal block receiving operation within the transmission window.
  • k may be a preset value, for example, it may be specified by an agreement.
  • k can be equal to 1.
  • the multiple signals or channels included in the i-th synchronization signal block may be in order of time: PSS sequence, PBCH and its DMRS, PBCH and its DMRS, SSS sequence, PBCH and Its DMRS and PBCH and its DMRS. That is, the i-th synchronization signal block may be transmitted in the time domain with the aforementioned structure.
  • the PBCH and its DMRS are sequentially mapped into the transmission window except for the mapping Frames other than the frame of the PSS sequence and the SSS sequence.
  • the value of the preset threshold y may be used to make no idle frames exist between frames mapped with adjacent signals or channels.
  • SSB burst ⁇ SSB0,SSB1,...,SSBn-1 ⁇
  • the length of each frame is 10ms
  • the first SSB (ie SSB0) is located in the first time slot of each frame
  • the second SSB (ie SSB1) is located in the second time slot of each frame
  • the nth SSB (ie SSBn-1) is located in the nth time slot of each frame.
  • the PSS sequence is fixedly mapped to the first frame in the transmission window, according to the PSS sequence, PBCH and its DMRS, PBCH and its DMRS, SSS sequence, PBCH and its DMRS, and PBCH and its DMRS
  • the preset threshold y is preferably 3.
  • the PBCH of the SSB0 and its DMRS are respectively located in the first time slot of the second frame, the third frame, the fifth frame and the sixth frame in the transmission window, as shown in the area filled with grid lines.
  • the PSS sequence of SSB1 can be located in the second time slot of the first frame in the transmission window (not shown); the SSS sequence of SSB1 can be located in the transmission window The second time slot of the 4th frame (not shown); the PBCH of SSB1 and its DMRS are respectively located in the second time slot of the second frame, the third frame, the fifth frame and the sixth frame within the transmission window Gap (not shown).
  • the PSS sequence of SSBn-1 may be located in the nth time slot of the first frame in the transmission window (not shown); the SSS sequence of SSB n-1 may be located in the The nth time slot of the 4th frame in the transmission window (not shown); the PBCH of SSB n-1 and its DMRS are respectively located in the 2nd, 3rd, 5th and 6th frames of the transmission window The nth time slot of the frame (not shown).
  • the PBCH of the SSB0 and its DMRS are respectively located in the first time slot of the second frame, the third frame, the fifth frame and the sixth frame within the transmission window, as shown in the area filled with grid lines.
  • the PSS sequence of SSB1 is mapped to the second time slot of the first frame
  • the SSS sequence is mapped to the second time slot of the fourth frame
  • the PBCH and its DMRS are mapped to the second frame, the third frame, and the fifth frame respectively.
  • the first index (SSB index) of the synchronization signal block in the synchronization signal block set may be It is not equal to the second index (slot index) of the time slot in a single frame.
  • the PSS sequence of SSB0 can be mapped to the first time slot of the first frame
  • the PSS sequence of SSB1 can be mapped to the third time slot of the first frame
  • the PSS sequence of SSB2 can be mapped to the fourth time slot of the first frame.
  • Time slots correspondingly, the SSS sequence of SSB0 can be mapped to the first time slot of the 4th frame
  • the SSS sequence of SSB1 can be mapped to the 3rd time slot of the 4th frame
  • the SSS sequence of SSB2 can be mapped to the 4th time slot of the 4th frame.
  • the PSS sequence of SSB2 can be mapped to the fourth time slot of the first frame.
  • the PBCH and DMRS of SSB0 can be mapped to the first time slot of the second frame, the third frame, the fifth frame and the sixth frame, and the PBCH and DMRS of SSB1 can be mapped to the second frame and the third frame.
  • the 3rd time slot of the 5th and 6th frames, the PBCH of SSB2 and its DMRS can be mapped to the 4th time slot of the 2nd, 3rd, 5th and 6th frames.
  • the value of the preset threshold y may be used to make the frame to which the SSS sequence is mapped is the x/2+1th frame. That is, by rationally designing the specific value of the preset threshold y, the starting position of the PSS sequence and the SSS sequence can equally divide the transmission window. For the UE, such a mapping pattern enables the UE to directly obtain T And T/2 timing, slot length and symbol length.
  • the preset threshold y is preferably 4.
  • the PBCH and DMRS of SSB0 are located in the second and fourth frames of the transmission window , The first time slot of the 6th frame and the 8th frame, as shown in the grid line filled area.
  • the PBCH of SSB0 and its DMRS may also be located in the first time slot of the second frame, the third frame, the sixth frame, and the seventh frame within the transmission window.
  • mapping rules from SSB1 to SSBn-1 can refer to the relevant description of SSB0, which will not be repeated here.
  • a single subframe includes 2 time slots.
  • the PBCH of the SSB0 and its DMRS are respectively located in the first time slot of the second frame, the fourth frame, the sixth frame and the eighth frame in the transmission window, as shown in the area filled with grid lines.
  • the PSS sequence of SSB1 is mapped to the second time slot of the first frame
  • the SSS sequence is mapped to the second time slot of the fifth frame
  • the PBCH and its DMRS are mapped to the second frame, the fourth frame, and the sixth frame respectively.
  • the first index (SSB index) of the synchronization signal block in the synchronization signal block set may be It is not equal to the second index (slot index) of the time slot in a single frame.
  • the PSS sequence of SSB0 can be mapped to the first time slot of the first frame
  • the PSS sequence of SSB1 can be mapped to the second time slot of the first frame
  • the PSS sequence of SSB2 can be mapped to the fifth time slot of the first frame.
  • Time slots correspond to the SSS sequence of SSB0
  • the SSS sequence of SSB1 can be mapped to the second time slot of the fifth frame
  • the SSS sequence of SSB2 can be mapped to the fifth time slot of the fifth frame.
  • the PBCH and DMRS of SSB0 can be mapped to the first time slot of the second frame, the fourth frame, the sixth frame and the eighth frame, and the PBCH and DMRS of SSB1 can be mapped to the second and fourth frame ,
  • the second time slot of the 6th frame and the 8th frame, the PBCH of SSB2 and its DMRS can be mapped to the 5th time slot of the second frame, the 4th frame, the 6th frame and the 8th frame.
  • the signals or channels included in the i-th synchronization signal block may be in the order of time: PSS sequence, SSS sequence, PBCH and its DMRS, PBCH and its DMRS, PBCH and its DMRS and PBCH and their DMRS. That is, the mapping position of the SSS sequence can be located before all PBCHs and their DMRS. Therefore, the starting position of the PSS sequence and the SSS sequence can directly define the length of a single frame in the transmission window. For the UE, such a mapping pattern enables the UE to directly obtain the frame timing and time slot according to the SSS sequence and the PSS sequence. Length and symbol length.
  • mapping position of the SSS sequence of SSB0 is located before the first PBCH and its DMRS in the time domain.
  • the PBCH of the SSB0 and its DMRS may be located in the first time slot of the 3rd, 4th, 5th and 6th frames in the transmission window, as shown in the area filled with grid lines.
  • mapping rules from SSB1 to SSBn-1 can refer to the relevant description of SSB0, which will not be repeated here.
  • the PBCH of SSB0 and its DMRS may be located in the first time slot of any four frames from the third frame to the eighth frame in the transmission window.
  • a single subframe includes 2 time slots.
  • the PBCH of the SSB0 and its DMRS may be located in the first time slot of the 3rd, 4th, 5th and 6th frames in the transmission window, as shown in the area filled with grid lines.
  • the first index (SSB index) of the synchronization signal block in the synchronization signal block set may be It is not equal to the second index (slot index) of the time slot in a single frame.
  • the PSS sequence of SSB0 can be mapped to the first time slot of the first frame, while the PSS sequence of SSB1 can be mapped to the fourth time slot of the first frame, and the PSS sequence of SSB2 can be mapped to the sixth time slot of the first frame.
  • Time slots correspond to the SSS sequence of SSB0 can be mapped to the first time slot of the second frame, the SSS sequence of SSB1 can be mapped to the fourth time slot of the second frame, and the SSS sequence of SSB2 can be mapped to the sixth time slot of the second frame. Time slots.
  • the PBCH and DMRS of SSB0 can be mapped to the first time slot of the 3rd, 4th, 4th and 6th frames
  • the PBCH and DMRS of SSB1 can be mapped to the 3rd and 4th frames , 4th frame and 6th frame 4th time slot
  • SSB2 PBCH and its DMRS can be mapped to 3rd frame, 4th frame, 4th frame and 6th frame 6th time slot.
  • the number of frames included in the transmission window may not be less than the number of multiple signals or channels included in the i-th synchronization signal block to ensure that each of the i-th synchronization signal block A signal or channel can be mapped to the corresponding frame one by one.
  • the number of frames included in the transmission window is not less than 6.
  • the number of synchronization signal blocks included in the synchronization signal block set may be determined according to the subcarrier spacing and the number of beams.
  • Lmax can take a larger value, because there can be more time slots in a single transmission window, and the mapping image in the transmission window can be referred to the above-mentioned Figure 5 to Figure 10. Show the example to confirm.
  • Narrow Band Internet of Things supports a minimum bandwidth of 180 kHz, and the length of the PSS sequence applied to the Narrow Band Internet of Things is 11 bits.
  • the 11-bit PSS sequence may be repeated 10 times and mapped onto 11 subcarriers and 10 OFDM symbols of one PRB.
  • the length of the SSS sequence applied to the narrowband Internet of Things is 132 bits, and can be mapped to 12 subcarriers and 11 OFDM symbols of one PRB in the step S103.
  • this embodiment provides a synchronization signal block and a set thereof that can support narrowband transmission.
  • the base station for the base station side, it is possible to provide a synchronization signal block set suitable for narrowband transmission to support synchronization signal blocks for multi-beam transmission. Further, by mapping the PSS sequence, SSS sequence, PBCH and DMRS in the same synchronization signal block to the same time slot in different frames, the resulting mapped image can better meet the flexible uplink and downlink time slots in the NR system Configuration to facilitate the transmission of the synchronization signal block set. Specifically, for any kind of uplink and downlink configuration, the base station can easily find the corresponding time-domain transmission position and send the PSS sequence, SSS sequence, PBCH and its DMRS in the synchronization signal block in time and successfully. For example, even if the DL time slot currently configured for the UE in the NR system is not continuous, the solution of this embodiment can still complete the transmission of the synchronization signal block set in time.
  • Fig. 11 is a schematic structural diagram of an apparatus for sending a synchronization signal block according to an embodiment of the present invention.
  • the synchronization signal block sending device 2 (hereinafter referred to as the sending device 2) in this embodiment can be used to implement the method and technical solutions described in the embodiments shown in FIGS. 4 to 10.
  • the sending device 2 of this embodiment may include: an acquisition module 21, configured to acquire a synchronization signal block set to be transmitted, the synchronization signal block set includes n synchronization signal blocks, n is a positive integer; a mapping module 22 , For the i-th synchronization signal block in the synchronization signal block set, map multiple signals or channels included in the i-th synchronization signal block to the same time slot of different frames in the transmission window, and The same signal or channel of different synchronization signal blocks in the synchronization signal block set is located in different time slots of the same frame, where 1 ⁇ i ⁇ n, and the multiple signals or channels are selected from PSS sequence, SSS sequence, PBCH and DMRS thereof; The sending module 23 is configured to send the synchronization signal block set according to the mapping pattern obtained by the mapping within the transmission window.
  • the same signal or channel of different synchronization signal blocks in the synchronization signal block set in different time slots of the same frame may refer to: the PSS sequence of the i-th synchronization signal block and the i-th synchronization signal block.
  • the PSS sequences of +k synchronization signal blocks are respectively located in the i-th time slot and the i+k-th time slot of the same frame; the SSS sequence of the i-th synchronization signal block and the SSS of the i+k-th synchronization signal block
  • the sequences are respectively located in the i-th slot and i+k-th slot in the same frame, where k is a positive integer.
  • the multiple signals or channels included in the i-th synchronization signal block may be in order of time: PSS sequence, PBCH and its DMRS, PBCH and its DMRS, SSS sequence, PBCH and Its DMRS and PBCH and its DMRS.
  • a second mapping sub-module 222 configured to map the SSS sequence to a system frame number determined based on the formula SFN
  • mapping sub-module 221 When the first mapping sub-module 221, the second mapping sub-module 222, and the third mapping sub-module 223 perform their respective operations, they may be executed synchronously or asynchronously.
  • the value of the preset threshold y may be used to make no idle frames exist between frames mapped with adjacent signals or channels.
  • the value of the preset threshold y may be used to make the frame to which the SSS sequence is mapped is the x/2+1th frame.
  • the signals or channels included in the i-th synchronization signal block may be in the order of time: PSS sequence, SSS sequence, PBCH and its DMRS, PBCH and DMRS, PBCH and DMRS And PBCH and its DMRS.
  • mapping sub-module 224 When the fourth mapping sub-module 224, the fifth mapping sub-module 225, and the sixth mapping sub-module 226 perform their respective operations, they may be executed synchronously or asynchronously.
  • the number of frames included in the transmission window may not be less than the number of multiple signals or channels included in the i-th synchronization signal block.
  • the number of synchronization signal blocks included in the synchronization signal block set may be determined according to the subcarrier spacing and the number of beams.
  • Fig. 12 is a flowchart of a method for determining the slot position of a synchronization signal block according to an embodiment of the present invention.
  • the solution of this embodiment can be applied to the narrowband transmission scenario of the NR system.
  • the solution in this embodiment may be applied to the user equipment side, such as executed by the UE.
  • the method for determining the slot position of a synchronization signal block in this embodiment may include the following steps:
  • Step S301 Receive a synchronization signal block set in the transmission window.
  • the synchronization signal block set includes n synchronization signal blocks, where n is a positive integer.
  • the synchronization signal block set is according to the foregoing embodiments shown in FIGS. 4 to 10 Sent by the method;
  • Step S302 Determine the first index of the currently received synchronization signal block among the n synchronization signal blocks;
  • Step S303 Determine the slot position of the currently received synchronization signal block according to the first index and the mapping pattern of the synchronization signal block set in the transmission window.
  • the length T of the transmission window may be predetermined by a protocol.
  • mapping image of the synchronization signal block set in the time domain may be predetermined by a protocol, or may be instructed to the UE in advance by the base station that sends the synchronization signal block set.
  • the UE may predetermine the first index of the synchronization signal block in the synchronization signal block set and the corresponding slot position. Therefore, by executing the steps S301 to S303, the UE can determine its first index according to the received synchronization signal block, and then determine its slot position, thereby completing the timing.
  • the step S302 may include the step of determining the payload according to the received PBCH and its DMRS, and/or the payload of the master information block (Master Information Block, MIB for short) The first index.
  • the master information block Master Information Block, MIB for short
  • all first indexes can be obtained based on the PBCH and its DMRS blind detection.
  • the UE executing the solution described in this embodiment can determine all the PSS sequences after searching for the PSS sequence.
  • the boundary of the transmission window such as the starting position; the length of the time slot, as shown in Figure 5, a PSS sequence occupies the length of a time slot; and the length of the symbol, such as can be determined according to the time-frequency domain mapping method of the PSS sequence .
  • two PBCHs and their DMRS can be received between the PSS sequence and the SSS sequence, and two PBCHs and their DMRS can be received after the SSS sequence.
  • the first index can be determined, and then the slot position of the currently received synchronization signal block can be determined according to the mapping pattern to complete the timing.
  • the UE when the synchronization signal block set is transmitted using the above-mentioned mapping pattern shown in FIG. 7 or FIG. 8, since the start position of the SSS sequence and the PSS sequence divides the transmission window equally, After searching for the PSS sequence and the SSS sequence, the UE can realize the timing of the transmission window and half of the transmission window, and determine the slot length and symbol length.
  • the UE can complete the timing of the synchronization signal block.
  • the UE when the synchronization signal block set is transmitted using the mapping pattern shown in FIG. 9 or FIG. 10, the UE can realize the frame timing after searching for the PSS sequence and the SSS sequence, and determine the time Gap length and symbol length.
  • the UE can complete the timing of the synchronization signal block.
  • the UE can determine the slot position according to the first index of the currently received synchronization signal block in the synchronization signal block set, thereby The received synchronization signal block completes timing for subsequent synchronization operations.
  • FIG. 13 is a schematic structural diagram of an apparatus for determining the position of a time slot of a synchronization signal block according to an embodiment of the present invention.
  • the time slot position determining device 4 of the synchronization signal block described in this embodiment is hereinafter referred to as the time slot position determining device 4) can be used to implement the method and technical solution described in the embodiment shown in FIG. 12.
  • the time slot position determining device 4 may include: a receiving module 41, configured to receive a synchronization signal block set within a transmission window, the synchronization signal block set including n synchronization signal blocks, n Is a positive integer, the synchronization signal block set is sent by the above-mentioned sending device; the first determining module 42 is used to determine the first index of the currently received synchronization signal block in n synchronization signal blocks; the second determining module 43 , Used to determine the slot position of the currently received synchronization signal block according to the first index and the mapping pattern of the synchronization signal block set in the transmission window.
  • the first determining module 42 may include: a determining sub-module 421 configured to determine the first index according to the received PBCH and its DMRS, and/or the load of the MIB.
  • the embodiment of the present invention also discloses a storage medium on which computer instructions are stored, and when the computer instructions are run, the method and technical solutions described in the embodiments shown in FIGS. 4 to 10 and 12 are executed.
  • the storage medium may include a computer-readable storage medium such as a non-volatile memory or a non-transitory memory.
  • the storage medium may include ROM, RAM, magnetic disk or optical disk, etc.
  • an embodiment of the present invention also discloses a terminal, including a memory and a processor, the memory stores computer instructions that can run on the processor, and the processor executes the above diagram when the computer instructions are executed. 12 shows the technical solution of the method described in the embodiment.
  • the terminal may be a 5G user terminal.
  • an embodiment of the present invention also discloses a base station, including a memory and a processor, the memory stores computer instructions that can run on the processor, and the processor executes the above diagram when the computer instructions are executed. 4 to the technical solution of the method described in the embodiment shown in FIG. 10.
  • the base station may be a gNB.

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Abstract

一种同步信号块的发送、时隙位置确定方法及装置、存储介质、基站、终端,发送方法包括:获取待发送的同步信号块集合,包括n个同步信号块;对于第i个同步信号块,将第i个同步信号块包括的多个信号或信道分别映射至传输窗口内不同帧的同一时隙,并且,同步信号块集合中不同同步信号块的同一信号或信道位于相同帧的不同时隙;在所述传输窗口内,根据映射得到的映射图样发送所述同步信号块集合。通过本发明方案能够提供一种适用于窄带传输的同步信号块集合,以支持多波束传输的同步信号块。进一步地,考虑到NR系统中灵活的上下行时隙配置,本发明方案提供一种更合理的时域同步信号块的映射图样,能够便利同步信号块集合的传输。

Description

同步信号块的发送、时隙位置确定方法及装置、存储介质、基站、终端
本申请要求于2019年7月25日提交中国专利局、申请号为201910676286.8、发明名称为“同步信号块的发送、时隙位置确定方法及装置、存储介质、基站、终端”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
技术领域
本发明涉及通信技术领域,具体地涉及一种同步信号块的发送、时隙位置确定方法及装置、存储介质、基站、终端。
背景技术
第三代合作伙伴计划(3rd Generation Partnership Project,简称3GPP)新空口(New Radio,简称NR,也可称为新无线)系统中,在时域长度为10毫秒(millisecond,简称ms)的无线帧内,每个无线帧被分为10个同样大小的长度为1ms的子帧,随着子载波间隔不同,每个子帧可包含多个时隙。其中,每个时隙由一定数量的符号构成,且符号数量由循环前缀(Cyclic Prefix,简称CP)类型决定。
另一方面,NR系统支持多波束的同步信号块(Synchronization Signal/Physical Broadcast Channel Block,简称SS/PBCH BLOCK,也即,SSB)传输,其中,同步信号块包括主同步信号(Primary Synchronization Signal,简称PSS)序列、辅同步信号(Secondary Synchronization Signal,简称SSS)序列和物理广播信道(Physical Broadcast Channel,简称PBCH)及其解调参考信号(Demodulation Reference Signal,简称DMRS)。
现有技术在将同步信号块映射至时隙时在时域上通常是连续的,但由于NR系统支持灵活的上行(Uplink,简称UL)时隙和下行(Downlink,简称DL)时隙配置,无法保证连续的多个时隙均可以用于传输同步信号块,这就导致现有的同步信号块传输方式无法良好适应NR系统的灵活时隙配置。
发明内容
本发明解决的技术问题是如何提供一种新的同步信号块映射图样,以满足NR系统中灵活的上下行时隙配置,便利同步信号块集合的传输。
为解决上述技术问题,本发明实施例提供一种同步信号块的发送方法,包括:获取待发送的同步信号块集合,所述同步信号块集合包括n个同步信号块,n为正整数;对于所述同步信号块集合中的第i个同步信号块,将所述第i个同步信号块包括的多个信号或信道分别映射至传输窗口内不同帧的同一时隙,并且,所述同步信号块集合中不同同步信号块的同一信号或信道位于相同帧的不同时隙,其中,1≤i≤n,所述多个信号或信道选自PSS序列、SSS序列、PBCH及其DMRS;在所述传输窗口内,根据映射得到的映射图样发送所述同步信号块集合。
可选的,所述同步信号块集合中不同同步信号块的同一信号或信道位于相同帧的不同时隙是指:所述第i个同步信号块的PSS序列和第i+k个同步信号块的PSS序列分别位于同一帧的第i个时隙和第i+k个时隙;所述第i个同步信号块的SSS序列和第i+k个同步信号块的SSS序列分别位于同一帧的第i个时隙和第i+k个时隙,其中,k为正整数。
可选的,所述第i个同步信号块包括的多个信号或信道按时间先后顺序依次为:PSS序列、PBCH及其DMRS、PBCH及其DMRS、SSS序列、PBCH及其DMRS和PBCH及其DMRS。
可选的,所述将所述第i个同步信号块包括的多个信号或信道分别映射至传输窗口内不同帧的同一时隙包括:将所述PSS序列映射至基于公式SFNmodx=0确定的系统帧号,其中,SFN为所述系统帧号,x为所述传输窗口包括的帧数;将所述SSS序列映射至基于公式SFNmodx=y确定的系统帧号,其中,y为预设阈值;将所述PBCH及其DMRS依序映射至传输窗口内除映射有PSS序列和SSS序列的帧之外的其他帧。
可选的,所述预设阈值y的取值用于使得映射有相邻信号或信道的帧之间不存在空闲帧。
可选的,所述预设阈值y的取值用于使得映射有SSS序列的帧为第x/2+1个帧。
可选的,所述第i个同步信号块包括的信号或信道按时间先后顺序依次为:PSS序列、SSS序列、PBCH及其DMRS、PBCH及其DMRS、PBCH及其DMRS和PBCH及其DMRS。
可选的,所述将所述第i个同步信号块包括的多个信号或信道分别映射至传输窗口内不同帧的同一时隙包括:将所述PSS序列映射至基于公式SFNmodx=0确定的系统帧号,其中,SFN为所述系统帧号,x为所述传输窗口包括的帧数;将所述SSS序列映射至基于公式SFNmodx=1确定的系统帧号;将所述PBCH及其DMRS依序映射至传输窗口内除映射有PSS序列和SSS序列的帧之外的其他帧。
可选的,所述传输窗口包括的帧数不小于所述第i个同步信号块包括的多个信号或信道的数量。
可选的,所述同步信号块集合包括的同步信号块的数量是根据子载波间隔和波束数量确定的。
为解决上述技术问题,本发明实施例还提供一种同步信号块的时隙位置确定方法,包括:在传输窗口内接收同步信号块集合,所述同步信号块集合包括n个同步信号块,n为正整数,所述同步信号块集 合是按照上述方法发送的;确定当前接收到的同步信号块在n个同步信号块中的第一索引;根据所述第一索引以及所述同步信号块集合在所述传输窗口内的映射图样确定所述当前接收到的同步信号块的时隙位置。
可选的,所述确定当前接收到的同步信号块在n个同步信号块中的第一索引包括:根据接收到的所述PBCH及其DMRS,和/或MIB的负荷确定所述第一索引。
为解决上述技术问题,本发明实施例还提供一种同步信号块的发送装置,包括:获取模块,用于获取待发送的同步信号块集合,所述同步信号块集合包括n个同步信号块,n为正整数;映射模块,对于所述同步信号块集合中的第i个同步信号块,将所述第i个同步信号块包括的多个信号或信道分别映射至传输窗口内不同帧的同一时隙,并且,所述同步信号块集合中不同同步信号块的同一信号或信道位于相同帧的不同时隙,其中,1≤i≤n,所述多个信号或信道选自PSS序列、SSS序列、PBCH及其DMRS;发送模块,用于在所述传输窗口内,根据映射得到的映射图样发送所述同步信号块集合。
为解决上述技术问题,本发明实施例还提供一种同步信号块的时隙位置确定装置,包括:接收模块,用于在传输窗口内接收同步信号块集合,所述同步信号块集合包括n个同步信号块,n为正整数,所述同步信号块集合是上述发送装置发送的;第一确定模块,用于确定当前接收到的同步信号块在n个同步信号块中的第一索引;第二确定模块,用于根据所述第一索引以及所述同步信号块集合在所述传输窗口内的映射图样确定所述当前接收到的同步信号块的时隙位置。
为解决上述技术问题,本发明实施例还提供一种存储介质,其上存储有计算机指令,所述计算机指令运行时执行上述方法的步骤。
为解决上述技术问题,本发明实施例还提供一种基站,包括存储器和处理器,所述存储器上存储有能够在所述处理器上运行的计算机指令,所述处理器运行所述计算机指令时执行上述方法的步骤。
为解决上述技术问题,本发明实施例还提供一种终端,包括存储器和处理器,所述存储器上存储有能够在所述处理器上运行的计算机指令,所述处理器运行所述计算机指令时执行上述方法的步骤。
与现有技术相比,本发明实施例的技术方案具有以下有益效果:
对于基站侧,本发明实施例提供一种同步信号块的发送方法,包括:获取待发送的同步信号块集合,所述同步信号块集合包括n个同步信号块,n为正整数;对于所述同步信号块集合中的第i个同步信号块,将所述第i个同步信号块包括的多个信号或信道分别映射至传输窗口内不同帧的同一时隙,并且,所述同步信号块集合中不同同步信号块的同一信号或信道位于相同帧的不同时隙,其中,1≤i≤n,所述多个信号或信道选自PSS序列、SSS序列、PBCH及其DMRS;在所述传输窗口内,根据映射得到的映射图样发送所述同步信号块集合。
采用本实施例的方案,能够提供一种适用于窄带传输的同步信号块集合,以支持多波束传输的同步信号块。进一步地,通过将同一同步信号块中的PSS序列、SSS序列和PBCH及其DMRS映射至不同帧的同一时隙,使得最终得到的映射图像能够更好的满足NR系统中灵活的上下行时隙配置,便利同步信号块集合的传输。具体而言,针对任一种上下行配置,基站均可以方便地找到对应的时域发送位置将同步信号块中的PSS序列、SSS序列和PBCH及其DMRS及时、成功发送完毕。例如,即使NR系统当前针对UE配置的DL时隙不连续,采用本实施例的方案仍能够及时完成同步信号块集合的传输。
对于UE侧,本发明实施例提供一种同步信号块的时隙位置确定方法,包括:在传输窗口内接收同步信号块集合,所述同步信号块集合包括n个同步信号块,n为正整数,所述同步信号块集合是按照上述方法发送的;确定当前接收到的同步信号块在n个同步信号块中的第一索引;根据所述第一索引以及所述同步信号块集合在所述传输窗口内的映射图样确定所述当前接收到的同步信号块的时隙位置。采用 本实施例的方案,结合预先获知的映射图样,UE可以根据当前接收到的同步信号块在所述同步信号块集合内的第一索引确定时隙位置,从而根据接收到的同步信号块完成定时,以便后续进行同步操作。
附图说明
图1是现有技术的一种同步信号块的示意图;
图2是现有技术的一种同步信号块在不同子载波间隔的时域映射示意图;
图3是现有技术的一种同步信号块在单个时隙内的位置示意图;
图4是本发明实施例的一种同步信号块的发送方法的流程图;
图5是本发明实施例所述同步信号块的第一种映射图样示意图;
图6是本发明实施例所述同步信号块的第二种映射图样示意图;
图7是本发明实施例所述同步信号块的第三种映射图样示意图;
图8是本发明实施例所述同步信号块的第四种映射图样示意图;
图9是本发明实施例所述同步信号块的第五种映射图样示意图;
图10是本发明实施例所述同步信号块的第六种映射图样示意图;
图11是本发明实施例的一种同步信号块的发送装置的结构示意图;
图12是本发明实施例的一种同步信号块的时隙位置确定方法的流程图;
图13是本发明实施例的一种同步信号块的时隙位置确定装置的结构示意图。
具体实施方式
如背景技术所言,现有的同步信号块传输方式无法良好适应NR系统的灵活时隙配置。
具体而言,参考图1,现有的同步信号块由4个正交频分复用(Orthogonal Frequency Division Multiplexing,简称OFDM)符号构成。其中,PSS序列11和SSS序列12分别占1个OFDM符号,PBCH及其DMRS13占2个OFDM符号。
PBCH及其DMRS13可以占据多个时隙(slot),PSS序列11和SSS序列12各占一个时隙。例如,参考图1,PSS序列11可以占据12个物理资源块(Physical Resource Block,简称PRB),SSS序列12可以占据12个PRB,PBCH及其DMRS可以占据20+4+4+20=48个PRB。
进一步地,同步信号块位于5ms内的位置与子载波间隔(Subcarrier Spacing,简称SCS)和波束数量L有关。
例如,参考图2,5ms周期内可以发送同步信号块的时隙的位置如图中交叉条纹填充区域所示。
当SCS=15kHz,L=4、8时,时隙长度等于子帧长度。此时,在5ms周期内同步信号块可以连续映射至前4个时隙。
当SCS=30kHz,L=4、8时,时隙长度等于1/2个子帧长度。此时,在5ms周期内同步信号块可以连续映射至前4个时隙。
以此类推,当SCS=120kHz,L=64时,以及,当SCS=240kHz,L=64时,同步信号块的可发送位置分别如对应图例所示。
其中,每一时隙中同步信号块的位置可以具有5种情况,如图3所示。具体而言,按照不同的SCS,时隙的长度不相同,可发送的同步信号块的数量和位置也不相同。图3中以网格线填充的区域表示发送同步信号块的位置。
进一步而言,多个同步信号块可以构成同步信号块集合,所述同步信号块集合内最大可以发送的同步信号块的数量记为Lmax,实际发送的同步信号块的数量L可以小于Lmax。
对于方案A(Case A),对应15kHz的子载波间隔:候选同步信号块的第一个时域符号位于{2,8}+14*n,当载波频率小于等于3GHz时,n=0,1;当载波频率小于等于6GHz时,n=0,1,2,3。
对于方案B(Case B),对应30kHz的子载波间隔:候选同步信号块的第一个时域符号位于{4,8,16,20}+28*n,当载波频率小于等于3GHz时,n=0;当载波频率小于等于6GHz时,n=0,1。
对于方案C(Case C),对应30kHz子载波间隔:候选同步信号块的第一个时域符号位于{2,8}+14*n,当载波频率小于等于3GHz时,n=0,1;当载波频率小于等于6GHz时,n=0,1,2,3。
对于方案D(Case D),对应120kHz的子载波间隔:候选同步信号块的第一个时域符号位于{4,8,16,20}+28*n。当载波频率大于6GHz时,n=0,1,2,3,5,6,7,8,10,11,12,13,15,16,17,18。
对于方案E(Case E),对应240kHz的子载波间隔:候选同步信号块的第一个时域符号位于{8,12,16,20,32,36,40,44}+56*n。当载波频率大于6GHz时,n=0,1,2,3,5,6,7,8。
可见,现有技术在发送同步信号块时,在时域上都是连续发送的,但由于NR系统支持灵活的上下行时隙配置,无法保证连续的多个时隙均可以用于传输同步信号块,这就导致现有的同步信号块传输方式无法良好适应NR系统的灵活时隙配置。
为解决上述技术问题,本发明实施例提供一种同步信号块的发送方法,包括:获取待发送的同步信号块集合,所述同步信号块集合包括n个同步信号块,n为正整数;对于所述同步信号块集合中的第i个同步信号块,将所述第i个同步信号块包括的多个信号或信道分别映射至传输窗口内不同帧的同一时隙,并且,所述同步信号块集合中 不同同步信号块的同一信号或信道位于相同帧的不同时隙,其中,1≤i≤n,所述多个信号或信道选自PSS序列、SSS序列、PBCH及其DMRS;在所述传输窗口内,根据映射得到的映射图样发送所述同步信号块集合。
采用本实施例的方案,能够提供一种适用于窄带传输的同步信号块集合,以支持多波束传输的同步信号块。进一步地,通过将同一同步信号块中的PSS序列、SSS序列和PBCH及其DMRS映射至不同帧的同一时隙,使得最终得到的映射图像能够更好的满足NR系统中灵活的上下行时隙配置,便利同步信号块集合的传输。具体而言,针对任一种上下行配置,基站均可以方便地找到对应的时域发送位置将同步信号块中的PSS序列、SSS序列和PBCH及其DMRS及时、成功发送完毕。例如,即使NR系统当前针对UE配置的DL时隙不连续,采用本实施例的方案仍能够及时完成同步信号块集合的传输。
为使本发明的上述目的、特征和有益效果能够更为明显易懂,下面结合附图对本发明的具体实施例做详细的说明。
图4是本发明实施例的一种同步信号块的发送方法的流程图。本实施例的方案可以应用于NR系统的窄带传输场景。本实施例的方案可以应用于网络侧,如由网络侧的基站(gNB)执行。
具体地,参考图1,本实施例所述同步信号块的发送方法可以包括如下步骤:
步骤S101,获取待发送的同步信号块集合,所述同步信号块集合包括n个同步信号块,n为正整数;
步骤S102,对于所述同步信号块集合中的第i个同步信号块,将所述第i个同步信号块包括的多个信号或信道分别映射至传输窗口内不同帧的同一时隙,并且,所述同步信号块集合中不同同步信号块的同一信号或信道位于相同帧的不同时隙,其中,1≤i≤n,所述多个信号或信道选自PSS序列、SSS序列、PBCH及其DMRS;
步骤S103,在所述传输窗口内,根据映射得到的映射图样发送所述同步信号块集合。
更为具体地,对于同一同步信号块,所述同步信号块包含的PSS序列、SSS序列、PBCH及其DMRS在时域上不再是连续发送的,而是被分别映射至不同帧的相同时隙内,以灵活适应NR系统的上下行配置。
进一步地,所述同步信号块集合中不同同步信号块的同一信号或信道位于相同帧的不同时隙可以是指:所述第i个同步信号块的PSS序列和第i+k个同步信号块的PSS序列分别位于同一帧的第i个时隙和第i+k个时隙;所述第i个同步信号块的SSS序列和第i+k个同步信号块的SSS序列分别位于同一帧的第i个时隙和第i+k个时隙,其中,k为正整数。
也即,所述传输窗口内的特定帧可以专用于传输所述同步信号块集合的所有同步信号块的同一信号或信道。同时,由于不同同步信号块的同一信号或信道映射至同一帧的不同时隙,能够避免不同同步信号块之间的映射冲突。
进一步地,所述传输窗口的长度可以根据协议确定,基站需要在所述传输窗口内完成同步信号块的发送操作,相应的,UE需要在所述传输窗口内完成同步信号块的接收操作。
在一个非限制性实施例中,k可以为预设数值,如可以由协议规定。例如,k可以等于1。
在一个非限制性实施例中,所述第i个同步信号块包括的多个信号或信道按时间先后顺序可以依次为:PSS序列、PBCH及其DMRS、PBCH及其DMRS、SSS序列、PBCH及其DMRS和PBCH及其DMRS。也即,所述第i个同步信号块可以是以前述结构在时域上进行发送的。
进一步地,所述步骤S102可以包括步骤:将所述PSS序列映射至基于公式SFNmodx=0确定的系统帧号,其中,SFN为所述系统帧 号,x为所述传输窗口包括的帧数;将所述SSS序列映射至基于公式SFNmodx=y确定的系统帧号,其中,mod函数为取余函数,y为预设阈值;将所述PBCH及其DMRS依序映射至传输窗口内除映射有PSS序列和SSS序列的帧之外的其他帧。
在一个非限制性实施例中,所述预设阈值y的取值可以用于使得映射有相邻信号或信道的帧之间不存在空闲帧。
以所述传输窗口的长度T=80ms,SCS=15kHz为例,参考图5,假设同步信号块集合(SSB burst)为{SSB0,SSB1,…,SSBn-1},一共有n个同步信号块。Lmax=4、8,相应的,n=4、8。
在本示例中,所述传输窗口的长度T=80ms,每一帧的长度为10ms,可以得到帧数x=8个。
假设k=1,也即,第1个SSB(即SSB0)位于每一帧的第1个时隙,第2个SSB(即SSB1)位于每一帧的第2个时隙,以此类推,第n个SSB(即SSBn-1)位于每一帧的第n个时隙。
对于SSB0,SSB0的PSS序列可以位于所述传输窗口内的第1帧的第1个时隙,即SFNmod8=0的位置,如图中斜线填充区域。
在本示例中,由于PSS序列是固定映射至所述传输窗口内的第1帧的,按照PSS序列、PBCH及其DMRS、PBCH及其DMRS、SSS序列、PBCH及其DMRS和PBCH及其DMRS的映射顺序,在SSS序列之前需要用两帧分别发送两个PBCH及其DMRS,因而,为使得发送SSS序列之前不存在空闲帧,所述预设阈值y优选地为3。
也即,SSB0的SSS序列可以位于所述传输窗口内的第4帧的第1个时隙,即SFNmod8=3的位置,如图中横线填充区域。
SSB0的PBCH及其DMRS分别位于所述传输窗口内的第2帧、第3帧、第5帧和第6帧的第1个时隙,如图中网格线填充的区域。
对于SSB1,与前述SSB0的映射规则相类似,SSB1的PSS序列 可以位于所述传输窗口内的第1帧的第2个时隙(图未示);SSB1的SSS序列可以位于所述传输窗口内的第4帧的第2个时隙(图未示);SSB1的PBCH及其DMRS分别位于所述传输窗口内的第2帧、第3帧、第5帧和第6帧的第2个时隙(图未示)。
依次类推,对于SSBn-1,所述SSBn-1的PSS序列可以位于所述传输窗口内的第1帧的第n个时隙(图未示);SSB n-1的SSS序列可以位于所述传输窗口内的第4帧的第n个时隙(图未示);SSB n-1的PBCH及其DMRS分别位于所述传输窗口内的第2帧、第3帧、第5帧和第6帧的第n个时隙(图未示)。
以所述传输窗口的长度T=80ms,SCS=30kHz为例,参考图6,与上述图5所示示例的区别在于:单个子帧内包括2个时隙。
对于SSB0,SSB0的PSS序列可以位于所述传输窗口内的第1帧的第1个时隙,即SFNmod8=0的位置,如图中斜线填充区域。
SSB0的SSS序列可以位于所述传输窗口内的第4帧的第1个时隙,即SFNmod8=3的位置,如图中横线填充区域。
SSB0的PBCH及其DMRS分别位于所述传输窗口内的第2帧、第3帧、第5帧和第6帧的第1个时隙,如图中网格线填充的区域。
类似的,SSB1的PSS序列映射至第1帧的第2个时隙、SSS序列映射至第4帧的第2个时隙、PBCH及其DMRS分别映射至第2帧、第3帧、第5帧和第6帧的第2个时隙。
在图6所示示例的一个变化例中,由于单个帧内的时隙数量大于同步信号块的数量n,因而,同步信号块在所述同步信号块集合内的第一索引(SSB index)可以不等于时隙在单个帧内的第二索引(slot index)。
例如,SSB0的PSS序列可以映射至第1帧的第1个时隙,而SSB1的PSS序列可以映射至第1帧的第3个时隙,SSB2的PSS序列可以映射至第1帧的第4个时隙。相应的,SSB0的SSS序列可以映射至 第4帧的第1个时隙,SSB1的SSS序列可以映射至第4帧的第3个时隙,SSB2的SSS序列可以映射至第4帧的第4个时隙。相应的,SSB0的PBCH及其DMRS可以映射至第2帧、第3帧、第5帧和第6帧的第1个时隙,SSB1的PBCH及其DMRS可以映射至第2帧、第3帧、第5帧和第6帧的第3个时隙,SSB2的PBCH及其DMRS可以映射至第2帧、第3帧、第5帧和第6帧的第4个时隙。
在另一个非限制性实施例中,所述预设阈值y的取值可以用于使得映射有SSS序列的帧为第x/2+1个帧。也即,通过合理设计所述预设阈值y的具体数值,使得PSS序列和SSS序列的起始位置能够将所述传输窗口均分,对于UE而言,这样的映射图样使得UE能够直接获得T和T/2的定时、时隙长度以及符号长度。
仍以所述传输窗口的长度T=80ms,SCS=15kHz为例,参考图7,接下来仅针对与上述图5所示示例的区别之处进行具体阐述。
仍以SSB0为例,SSB0的PSS序列仍可以位于所述传输窗口内的第1帧的第1个时隙,即SFNmod8=0的位置,如图中斜线填充区域。
本示例与上述图5所示示例的区别在于,为使SSS序列映射至传输窗口的中间位置,所述预设阈值y优选地为4。
也即,对于包含8帧的所述传输窗口,SSB0的SSS序列可以位于所述传输窗口内的第5帧的第1个时隙,即SFNmod8=4的位置,如图中横线填充区域。
按照PSS序列、PBCH及其DMRS、PBCH及其DMRS、SSS序列、PBCH及其DMRS和PBCH及其DMRS的映射顺序,SSB0的PBCH及其DMRS位于所述传输窗口内的第2帧、第4帧、第6帧和第8帧的第1个时隙,如图中网格线填充的区域。
或者,SSB0的PBCH及其DMRS也可以位于所述传输窗口内的第2帧、第3帧、第6帧和第7帧的第1个时隙。
SSB1至SSBn-1的映射规则可以参照SSB0的相关描述,在此不与赘述。
以所述传输窗口的长度T=80ms,SCS=30kHz为例,参考图8,与上述图7所示示例的区别在于:单个子帧内包括2个时隙。
对于SSB0,SSB0的PSS序列可以位于所述传输窗口内的第1帧的第1个时隙,即SFNmod8=0的位置,如图中斜线填充区域。
SSB0的SSS序列可以位于所述传输窗口内的第5帧的第1个时隙,即SFNmod8=4的位置,如图中横线填充区域。
SSB0的PBCH及其DMRS分别位于所述传输窗口内的第2帧、第4帧、第6帧和第8帧的第1个时隙,如图中网格线填充的区域。
类似的,SSB1的PSS序列映射至第1帧的第2个时隙、SSS序列映射至第5帧的第2个时隙、PBCH及其DMRS分别映射至第2帧、第4帧、第6帧和第8帧的第2个时隙。
在图8所示示例的一个变化例中,由于单个帧内的时隙数量大于同步信号块的数量n,因而,同步信号块在所述同步信号块集合内的第一索引(SSB index)可以不等于时隙在单个帧内的第二索引(slot index)。
例如,SSB0的PSS序列可以映射至第1帧的第1个时隙,而SSB1的PSS序列可以映射至第1帧的第2个时隙,SSB2的PSS序列可以映射至第1帧的第5个时隙。相应的,SSB0的SSS序列可以映射至第5帧的第1个时隙,SSB1的SSS序列可以映射至第5帧的第2个时隙,SSB2的SSS序列可以映射至第5帧的第5个时隙。相应的,SSB0的PBCH及其DMRS可以映射至第2帧、第4帧、第6帧和第8帧的第1个时隙,SSB1的PBCH及其DMRS可以映射至第2帧、第4帧、第6帧和第8帧的第2个时隙,SSB2的PBCH及其DMRS可以映射至第2帧、第4帧、第6帧和第8帧的第5个时隙。
在又一个非限制性实施例中,所述第i个同步信号块包括的信号 或信道按时间先后顺序可以依次为:PSS序列、SSS序列、PBCH及其DMRS、PBCH及其DMRS、PBCH及其DMRS和PBCH及其DMRS。也即,SSS序列的映射位置可以位于所有PBCH及其DMRS之前。由此,PSS序列和SSS序列的起始位置能够直接定义所述传输窗口内单个帧的长度,对于UE而言,这样的映射图样使得UE能够根据SSS序列和PSS序列直接得到帧定时、时隙长度以及符号长度。
进一步地,所述步骤S102可以包括步骤:将所述PSS序列映射至基于公式SFNmodx=0确定的系统帧号,其中,SFN为所述系统帧号,x为所述传输窗口包括的帧数;将所述SSS序列映射至基于公式SFNmodx=1确定的系统帧号;将所述PBCH及其DMRS依序映射至传输窗口内除映射有PSS序列和SSS序列的帧之外的其他帧。
仍以所述传输窗口的长度T=80ms,SCS=15kHz为例,参考图9,接下来仅针对与上述图5和图7所示示例的区别之处进行具体阐述。
仍以SSB0为例,SSB0的PSS序列仍可以位于所述传输窗口内的第1帧的第1个时隙,即SFNmod8=0的位置,如图中斜线填充区域。
本示例与上述图5和图7所示示例的区别在于,SSB0的SSS序列的映射位置在时域上位于第一个PBCH及其DMRS之前。
也即,SSB0的SSS序列可以位于所述传输窗口内的第2帧的第1个时隙,即SFNmod8=1的位置,如图中横线填充区域。
SSB0的PBCH及其DMRS可以位于所述传输窗口内的第3帧、第4帧、第5帧和第6帧的第1个时隙,如图中网格线填充的区域。
SSB1至SSBn-1的映射规则可以参照SSB0的相关描述,在此不与赘述。
或者,SSB0的PBCH及其DMRS可以位于所述传输窗口内的第3帧至第8帧中任意四帧的第1个时隙。
以所述传输窗口的长度T=80ms,SCS=30kHz为例,参考图10,与上述图9所示示例的区别在于:单个子帧内包括2个时隙。
对于SSB0,SSB0的PSS序列仍可以位于所述传输窗口内的第1帧的第1个时隙,即SFNmod8=0的位置,如图中斜线填充区域。
SSB0的SSS序列可以位于所述传输窗口内的第2帧的第1个时隙,即SFNmod8=1的位置,如图中横线填充区域。
SSB0的PBCH及其DMRS可以位于所述传输窗口内的第3帧、第4帧、第5帧和第6帧的第1个时隙,如图中网格线填充的区域。
在图10所示示例的一个变化例中,由于单个帧内的时隙数量大于同步信号块的数量n,因而,同步信号块在所述同步信号块集合内的第一索引(SSB index)可以不等于时隙在单个帧内的第二索引(slot index)。
例如,SSB0的PSS序列可以映射至第1帧的第1个时隙,而SSB1的PSS序列可以映射至第1帧的第4个时隙,SSB2的PSS序列可以映射至第1帧的第6个时隙。相应的,SSB0的SSS序列可以映射至第2帧的第1个时隙,SSB1的SSS序列可以映射至第2帧的第4个时隙,SSB2的SSS序列可以映射至第2帧的第6个时隙。相应的,SSB0的PBCH及其DMRS可以映射至第3帧、第4帧、第4帧和第6帧的第1个时隙,SSB1的PBCH及其DMRS可以映射至第3帧、第4帧、第4帧和第6帧的第4个时隙,SSB2的PBCH及其DMRS可以映射至第3帧、第4帧、第4帧和第6帧的第6个时隙。
在一个非限制性实施例中,所述传输窗口包括的帧数可以不小于所述第i个同步信号块包括的多个信号或信道的数量,以确保所述第i个同步信号块的每一信号或信道均能一一映射至对应的帧上。
例如,当所述同步信号块包括一个PSS序列、一个SSS序列和四个PBCH及其DMRS时,所述传输窗口包括的帧数不小于6个。
在一个非限制性实施例中,所述同步信号块集合包括的同步信号 块的数量可以是根据子载波间隔和波束数量确定的。
当SCS为120kHz、240kHz甚至更大时,Lmax可以取更大的值,因为单个传输窗口内可以有更多的时隙,在所述传输窗口内的映射图像可以参考上述图5至图10所示示例确定。
在一个非限制性实施例中,窄带物联网(Narrow Band Internet of Things,简称NB-IoT)支持最小180kHz带宽,应用于窄带物联网的PSS序列的长度为11位。
在所述步骤S103中,可以将该11位的PSS序列重复10次映射到一个PRB的11个子载波10个OFDM符号上。
类似的,应用于窄带物联网的SSS序列的长度为132位,在所述步骤S103中可以映射到一个PRB的12个子载波11个OFDM符号上。
较之现有技术中只有当带宽大于20个资源块(Resource Block,简称RB)时才能进行数据接收,采用本实施例的方案,带宽只需大于1个RB就能够进行同步信号块的接收。由此,本实施例提供了一种可支持窄带传输的同步信号块及其集合。
由上,采用本实施例的方案,对于基站侧,能够提供一种适用于窄带传输的同步信号块集合,以支持多波束传输的同步信号块。进一步地,通过将同一同步信号块中的PSS序列、SSS序列和PBCH及其DMRS映射至不同帧的同一时隙,使得最终得到的映射图像能够更好的满足NR系统中灵活的上下行时隙配置,便利同步信号块集合的传输。具体而言,针对任一种上下行配置,基站均可以方便地找到对应的时域发送位置将同步信号块中的PSS序列、SSS序列和PBCH及其DMRS及时、成功发送完毕。例如,即使NR系统当前针对UE配置的DL时隙不连续,采用本实施例的方案仍能够及时完成同步信号块集合的传输。
图11是本发明实施例的一种同步信号块的发送装置的结构示意 图。本领域技术人员理解,本实施例所述同步信号块的发送装置2(以下简称为发送装置2)可以用于实施上述图4至图10所示实施例中所述的方法技术方案。
具体地,本实施例所述发送装置2可以包括:获取模块21,用于获取待发送的同步信号块集合,所述同步信号块集合包括n个同步信号块,n为正整数;映射模块22,对于所述同步信号块集合中的第i个同步信号块,将所述第i个同步信号块包括的多个信号或信道分别映射至传输窗口内不同帧的同一时隙,并且,所述同步信号块集合中不同同步信号块的同一信号或信道位于相同帧的不同时隙,其中,1≤i≤n,所述多个信号或信道选自PSS序列、SSS序列、PBCH及其DMRS;发送模块23,用于在所述传输窗口内,根据映射得到的映射图样发送所述同步信号块集合。
在一个非限制性实施例中,所述同步信号块集合中不同同步信号块的同一信号或信道位于相同帧的不同时隙可以是指:所述第i个同步信号块的PSS序列和第i+k个同步信号块的PSS序列分别位于同一帧的第i个时隙和第i+k个时隙;所述第i个同步信号块的SSS序列和第i+k个同步信号块的SSS序列分别位于同一帧的第i个时隙和第i+k个时隙,其中,k为正整数。
在一个非限制性实施例中,所述第i个同步信号块包括的多个信号或信道按时间先后顺序可以依次为:PSS序列、PBCH及其DMRS、PBCH及其DMRS、SSS序列、PBCH及其DMRS和PBCH及其DMRS。
进一步地,所述映射模块22可以包括:第一映射子模块221,用于将所述PSS序列映射至基于公式SFNmodx=0确定的系统帧号,其中,SFN为所述系统帧号,x为所述传输窗口包括的帧数;第二映射子模块222,用于将所述SSS序列映射至基于公式SFNmodx=y确定的系统帧号,其中,y为预设阈值;第三映射子模块223,用于将所述PBCH及其DMRS依序映射至传输窗口内除映射有PSS序列和SSS序列的帧之外的其他帧。
所述第一映射子模块221、第二映射子模块222和第三映射子模块223执行各自的操作时,可以是同步执行的,或者,也可以是异步执行的。
在一个非限制性实施例中,所述预设阈值y的取值可以用于使得映射有相邻信号或信道的帧之间不存在空闲帧。
在一个非限制性实施例中,所述预设阈值y的取值可以用于使得映射有SSS序列的帧为第x/2+1个帧。
在一个非限制性实施例中,所述第i个同步信号块包括的信号或信道按时间先后顺序可以依次为:PSS序列、SSS序列、PBCH及其DMRS、PBCH及其DMRS、PBCH及其DMRS和PBCH及其DMRS。
进一步地,所述映射模块22可以包括:第四映射子模块224,用于将所述PSS序列映射至基于公式SFNmodx=0确定的系统帧号,其中,SFN为所述系统帧号,x为所述传输窗口包括的帧数;第五映射子模块225,用于将所述SSS序列映射至基于公式SFNmodx=1确定的系统帧号;第六映射子模块226,用于将所述PBCH及其DMRS依序映射至传输窗口内除映射有PSS序列和SSS序列的帧之外的其他帧。
所述第四映射子模块224、第五映射子模块225和第六映射子模块226执行各自的操作时,可以是同步执行的,或者,也可以是异步执行的。
在一个非限制性实施例中,所述传输窗口包括的帧数可以不小于所述第i个同步信号块包括的多个信号或信道的数量。
在一个非限制性实施例中,所述同步信号块集合包括的同步信号块的数量可以是根据子载波间隔和波束数量确定的。
关于所述发送装置2的工作原理、工作方式的更多内容,可以参照上述图4至图10中的相关描述,这里不再赘述。
图12是本发明实施例的一种同步信号块的时隙位置确定方法的流程图。本实施例的方案可以应用于NR系统的窄带传输场景。本实施例的方案可以应用于用户设备侧,如由UE执行。
具体地,参考图12,本实施例所述同步信号块的时隙位置确定方法可以包括如下步骤:
步骤S301,在传输窗口内接收同步信号块集合,所述同步信号块集合包括n个同步信号块,n为正整数,所述同步信号块集合是按照上述图4至图10所示实施例中所述方法发送的;
步骤S302,确定当前接收到的同步信号块在n个同步信号块中的第一索引;
步骤S303,根据所述第一索引以及所述同步信号块集合在所述传输窗口内的映射图样确定所述当前接收到的同步信号块的时隙位置。
更为具体地,所述传输窗口的长度T可以由协议预先确定。
进一步地,所述同步信号块集合在时域上的映射图像可以由协议预先确定,或者,由发送所述同步信号块集合的基站预先指示给UE。
根据所述映射图像,UE可以预先确定所述同步信号块集合中的同步信号块的第一索引以及对应的时隙位置。由此,通过执行所述步骤S301至步骤S303,UE能够根据接收到的同步信号块确定其第一索引,进而确定其时隙位置,从而完成定时。
在一个非限制性实施例中,所述步骤S302可以包括步骤:根据接收到的所述PBCH及其DMRS,和/或主信息块(Master Information Block,简称MIB)的负荷(payload)确定所述第一索引。
例如,对于频率1(Frequency 1,简称FR1),可以基于所述PBCH及其DMRS盲检得到所有第一索引。
又例如,对于频率2(Frequency 2,简称FR2),可以基于PBCH 及其DMRS,以及MIB的负荷盲检得到所有第一索引。
在一个非限制性实施例中,当采用上述图5或图6所示映射图样发送所述同步信号块集合时,执行本实施例所述方案的UE在搜索到PSS序列后,就可以确定所述传输窗口的边界,如起始位置;时隙的长度,如图5中一个PSS序列占据一个时隙的长度;以及,符号的长度,如可以根据所述PSS序列的时频域映射方式确定。
由于采用上述图5和图6所示映射图样发送时,不同同步信号块的PSS序列会占据不同的时隙,因而,需要进一步确定当前接收到的PSS序列所属SSB的第一索引,进而确定当前接收到的PSS序列所属SSB的时隙位置。
进一步地,当UE搜索到SSS序列后,可以得到30ms的边界。
进一步地,在PSS序列和SSS序列之间可以接收到2个PBCH及其DMRS,在SSS序列之后又可以接收到2个PBCH及其DMRS。由此,基于接收到的4个PBCH及其DMRS以及MIB的负荷,可以确定所述第一索引,进而根据所述映射图样确定当前接收到的同步信号块的时隙位置,完成定时。
在另一个非限制性实施例中,当采用上述图7或图8所示映射图样发送所述同步信号块集合时,由于SSS序列和PSS序列的起始位置将所述传输窗口均分,因而在搜索到PSS序列和SSS序列之后,UE即可实现对传输窗口以及半个传输窗口的定时,并确定时隙长度以及符号长度。
进一步地,在接收完4个PBCH及其DMRS后,UE可以完成对所述同步信号块的定时。
在又一个非限制性实施例中,当采用上述图9或图10所示映射图样发送所述同步信号块集合时,在搜索到PSS序列和SSS序列后UE即可实现帧定时,并确定时隙长度和符号长度。
进一步地,在接收完4个PBCH及其DMRS后,UE可以完成对 所述同步信号块的定时。
由上,对于UE侧,采用本实施例的方案,结合预先获知的映射图样,UE可以根据当前接收到的同步信号块在所述同步信号块集合内的第一索引确定时隙位置,从而根据接收到的同步信号块完成定时,以便后续进行同步操作。
图13是本发明实施例的一种同步信号块的时隙位置确定装置的结构示意图。本领域技术人员理解,本实施例所述同步信号块的时隙位置确定装置4以下简称为时隙位置确定装置4)可以用于实施上述图12所示实施例中所述的方法技术方案。
具体地,在本实施例中,所述时隙位置确定装置4可以包括:接收模块41,用于在传输窗口内接收同步信号块集合,所述同步信号块集合包括n个同步信号块,n为正整数,所述同步信号块集合是上述发送装置发送的;第一确定模块42,用于确定当前接收到的同步信号块在n个同步信号块中的第一索引;第二确定模块43,用于根据所述第一索引以及所述同步信号块集合在所述传输窗口内的映射图样确定所述当前接收到的同步信号块的时隙位置。
在一个非限制性实施例中,所述第一确定模块42可以包括:确定子模块421,用于根据接收到的所述PBCH及其DMRS,和/或MIB的负荷确定所述第一索引。
关于所述时隙位置确定装置4的工作原理、工作方式的更多内容,可以参照上述图12中的相关描述,这里不再赘述。
进一步地,本发明实施例还公开一种存储介质,其上存储有计算机指令,所述计算机指令运行时执行上述图4至图10、图12所示实施例中所述的方法技术方案。优选地,所述存储介质可以包括诸如非挥发性(non-volatile)存储器或者非瞬态(non-transitory)存储器等计算机可读存储介质。所述存储介质可以包括ROM、RAM、磁盘或光盘等。
进一步地,本发明实施例还公开一种终端,包括存储器和处理器,所述存储器上存储有能够在所述处理器上运行的计算机指令,所述处理器运行所述计算机指令时执行上述图12所示实施例中所述的方法技术方案。优选地,所述终端可以是5G用户终端。
进一步地,本发明实施例还公开一种基站,包括存储器和处理器,所述存储器上存储有能够在所述处理器上运行的计算机指令,所述处理器运行所述计算机指令时执行上述图4至图10所示实施例中所述的方法技术方案。优选地,所述基站可以是gNB。
虽然本发明披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (17)

  1. 一种同步信号块的发送方法,其特征在于,包括:
    获取待发送的同步信号块集合,所述同步信号块集合包括n个同步信号块,n为正整数;
    对于所述同步信号块集合中的第i个同步信号块,将所述第i个同步信号块包括的多个信号或信道分别映射至传输窗口内不同帧的同一时隙,并且,所述同步信号块集合中不同同步信号块的同一信号或信道位于相同帧的不同时隙,其中,1≤i≤n,所述多个信号或信道选自PSS序列、SSS序列、PBCH及其DMRS;
    在所述传输窗口内,根据映射得到的映射图样发送所述同步信号块集合。
  2. 根据权利要求1所述的发送方法,其特征在于,所述同步信号块集合中不同同步信号块的同一信号或信道位于相同帧的不同时隙是指:所述第i个同步信号块的PSS序列和第i+k个同步信号块的PSS序列分别位于同一帧的第i个时隙和第i+k个时隙;所述第i个同步信号块的SSS序列和第i+k个同步信号块的SSS序列分别位于同一帧的第i个时隙和第i+k个时隙,其中,k为正整数。
  3. 根据权利要求1所述的发送方法,其特征在于,所述第i个同步信号块包括的多个信号或信道按时间先后顺序依次为:PSS序列、PBCH及其DMRS、PBCH及其DMRS、SSS序列、PBCH及其DMRS和PBCH及其DMRS。
  4. 根据权利要求3所述的发送方法,其特征在于,所述将所述第i个同步信号块包括的多个信号或信道分别映射至传输窗口内不同帧的同一时隙包括:
    将所述PSS序列映射至基于公式SFNmodx=0确定的系统帧号,其中,SFN为所述系统帧号,x为所述传输窗口包括的帧数;
    将所述SSS序列映射至基于公式SFNmodx=y确定的系统帧号,其中,y为预设阈值;
    将所述PBCH及其DMRS依序映射至传输窗口内除映射有PSS序列和SSS序列的帧之外的其他帧。
  5. 根据权利要求4所述的发送方法,其特征在于,所述预设阈值y的取值用于使得映射有相邻信号或信道的帧之间不存在空闲帧。
  6. 根据权利要求4所述的发送方法,其特征在于,所述预设阈值y的取值用于使得映射有SSS序列的帧为第x/2+1个帧。
  7. 根据权利要求1所述的发送方法,其特征在于,所述第i个同步信号块包括的信号或信道按时间先后顺序依次为:PSS序列、SSS序列、PBCH及其DMRS、PBCH及其DMRS、PBCH及其DMRS和PBCH及其DMRS。
  8. 根据权利要求7所述的发送方法,其特征在于,所述将所述第i个同步信号块包括的多个信号或信道分别映射至传输窗口内不同帧的同一时隙包括:
    将所述PSS序列映射至基于公式SFNmodx=0确定的系统帧号,其中,SFN为所述系统帧号,x为所述传输窗口包括的帧数;
    将所述SSS序列映射至基于公式SFNmodx=1确定的系统帧号;
    将所述PBCH及其DMRS依序映射至传输窗口内除映射有PSS序列和SSS序列的帧之外的其他帧。
  9. 根据权利要求1所述的发送方法,其特征在于,所述传输窗口包括的帧数不小于所述第i个同步信号块包括的多个信号或信道的数量。
  10. 根据权利要求1所述的发送方法,其特征在于,所述同步信号块集合包括的同步信号块的数量是根据子载波间隔和波束数量确定的。
  11. 一种同步信号块的时隙位置确定方法,其特征在于,包括:
    在传输窗口内接收同步信号块集合,所述同步信号块集合包括n个同步信号块,n为正整数,所述同步信号块集合是按照上述权利要求1至10中任一项所述方法发送的;
    确定当前接收到的同步信号块在n个同步信号块中的第一索引;
    根据所述第一索引以及所述同步信号块集合在所述传输窗口内的映射图样确定所述当前接收到的同步信号块的时隙位置。
  12. 根据权利要求11所述的时隙位置确定方法,其特征在于,所述确定当前接收到的同步信号块在n个同步信号块中的第一索引包括:
    根据接收到的所述PBCH及其DMRS,和/或MIB的负荷确定所述第一索引。
  13. 一种同步信号块的发送装置,其特征在于,包括:
    获取模块,用于获取待发送的同步信号块集合,所述同步信号块集合包括n个同步信号块,n为正整数;
    映射模块,对于所述同步信号块集合中的第i个同步信号块,将所述第i个同步信号块包括的多个信号或信道分别映射至传输窗口内不同帧的同一时隙,并且,所述同步信号块集合中不同同步信号块的同一信号或信道位于相同帧的不同时隙,其中,1≤i≤n,所述多个信号或信道选自PSS序列、SSS序列、PBCH及其DMRS;
    发送模块,用于在所述传输窗口内,根据映射得到的映射图样发送所述同步信号块集合。
  14. 一种同步信号块的时隙位置确定装置,其特征在于,包括:
    接收模块,用于在传输窗口内接收同步信号块集合,所述同步信号块集合包括n个同步信号块,n为正整数,所述同步信号块集合是上述权利要求13所述发送装置发送的;
    第一确定模块,用于确定当前接收到的同步信号块在n个同步信号块中的第一索引;
    第二确定模块,用于根据所述第一索引以及所述同步信号块集合在所述传输窗口内的映射图样确定所述当前接收到的同步信号块的时隙位置。
  15. 一种存储介质,其上存储有计算机指令,其特征在于,所述计算机指令运行时执行权利要求1至12任一项所述方法的步骤。
  16. 一种基站,包括存储器和处理器,所述存储器上存储有能够在所述处理器上运行的计算机指令,其特征在于,所述处理器运行所述计算机指令时执行权利要求1至10任一项所述方法的步骤。
  17. 一种终端,包括存储器和处理器,所述存储器上存储有能够在所述处理器上运行的计算机指令,其特征在于,所述处理器运行所述计算机指令时执行权利要求11或12所述方法的步骤。
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