WO2021007931A1 - Tft array substrate and display panel - Google Patents

Tft array substrate and display panel Download PDF

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Publication number
WO2021007931A1
WO2021007931A1 PCT/CN2019/104288 CN2019104288W WO2021007931A1 WO 2021007931 A1 WO2021007931 A1 WO 2021007931A1 CN 2019104288 W CN2019104288 W CN 2019104288W WO 2021007931 A1 WO2021007931 A1 WO 2021007931A1
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WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
goa unit
electrically connected
signal
Prior art date
Application number
PCT/CN2019/104288
Other languages
French (fr)
Chinese (zh)
Inventor
张留旗
韩佰祥
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Publication of WO2021007931A1 publication Critical patent/WO2021007931A1/en

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention relates to the field of display technology, in particular to a TFT array substrate and a display panel.
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Display
  • LCD TV mobile phone
  • PDA personal digital assistant
  • digital camera computer screen or laptop screen, etc.
  • the existing GOA circuit includes multi-level GOA units.
  • Each level of GOA unit includes a pull-up control module, a pull-up module, a download module, a pull-down module, and a pull-down maintenance module.
  • the pull-up control module is used to pull up the first The potential of the node
  • the pull-up module is used to output the scan signal under the control of the potential of the first node
  • the download module is used to output the level transmission signal under the control of the potential of the first node
  • the pull-down module is used to control the first node and the scan signal
  • the pull-down maintenance module is used to maintain the potential of the first node and the scan signal at a low potential under the control of the potential of the first node.
  • the pull-down maintenance module is generally equipped with an inverter, and the input terminal of the inverter Connected to the first node, and the output terminal is connected to the gate of the thin film transistor for maintaining the first node and the scan signal at a low potential.
  • the inverter When the first node is at a high potential, the inverter outputs a low potential control to maintain the first node And the thin film transistor whose scan signal is at a low potential is turned off.
  • the inverter When the first node is at a low potential, the inverter outputs a high potential.
  • the thin film transistor is used to maintain the first node and the scan signal at a low potential. The potential of the signal is maintained at a low potential.
  • the purpose of the present invention is to provide a TFT array substrate, the number of components in the GOA circuit is small, the size of the GOA circuit is small, and a narrow frame design can be realized.
  • Another object of the present invention is to provide a display panel in which the number of components in the GOA circuit is small, the size of the GOA circuit is small, and a narrow frame design can be realized.
  • the present invention first provides a TFT array substrate, which includes a substrate, a plurality of pixels arranged on the substrate and arranged in an array, a plurality of scan lines, and at least one GOA arranged outside the area where the plurality of pixels are located. Circuit; each scan line is electrically connected to a row of sub-pixels; the GOA circuit includes a multi-level external GOA unit, and the multi-level external GOA unit is electrically connected to a plurality of scan lines respectively;
  • Each level of external GOA unit includes a pull-up control module, a pull-up module and a downstream module;
  • the download module is connected to the second clock signal and is electrically connected to the first node, and is used for output stage signal transmission according to the second clock signal under the control of the first node.
  • Each level of external GOA unit also includes an external pull-down module and an external pull-down maintenance module;
  • the external pull-down module is connected to the scanning signal, the first constant voltage low potential, the second constant voltage low potential, the scanning signal of the N+1th level external GOA unit, and is electrically connected to the first node for Under the control of the scan signal of the +1 level external GOA unit, the potential of the first node is pulled down to the first constant voltage low potential and the potential of the scan signal is pulled down to the second constant voltage low potential;
  • the external pull-down module includes the 41st thin film transistor, the 42nd thin film transistor, and the 43rd thin film transistor; the gate of the 41st thin film transistor is connected to the N+1th level external GOA unit
  • the source of the scan signal is electrically connected to the first node, and the drain is electrically connected to the source of the forty-second thin film transistor; the gate of the forty-second thin film transistor is connected to the N+1 level external GOA unit
  • the drain is connected to the first constant voltage low potential;
  • the gate of the forty-third thin film transistor is connected to the scanning signal of the N+1 level external GOA unit, the source is connected to the scanning signal, and the drain is Connect to the second constant voltage low potential;
  • the built-in GOA unit also includes a pull-down sustain signal generation module; in addition to the first row of sub-pixels, in the built-in GOA unit of the Nth row of sub-pixels, the pull-down sustain signal generation module is electrically connected to the N-1th scan line and the N scan lines and the input terminal of the inverter are used to input a high potential pull-down to the input terminal of the inverter when the potential of at least one of the N-1 scan line and the N scan line is high
  • the sustain signal when the potentials of the N-1th scan line and the Nth scan line are both low potentials, a low potential pull-down sustain signal is input to the input terminal of the inverter.
  • the built-in pull-down module is connected to the scan signal of the N+1 level external GOA unit of the GOA circuit, the negative potential of the power supply, the scan signal of the N level external GOA unit of the GOA circuit, and is electrically connected to the Nth level of the GOA circuit
  • the first node of the first-level external GOA unit is used to control the potential of the first node of the N-level external GOA unit of the GOA circuit and the GOA circuit under the control of the scan signal of the N+1th-level external GOA unit of the GOA circuit
  • the potential of the scanning signal of the Nth level external GOA unit is pulled down to the negative potential of the power supply;
  • the built-in pull-down maintenance module is connected to the negative potential of the power supply, the scan signal of the Nth level external GOA unit of the GOA circuit, the level transmission signal of the Nth level external GOA unit of the GOA circuit, and are electrically connected to the Nth level of the GOA circuit
  • the first node of the external GOA unit and the output terminal of the inverter are used to reduce the potential of the first node of the Nth stage external GOA unit of the GOA circuit under the control of the control signal output from the inverter output terminal.
  • the potential of the stage transfer signal of the Nth level external GOA unit and the potential of the scan signal of the Nth level external GOA unit of the GOA circuit are maintained at the negative potential of the power supply.
  • the built-in pull-down module includes the sixty-first thin film transistor, the sixty-second thin film transistor, and the sixty-third thin film transistor; the gate of the sixty-first thin film transistor is connected to the N+1th level of the GOA
  • the source of the scan signal of the GOA unit is electrically connected to the first node of the Nth stage external GOA unit of the GOA circuit, and the drain is electrically connected to the source of the 62nd thin film transistor;
  • the gate is connected to the scan signal of the N+1 level external GOA unit of the GOA circuit, and the drain is connected to the negative potential of the power supply;
  • the gate of the 63rd thin film transistor is connected to the N+1 level outside of the GOA circuit Set the scan signal of the GOA unit, the source is connected to the scan signal of the Nth stage external GOA unit of the GOA circuit, and the drain is connected to the negative potential of the power supply;
  • the built-in pull-down maintenance module includes a 75th thin film transistor, a 76th thin film transistor, a 77th thin film transistor, and a 78th thin film transistor; the gate of the 75th thin film transistor is electrically connected reversely
  • the source of the output terminal of the phaser is electrically connected to the first node of the Nth stage external GOA unit of the GOA circuit, and the drain is electrically connected to the source of the 76th thin film transistor;
  • the gate is electrically connected to the output terminal of the inverter, and the drain is connected to the negative potential of the power supply;
  • the gate of the 77th thin film transistor is electrically connected to the output terminal of the inverter, and the source is connected to the Nth of the GOA circuit
  • the drain is connected to the negative potential of the power supply;
  • the gate of the 78th thin film transistor is electrically connected to the output terminal of the inverter, and the source is connected to the Nth stage of the GOA circuit.
  • Each sub-pixel also includes a pixel drive circuit electrically connected to one scan line and a pixel electrode electrically connected to the pixel drive circuit.
  • the pixel drive circuit, the built-in GOA unit and the pixel electrode are in a direction parallel to the plane where the substrate is located. Set up in turn.
  • the present invention also provides a display panel including the above-mentioned TFT array substrate.
  • FIG. 1 is a schematic diagram of the structure of the TFT array substrate of the present invention.
  • FIG. 2 is a schematic diagram of sub-pixels with built-in GOA units in the TFT array substrate of the present invention
  • FIG. 3 is a schematic circuit diagram of the built-in GOA unit of the first embodiment of the TFT array substrate of the present invention.
  • FIG. 4 is a schematic circuit diagram of the external GOA unit of the first embodiment of the TFT array substrate of the present invention.
  • FIG. 5 is a schematic circuit diagram of a built-in GOA unit of the second embodiment of the TFT array substrate of the present invention.
  • the TFT array substrate of the first embodiment of the present invention includes a substrate 10, a plurality of pixels 20 arranged on the substrate 10 and arranged in an array, a plurality of scan lines 30, and a plurality of pixels. At least one GOA circuit 40 outside the area where 20 is located. Each scan line 30 is electrically connected to a row of sub-pixels 20 correspondingly.
  • the GOA circuit 40 includes a multi-level external GOA unit, and the multi-level external GOA unit is electrically connected to a plurality of scan lines 30 respectively.
  • the TFT array substrate further includes a plurality of data lines 50 arranged on the substrate 10, and each data line 50 is electrically connected to a column of sub-pixels 20.
  • At least one of the sub-pixels 20 in each row includes a built-in GOA unit 21.
  • the built-in GOA unit 21 includes an inverter 211.
  • the input terminal A of the inverter 211 is connected to the pull-down sustain signal, and the output terminal B output control signal.
  • the inverter 211 includes a fifty-first thin film transistor T51, a fifty-second thin film transistor T52, a fifty-third thin film transistor T53, and a fifty-fourth thin film transistor T54.
  • the gate and source of the fifty-first thin film transistor T51 are both connected to the positive power supply VDD, and the drain is electrically connected to the gate of the fifty-second thin film transistor T52.
  • the source of the fifty-second thin film transistor T52 is connected to the positive potential VDD of the power supply, and the drain is the output terminal B of the inverter 211.
  • the gate of the fifty-third thin film transistor T53 is the input terminal A of the inverter 211, the source is electrically connected to the drain of the fifty-first thin film transistor T51, and the drain is connected to the negative power potential VSS.
  • the gate of the fifty-fourth thin film transistor T54 is electrically connected to the gate of the fifty-third thin film transistor T53, the source is electrically connected to the drain of the fifty-second thin film transistor T52, and the drain is connected to the negative power potential VSS.
  • N be a positive integer, except for the first and last level external GOA units, in the Nth level external GOA unit,
  • the pull-up control module 41 is connected to the stage transmission signal ST(N-1) and the first clock signal CLK of the N-1th stage external GOA unit and is electrically connected to the first node Q(N) for Under the control of a clock signal CLK, the potential of the first node Q(N) is pulled up according to the stage transmission signal ST(N-1) of the N-1 stage external GOA unit.
  • the download module 43 accesses the second clock signal CLKB and is electrically connected to the first node Q(N) for outputting the stage transmission signal ST() according to the second clock signal CLKB under the control of the first node Q(N). N).
  • the external pull-down module 44 is connected to the scan signal G(N+1), the first constant voltage low potential VGL1, the second constant voltage low potential VGL2, and the scan signal G(N) of the N+1 level external GOA unit And electrically connected to the first node Q(N) for pulling down the potential of the first node Q(N) to the first node under the control of the scan signal G(N+1) of the N+1th stage external GOA unit
  • the constant voltage low potential VGL1 and the scanning signal G(N) are pulled down to the second constant voltage low potential VGL2.
  • the external pull-down maintenance module 45 is connected to the first constant voltage low potential VGL1, the second constant voltage low potential VGL2, the scan signal G(N), the stage transmission signal ST(N), and is electrically connected to the first node Q(N). ) And the output terminal B of the inverter 211 are used to maintain the potential of the first node Q(N) and the stage transfer signal ST(N) at the first node under the control of the control signal output from the output terminal B of the inverter 211 A constant voltage low potential VGL1 maintains the potential of the scanning signal G(N) at a second constant voltage low potential VGL2.
  • the pull-up control module 41 includes an eleventh thin film transistor T11, a twelfth thin film transistor T12, and a thirteenth thin film transistor T13.
  • the gate of the eleventh thin film transistor T11 is connected to the first clock signal CLK
  • the source is connected to the stage transmission signal ST(N-1) of the N-1th GOA unit
  • the drain is electrically connected to the twelfth thin film Source of transistor T12.
  • the gate of the twelfth thin film transistor T12 is connected to the first clock signal CLK, and the drain is electrically connected to the first node Q(N).
  • the gate of the thirteenth thin film transistor T13 is connected to the stage transmission signal ST(N-1), the source is electrically connected to the second node K(N), and the drain is electrically connected to the drain of the eleventh thin film transistor T11 .
  • the pull-up module 42 includes a twenty-first thin film transistor T21, a twenty-second thin film transistor T22, and a bootstrap capacitor C1.
  • the gate of the twenty-first thin film transistor T21 is electrically connected to the first node Q(N), the source is connected to the second clock signal CLKB, and the drain is electrically connected to the Nth scan line 30 and outputs the scan signal G( N).
  • the gate of the twenty-second thin film transistor T22 is electrically connected to the first node Q(N), the source is connected to the second clock signal CLKB, and the drain is electrically connected to the second node K(N).
  • One end of the bootstrap capacitor C1 is electrically connected to the first node Q(N), and the other end is connected to the scanning signal G(N).
  • the download module 43 includes a thirty-first thin film transistor T31.
  • the gate of the thirty-first thin film transistor T31 is electrically connected to the first node Q(N), the source is connected to the second clock signal CLKB, and the drain outputs the stage transmission signal ST(N).
  • the external pull-down module 44 includes a forty-first thin film transistor T41, a forty-second thin film transistor T42, and a forty-third thin film transistor T43.
  • the gate of the forty-first thin film transistor T41 is connected to the scanning signal G(N+1) of the N+1th stage external GOA unit, the source is electrically connected to the first node Q(N), and the drain is electrically connected
  • the source of the forty-second thin film transistor T42 is connected.
  • the gate of the forty-second thin film transistor T42 is connected to the scan signal G(N+1) of the N+1th stage external GOA unit, and the drain is connected to the first constant voltage low potential VGL1.
  • the gate of the forty-third thin film transistor T43 is connected to the scan signal G(N+1) of the N+1th stage external GOA unit, the source is connected to the scan signal G(N), and the drain is connected to the second Constant voltage low potential VGL2.
  • the external pull-down maintenance module 45 includes a fifty-fifth thin film transistor T55, a fifty-sixth thin film transistor T56, a fifty-seventh thin film transistor T57, a fifty-eighth thin film transistor T58, and a fifty-ninth thin film transistor T59.
  • the gate of the fifty-fifth thin film transistor T55 is electrically connected to the output terminal B of the inverter 211, the source is electrically connected to the first node Q(N), and the drain is electrically connected to the fifty-sixth thin film transistor T56.
  • the source electrode is electrically connected to the drain electrode of the eleventh thin film transistor T11.
  • the gate of the fifty-sixth thin film transistor T56 is electrically connected to the output terminal B of the inverter 211, and the drain is connected to the first constant voltage low potential VGL1.
  • the gate of the fifty-seventh thin film transistor T57 is electrically connected to the output terminal B of the inverter 211, the source is connected to the stage transmission signal ST(N), and the drain is connected to the first constant voltage low potential VGL1.
  • the gate of the fifty-eighth thin film transistor T58 is electrically connected to the output terminal B of the inverter 211, the source is connected to the scan signal G(N), and the drain is connected to the second constant voltage low potential VGL2.
  • the gate of the fifty-ninth thin film transistor T59 is electrically connected to the output terminal B of the inverter 211, the source is electrically connected to the second node K(N), and the drain is connected to the second constant voltage low potential VGL2.
  • the gate of the eleventh thin film transistor T11 is connected to the start signal (not shown).
  • the gates of the forty-first thin film transistor T41, the forty-second thin film transistor T42, and the forty-third thin film transistor T43 are connected to the start signal.
  • the built-in GOA unit 21 further includes a pull-down sustain signal generating module 212. Except for the first row of sub-pixels 20, in the built-in GOA unit 21 of the Nth row of sub-pixels 20, the pull-down sustain signal generating module 212 is electrically connected to the N-1th scan line 30, that is, the N-th receiving GOA circuit 50
  • the scan signal G(N-1) of the level 1 external GOA unit, the Nth scan line 30 also receives the scan signal G(N) of the Nth level external GOA unit in the GOA circuit 50 and the input of the inverter 211 Terminal A is used to input a high-level pull-down sustain signal to the input terminal A of the inverter 211 when the potential of at least one of the N-1th scan line 30 and the Nth scan line 30 is high.
  • a low-level pull-down sustain signal is input to the input
  • the pull-down sustain signal generating module 212 includes a sixty-first thin film transistor T61 and a sixty-second thin film transistor T62.
  • the gate and source of the 61st thin film transistor T61 are electrically connected to the N-1th scan line 30, and the drain is electrically connected to the input terminal A of the inverter 211.
  • the gate and source of the 62nd thin film transistor T62 are electrically connected to the Nth scan line 30, and the drain is electrically connected to the input terminal A of the inverter 211.
  • the gate of the sixtieth thin film transistor T61 is connected to the start signal.
  • the sub-pixels provided with the built-in GOA unit 21 among the plurality of sub-pixels 20 may be normal display pixels, or may be dummy pixels with other functions.
  • each sub-pixel 20 includes a built-in GOA unit 21.
  • each sub-pixel 20 also includes a pixel driving circuit 22 electrically connected to one scan line 30 and a data line 50, and a pixel electrode 23 electrically connected to the pixel driving circuit 22.
  • the built-in GOA unit 21 and the pixel electrode 23 are sequentially arranged in a direction parallel to the plane where the substrate 10 is located, and the sequence can be adjusted according to actual requirements.
  • the pixel drive circuit may be an OLED pixel drive circuit or a liquid crystal pixel drive circuit in the prior art, and its specific structure is the prior art, and will not be discussed here.
  • the TFT array substrate is the TFT array substrate of the OLED display panel, and the pixel electrode 23 corresponds to the anode of the OLED device.
  • the TFT array substrate is the TFT array substrate of the liquid crystal display panel. 23 is opposed to the common electrode in the color filter substrate, and drives the liquid crystal layer sandwiched between the two.
  • the number of GOA circuits 50 is two, and the two GOA circuits 50 are respectively located on both sides of the area where the multiple sub-pixels 20 are located.
  • a built-in GOA unit 21 is provided in the sub-pixel 20, which is used to maintain the first node, scan signal, and stage transfer signal in the GOA circuit 50 at a low potential.
  • the inverter 211 controlled by the fifteenth film transistor T55, the fifty-sixth film transistor T56, the fifty-seventh film transistor T57, and the fifty-eighth film transistor T58 is provided in the built-in GOA unit 21, so that the GOA circuit 50 There is no need to install an inverter in each level of external GOA unit, and the number of components of the GOA circuit 50 is greatly reduced compared with the prior art, so that the size of the GOA circuit 50 is reduced, which is conducive to the realization of a narrow frame design to improve product quality .
  • the difference between the second embodiment of the present invention and the above-mentioned first embodiment is that in the built-in GOA unit 21 of the sub-pixel 20 in the Nth row, the inverter The input terminal A of 211 is electrically connected to the first node Q(N) of the N-th stage external GOA unit of the GOA circuit 50 to receive the pull-down sustain signal transmitted therefrom.
  • each level of external GOA unit is no longer provided with an external pull-down module 44 and an external pull-down maintenance module 45
  • the built-in GOA unit 21 further includes a built-in pull-down module 213 and a built-in pull-down maintenance module 214.
  • the built-in pull-down module 213 is connected to the scan signal G(N+1) of the N+1 level external GOA unit of the GOA circuit 50, the negative power supply potential VSS, and the scan signal of the N level external GOA unit of the GOA circuit 50 G(N), and electrically connected to the first node Q(N) of the Nth stage external GOA unit of the GOA circuit 50, for the scanning signal G( Under the control of N+1), the potential of the first node Q(N) of the N-level external GOA unit of the GOA circuit 50 and the potential of the scanning signal G(N) of the N-th external GOA unit of the GOA circuit 50 are pulled down To the negative potential VSS of the power supply.
  • the built-in pull-down maintenance module 214 is connected to the negative power potential VSS, the scan signal G(N) of the Nth level external GOA unit of the GOA circuit 50, and the level transmission signal ST( N) and electrically connected to the first node Q(N) of the N-th stage external GOA unit of the GOA circuit 50 and the output terminal B of the inverter 211 for the control signal output from the output terminal B of the inverter 211 Under the control, the potential of the first node Q(N) of the Nth external GOA unit of the GOA circuit 50, the potential of the stage transfer signal ST(N) of the Nth external GOA unit and the Nth of the GOA circuit 50 The level of the scanning signal G(N) of the external GOA unit is maintained at the negative power potential VSS.
  • the built-in pull-down module 213 includes a sixty-first thin film transistor T61', a sixty-second thin film transistor T62', and a sixty-third thin film transistor T63. '.
  • the gate of the sixty-first thin film transistor T61' is connected to the scanning signal G(N+1) of the N+1th stage external GOA unit of the GOA circuit 50, and the source is electrically connected to the Nth stage of the GOA circuit 50
  • the drain of the first node Q(N) of the external GOA unit is electrically connected to the source of the 62nd thin film transistor T62'.
  • the gate of the sixty-second thin film transistor T62' is connected to the scanning signal G(N+1) of the N+1th stage external GOA unit of the GOA circuit 50, and the drain is connected to the negative power supply VSS.
  • the gate of the sixty-third thin film transistor T63' is connected to the scanning signal G(N+1) of the N+1th stage of the external GOA unit of the GOA circuit 50, and the source is connected to the Nth stage of the GOA circuit 50.
  • Set the scan signal G(N) of the GOA unit, and the drain is connected to the negative potential VSS of the power supply.
  • the built-in pull-down maintenance module 214 includes a seventy-fifth thin film transistor T75', a seventy-sixth thin film transistor T76', a seventy-seventh thin film transistor T77', a seventy-eighth thin film transistor T78', and a seventy-ninth thin film transistor T79'.
  • the gate of the seventy-fifth thin film transistor T75' is electrically connected to the output terminal B of the inverter 211, and the source is electrically connected to the first node Q(N) of the Nth stage external GOA unit of the GOA circuit 50,
  • the drain is electrically connected to the source of the 76th thin film transistor T76' and the drain of the eleventh thin film transistor T11 of the Nth stage external GOA unit of the GOA circuit 50, and the connection point is a third node L(N ).
  • the gate of the seventy-sixth thin film transistor T76' is electrically connected to the output terminal B of the inverter 211, and the drain is connected to the negative power potential VSS.
  • the gate of the seventy-seventh thin film transistor T77' is electrically connected to the output terminal B of the inverter 211, the source is connected to the stage transmission signal ST(N) of the Nth stage of the external GOA unit of the GOA circuit 50, and the drain is The pole is connected to the negative potential VSS of the power supply.
  • the gate of the 78th thin film transistor T78' is electrically connected to the output terminal B of the inverter 211, the source is connected to the scanning signal G(N) of the Nth stage external GOA unit of the GOA circuit 50, and the drain is Connect the power supply negative potential VSS.
  • the gate of the seventy-ninth thin film transistor T79' is electrically connected to the output terminal B of the inverter 211, the source is connected to the second node K(N) of the Nth stage external GOA unit of the GOA circuit 50, and the drain is The pole is connected to the negative power supply voltage VSS.
  • the gates of the 61st thin film transistor T61', the 62nd thin film transistor T62', and the 63rd thin film transistor T63' are connected to each other. Start signal.
  • the present invention also provides a display panel including the above-mentioned TFT array substrate.
  • the structure of the TFT array substrate will not be described repeatedly here.
  • the built-in GOA unit 21 is provided in the sub-pixel 20, and the inverter 211, the built-in pull-down module 213, and the built-in pull-down maintenance module 214 are all provided in the built-in GOA unit 21, or only
  • the inverter 211 is arranged in the built-in GOA unit 21, so that the number of components of the GOA circuit 50 is greatly reduced compared with the prior art, so that the size of the GOA circuit 50 is reduced, which is beneficial to realize a narrow frame design and improve the quality of the product .
  • the TFT array substrate of the present invention includes a substrate, a plurality of pixels arranged on the substrate and arranged in an array, a plurality of scan lines, and a GOA circuit arranged outside the area where the plurality of pixels are located.
  • Each scan line Correspondingly to be electrically connected to a row of sub-pixels, the GOA circuit includes a multi-level external GOA unit.
  • the multi-level external GOA unit is electrically connected to a plurality of scan lines. At least one of the sub-pixels in each row includes a built-in GOA unit.
  • the GOA unit includes an inverter.
  • the input terminal of the inverter is connected to a pull-down sustain signal, and the output terminal outputs a control signal, which is beneficial to reduce the number of components in the GOA circuit, thereby reducing the size of the GOA circuit to achieve a narrow frame.
  • the number of components is small, the size of the GOA circuit is small, and a narrow frame design can be realized.

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Abstract

A TFT array substrate and a display panel. The array substrate comprises a substrate (10), a plurality of pixels (20) arranged on the substrate (10) and arranged in an array, a plurality of scanning lines (30), and a GOA circuit (40) arranged outside the region where the plurality of pixels (20) are located, wherein each scanning line (30) is electrically connected to one row of sub-pixels (20) correspondingly; the GOA circuit (40) comprises a plurality of stages of external GOA units; the plurality of stages of external GOA units are correspondingly electrically connected to the plurality of scanning lines (30) respectively; at least one of the sub-pixels (20) in each row comprises a built-in GOA unit (21); the built-in GOA unit (21) comprises a phase inverter (211); and an input end of the phase inverter (211) is connected to a pull-down holding signal, and an output end thereof outputs a control signal. The present invention facilitates reduction of the number of components in the GOA circuit (40), thereby reducing the size of the GOA circuit (40) so as to realize a narrow bezel.

Description

TFT阵列基板及显示面板TFT array substrate and display panel 技术领域Technical field
本发明涉及显示技术领域，尤其涉及一种TFT阵列基板及显示面板。The present invention relates to the field of display technology, in particular to a TFT array substrate and a display panel.
背景技术Background technique
液晶显示器（Liquid Crystal Display，LCD）及有机发光二极管显示装置（Organic Light Emitting Display，OLED）等平板显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理（PDA）、数字相机、计算机屏幕或笔记本电脑屏幕等。Flat panel display devices such as Liquid Crystal Display (LCD) and Organic Light Emitting Display (OLED) have many advantages such as thin body, power saving, and no radiation, and have been widely used. Such as: LCD TV, mobile phone, personal digital assistant (PDA), digital camera, computer screen or laptop screen, etc.
GOA（Gate Driver on Array）技术即阵列基板行驱动技术，是利用薄膜晶体管（Thin Film Transistor，TFT）阵列制程将栅极扫描驱动电路制作在LCD及OLED显示装置的TFT阵列基板上，以实现逐行扫描的驱动方式，具有降低生产成本和实现面板窄边框设计的优点。GOA电路具有两项基本功能：第一是输出栅极扫描驱动信号，驱动面板内的栅极线，打开显示区内的TFT，以对像素进行充电；第二是移位寄存功能，当一个栅极扫描驱动信号输出完成后，通过时钟控制进行下一个栅极扫描驱动信号的输出，并依次传递下去。GOA技术能减少外接集成电路（IC）的焊接（bonding）工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框的显示产品。GOA (Gate Driver on Array) technology is the array substrate row drive technology, which uses thin film transistors (Thin The Film Transistor (TFT) array process manufactures gate scan driving circuits on the TFT array substrates of LCD and OLED display devices to realize a progressive scan driving method, which has the advantages of reducing production costs and achieving a narrow frame design of the panel. The GOA circuit has two basic functions: the first is to output the gate scan driving signal, which drives the gate line in the panel, and turns on the TFT in the display area to charge the pixels; the second is the shift register function, which acts as a gate After the output of the pole scan drive signal is completed, the next gate scan drive signal is output through clock control, and is passed on in sequence. GOA technology can reduce the bonding process of an external integrated circuit (IC), which has the opportunity to increase production capacity and reduce product costs, and it can make LCD panels more suitable for manufacturing display products with narrow bezels.
现有的GOA电路包括多级GOA单元，每一级GOA单元均包括上拉控制模块、上拉模块、下传模块、下拉模块及下拉维持模块，其中，上拉控制模块用于上拉第一节点的电位，上拉模块用于在第一节点的电位控制下输出扫描信号，下传模块用于在第一节点的电位控制下输出级传信号，下拉模块用于对第一节点及扫描信号的电位进行下拉，而下拉维持模块用于受第一节点的电位控制将第一节点及扫描信号的电位维持在低电位，下拉维持模块中一般设有一反相器，该反相器的输入端与第一节点连接，输出端与用于维持第一节点及扫描信号为低电位的薄膜晶体管的栅极连接，在第一节点为高电位时反相器输出低电位控制用于维持第一节点及扫描信号为低电位的薄膜晶体管截止，在第一节点为低电位时反相器输出高电位控制用于维持第一节点及扫描信号为低电位的薄膜晶体管导通从而将第一节点及扫描信号的电位维持为低电位。The existing GOA circuit includes multi-level GOA units. Each level of GOA unit includes a pull-up control module, a pull-up module, a download module, a pull-down module, and a pull-down maintenance module. The pull-up control module is used to pull up the first The potential of the node, the pull-up module is used to output the scan signal under the control of the potential of the first node, the download module is used to output the level transmission signal under the control of the potential of the first node, and the pull-down module is used to control the first node and the scan signal The pull-down maintenance module is used to maintain the potential of the first node and the scan signal at a low potential under the control of the potential of the first node. The pull-down maintenance module is generally equipped with an inverter, and the input terminal of the inverter Connected to the first node, and the output terminal is connected to the gate of the thin film transistor for maintaining the first node and the scan signal at a low potential. When the first node is at a high potential, the inverter outputs a low potential control to maintain the first node And the thin film transistor whose scan signal is at a low potential is turned off. When the first node is at a low potential, the inverter outputs a high potential. The thin film transistor is used to maintain the first node and the scan signal at a low potential. The potential of the signal is maintained at a low potential.
传统的采用GOA技术的TFT阵列基板中，一般将GOA电路设置在子像素所在的显示区外侧的边框区内，对于窄边框设计的显示面板来说，需要将边框区的尺寸设计得较小，而现有的GOA电路中元件数目较多，导致GOA电路尺寸较大，不利于实现窄边框设计。In the traditional TFT array substrate using GOA technology, the GOA circuit is generally arranged in the frame area outside the display area where the sub-pixels are located. For display panels with a narrow frame design, the size of the frame area needs to be designed to be smaller. However, the large number of components in the existing GOA circuit results in a larger GOA circuit size, which is not conducive to achieving a narrow frame design.
技术问题technical problem
本发明的目的在于提供一种TFT阵列基板，其GOA电路中元器件数目少，GOA电路的尺寸较小，能够实现窄边框设计。The purpose of the present invention is to provide a TFT array substrate, the number of components in the GOA circuit is small, the size of the GOA circuit is small, and a narrow frame design can be realized.
本发明的另一目的在于提供一种显示面板，其GOA电路中元器件数目少，GOA电路的尺寸较小，能够实现窄边框设计。Another object of the present invention is to provide a display panel in which the number of components in the GOA circuit is small, the size of the GOA circuit is small, and a narrow frame design can be realized.
技术解决方案Technical solutions
为实现上述目的，本发明首先提供一种TFT阵列基板，包括衬底、设于衬底上且阵列排布的多个像素、多条扫描线及设于多个像素所在区域外侧的至少一个GOA电路；每一条扫描线对应与一行子像素电性连接；所述GOA电路包括多级外置GOA单元，多级外置GOA单元分别与多条扫描线对应电性连接；To achieve the above objective, the present invention first provides a TFT array substrate, which includes a substrate, a plurality of pixels arranged on the substrate and arranged in an array, a plurality of scan lines, and at least one GOA arranged outside the area where the plurality of pixels are located. Circuit; each scan line is electrically connected to a row of sub-pixels; the GOA circuit includes a multi-level external GOA unit, and the multi-level external GOA unit is electrically connected to a plurality of scan lines respectively;
每一行子像素中的至少一个包括内置GOA单元，所述内置GOA单元包括反相器，所述反相器的输入端接入下拉维持信号，输出端输出控制信号。At least one of the sub-pixels in each row includes a built-in GOA unit, the built-in GOA unit includes an inverter, the input end of the inverter is connected to a pull-down sustain signal, and the output end outputs a control signal.
每一级外置GOA单元均包括上拉控制模块、上拉模块及下传模块；Each level of external GOA unit includes a pull-up control module, a pull-up module and a downstream module;
设N为正整数，除了第一级外置GOA单元外，在第N级外置GOA单元中，Set N to be a positive integer, except for the first-level external GOA unit, in the Nth-level external GOA unit,
所述上拉控制模块接入第N-1级外置GOA单元的级传信号、第一时钟信号并电性连接第一节点，用于在第一时钟信号的控制下依据N-1级外置GOA单元的级传信号上拉第一节点的电位；The pull-up control module is connected to the stage transmission signal and the first clock signal of the N-1th stage external GOA unit and is electrically connected to the first node, and is used to control the first clock signal according to the N-1 stage external Set the level transmission signal of the GOA unit to pull up the potential of the first node;
所述上拉模块接入第二时钟信号并电性连接第一节点及第N条扫描线，用于在第一节点的控制下依据第二时钟信号输出扫描信号至第N条扫描线；The pull-up module is connected to the second clock signal and is electrically connected to the first node and the Nth scan line for outputting the scan signal to the Nth scan line according to the second clock signal under the control of the first node;
所述下传模块接入第二时钟信号并电性连接第一节点，用于在第一节点的控制下依据第二时钟信号输出级传信号。The download module is connected to the second clock signal and is electrically connected to the first node, and is used for output stage signal transmission according to the second clock signal under the control of the first node.
每一级外置GOA单元还包括外置下拉模块以及外置下拉维持模块；Each level of external GOA unit also includes an external pull-down module and an external pull-down maintenance module;
除了最后一级外置GOA单元外，在第N级外置GOA单元中，In addition to the last level external GOA unit, in the Nth level external GOA unit,
所述外置下拉模块接入第N+1级外置GOA单元的扫描信号、第一恒压低电位、第二恒压低电位、扫描信号并电性连接第一节点，用于在第N+1级外置GOA单元的扫描信号的控制下将第一节点的电位下拉至第一恒压低电位并将扫描信号的电位下拉至第二恒压低电位；The external pull-down module is connected to the scanning signal, the first constant voltage low potential, the second constant voltage low potential, the scanning signal of the N+1th level external GOA unit, and is electrically connected to the first node for Under the control of the scan signal of the +1 level external GOA unit, the potential of the first node is pulled down to the first constant voltage low potential and the potential of the scan signal is pulled down to the second constant voltage low potential;
所述外置下拉维持模块接入第一恒压低电位、第二恒压低电位、扫描信号、级传信号并电性连接第一节点以及反相器的输出端，用于在反相器输出端输出的控制信号的控制下，将第一节点及级传信号的电位维持在第一恒压低电位并将扫描信号的电位维持在第二恒压低电位。The external pull-down maintenance module is connected to the first constant voltage low potential, the second constant voltage low potential, the scanning signal, the stage transmission signal and is electrically connected to the first node and the output terminal of the inverter for Under the control of the control signal output from the output terminal, the potential of the first node and the level transfer signal is maintained at the first constant voltage low potential and the potential of the scanning signal is maintained at the second constant voltage low potential.
所述外置下拉模块包括第四十一薄膜晶体管、第四十二薄膜晶体管、第四十三薄膜晶体管；所述第四十一薄膜晶体管的栅极接入第N+1级外置GOA单元的扫描信号，源极电性连接第一节点，漏极电性连接第四十二薄膜晶体管的源极；所述第四十二薄膜晶体管的栅极接入第N+1级外置GOA单元的扫描信号，漏极接入第一恒压低电位；所述第四十三薄膜晶体管的栅极接入第N+1级外置GOA单元的扫描信号，源极接入扫描信号，漏极接入第二恒压低电位；The external pull-down module includes the 41st thin film transistor, the 42nd thin film transistor, and the 43rd thin film transistor; the gate of the 41st thin film transistor is connected to the N+1th level external GOA unit The source of the scan signal is electrically connected to the first node, and the drain is electrically connected to the source of the forty-second thin film transistor; the gate of the forty-second thin film transistor is connected to the N+1 level external GOA unit The drain is connected to the first constant voltage low potential; the gate of the forty-third thin film transistor is connected to the scanning signal of the N+1 level external GOA unit, the source is connected to the scanning signal, and the drain is Connect to the second constant voltage low potential;
所述外置下拉维持模块包括第五十五薄膜晶体管、第五十六薄膜晶体管、第五十七薄膜晶体管及第五十八薄膜晶体管；所述第五十五薄膜晶体管的栅极电性连接反相器的输出端，源极电性连接第一节点，漏极电性连接第五十六薄膜晶体管的源极；所述第五十六薄膜晶体管的栅极电性连接反相器的输出端，漏极接入第一恒压低电位；所述第五十七薄膜晶体管的栅极电性连接反相器的输出端，源极接入级传信号，漏极接入第一恒压低电位；所述第五十八薄膜晶体管的栅极电性连接反相器的输出端，源极接入扫描信号，漏极接入第二恒压低电位。The external pull-down maintenance module includes a fifty-fifth thin film transistor, a fifty-sixth thin film transistor, a fifty-seventh thin film transistor and a fifty-eighth thin film transistor; the gate of the fifty-fifth thin film transistor is electrically connected The output terminal of the inverter, the source is electrically connected to the first node, and the drain is electrically connected to the source of the fifty-sixth thin film transistor; the gate of the fifty-sixth thin film transistor is electrically connected to the output of the inverter The drain is connected to the first constant voltage low potential; the gate of the fifty-seventh thin film transistor is electrically connected to the output terminal of the inverter, the source is connected to the stage signal, and the drain is connected to the first constant voltage Low potential; the gate of the fifty-eighth thin film transistor is electrically connected to the output terminal of the inverter, the source is connected to the scan signal, and the drain is connected to the second constant voltage low potential.
所述内置GOA单元还包括下拉维持信号产生模块；除了第一行子像素外，在第N行子像素的内置GOA单元中，下拉维持信号产生模块电性连接第N-1条扫描线、第N条扫描线以及反相器的输入端，用于在第N-1条扫描线及第N条扫描线中的至少一个的电位为高电位时向反相器的输入端输入高电位的下拉维持信号，在第N-1条扫描线及第N条扫描线的电位均为低电位时向反相器的输入端输入低电位的下拉维持信号。The built-in GOA unit also includes a pull-down sustain signal generation module; in addition to the first row of sub-pixels, in the built-in GOA unit of the Nth row of sub-pixels, the pull-down sustain signal generation module is electrically connected to the N-1th scan line and the N scan lines and the input terminal of the inverter are used to input a high potential pull-down to the input terminal of the inverter when the potential of at least one of the N-1 scan line and the N scan line is high For the sustain signal, when the potentials of the N-1th scan line and the Nth scan line are both low potentials, a low potential pull-down sustain signal is input to the input terminal of the inverter.
所述下拉维持信号产生模块包括第六十一薄膜晶体管及第六十二薄膜晶体管；所述第六十一薄膜晶体管的栅极及源极均电性连接第N-1条扫描线，漏极电性连接反相器的输入端；所述第六十二薄膜晶体管的栅极及源极均电性连接第N条扫描线，漏极电性连接反相器的输入端。The pull-down sustain signal generating module includes a 61st thin film transistor and a 62nd thin film transistor; the gate and source of the 61st thin film transistor are electrically connected to the N-1th scan line, and the drain The input terminal of the inverter is electrically connected; the gate and source of the 62nd thin film transistor are electrically connected to the Nth scan line, and the drain is electrically connected to the input terminal of the inverter.
在第N行子像素的内置GOA单元中，所述反相器的输入端电性连接GOA电路的第N级外置GOA单元的第一节点接收其传输的下拉维持信号；In the built-in GOA unit of the Nth row of sub-pixels, the input terminal of the inverter is electrically connected to the first node of the Nth stage external GOA unit of the GOA circuit to receive the pull-down sustain signal transmitted therefrom;
所述内置GOA单元还包括内置下拉模块及内置下拉维持模块；The built-in GOA unit also includes a built-in pull-down module and a built-in pull-down maintenance module;
除了最后一行子像素外，在第N行子像素的内置GOA单元中，Except for the last row of sub-pixels, in the built-in GOA unit of the Nth row of sub-pixels,
所述内置下拉模块接入GOA电路的第N+1级外置GOA单元的扫描信号、电源负电位、GOA电路的第N级外置GOA单元的扫描信号，并电性连接GOA电路的第N级外置GOA单元的第一节点，用于在GOA电路的第N+1级外置GOA单元的扫描信号的控制下将GOA电路的N级外置GOA单元的第一节点的电位及GOA电路的第N级外置GOA单元的扫描信号的电位下拉至电源负电位；The built-in pull-down module is connected to the scan signal of the N+1 level external GOA unit of the GOA circuit, the negative potential of the power supply, the scan signal of the N level external GOA unit of the GOA circuit, and is electrically connected to the Nth level of the GOA circuit The first node of the first-level external GOA unit is used to control the potential of the first node of the N-level external GOA unit of the GOA circuit and the GOA circuit under the control of the scan signal of the N+1th-level external GOA unit of the GOA circuit The potential of the scanning signal of the Nth level external GOA unit is pulled down to the negative potential of the power supply;
所述内置下拉维持模块接入电源负电位、GOA电路的第N级外置GOA单元的扫描信号、GOA电路的第N级外置GOA单元的级传信号并电性连接GOA电路的第N级外置GOA单元的第一节点以及反相器的输出端，用于在反相器输出端输出的控制信号的控制下，将GOA电路的第N级外置GOA单元的第一节点的电位、第N级外置GOA单元的级传信号的电位及GOA电路的第N级外置GOA单元的扫描信号的电位维持在电源负电位。The built-in pull-down maintenance module is connected to the negative potential of the power supply, the scan signal of the Nth level external GOA unit of the GOA circuit, the level transmission signal of the Nth level external GOA unit of the GOA circuit, and are electrically connected to the Nth level of the GOA circuit The first node of the external GOA unit and the output terminal of the inverter are used to reduce the potential of the first node of the Nth stage external GOA unit of the GOA circuit under the control of the control signal output from the inverter output terminal. The potential of the stage transfer signal of the Nth level external GOA unit and the potential of the scan signal of the Nth level external GOA unit of the GOA circuit are maintained at the negative potential of the power supply.
所述内置下拉模块包括第六十一薄膜晶体管、第六十二薄膜晶体管、第六十三薄膜晶体管；所述第六十一薄膜晶体管的栅极接入GOA电路的第N+1级外置GOA单元的扫描信号，源极电性连接GOA电路的第N级外置GOA单元的第一节点，漏极电性连接第六十二薄膜晶体管的源极；所述第六十二薄膜晶体管的栅极接入GOA电路的第N+1级外置GOA单元的扫描信号，漏极接入电源负电位；所述第六十三薄膜晶体管的栅极接入GOA电路的第N+1级外置GOA单元的扫描信号，源极接入GOA电路的第N级外置GOA单元的扫描信号，漏极接入电源负电位；The built-in pull-down module includes the sixty-first thin film transistor, the sixty-second thin film transistor, and the sixty-third thin film transistor; the gate of the sixty-first thin film transistor is connected to the N+1th level of the GOA The source of the scan signal of the GOA unit is electrically connected to the first node of the Nth stage external GOA unit of the GOA circuit, and the drain is electrically connected to the source of the 62nd thin film transistor; The gate is connected to the scan signal of the N+1 level external GOA unit of the GOA circuit, and the drain is connected to the negative potential of the power supply; the gate of the 63rd thin film transistor is connected to the N+1 level outside of the GOA circuit Set the scan signal of the GOA unit, the source is connected to the scan signal of the Nth stage external GOA unit of the GOA circuit, and the drain is connected to the negative potential of the power supply;
所述内置下拉维持模块包括第七十五薄膜晶体管、第七十六薄膜晶体管、第七十七薄膜晶体管及第七十八薄膜晶体管；所述第七十五薄膜晶体管的栅极电性连接反相器的输出端，源极电性连接GOA电路的第N级外置GOA单元的第一节点，漏极电性连接第七十六薄膜晶体管的源极；所述第七十六薄膜晶体管的栅极电性连接反相器的输出端，漏极接入电源负电位；所述第七十七薄膜晶体管的栅极电性连接反相器的输出端，源极接入GOA电路的第N级外置GOA单元的级传信号，漏极接入电源负电位；所述第七十八薄膜晶体管的栅极电性连接反相器的输出端，源极接入GOA电路的第N级外置GOA单元的扫描信号，漏极接入电源负电位。The built-in pull-down maintenance module includes a 75th thin film transistor, a 76th thin film transistor, a 77th thin film transistor, and a 78th thin film transistor; the gate of the 75th thin film transistor is electrically connected reversely The source of the output terminal of the phaser is electrically connected to the first node of the Nth stage external GOA unit of the GOA circuit, and the drain is electrically connected to the source of the 76th thin film transistor; The gate is electrically connected to the output terminal of the inverter, and the drain is connected to the negative potential of the power supply; the gate of the 77th thin film transistor is electrically connected to the output terminal of the inverter, and the source is connected to the Nth of the GOA circuit For the stage transmission signal of the external GOA unit, the drain is connected to the negative potential of the power supply; the gate of the 78th thin film transistor is electrically connected to the output terminal of the inverter, and the source is connected to the Nth stage of the GOA circuit. Set the scan signal of the GOA unit, and connect the drain to the negative potential of the power supply.
每一子像素均包括内置GOA单元；Each sub-pixel includes a built-in GOA unit;
每一子像素还包括电性连接对应一条扫描线的像素驱动电路及与像素驱动电路电性连接的像素电极，所述像素驱动电路、内置GOA单元及像素电极在平行于衬底所在平面的方向上依次设置。Each sub-pixel also includes a pixel drive circuit electrically connected to one scan line and a pixel electrode electrically connected to the pixel drive circuit. The pixel drive circuit, the built-in GOA unit and the pixel electrode are in a direction parallel to the plane where the substrate is located. Set up in turn.
本发明还提供一种显示面板，包括上述的TFT阵列基板。The present invention also provides a display panel including the above-mentioned TFT array substrate.
有益效果Beneficial effect
本发明的有益效果：本发明的TFT阵列基板包括衬底、设于衬底上且阵列排布的多个像素、多条扫描线及设于多个像素所在区域外侧的GOA电路，每一条扫描线对应与一行子像素电性连接， GOA电路包括多级外置GOA单元，多级外置GOA单元分别与多条扫描线对应电性连接，每一行子像素中的至少一个包括内置GOA单元，内置GOA单元包括反相器，反相器的输入端接入下拉维持信号，输出端输出控制信号，有利于减少GOA电路中元器件的数目，从而减小GOA电路的尺寸，以实现窄边框。本发明的显示面板的 GOA电路中元器件数目少，GOA电路的尺寸较小，能够实现窄边框设计。The beneficial effects of the present invention: the TFT array substrate of the present invention includes a substrate, a plurality of pixels arranged on the substrate and arranged in an array, a plurality of scan lines, and a GOA circuit arranged outside the area where the plurality of pixels are located. The lines are electrically connected to a row of sub-pixels. The GOA circuit includes multi-level external GOA units. The multi-level external GOA units are electrically connected to multiple scan lines. At least one of the sub-pixels in each row includes a built-in GOA unit. The built-in GOA unit includes an inverter. The input end of the inverter is connected to the pull-down sustain signal, and the output end outputs a control signal, which is beneficial to reduce the number of components in the GOA circuit, thereby reducing the size of the GOA circuit to achieve a narrow frame. In the GOA circuit of the display panel of the present invention, the number of components is small, the size of the GOA circuit is small, and a narrow frame design can be realized.
附图说明Description of the drawings
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。In order to further understand the features and technical content of the present invention, please refer to the following detailed description and accompanying drawings of the present invention. However, the accompanying drawings are only provided for reference and illustration and are not used to limit the present invention.
附图中，In the attached picture,
图1为本发明的TFT阵列基板的结构示意图； FIG. 1 is a schematic diagram of the structure of the TFT array substrate of the present invention;
图2为本发明的TFT阵列基板中具有内置GOA单元的子像素的示意图；2 is a schematic diagram of sub-pixels with built-in GOA units in the TFT array substrate of the present invention;
图3为本发明的TFT阵列基板的第一实施例的内置GOA单元的电路示意图；3 is a schematic circuit diagram of the built-in GOA unit of the first embodiment of the TFT array substrate of the present invention;
图4为本发明的TFT阵列基板的第一实施例的外置GOA单元的电路示意图；4 is a schematic circuit diagram of the external GOA unit of the first embodiment of the TFT array substrate of the present invention;
图5为本发明的TFT阵列基板的第二实施例的内置GOA单元的电路示意图；5 is a schematic circuit diagram of a built-in GOA unit of the second embodiment of the TFT array substrate of the present invention;
图6为本发明的TFT阵列基板的第二实施例的外置GOA单元的电路示意图。6 is a schematic circuit diagram of the external GOA unit of the second embodiment of the TFT array substrate of the present invention.
本发明的实施方式Embodiments of the invention
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。In order to further explain the technical means adopted by the present invention and its effects, the following describes in detail the preferred embodiments of the present invention and the accompanying drawings.
请参阅图1至图4，本发明第一实施例的TFT阵列基板包括衬底10、设于衬底10上且阵列排布的多个像素20、多条扫描线30及设于多个像素20所在区域外侧的至少一个GOA电路40。每一条扫描线30对应与一行子像素20电性连接。所述GOA电路40包括多级外置GOA单元，多级外置GOA单元分别与多条扫描线30对应电性连接。所述TFT阵列基板还包括设于衬底10上的多条数据线50，每一条数据线50对应与一列子像素20电性连接。1 to 4, the TFT array substrate of the first embodiment of the present invention includes a substrate 10, a plurality of pixels 20 arranged on the substrate 10 and arranged in an array, a plurality of scan lines 30, and a plurality of pixels. At least one GOA circuit 40 outside the area where 20 is located. Each scan line 30 is electrically connected to a row of sub-pixels 20 correspondingly. The GOA circuit 40 includes a multi-level external GOA unit, and the multi-level external GOA unit is electrically connected to a plurality of scan lines 30 respectively. The TFT array substrate further includes a plurality of data lines 50 arranged on the substrate 10, and each data line 50 is electrically connected to a column of sub-pixels 20.
每一行子像素20中的至少一个包括内置GOA单元21，请参阅图3，所述内置GOA单元21包括反相器211，所述反相器211的输入端A接入下拉维持信号，输出端B输出控制信号。At least one of the sub-pixels 20 in each row includes a built-in GOA unit 21. Referring to FIG. 3, the built-in GOA unit 21 includes an inverter 211. The input terminal A of the inverter 211 is connected to the pull-down sustain signal, and the output terminal B output control signal.
具体地，请参阅图3，所述反相器211包括第五十一薄膜晶体管T51、第五十二薄膜晶体管T52、第五十三薄膜晶体管T53、第五十四薄膜晶体管T54。所述第五十一薄膜晶体管T51的栅极及源极均接入电源正电位VDD，漏极电性连接第五十二薄膜晶体管T52的栅极。所述第五十二薄膜晶体管T52的源极接入电源正电位VDD，漏极为反相器211的输出端B。所述第五十三薄膜晶体管T53的栅极为反相器211的输入端A，源极电性连接第五十一薄膜晶体管T51的漏极，漏极接入电源负电位VSS。第五十四薄膜晶体管T54的栅极电性连接第五十三薄膜晶体管T53的栅极，源极电性连接第五十二薄膜晶体管T52的漏极，漏极接入电源负电位VSS。Specifically, referring to FIG. 3, the inverter 211 includes a fifty-first thin film transistor T51, a fifty-second thin film transistor T52, a fifty-third thin film transistor T53, and a fifty-fourth thin film transistor T54. The gate and source of the fifty-first thin film transistor T51 are both connected to the positive power supply VDD, and the drain is electrically connected to the gate of the fifty-second thin film transistor T52. The source of the fifty-second thin film transistor T52 is connected to the positive potential VDD of the power supply, and the drain is the output terminal B of the inverter 211. The gate of the fifty-third thin film transistor T53 is the input terminal A of the inverter 211, the source is electrically connected to the drain of the fifty-first thin film transistor T51, and the drain is connected to the negative power potential VSS. The gate of the fifty-fourth thin film transistor T54 is electrically connected to the gate of the fifty-third thin film transistor T53, the source is electrically connected to the drain of the fifty-second thin film transistor T52, and the drain is connected to the negative power potential VSS.
具体地，请参阅图4，在本发明的第一实施例中，每一级外置GOA单元均包括上拉控制模块41、上拉模块42、下传模块43、外置下拉模块44、外置下拉维持模块45。Specifically, referring to Figure 4, in the first embodiment of the present invention, each level of external GOA unit includes a pull-up control module 41, a pull-up module 42, a downstream module 43, an external pull-down module 44, and external Set the pull-down maintenance module 45.
设N为正整数，除了第一级及最后一级外置GOA单元外，在第N级外置GOA单元中，Let N be a positive integer, except for the first and last level external GOA units, in the Nth level external GOA unit,
所述上拉控制模块41接入第N-1级外置GOA单元的级传信号ST(N-1)、第一时钟信号CLK并电性连接第一节点Q(N)，用于在第一时钟信号CLK的控制下依据N-1级外置GOA单元的级传信号ST(N-1)上拉第一节点Q(N)的电位。The pull-up control module 41 is connected to the stage transmission signal ST(N-1) and the first clock signal CLK of the N-1th stage external GOA unit and is electrically connected to the first node Q(N) for Under the control of a clock signal CLK, the potential of the first node Q(N) is pulled up according to the stage transmission signal ST(N-1) of the N-1 stage external GOA unit.
所述上拉模块42接入第二时钟信号CLKB并电性连接第一节点Q(N)及第N条扫描线30，用于在第一节点Q(N)的控制下依据第二时钟信号CLKB输出扫描信号G(N)至第N条扫描线30。The pull-up module 42 is connected to the second clock signal CLKB and is electrically connected to the first node Q(N) and the Nth scan line 30, and is used to respond to the second clock signal under the control of the first node Q(N) CLKB outputs the scan signal G(N) to the Nth scan line 30.
所述下传模块43接入第二时钟信号CLKB并电性连接第一节点Q(N)，用于在第一节点Q(N)的控制下依据第二时钟信号CLKB输出级传信号ST(N)。The download module 43 accesses the second clock signal CLKB and is electrically connected to the first node Q(N) for outputting the stage transmission signal ST() according to the second clock signal CLKB under the control of the first node Q(N). N).
所述外置下拉模块44接入第N+1级外置GOA单元的扫描信号G(N+1)、第一恒压低电位VGL1、第二恒压低电位VGL2、扫描信号G(N)并电性连接第一节点Q(N)，用于在第N+1级外置GOA单元的扫描信号G(N+1)的控制下将第一节点Q(N)的电位下拉至第一恒压低电位VGL1并将扫描信号G(N)的电位下拉至第二恒压低电位VGL2。The external pull-down module 44 is connected to the scan signal G(N+1), the first constant voltage low potential VGL1, the second constant voltage low potential VGL2, and the scan signal G(N) of the N+1 level external GOA unit And electrically connected to the first node Q(N) for pulling down the potential of the first node Q(N) to the first node under the control of the scan signal G(N+1) of the N+1th stage external GOA unit The constant voltage low potential VGL1 and the scanning signal G(N) are pulled down to the second constant voltage low potential VGL2.
所述外置下拉维持模块45接入第一恒压低电位VGL1、第二恒压低电位VGL2、扫描信号G(N)、级传信号ST(N)并电性连接第一节点Q(N)以及反相器211的输出端B，用于在反相器211输出端B输出的控制信号的控制下，将第一节点Q(N)及级传信号ST(N)的电位维持在第一恒压低电位VGL1并将扫描信号G(N)的电位维持在第二恒压低电位VGL2。The external pull-down maintenance module 45 is connected to the first constant voltage low potential VGL1, the second constant voltage low potential VGL2, the scan signal G(N), the stage transmission signal ST(N), and is electrically connected to the first node Q(N). ) And the output terminal B of the inverter 211 are used to maintain the potential of the first node Q(N) and the stage transfer signal ST(N) at the first node under the control of the control signal output from the output terminal B of the inverter 211 A constant voltage low potential VGL1 maintains the potential of the scanning signal G(N) at a second constant voltage low potential VGL2.
进一步地，请参阅图3，所述上拉控制模块41包括第十一薄膜晶体管T11、第十二薄膜晶体管T12及第十三薄膜晶体管T13。所述第十一薄膜晶体管T11的栅极接入第一时钟信号CLK，源极接入第N-1级GOA单元的级传信号ST(N-1)，漏极电性连接第十二薄膜晶体管T12的源极。所述第十二薄膜晶体管T12的栅极接入第一时钟信号CLK，漏极电性连接第一节点Q(N)。所述第十三薄膜晶体管T13的栅极接入级传信号ST(N-1)，源极电性连接第二节点K(N)，漏极电性连接第十一薄膜晶体管T11的漏极。Further, referring to FIG. 3, the pull-up control module 41 includes an eleventh thin film transistor T11, a twelfth thin film transistor T12, and a thirteenth thin film transistor T13. The gate of the eleventh thin film transistor T11 is connected to the first clock signal CLK, the source is connected to the stage transmission signal ST(N-1) of the N-1th GOA unit, and the drain is electrically connected to the twelfth thin film Source of transistor T12. The gate of the twelfth thin film transistor T12 is connected to the first clock signal CLK, and the drain is electrically connected to the first node Q(N). The gate of the thirteenth thin film transistor T13 is connected to the stage transmission signal ST(N-1), the source is electrically connected to the second node K(N), and the drain is electrically connected to the drain of the eleventh thin film transistor T11 .
所述上拉模块42包括第二十一薄膜晶体管T21、第二十二薄膜晶体管T22及自举电容C1。所述第二十一薄膜晶体管T21的栅极电性连接第一节点Q(N)，源极接入第二时钟信号CLKB，漏极电性连接第N条扫描线30并输出扫描信号G(N)。所述第二十二薄膜晶体管T22的栅极电性连接第一节点Q(N)，源极接入第二时钟信号CLKB，漏极电性连接第二节点K(N)。所述自举电容C1的一端电性连接第一节点Q(N)，另一端接入扫描信号G(N)。The pull-up module 42 includes a twenty-first thin film transistor T21, a twenty-second thin film transistor T22, and a bootstrap capacitor C1. The gate of the twenty-first thin film transistor T21 is electrically connected to the first node Q(N), the source is connected to the second clock signal CLKB, and the drain is electrically connected to the Nth scan line 30 and outputs the scan signal G( N). The gate of the twenty-second thin film transistor T22 is electrically connected to the first node Q(N), the source is connected to the second clock signal CLKB, and the drain is electrically connected to the second node K(N). One end of the bootstrap capacitor C1 is electrically connected to the first node Q(N), and the other end is connected to the scanning signal G(N).
所述下传模块43包括第三十一薄膜晶体管T31。所述第三十一薄膜晶体管T31的栅极电性连接第一节点Q(N)，源极接入第二时钟信号CLKB，漏极输出级传信号ST(N)。The download module 43 includes a thirty-first thin film transistor T31. The gate of the thirty-first thin film transistor T31 is electrically connected to the first node Q(N), the source is connected to the second clock signal CLKB, and the drain outputs the stage transmission signal ST(N).
所述外置下拉模块44包括第四十一薄膜晶体管T41、第四十二薄膜晶体管T42、第四十三薄膜晶体管T43。所述第四十一薄膜晶体管T41的栅极接入第N+1级外置GOA单元的扫描信号G(N+1)，源极电性连接第一节点Q(N)，漏极电性连接第四十二薄膜晶体管T42的源极。所述第四十二薄膜晶体管T42的栅极接入第N+1级外置GOA单元的扫描信号G(N+1)，漏极接入第一恒压低电位VGL1。所述第四十三薄膜晶体管T43的栅极接入第N+1级外置GOA单元的扫描信号G(N+1)，源极接入扫描信号G(N)，漏极接入第二恒压低电位VGL2。The external pull-down module 44 includes a forty-first thin film transistor T41, a forty-second thin film transistor T42, and a forty-third thin film transistor T43. The gate of the forty-first thin film transistor T41 is connected to the scanning signal G(N+1) of the N+1th stage external GOA unit, the source is electrically connected to the first node Q(N), and the drain is electrically connected The source of the forty-second thin film transistor T42 is connected. The gate of the forty-second thin film transistor T42 is connected to the scan signal G(N+1) of the N+1th stage external GOA unit, and the drain is connected to the first constant voltage low potential VGL1. The gate of the forty-third thin film transistor T43 is connected to the scan signal G(N+1) of the N+1th stage external GOA unit, the source is connected to the scan signal G(N), and the drain is connected to the second Constant voltage low potential VGL2.
所述外置下拉维持模块45包括第五十五薄膜晶体管T55、第五十六薄膜晶体管T56、第五十七薄膜晶体管T57、第五十八薄膜晶体管T58及第五十九薄膜晶体管T59。所述第五十五薄膜晶体管T55的栅极电性连接反相器211的输出端B，源极电性连接第一节点Q(N)，漏极电性连接第五十六薄膜晶体管T56的源极并电性连接第十一薄膜晶体管T11的漏极。所述第五十六薄膜晶体管T56的栅极电性连接反相器211的输出端B，漏极接入第一恒压低电位VGL1。所述第五十七薄膜晶体管T57的栅极电性连接反相器211的输出端B，源极接入级传信号ST(N)，漏极接入第一恒压低电位VGL1。所述第五十八薄膜晶体管T58的栅极电性连接反相器211的输出端B，源极接入扫描信号G(N)，漏极接入第二恒压低电位VGL2。所述第五十九薄膜晶体管T59的栅极电性连接反相器211的输出端B，源极电性连接第二节点K(N)，漏极接入第二恒压低电位VGL2。The external pull-down maintenance module 45 includes a fifty-fifth thin film transistor T55, a fifty-sixth thin film transistor T56, a fifty-seventh thin film transistor T57, a fifty-eighth thin film transistor T58, and a fifty-ninth thin film transistor T59. The gate of the fifty-fifth thin film transistor T55 is electrically connected to the output terminal B of the inverter 211, the source is electrically connected to the first node Q(N), and the drain is electrically connected to the fifty-sixth thin film transistor T56. The source electrode is electrically connected to the drain electrode of the eleventh thin film transistor T11. The gate of the fifty-sixth thin film transistor T56 is electrically connected to the output terminal B of the inverter 211, and the drain is connected to the first constant voltage low potential VGL1. The gate of the fifty-seventh thin film transistor T57 is electrically connected to the output terminal B of the inverter 211, the source is connected to the stage transmission signal ST(N), and the drain is connected to the first constant voltage low potential VGL1. The gate of the fifty-eighth thin film transistor T58 is electrically connected to the output terminal B of the inverter 211, the source is connected to the scan signal G(N), and the drain is connected to the second constant voltage low potential VGL2. The gate of the fifty-ninth thin film transistor T59 is electrically connected to the output terminal B of the inverter 211, the source is electrically connected to the second node K(N), and the drain is connected to the second constant voltage low potential VGL2.
更进一步地，在第一级外置GOA单元中，第十一薄膜晶体管T11的栅极接入起始信号（未图示）。在最后一级外置GOA单元中，所述第四十一薄膜晶体管T41、第四十二薄膜晶体管T42及第四十三薄膜晶体管T43的栅极接入起始信号。Furthermore, in the first-stage external GOA unit, the gate of the eleventh thin film transistor T11 is connected to the start signal (not shown). In the last stage of the external GOA unit, the gates of the forty-first thin film transistor T41, the forty-second thin film transistor T42, and the forty-third thin film transistor T43 are connected to the start signal.
具体地，请参阅图3，在本发明的第一实施例中，所述内置GOA单元21还包括下拉维持信号产生模块212。除了第一行子像素20外，在第N行子像素20的内置GOA单元21中，下拉维持信号产生模块212电性连接第N-1条扫描线30也即接收GOA电路50中第N-1级外置GOA单元的扫描信号G(N-1)、第N条扫描线30也即接收GOA电路50中第N级外置GOA单元的扫描信号G(N)以及反相器211的输入端A，用于在第N-1条扫描线30及第N条扫描线30中的至少一个的电位为高电位时向反相器211的输入端A输入高电位的下拉维持信号，在第N-1条扫描线30及第N条扫描线30的电位均为低电位时向反相器211的输入端A输入低电位的下拉维持信号。Specifically, referring to FIG. 3, in the first embodiment of the present invention, the built-in GOA unit 21 further includes a pull-down sustain signal generating module 212. Except for the first row of sub-pixels 20, in the built-in GOA unit 21 of the Nth row of sub-pixels 20, the pull-down sustain signal generating module 212 is electrically connected to the N-1th scan line 30, that is, the N-th receiving GOA circuit 50 The scan signal G(N-1) of the level 1 external GOA unit, the Nth scan line 30 also receives the scan signal G(N) of the Nth level external GOA unit in the GOA circuit 50 and the input of the inverter 211 Terminal A is used to input a high-level pull-down sustain signal to the input terminal A of the inverter 211 when the potential of at least one of the N-1th scan line 30 and the Nth scan line 30 is high. When the potentials of the N-1 scan lines 30 and the Nth scan line 30 are both low, a low-level pull-down sustain signal is input to the input terminal A of the inverter 211.
进一步的，请参阅图3，所述下拉维持信号产生模块212包括第六十一薄膜晶体管T61及第六十二薄膜晶体管T62。所述第六十一薄膜晶体管T61的栅极及源极均电性连接第N-1条扫描线30，漏极电性连接反相器211的输入端A。所述第六十二薄膜晶体管T62的栅极及源极均电性连接第N条扫描线30，漏极电性连接反相器211的输入端A。Further, referring to FIG. 3, the pull-down sustain signal generating module 212 includes a sixty-first thin film transistor T61 and a sixty-second thin film transistor T62. The gate and source of the 61st thin film transistor T61 are electrically connected to the N-1th scan line 30, and the drain is electrically connected to the input terminal A of the inverter 211. The gate and source of the 62nd thin film transistor T62 are electrically connected to the Nth scan line 30, and the drain is electrically connected to the input terminal A of the inverter 211.
更进一步的，在第一行子像素20的内置GOA单元21中，第六十薄膜晶体管T61的栅极接入起始信号。Furthermore, in the built-in GOA unit 21 of the first row of sub-pixels 20, the gate of the sixtieth thin film transistor T61 is connected to the start signal.
具体地，多个子像素20中设置有内置GOA单元21的子像素可以是正常的显示像素，也可以是具有其他功能的虚拟（dummy）像素。Specifically, the sub-pixels provided with the built-in GOA unit 21 among the plurality of sub-pixels 20 may be normal display pixels, or may be dummy pixels with other functions.
优选地，每一子像素20均包括内置GOA单元21。请参阅图2，每一子像素20还包括电性连接对应一条扫描线30及数据线50的像素驱动电路22及与像素驱动电路22电性连接的像素电极23，所述像素驱动电路22、内置GOA单元21及像素电极23在平行于衬底10所在平面的方向上依次设置，顺序可以根据实际需求进行调整。Preferably, each sub-pixel 20 includes a built-in GOA unit 21. Referring to FIG. 2, each sub-pixel 20 also includes a pixel driving circuit 22 electrically connected to one scan line 30 and a data line 50, and a pixel electrode 23 electrically connected to the pixel driving circuit 22. The pixel driving circuit 22, The built-in GOA unit 21 and the pixel electrode 23 are sequentially arranged in a direction parallel to the plane where the substrate 10 is located, and the sequence can be adjusted according to actual requirements.
进一步的，所述像素驱动电路可以为现有技术中的OLED像素驱动电路或液晶像素驱动电路，其具体结构为现有技术，在此不展开进行论述，当像素驱动电路为OLED像素驱动电路时，该TFT阵列基板为OLED显示面板的TFT阵列基板，像素电极23对应为OLED器件的阳极，当像素驱动电路为液晶像素驱动电路时，该TFT阵列基板为液晶显示面板的TFT阵列基板，像素电极23与彩膜基板中的公共电极相对，对夹与两者时间的液晶层进行驱动。Further, the pixel drive circuit may be an OLED pixel drive circuit or a liquid crystal pixel drive circuit in the prior art, and its specific structure is the prior art, and will not be discussed here. When the pixel drive circuit is an OLED pixel drive circuit The TFT array substrate is the TFT array substrate of the OLED display panel, and the pixel electrode 23 corresponds to the anode of the OLED device. When the pixel driving circuit is a liquid crystal pixel driving circuit, the TFT array substrate is the TFT array substrate of the liquid crystal display panel. 23 is opposed to the common electrode in the color filter substrate, and drives the liquid crystal layer sandwiched between the two.
具体地，在图1所示的实施例中， GOA电路50的数量为两个，该两个GOA电路50分别位于多个子像素20所在区域的两侧。Specifically, in the embodiment shown in FIG. 1, the number of GOA circuits 50 is two, and the two GOA circuits 50 are respectively located on both sides of the area where the multiple sub-pixels 20 are located.
需要说明的是，本发明的第一实施例中在子像素20中设置内置GOA单元21，将用于对GOA电路50中将第一节点、扫描信号及级传信号维持在低电位的第五十五薄膜晶体管T55、第五十六薄膜晶体管T56、第五十七薄膜晶体管T57及第五十八薄膜晶体管T58进行控制的反相器211设置在内置GOA单元21之中，从而GOA电路50的每一级外置GOA单元中无需设置反相器，GOA电路50的元器件数量相较于现有技术大大降低，从而使得GOA电路50的尺寸降低，有利于实现窄边框设计以提升产品的品质。It should be noted that in the first embodiment of the present invention, a built-in GOA unit 21 is provided in the sub-pixel 20, which is used to maintain the first node, scan signal, and stage transfer signal in the GOA circuit 50 at a low potential. The inverter 211 controlled by the fifteenth film transistor T55, the fifty-sixth film transistor T56, the fifty-seventh film transistor T57, and the fifty-eighth film transistor T58 is provided in the built-in GOA unit 21, so that the GOA circuit 50 There is no need to install an inverter in each level of external GOA unit, and the number of components of the GOA circuit 50 is greatly reduced compared with the prior art, so that the size of the GOA circuit 50 is reduced, which is conducive to the realization of a narrow frame design to improve product quality .
请结合图1、图2、图5及图6，本发明的第二实施例与上述第一实施例的区别在于，在第N行子像素20的内置GOA单元21中，所述反相器211的输入端A电性连接GOA电路50的第N级外置GOA单元的第一节点Q(N) 接收其传输的下拉维持信号。与此同时，每一级外置GOA单元不再设置有外置下拉模块44、外置下拉维持模块45，而所述内置GOA单元21还包括内置下拉模块213及内置下拉维持模块214。Referring to Figure 1, Figure 2, Figure 5 and Figure 6, the difference between the second embodiment of the present invention and the above-mentioned first embodiment is that in the built-in GOA unit 21 of the sub-pixel 20 in the Nth row, the inverter The input terminal A of 211 is electrically connected to the first node Q(N) of the N-th stage external GOA unit of the GOA circuit 50 to receive the pull-down sustain signal transmitted therefrom. At the same time, each level of external GOA unit is no longer provided with an external pull-down module 44 and an external pull-down maintenance module 45, and the built-in GOA unit 21 further includes a built-in pull-down module 213 and a built-in pull-down maintenance module 214.
具体地，请参阅图5，除了最后一行子像素20外，在第N行子像素20的内置GOA单元21中，Specifically, referring to FIG. 5, except for the last row of sub-pixels 20, in the built-in GOA unit 21 of the Nth row of sub-pixels 20,
所述内置下拉模块213接入GOA电路50的第N+1级外置GOA单元的扫描信号G(N+1)、电源负电位VSS、GOA电路50的第N级外置GOA单元的扫描信号G(N)，并电性连接GOA电路50的第N级外置GOA单元的第一节点Q(N)，用于在GOA电路50的第N+1级外置GOA单元的扫描信号G(N+1)的控制下将GOA电路50的N级外置GOA单元的第一节点Q(N)的电位及GOA电路50的第N级外置GOA单元的扫描信号G(N)的电位下拉至电源负电位VSS。The built-in pull-down module 213 is connected to the scan signal G(N+1) of the N+1 level external GOA unit of the GOA circuit 50, the negative power supply potential VSS, and the scan signal of the N level external GOA unit of the GOA circuit 50 G(N), and electrically connected to the first node Q(N) of the Nth stage external GOA unit of the GOA circuit 50, for the scanning signal G( Under the control of N+1), the potential of the first node Q(N) of the N-level external GOA unit of the GOA circuit 50 and the potential of the scanning signal G(N) of the N-th external GOA unit of the GOA circuit 50 are pulled down To the negative potential VSS of the power supply.
所述内置下拉维持模块214接入电源负电位VSS、GOA电路50的第N级外置GOA单元的扫描信号G(N)、GOA电路50的第N级外置GOA单元的级传信号ST(N)并电性连接GOA电路50的第N级外置GOA单元的第一节点Q(N)以及反相器211的输出端B，用于在反相器211输出端B输出的控制信号的控制下，将GOA电路50的第N级外置GOA单元的第一节点Q(N)的电位、第N级外置GOA单元的级传信号ST(N)的电位及GOA电路50的第N级外置GOA单元的扫描信号G(N)的电位维持在电源负电位VSS。The built-in pull-down maintenance module 214 is connected to the negative power potential VSS, the scan signal G(N) of the Nth level external GOA unit of the GOA circuit 50, and the level transmission signal ST( N) and electrically connected to the first node Q(N) of the N-th stage external GOA unit of the GOA circuit 50 and the output terminal B of the inverter 211 for the control signal output from the output terminal B of the inverter 211 Under the control, the potential of the first node Q(N) of the Nth external GOA unit of the GOA circuit 50, the potential of the stage transfer signal ST(N) of the Nth external GOA unit and the Nth of the GOA circuit 50 The level of the scanning signal G(N) of the external GOA unit is maintained at the negative power potential VSS.
进一步地，请参阅图5，在本发明的第二实施例中，所述内置下拉模块213包括第六十一薄膜晶体管T61’、第六十二薄膜晶体管T62’、第六十三薄膜晶体管T63’。所述第六十一薄膜晶体管T61’的栅极接入GOA电路50的第N+1级外置GOA单元的扫描信号G(N+1)，源极电性连接GOA电路50的第N级外置GOA单元的第一节点Q(N)，漏极电性连接第六十二薄膜晶体管T62’的源极。所述第六十二薄膜晶体管T62’的栅极接入GOA电路50的第N+1级外置GOA单元的扫描信号G(N+1)，漏极接入电源负电位VSS。所述第六十三薄膜晶体管T63’的栅极接入GOA电路50的第N+1级外置GOA单元的扫描信号G(N+1)，源极接入GOA电路50的第N级外置GOA单元的扫描信号G(N)，漏极接入电源负电位VSS。Further, referring to FIG. 5, in the second embodiment of the present invention, the built-in pull-down module 213 includes a sixty-first thin film transistor T61', a sixty-second thin film transistor T62', and a sixty-third thin film transistor T63. '. The gate of the sixty-first thin film transistor T61' is connected to the scanning signal G(N+1) of the N+1th stage external GOA unit of the GOA circuit 50, and the source is electrically connected to the Nth stage of the GOA circuit 50 The drain of the first node Q(N) of the external GOA unit is electrically connected to the source of the 62nd thin film transistor T62'. The gate of the sixty-second thin film transistor T62' is connected to the scanning signal G(N+1) of the N+1th stage external GOA unit of the GOA circuit 50, and the drain is connected to the negative power supply VSS. The gate of the sixty-third thin film transistor T63' is connected to the scanning signal G(N+1) of the N+1th stage of the external GOA unit of the GOA circuit 50, and the source is connected to the Nth stage of the GOA circuit 50. Set the scan signal G(N) of the GOA unit, and the drain is connected to the negative potential VSS of the power supply.
所述内置下拉维持模块214包括第七十五薄膜晶体管T75’、第七十六薄膜晶体管T76’、第七十七薄膜晶体管T77’、第七十八薄膜晶体管T78’及第七十九薄膜晶体管T79’。所述第七十五薄膜晶体管T75’的栅极电性连接反相器211的输出端B，源极电性连接GOA电路50的第N级外置GOA单元的第一节点Q(N)，漏极电性连接第七十六薄膜晶体管T76’的源极以及GOA电路50的第N级外置GOA单元的第十一薄膜晶体管T11的漏极，该连接点为一第三节点L(N)。所述第七十六薄膜晶体管T76’的栅极电性连接反相器211的输出端B，漏极接入电源负电位VSS。所述第七十七薄膜晶体管T77’的栅极电性连接反相器211的输出端B，源极接入GOA电路50的第N级外置GOA单元的级传信号ST(N)，漏极接入电源负电位VSS。所述第七十八薄膜晶体管T78’的栅极电性连接反相器211的输出端B，源极接入GOA电路50的第N级外置GOA单元的扫描信号G(N)，漏极接入电源负电位VSS。所述第七十九薄膜晶体管T79’的栅极电性连接反相器211的输出端B，源极接入GOA电路50的第N级外置GOA单元的第二节点K(N)，漏极接入电源负电压VSS。The built-in pull-down maintenance module 214 includes a seventy-fifth thin film transistor T75', a seventy-sixth thin film transistor T76', a seventy-seventh thin film transistor T77', a seventy-eighth thin film transistor T78', and a seventy-ninth thin film transistor T79'. The gate of the seventy-fifth thin film transistor T75' is electrically connected to the output terminal B of the inverter 211, and the source is electrically connected to the first node Q(N) of the Nth stage external GOA unit of the GOA circuit 50, The drain is electrically connected to the source of the 76th thin film transistor T76' and the drain of the eleventh thin film transistor T11 of the Nth stage external GOA unit of the GOA circuit 50, and the connection point is a third node L(N ). The gate of the seventy-sixth thin film transistor T76' is electrically connected to the output terminal B of the inverter 211, and the drain is connected to the negative power potential VSS. The gate of the seventy-seventh thin film transistor T77' is electrically connected to the output terminal B of the inverter 211, the source is connected to the stage transmission signal ST(N) of the Nth stage of the external GOA unit of the GOA circuit 50, and the drain is The pole is connected to the negative potential VSS of the power supply. The gate of the 78th thin film transistor T78' is electrically connected to the output terminal B of the inverter 211, the source is connected to the scanning signal G(N) of the Nth stage external GOA unit of the GOA circuit 50, and the drain is Connect the power supply negative potential VSS. The gate of the seventy-ninth thin film transistor T79' is electrically connected to the output terminal B of the inverter 211, the source is connected to the second node K(N) of the Nth stage external GOA unit of the GOA circuit 50, and the drain is The pole is connected to the negative power supply voltage VSS.
更进一步地，在最后一行子像素20的内置GOA单元21中，第六十一薄膜晶体管T61’、第六十二薄膜晶体管T62’及第六十三薄膜晶体管T63’的栅极均接入起始信号。Furthermore, in the built-in GOA unit 21 of the last row of sub-pixels 20, the gates of the 61st thin film transistor T61', the 62nd thin film transistor T62', and the 63rd thin film transistor T63' are connected to each other. Start signal.
其余均与上述第一实施例相同，在此不再进行赘述。The rest are the same as the above-mentioned first embodiment, and will not be repeated here.
需要说明是，本发明的第二实施例中在子像素20中设置内置GOA单元21，将反相器211、内置下拉模块213及内置下拉维持模块214均设置在内置GOA单元21中，从而GOA电路50中无需设置反相器、下拉模块及下拉维持模块，GOA电路50的元器件数量相较于现有技术大大降低，从而使得GOA电路50的尺寸降低，有利于实现窄边框设计以提升产品的品质。It should be noted that in the second embodiment of the present invention, the built-in GOA unit 21 is provided in the sub-pixel 20, and the inverter 211, the built-in pull-down module 213, and the built-in pull-down maintenance module 214 are all provided in the built-in GOA unit 21, so that the GOA There is no need to provide an inverter, pull-down module, and pull-down maintenance module in the circuit 50. Compared with the prior art, the number of components of the GOA circuit 50 is greatly reduced, so that the size of the GOA circuit 50 is reduced, which is conducive to the realization of a narrow frame design to improve the product Quality.
基于同一发明构思，本发明还提供一种显示面板，包括上述的TFT阵列基板。在此不再对TFT阵列基板的结构进行重复性描述。Based on the same inventive concept, the present invention also provides a display panel including the above-mentioned TFT array substrate. The structure of the TFT array substrate will not be described repeatedly here.
需要说明的是，本发明的显示面板中，在子像素20中设置内置GOA单元21，将反相器211、内置下拉模块213及内置下拉维持模块214均设置在内置GOA单元21中，或者仅将反相器211设置在内置GOA单元21中，使得GOA电路50的元器件数量相较于现有技术大大降低，从而使得GOA电路50的尺寸降低，有利于实现窄边框设计以提升产品的品质。It should be noted that in the display panel of the present invention, the built-in GOA unit 21 is provided in the sub-pixel 20, and the inverter 211, the built-in pull-down module 213, and the built-in pull-down maintenance module 214 are all provided in the built-in GOA unit 21, or only The inverter 211 is arranged in the built-in GOA unit 21, so that the number of components of the GOA circuit 50 is greatly reduced compared with the prior art, so that the size of the GOA circuit 50 is reduced, which is beneficial to realize a narrow frame design and improve the quality of the product .
综上所述，本发明的TFT阵列基板包括衬底、设于衬底上且阵列排布的多个像素、多条扫描线及设于多个像素所在区域外侧的GOA电路，每一条扫描线对应与一行子像素电性连接， GOA电路包括多级外置GOA单元，多级外置GOA单元分别与多条扫描线对应电性连接，每一行子像素中的至少一个包括内置GOA单元，内置GOA单元包括反相器，反相器的输入端接入下拉维持信号，输出端输出控制信号，有利于减少GOA电路中元器件的数目，从而减小GOA电路的尺寸，以实现窄边框。本发明的显示面板的 GOA电路中元器件数目少，GOA电路的尺寸较小，能够实现窄边框设计。In summary, the TFT array substrate of the present invention includes a substrate, a plurality of pixels arranged on the substrate and arranged in an array, a plurality of scan lines, and a GOA circuit arranged outside the area where the plurality of pixels are located. Each scan line Correspondingly to be electrically connected to a row of sub-pixels, the GOA circuit includes a multi-level external GOA unit. The multi-level external GOA unit is electrically connected to a plurality of scan lines. At least one of the sub-pixels in each row includes a built-in GOA unit. The GOA unit includes an inverter. The input terminal of the inverter is connected to a pull-down sustain signal, and the output terminal outputs a control signal, which is beneficial to reduce the number of components in the GOA circuit, thereby reducing the size of the GOA circuit to achieve a narrow frame. In the GOA circuit of the display panel of the present invention, the number of components is small, the size of the GOA circuit is small, and a narrow frame design can be realized.
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。As mentioned above, for those of ordinary skill in the art, various other corresponding changes and modifications can be made according to the technical solutions and technical ideas of the present invention, and all these changes and modifications shall fall within the protection scope of the claims of the present invention. .

Claims (18)

  1. 一种TFT阵列基板，包括衬底、设于衬底上且阵列排布的多个像素、多条扫描线及设于多个像素所在区域外侧的至少一个GOA电路；每一条扫描线对应与一行子像素电性连接；所述GOA电路包括多级外置GOA单元，多级外置GOA单元分别与多条扫描线对应电性连接；A TFT array substrate includes a substrate, a plurality of pixels arranged on the substrate and arranged in an array, a plurality of scan lines, and at least one GOA circuit arranged outside the area where the plurality of pixels are located; each scan line corresponds to one row The sub-pixels are electrically connected; the GOA circuit includes a multi-level external GOA unit, and the multi-level external GOA unit is electrically connected to a plurality of scan lines respectively;
    每一行子像素中的至少一个包括内置GOA单元，所述内置GOA单元包括反相器，所述反相器的输入端接入下拉维持信号，输出端输出控制信号。At least one of the sub-pixels in each row includes a built-in GOA unit, the built-in GOA unit includes an inverter, the input end of the inverter is connected to a pull-down sustain signal, and the output end outputs a control signal.
  2. 如权利要求1所述的TFT阵列基板，其中，每一级外置GOA单元均包括上拉控制模块、上拉模块及下传模块；3. The TFT array substrate of claim 1, wherein each level of external GOA unit includes a pull-up control module, a pull-up module, and a downstream module;
    设N为正整数，除了第一级外置GOA单元外，在第N级外置GOA单元中，Set N to be a positive integer, except for the first-level external GOA unit, in the Nth-level external GOA unit,
    所述上拉控制模块接入第N-1级外置GOA单元的级传信号、第一时钟信号并电性连接第一节点，用于在第一时钟信号的控制下依据N-1级外置GOA单元的级传信号上拉第一节点的电位；The pull-up control module is connected to the stage transmission signal and the first clock signal of the N-1th stage external GOA unit and is electrically connected to the first node, and is used to control the first clock signal according to the N-1 stage external Set the level transmission signal of the GOA unit to pull up the potential of the first node;
    所述上拉模块接入第二时钟信号并电性连接第一节点及第N条扫描线，用于在第一节点的控制下依据第二时钟信号输出扫描信号至第N条扫描线；The pull-up module is connected to the second clock signal and is electrically connected to the first node and the Nth scan line for outputting the scan signal to the Nth scan line according to the second clock signal under the control of the first node;
    所述下传模块接入第二时钟信号并电性连接第一节点，用于在第一节点的控制下依据第二时钟信号输出级传信号。The download module is connected to the second clock signal and is electrically connected to the first node, and is used for output stage signal transmission according to the second clock signal under the control of the first node.
  3. 如权利要求2所述的TFT阵列基板，其中，每一级外置GOA单元还包括外置下拉模块以及外置下拉维持模块；3. The TFT array substrate of claim 2, wherein each level of external GOA unit further comprises an external pull-down module and an external pull-down maintenance module;
    除了最后一级外置GOA单元外，在第N级外置GOA单元中，In addition to the last level external GOA unit, in the Nth level external GOA unit,
    所述外置下拉模块接入第N+1级外置GOA单元的扫描信号、第一恒压低电位、第二恒压低电位、扫描信号并电性连接第一节点，用于在第N+1级外置GOA单元的扫描信号的控制下将第一节点的电位下拉至第一恒压低电位并将扫描信号的电位下拉至第二恒压低电位；The external pull-down module is connected to the scanning signal, the first constant voltage low potential, the second constant voltage low potential, the scanning signal of the N+1th level external GOA unit, and is electrically connected to the first node for Under the control of the scan signal of the +1 level external GOA unit, the potential of the first node is pulled down to the first constant voltage low potential and the potential of the scan signal is pulled down to the second constant voltage low potential;
    所述外置下拉维持模块接入第一恒压低电位、第二恒压低电位、扫描信号、级传信号并电性连接第一节点以及反相器的输出端，用于在反相器输出端输出的控制信号的控制下，将第一节点及级传信号的电位维持在第一恒压低电位并将扫描信号的电位维持在第二恒压低电位。The external pull-down maintenance module is connected to the first constant voltage low potential, the second constant voltage low potential, the scanning signal, the stage transmission signal and is electrically connected to the first node and the output terminal of the inverter for Under the control of the control signal output from the output terminal, the potential of the first node and the level transfer signal is maintained at the first constant voltage low potential and the potential of the scanning signal is maintained at the second constant voltage low potential.
  4. 如权利要求3所述的TFT阵列基板，其中，所述外置下拉模块包括第四十一薄膜晶体管、第四十二薄膜晶体管、第四十三薄膜晶体管；所述第四十一薄膜晶体管的栅极接入第N+1级外置GOA单元的扫描信号，源极电性连接第一节点，漏极电性连接第四十二薄膜晶体管的源极；所述第四十二薄膜晶体管的栅极接入第N+1级外置GOA单元的扫描信号，漏极接入第一恒压低电位；所述第四十三薄膜晶体管的栅极接入第N+1级外置GOA单元的扫描信号，源极接入扫描信号，漏极接入第二恒压低电位；The TFT array substrate of claim 3, wherein the external pull-down module comprises a forty-first thin film transistor, a forty-second thin film transistor, and a forty-third thin film transistor; The gate is connected to the scan signal of the N+1 level external GOA unit, the source is electrically connected to the first node, and the drain is electrically connected to the source of the 42nd thin film transistor; The gate is connected to the scan signal of the N+1 level external GOA unit, and the drain is connected to the first constant voltage low potential; the gate of the 43rd thin film transistor is connected to the N+1 level external GOA unit The source is connected to the scanning signal, and the drain is connected to the second constant voltage low potential;
    所述外置下拉维持模块包括第五十五薄膜晶体管、第五十六薄膜晶体管、第五十七薄膜晶体管及第五十八薄膜晶体管；所述第五十五薄膜晶体管的栅极电性连接反相器的输出端，源极电性连接第一节点，漏极电性连接第五十六薄膜晶体管的源极；所述第五十六薄膜晶体管的栅极电性连接反相器的输出端，漏极接入第一恒压低电位；所述第五十七薄膜晶体管的栅极电性连接反相器的输出端，源极接入级传信号，漏极接入第一恒压低电位；所述第五十八薄膜晶体管的栅极电性连接反相器的输出端，源极接入扫描信号，漏极接入第二恒压低电位。The external pull-down maintenance module includes a fifty-fifth thin film transistor, a fifty-sixth thin film transistor, a fifty-seventh thin film transistor and a fifty-eighth thin film transistor; the gate of the fifty-fifth thin film transistor is electrically connected The output terminal of the inverter, the source is electrically connected to the first node, and the drain is electrically connected to the source of the fifty-sixth thin film transistor; the gate of the fifty-sixth thin film transistor is electrically connected to the output of the inverter The drain is connected to the first constant voltage low potential; the gate of the fifty-seventh thin film transistor is electrically connected to the output terminal of the inverter, the source is connected to the stage signal, and the drain is connected to the first constant voltage Low potential; the gate of the fifty-eighth thin film transistor is electrically connected to the output terminal of the inverter, the source is connected to the scan signal, and the drain is connected to the second constant voltage low potential.
  5. 如权利要求3所述的TFT阵列基板，其中，所述内置GOA单元还包括下拉维持信号产生模块；除了第一行子像素外，在第N行子像素的内置GOA单元中，下拉维持信号产生模块电性连接第N-1条扫描线、第N条扫描线以及反相器的输入端，用于在第N-1条扫描线及第N条扫描线中的至少一个的电位为高电位时向反相器的输入端输入高电位的下拉维持信号，在第N-1条扫描线及第N条扫描线的电位均为低电位时向反相器的输入端输入低电位的下拉维持信号。The TFT array substrate of claim 3, wherein the built-in GOA unit further comprises a pull-down sustain signal generating module; in addition to the first row of sub-pixels, in the built-in GOA unit of the Nth row of sub-pixels, the pull-down sustain signal is generated The module is electrically connected to the N-1th scan line, the Nth scan line, and the input terminal of the inverter, and is used to set the potential of at least one of the N-1th scan line and the Nth scan line to a high potential When inputting a high-level pull-down sustain signal to the input terminal of the inverter, input a low-level pull-down sustaining signal to the input terminal of the inverter when the potentials of the N-1th scan line and the Nth scan line are both low. signal.
  6. 如权利要求5所述的TFT阵列基板，其中，所述下拉维持信号产生模块包括第六十一薄膜晶体管及第六十二薄膜晶体管；所述第六十一薄膜晶体管的栅极及源极均电性连接第N-1条扫描线，漏极电性连接反相器的输入端；所述第六十二薄膜晶体管的栅极及源极均电性连接第N条扫描线，漏极电性连接反相器的输入端。7. The TFT array substrate of claim 5, wherein the pull-down sustain signal generating module includes a 61st thin film transistor and a 62nd thin film transistor; the gate and source of the 61st thin film transistor are both The N-1th scan line is electrically connected, and the drain is electrically connected to the input terminal of the inverter; the gate and source of the 62nd thin film transistor are electrically connected to the Nth scan line, and the drain is electrically connected Connect the input terminal of the inverter.
  7. 如权利要求2所述的TFT阵列基板，其中，在第N行子像素的内置GOA单元中，所述反相器的输入端电性连接GOA电路的第N级外置GOA单元的第一节点接收其传输的下拉维持信号；The TFT array substrate of claim 2, wherein in the built-in GOA unit of the Nth row of sub-pixels, the input terminal of the inverter is electrically connected to the first node of the Nth stage external GOA unit of the GOA circuit Receive the pull-down sustain signal transmitted by it;
    所述内置GOA单元还包括内置下拉模块及内置下拉维持模块；The built-in GOA unit also includes a built-in pull-down module and a built-in pull-down maintenance module;
    除了最后一行子像素外，在第N行子像素的内置GOA单元中，Except for the last row of sub-pixels, in the built-in GOA unit of the Nth row of sub-pixels,
    所述内置下拉模块接入GOA电路的第N+1级外置GOA单元的扫描信号、电源负电位、GOA电路的第N级外置GOA单元的扫描信号，并电性连接GOA电路的第N级外置GOA单元的第一节点，用于在GOA电路的第N+1级外置GOA单元的扫描信号的控制下将GOA电路的N级外置GOA单元的第一节点的电位及GOA电路的第N级外置GOA单元的扫描信号的电位下拉至电源负电位；The built-in pull-down module is connected to the scan signal of the N+1 level external GOA unit of the GOA circuit, the negative potential of the power supply, the scan signal of the N level external GOA unit of the GOA circuit, and is electrically connected to the Nth level of the GOA circuit The first node of the first-level external GOA unit is used to control the potential of the first node of the N-level external GOA unit of the GOA circuit and the GOA circuit under the control of the scan signal of the N+1th-level external GOA unit of the GOA circuit The potential of the scanning signal of the Nth level external GOA unit is pulled down to the negative potential of the power supply;
    所述内置下拉维持模块接入电源负电位、GOA电路的第N级外置GOA单元的扫描信号、GOA电路的第N级外置GOA单元的级传信号并电性连接GOA电路的第N级外置GOA单元的第一节点以及反相器的输出端，用于在反相器输出端输出的控制信号的控制下，将GOA电路的第N级外置GOA单元的第一节点的电位、第N级外置GOA单元的级传信号的电位及GOA电路的第N级外置GOA单元的扫描信号的电位维持在电源负电位。The built-in pull-down maintenance module is connected to the negative potential of the power supply, the scan signal of the Nth level external GOA unit of the GOA circuit, the level transmission signal of the Nth level external GOA unit of the GOA circuit, and are electrically connected to the Nth level of the GOA circuit The first node of the external GOA unit and the output terminal of the inverter are used to reduce the potential of the first node of the Nth stage external GOA unit of the GOA circuit under the control of the control signal output from the inverter output terminal. The potential of the stage transfer signal of the Nth level external GOA unit and the potential of the scan signal of the Nth level external GOA unit of the GOA circuit are maintained at the negative potential of the power supply.
  8. 如权利要求7所述的TFT阵列基板，其中，所述内置下拉模块包括第六十一薄膜晶体管、第六十二薄膜晶体管、第六十三薄膜晶体管；所述第六十一薄膜晶体管的栅极接入GOA电路的第N+1级外置GOA单元的扫描信号，源极电性连接GOA电路的第N级外置GOA单元的第一节点，漏极电性连接第六十二薄膜晶体管的源极；所述第六十二薄膜晶体管的栅极接入GOA电路的第N+1级外置GOA单元的扫描信号，漏极接入电源负电位；所述第六十三薄膜晶体管的栅极接入GOA电路的第N+1级外置GOA单元的扫描信号，源极接入GOA电路的第N级外置GOA单元的扫描信号，漏极接入电源负电位；The TFT array substrate of claim 7, wherein the built-in pull-down module includes a sixty-first thin film transistor, a sixty-second thin film transistor, and a sixty-third thin film transistor; the gate of the sixty-first thin film transistor The electrode is connected to the scanning signal of the N+1th level external GOA unit of the GOA circuit, the source is electrically connected to the first node of the Nth level external GOA unit of the GOA circuit, and the drain is electrically connected to the 62nd thin film transistor The source of the 62nd thin film transistor; the gate of the 62nd thin film transistor is connected to the scanning signal of the N+1 level external GOA unit of the GOA circuit, and the drain is connected to the negative potential of the power supply; The gate is connected to the scan signal of the N+1 level external GOA unit of the GOA circuit, the source is connected to the scan signal of the N level external GOA unit of the GOA circuit, and the drain is connected to the negative potential of the power supply;
    所述内置下拉维持模块包括第七十五薄膜晶体管、第七十六薄膜晶体管、第七十七薄膜晶体管及第七十八薄膜晶体管；所述第七十五薄膜晶体管的栅极电性连接反相器的输出端，源极电性连接GOA电路的第N级外置GOA单元的第一节点，漏极电性连接第七十六薄膜晶体管的源极；所述第七十六薄膜晶体管的栅极电性连接反相器的输出端，漏极接入电源负电位；所述第七十七薄膜晶体管的栅极电性连接反相器的输出端，源极接入GOA电路的第N级外置GOA单元的级传信号，漏极接入电源负电位；所述第七十八薄膜晶体管的栅极电性连接反相器的输出端，源极接入GOA电路的第N级外置GOA单元的扫描信号，漏极接入电源负电位。The built-in pull-down maintenance module includes a 75th thin film transistor, a 76th thin film transistor, a 77th thin film transistor, and a 78th thin film transistor; the gate of the 75th thin film transistor is electrically connected reversely The source of the output terminal of the phaser is electrically connected to the first node of the Nth stage external GOA unit of the GOA circuit, and the drain is electrically connected to the source of the 76th thin film transistor; The gate is electrically connected to the output terminal of the inverter, and the drain is connected to the negative potential of the power supply; the gate of the 77th thin film transistor is electrically connected to the output terminal of the inverter, and the source is connected to the Nth of the GOA circuit For the stage transmission signal of the external GOA unit, the drain is connected to the negative potential of the power supply; the gate of the 78th thin film transistor is electrically connected to the output terminal of the inverter, and the source is connected to the Nth stage of the GOA circuit. Set the scan signal of the GOA unit, and connect the drain to the negative potential of the power supply.
  9. 如权利要求1所述的TFT阵列基板，其中，每一子像素均包括内置GOA单元；5. The TFT array substrate of claim 1, wherein each sub-pixel includes a built-in GOA unit;
    每一子像素还包括电性连接对应一条扫描线的像素驱动电路及与像素驱动电路电性连接的像素电极，所述像素驱动电路、内置GOA单元及像素电极在平行于衬底所在平面的方向上依次设置。Each sub-pixel also includes a pixel drive circuit electrically connected to one scan line and a pixel electrode electrically connected to the pixel drive circuit. The pixel drive circuit, the built-in GOA unit and the pixel electrode are in a direction parallel to the plane where the substrate is located. Set up in turn.
  10. 一种显示面板，包括TFT阵列基板；A display panel including a TFT array substrate;
    所述TFT阵列基板包括衬底、设于衬底上且阵列排布的多个像素、多条扫描线及设于多个像素所在区域外侧的至少一个GOA电路；每一条扫描线对应与一行子像素电性连接；所述GOA电路包括多级外置GOA单元，多级外置GOA单元分别与多条扫描线对应电性连接；The TFT array substrate includes a substrate, a plurality of pixels arranged on the substrate and arranged in an array, a plurality of scan lines, and at least one GOA circuit arranged outside the area where the plurality of pixels are located; each scan line corresponds to a row The pixels are electrically connected; the GOA circuit includes a multi-level external GOA unit, and the multi-level external GOA unit is electrically connected to a plurality of scan lines respectively;
    每一行子像素中的至少一个包括内置GOA单元，所述内置GOA单元包括反相器，所述反相器的输入端接入下拉维持信号，输出端输出控制信号。At least one of the sub-pixels in each row includes a built-in GOA unit, the built-in GOA unit includes an inverter, the input end of the inverter is connected to a pull-down sustain signal, and the output end outputs a control signal.
  11. 如权利要求10所述的显示面板，其中，每一级外置GOA单元均包括上拉控制模块、上拉模块及下传模块；10. The display panel of claim 10, wherein each level of external GOA unit includes a pull-up control module, a pull-up module, and a downstream module;
    设N为正整数，除了第一级外置GOA单元外，在第N级外置GOA单元中，Set N to be a positive integer, except for the first-level external GOA unit, in the Nth-level external GOA unit,
    所述上拉控制模块接入第N-1级外置GOA单元的级传信号、第一时钟信号并电性连接第一节点，用于在第一时钟信号的控制下依据N-1级外置GOA单元的级传信号上拉第一节点的电位；The pull-up control module is connected to the stage transmission signal and the first clock signal of the N-1th stage external GOA unit and is electrically connected to the first node, and is used to control the first clock signal according to the N-1 stage external Set the level transmission signal of the GOA unit to pull up the potential of the first node;
    所述上拉模块接入第二时钟信号并电性连接第一节点及第N条扫描线，用于在第一节点的控制下依据第二时钟信号输出扫描信号至第N条扫描线；The pull-up module is connected to the second clock signal and is electrically connected to the first node and the Nth scan line for outputting the scan signal to the Nth scan line according to the second clock signal under the control of the first node;
    所述下传模块接入第二时钟信号并电性连接第一节点，用于在第一节点的控制下依据第二时钟信号输出级传信号。The download module is connected to the second clock signal and is electrically connected to the first node, and is used for output stage signal transmission according to the second clock signal under the control of the first node.
  12. 如权利要求11所述的显示面板，其中，每一级外置GOA单元还包括外置下拉模块以及外置下拉维持模块；11. The display panel of claim 11, wherein each level of external GOA unit further comprises an external pull-down module and an external pull-down maintenance module;
    除了最后一级外置GOA单元外，在第N级外置GOA单元中，In addition to the last level external GOA unit, in the Nth level external GOA unit,
    所述外置下拉模块接入第N+1级外置GOA单元的扫描信号、第一恒压低电位、第二恒压低电位、扫描信号并电性连接第一节点，用于在第N+1级外置GOA单元的扫描信号的控制下将第一节点的电位下拉至第一恒压低电位并将扫描信号的电位下拉至第二恒压低电位；The external pull-down module is connected to the scanning signal, the first constant voltage low potential, the second constant voltage low potential, the scanning signal of the N+1th level external GOA unit, and is electrically connected to the first node for Under the control of the scan signal of the +1 level external GOA unit, the potential of the first node is pulled down to the first constant voltage low potential and the potential of the scan signal is pulled down to the second constant voltage low potential;
    所述外置下拉维持模块接入第一恒压低电位、第二恒压低电位、扫描信号、级传信号并电性连接第一节点以及反相器的输出端，用于在反相器输出端输出的控制信号的控制下，将第一节点及级传信号的电位维持在第一恒压低电位并将扫描信号的电位维持在第二恒压低电位。The external pull-down maintenance module is connected to the first constant voltage low potential, the second constant voltage low potential, the scanning signal, the stage transmission signal and is electrically connected to the first node and the output terminal of the inverter for Under the control of the control signal output from the output terminal, the potential of the first node and the level transfer signal is maintained at the first constant voltage low potential and the potential of the scanning signal is maintained at the second constant voltage low potential.
  13. 如权利要求12所述的显示面板，其中，所述外置下拉模块包括第四十一薄膜晶体管、第四十二薄膜晶体管、第四十三薄膜晶体管；所述第四十一薄膜晶体管的栅极接入第N+1级外置GOA单元的扫描信号，源极电性连接第一节点，漏极电性连接第四十二薄膜晶体管的源极；所述第四十二薄膜晶体管的栅极接入第N+1级外置GOA单元的扫描信号，漏极接入第一恒压低电位；所述第四十三薄膜晶体管的栅极接入第N+1级外置GOA单元的扫描信号，源极接入扫描信号，漏极接入第二恒压低电位；The display panel of claim 12, wherein the external pull-down module comprises a forty-first thin film transistor, a forty-second thin film transistor, and a forty-third thin film transistor; the gate of the forty-first thin film transistor The electrode is connected to the scan signal of the N+1 level external GOA unit, the source is electrically connected to the first node, and the drain is electrically connected to the source of the 42nd thin film transistor; the gate of the 42nd thin film transistor The electrode is connected to the scan signal of the N+1 level external GOA unit, and the drain is connected to the first constant voltage low potential; the gate of the forty-third thin film transistor is connected to the N+1 level external GOA unit Scan signal, the source is connected to the scan signal, and the drain is connected to the second constant voltage low potential;
    所述外置下拉维持模块包括第五十五薄膜晶体管、第五十六薄膜晶体管、第五十七薄膜晶体管及第五十八薄膜晶体管；所述第五十五薄膜晶体管的栅极电性连接反相器的输出端，源极电性连接第一节点，漏极电性连接第五十六薄膜晶体管的源极；所述第五十六薄膜晶体管的栅极电性连接反相器的输出端，漏极接入第一恒压低电位；所述第五十七薄膜晶体管的栅极电性连接反相器的输出端，源极接入级传信号，漏极接入第一恒压低电位；所述第五十八薄膜晶体管的栅极电性连接反相器的输出端，源极接入扫描信号，漏极接入第二恒压低电位。The external pull-down maintenance module includes a fifty-fifth thin film transistor, a fifty-sixth thin film transistor, a fifty-seventh thin film transistor and a fifty-eighth thin film transistor; the gate of the fifty-fifth thin film transistor is electrically connected The output terminal of the inverter, the source is electrically connected to the first node, and the drain is electrically connected to the source of the fifty-sixth thin film transistor; the gate of the fifty-sixth thin film transistor is electrically connected to the output of the inverter The drain is connected to the first constant voltage low potential; the gate of the fifty-seventh thin film transistor is electrically connected to the output terminal of the inverter, the source is connected to the stage signal, and the drain is connected to the first constant voltage Low potential; the gate of the fifty-eighth thin film transistor is electrically connected to the output terminal of the inverter, the source is connected to the scan signal, and the drain is connected to the second constant voltage low potential.
  14. 如权利要求12所述的显示面板，其中，所述内置GOA单元还包括下拉维持信号产生模块；除了第一行子像素外，在第N行子像素的内置GOA单元中，下拉维持信号产生模块电性连接第N-1条扫描线、第N条扫描线以及反相器的输入端，用于在第N-1条扫描线及第N条扫描线中的至少一个的电位为高电位时向反相器的输入端输入高电位的下拉维持信号，在第N-1条扫描线及第N条扫描线的电位均为低电位时向反相器的输入端输入低电位的下拉维持信号。The display panel of claim 12, wherein the built-in GOA unit further comprises a pull-down sustain signal generation module; in addition to the first row of sub-pixels, in the built-in GOA unit of the Nth row of sub-pixels, the pull-down sustain signal generation module Electrically connected to the N-1th scan line, the Nth scan line, and the input terminal of the inverter, for when the potential of at least one of the N-1th scan line and the Nth scan line is high Input a high-level pull-down sustain signal to the input terminal of the inverter, and input a low-level pull-down sustain signal to the input terminal of the inverter when the potentials of the N-1th scan line and the Nth scan line are both low .
  15. 如权利要求14所述的显示面板，其中，所述下拉维持信号产生模块包括第六十一薄膜晶体管及第六十二薄膜晶体管；所述第六十一薄膜晶体管的栅极及源极均电性连接第N-1条扫描线，漏极电性连接反相器的输入端；所述第六十二薄膜晶体管的栅极及源极均电性连接第N条扫描线，漏极电性连接反相器的输入端。The display panel of claim 14, wherein the pull-down sustain signal generation module includes a sixty-first thin film transistor and a sixty-second thin film transistor; the gate and source of the sixty-first thin film transistor are both electrically connected. The N-1th scan line is electrically connected, and the drain is electrically connected to the input terminal of the inverter; the gate and source of the 62nd thin film transistor are electrically connected to the Nth scan line, and the drain is electrically connected Connect the input terminal of the inverter.
  16. 如权利要求11所述的显示面板，其中，在第N行子像素的内置GOA单元中，所述反相器的输入端电性连接GOA电路的第N级外置GOA单元的第一节点接收其传输的下拉维持信号；The display panel of claim 11, wherein, in the built-in GOA unit of the Nth row of sub-pixels, the input terminal of the inverter is electrically connected to the first node of the Nth stage external GOA unit of the GOA circuit. The pull-down sustain signal transmitted by it;
    所述内置GOA单元还包括内置下拉模块及内置下拉维持模块；The built-in GOA unit also includes a built-in pull-down module and a built-in pull-down maintenance module;
    除了最后一行子像素外，在第N行子像素的内置GOA单元中，Except for the last row of sub-pixels, in the built-in GOA unit of the Nth row of sub-pixels,
    所述内置下拉模块接入GOA电路的第N+1级外置GOA单元的扫描信号、电源负电位、GOA电路的第N级外置GOA单元的扫描信号，并电性连接GOA电路的第N级外置GOA单元的第一节点，用于在GOA电路的第N+1级外置GOA单元的扫描信号的控制下将GOA电路的N级外置GOA单元的第一节点的电位及GOA电路的第N级外置GOA单元的扫描信号的电位下拉至电源负电位；The built-in pull-down module is connected to the scan signal of the N+1 level external GOA unit of the GOA circuit, the negative potential of the power supply, the scan signal of the N level external GOA unit of the GOA circuit, and is electrically connected to the Nth level of the GOA circuit The first node of the first-level external GOA unit is used to control the potential of the first node of the N-level external GOA unit of the GOA circuit and the GOA circuit under the control of the scan signal of the N+1th-level external GOA unit of the GOA circuit The potential of the scanning signal of the Nth level external GOA unit is pulled down to the negative potential of the power supply;
    所述内置下拉维持模块接入电源负电位、GOA电路的第N级外置GOA单元的扫描信号、GOA电路的第N级外置GOA单元的级传信号并电性连接GOA电路的第N级外置GOA单元的第一节点以及反相器的输出端，用于在反相器输出端输出的控制信号的控制下，将GOA电路的第N级外置GOA单元的第一节点的电位、第N级外置GOA单元的级传信号的电位及GOA电路的第N级外置GOA单元的扫描信号的电位维持在电源负电位。The built-in pull-down maintenance module is connected to the negative potential of the power supply, the scan signal of the Nth level external GOA unit of the GOA circuit, the level transmission signal of the Nth level external GOA unit of the GOA circuit, and are electrically connected to the Nth level of the GOA circuit The first node of the external GOA unit and the output terminal of the inverter are used to reduce the potential of the first node of the Nth stage external GOA unit of the GOA circuit under the control of the control signal output from the inverter output terminal. The potential of the stage transfer signal of the Nth level external GOA unit and the potential of the scan signal of the Nth level external GOA unit of the GOA circuit are maintained at the negative potential of the power supply.
  17. 如权利要求16所述的显示面板，其中，所述内置下拉模块包括第六十一薄膜晶体管、第六十二薄膜晶体管、第六十三薄膜晶体管；所述第六十一薄膜晶体管的栅极接入GOA电路的第N+1级外置GOA单元的扫描信号，源极电性连接GOA电路的第N级外置GOA单元的第一节点，漏极电性连接第六十二薄膜晶体管的源极；所述第六十二薄膜晶体管的栅极接入GOA电路的第N+1级外置GOA单元的扫描信号，漏极接入电源负电位；所述第六十三薄膜晶体管的栅极接入GOA电路的第N+1级外置GOA单元的扫描信号，源极接入GOA电路的第N级外置GOA单元的扫描信号，漏极接入电源负电位；The display panel of claim 16, wherein the built-in pull-down module comprises a sixty-first thin film transistor, a sixty-second thin film transistor, and a sixty-third thin film transistor; and the gate of the sixty-first thin film transistor The scan signal of the N+1th level external GOA unit connected to the GOA circuit, the source is electrically connected to the first node of the Nth level external GOA unit of the GOA circuit, and the drain is electrically connected to the 62nd thin film transistor Source; the gate of the 62nd thin film transistor is connected to the scanning signal of the N+1 level external GOA unit of the GOA circuit, and the drain is connected to the negative potential of the power supply; the gate of the 63rd thin film transistor The pole is connected to the scan signal of the N+1th level external GOA unit of the GOA circuit, the source is connected to the scan signal of the Nth level external GOA unit of the GOA circuit, and the drain is connected to the negative potential of the power supply;
    所述内置下拉维持模块包括第七十五薄膜晶体管、第七十六薄膜晶体管、第七十七薄膜晶体管及第七十八薄膜晶体管；所述第七十五薄膜晶体管的栅极电性连接反相器的输出端，源极电性连接GOA电路的第N级外置GOA单元的第一节点，漏极电性连接第七十六薄膜晶体管的源极；所述第七十六薄膜晶体管的栅极电性连接反相器的输出端，漏极接入电源负电位；所述第七十七薄膜晶体管的栅极电性连接反相器的输出端，源极接入GOA电路的第N级外置GOA单元的级传信号，漏极接入电源负电位；所述第七十八薄膜晶体管的栅极电性连接反相器的输出端，源极接入GOA电路的第N级外置GOA单元的扫描信号，漏极接入电源负电位。The built-in pull-down maintenance module includes a 75th thin film transistor, a 76th thin film transistor, a 77th thin film transistor, and a 78th thin film transistor; the gate of the 75th thin film transistor is electrically connected reversely The source of the output terminal of the phaser is electrically connected to the first node of the Nth stage external GOA unit of the GOA circuit, and the drain is electrically connected to the source of the 76th thin film transistor; The gate is electrically connected to the output terminal of the inverter, and the drain is connected to the negative potential of the power supply; the gate of the 77th thin film transistor is electrically connected to the output terminal of the inverter, and the source is connected to the Nth of the GOA circuit For the stage transmission signal of the external GOA unit, the drain is connected to the negative potential of the power supply; the gate of the 78th thin film transistor is electrically connected to the output terminal of the inverter, and the source is connected to the Nth stage of the GOA circuit. Set the scan signal of the GOA unit, and connect the drain to the negative potential of the power supply.
  18. 如权利要求10所述的显示面板，其中，每一子像素均包括内置GOA单元；10. The display panel of claim 10, wherein each sub-pixel includes a built-in GOA unit;
    每一子像素还包括电性连接对应一条扫描线的像素驱动电路及与像素驱动电路电性连接的像素电极，所述像素驱动电路、内置GOA单元及像素电极在平行于衬底所在平面的方向上依次设置。Each sub-pixel also includes a pixel drive circuit electrically connected to one scan line and a pixel electrode electrically connected to the pixel drive circuit. The pixel drive circuit, the built-in GOA unit and the pixel electrode are in a direction parallel to the plane where the substrate is located. Set up in turn.
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