CN114664250B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN114664250B CN114664250B CN202210369176.9A CN202210369176A CN114664250B CN 114664250 B CN114664250 B CN 114664250B CN 202210369176 A CN202210369176 A CN 202210369176A CN 114664250 B CN114664250 B CN 114664250B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses a display panel and a display device, wherein the display panel comprises a display area and a non-display area, the display area comprises a plurality of sub-pixel units, each sub-pixel unit comprises a sub-pixel and a pixel driving circuit unit, a line sparse area is arranged between two adjacent pixel driving circuit units, and a plurality of cascaded GOA units of a grid driving circuit are positioned in the line sparse area.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
An Active-matrix organic light-emitting diode (Active matrix organic light emitting diode) display screen has been rapidly developed in recent years, and an important application scene of the Active-matrix organic light emitting diode display screen is a display screen of a mobile terminal such as a mobile phone screen, and the mobile terminal pursues a narrower frame. However, the left and right frames of the AMOLED display screen generally include a crack prevention area, a package edge area, a power signal line routing area, and a GOA (row driving scanning circuit) area, where the GOA area occupies a large area, which is not beneficial to realizing a narrow frame.
Disclosure of Invention
The embodiment of the invention provides a display panel and a display device, which are used for solving the technical problems that the GOA areas of the existing display panel and display device are positioned on left and right frames and are not beneficial to realizing narrow frames.
In order to solve the problems, the technical scheme provided by the invention is as follows:
the invention provides a display panel, which comprises a display area and a non-display area positioned at the periphery of the display area; the display area comprises a plurality of sub-pixel units which are arranged in a multi-row multi-column array, each sub-pixel unit comprises a sub-pixel and a pixel driving circuit unit used for driving the sub-pixel, and a line sparse area is arranged between two adjacent pixel driving circuit units;
the display panel further comprises a gate driving circuit, wherein the gate driving circuit comprises a plurality of cascaded GOA units, and the GOA units are located in the line sparse region.
According to the display panel provided by the invention, the display panel comprises a plurality of signal lines, the signal lines extend along the row direction or the column direction of a plurality of sub-pixels, the signal lines are configured to respectively transmit driving signals to a plurality of pixel driving circuit units positioned in the same row or the same column, two adjacent signal lines are positioned between two adjacent pixel driving circuit units positioned in the same row or the same column, and two signal lines are wound to form the line sparse area.
According to the display panel provided by the invention, the plurality of signal lines comprise a plurality of data lines, the plurality of data lines extend along the column direction of the plurality of sub-pixel units, the data lines are configured to respectively transmit data driving signals to the plurality of pixel driving circuit units in the same column, two adjacent data lines are positioned between two adjacent pixel driving circuit units in the same column, and the two data lines are wound to form the line sparse area.
According to the display panel provided by the invention, the data line comprises a plurality of main body sections and a plurality of winding sections which are connected, the winding sections are arranged between two adjacent main body sections, the main body sections extend along the column direction of the plurality of sub-pixel units, and the winding sections extend along the extending direction of the edges of the line sparse area.
According to the display panel provided by the invention, the GOA unit comprises a plurality of connected GOA devices, each line sparse area is provided with at least one GOA device, and the GOA devices comprise a first transistor or a first capacitor.
According to the display panel provided by the invention, each pixel driving circuit unit comprises at least two second transistors and second capacitors, and the second transistors and the second capacitors are arranged on the same layer as the GOA device.
According to the present invention, there is provided a display panel including:
a substrate;
the driving circuit layer is arranged on the substrate and comprises the pixel driving circuit unit and the GOA unit; and
a plurality of sub-pixels disposed on the driving circuit layer;
wherein the driving circuit layer includes:
a semiconductor layer disposed on the substrate and including a first semiconductor and a second semiconductor;
a first gate insulating layer overlying the semiconductor layer;
the first metal layer is arranged on the first grid insulation layer and comprises a first grid and a second grid;
a second gate insulating layer overlying the first metal layer;
the second metal layer is arranged on the second grid insulation layer and comprises a third grid electrode;
the first interlayer dielectric layer is covered on the second metal layer; and
the first source-drain metal layer is arranged on the first interlayer dielectric layer and comprises a first source electrode, a first drain electrode, a second source electrode and a second drain electrode;
the first semiconductor, the first gate insulating layer, the first gate, the second gate insulating layer, the first interlayer dielectric layer, the first source electrode and the first drain electrode form the first transistor, and the second semiconductor, the first gate insulating layer, the second gate insulating layer, the third gate, the first interlayer dielectric layer, the second source electrode and the second drain electrode form the second transistor.
According to the display panel provided by the invention, the display panel further comprises:
the second interlayer dielectric layer is covered on the first source drain electrode metal layer; and
the second source drain electrode metal layer is arranged on the second interlayer dielectric layer and comprises a first connecting wire and a second connecting wire, and the first connecting wire is respectively and electrically connected with two adjacent GOA devices through a first via hole and a second via hole which penetrate through the second interlayer dielectric layer; the second connection line electrically connects the sub-pixel and one of the second source electrode and the second drain electrode through a third via hole penetrating the second interlayer dielectric layer.
According to the display panel provided by the invention, at least one first transistor of the GOA unit is formed by a plurality of first sub-transistors connected in parallel.
According to the display panel provided by the invention, the pixel driving circuit is any one of 2T1C, 3T1C, 5T1C and 7T 1C.
The invention provides a display device which comprises the display panel.
The beneficial effects of the invention are as follows: compared with the prior art, the display panel and the display device provided by the invention have the advantages that the GOA units in the gate driving circuits are arranged in the line sparse area between the two adjacent pixel driving circuit units, and compared with the prior art, the gate driving circuits in the invention are arranged in the display area without being arranged in the frame areas positioned at the left side and the right side of the display area, so that the width of the left frame and the right frame of the display panel can be obviously reduced, and the goal of borderless display panel can be realized.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic plan view of a display panel according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a wiring structure of a display panel according to an embodiment of the present invention;
FIG. 3 is a simplified schematic plan view of a display panel according to an embodiment of the present invention;
fig. 4 is an equivalent circuit diagram of a pixel driving circuit unit according to an embodiment of the present invention;
fig. 5 is an equivalent circuit diagram of a GOA unit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a wiring structure of a GOA unit according to an embodiment of the present invention;
fig. 7 is a schematic cross-sectional structure of a display panel according to an embodiment of the invention.
Reference numerals illustrate:
100a, a display area; 100b, a non-display area; 1001a, a line sparse region;
11. a sub-pixel; 12. a pixel driving circuit unit; 121. a second transistor; 122. a second capacitor; 13. a GOA unit; 131. a GOA device; 132. a first transistor; 133. a first capacitor; 14. a scanning line; 15. a data line; 151. a main body section; 152. winding a wire segment; 16. an auxiliary connecting line;
101. a substrate; 102. a buffer layer; 103. a semiconductor layer; 1031. a first semiconductor; 1032. a second semiconductor; 104. a first gate insulating layer; 105. a first metal layer; 1051. a first gate; 1052. a second gate; 106. a second gate insulating layer; 107. a second metal layer; 1071. a third gate; 108. a first interlayer dielectric layer; 109. a first source/drain metal layer; 1091. a first source electrode; 1092. a first drain electrode; 1093. a second source electrode; 1094. a second drain electrode; 110. a second interlayer dielectric layer; 111. a second source/drain metal layer; 1111. a first connecting line; 1112. a second connecting line; 112. a flat layer; 113. and an anode.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention. Furthermore, it should be understood that the detailed description is presented herein for purposes of illustration and description only, and is not intended to limit the invention. In the present invention, unless otherwise indicated, terms of orientation such as "upper" and "lower" are used to generally refer to the upper and lower positions of the device in actual use or operation, and specifically the orientation of the drawing figures; while "inner" and "outer" are for the outline of the device.
Referring to fig. 1, fig. 1 is a schematic plan view of a display panel according to an embodiment of the invention. The embodiment of the invention provides a display panel, which comprises an OLED display panel and the like, and can be an AMOLED display panel. The display panel includes a display area 100a and a non-display area 100b located at the periphery of the display area 100a, where the display area 100a is an Active area (Active area) of the display panel for displaying a picture, and the non-display area 100b surrounds the periphery of the display area 100a and is used as a layout space of circuits and related wires.
Referring to fig. 2 and 3, fig. 2 is a schematic diagram of a wiring structure of a display panel according to an embodiment of the invention; fig. 3 is a schematic plan view of a simplified structure of a display panel according to an embodiment of the present invention. The display area 100a includes a plurality of sub-pixel units arranged in a multi-row multi-column array, each sub-pixel unit includes a sub-pixel 11 and a pixel driving circuit unit 12 for driving the sub-pixel 11, and a line sparse area 1001a is disposed between two adjacent pixel driving circuit units 12; the display panel further includes a gate driving circuit, the gate driving circuit includes a plurality of cascaded GOA units 13, and the GOA units 13 are located in the line sparse region 1001a.
Specifically, the display area 100a further includes a plurality of scan lines 14 and a plurality of data lines 15, where an extending direction of the scan lines 14 is parallel to a row direction of the sub-pixel units, an extending direction of the data lines 15 is parallel to a column direction of the sub-pixel units, a plurality of the scan lines 14 and a plurality of the data lines 15 are disposed across to define a plurality of sub-pixel units arranged in a matrix, a number of rows of the sub-pixel units is equal to a number of the scan lines 14, a number of columns of the sub-pixel units is equal to a number of the data lines 15, the sub-pixels 11 located in a same row are electrically connected to a corresponding one of the scan lines 14, and the sub-pixels 11 located in a same column are electrically connected to a corresponding one of the data lines 15.
Each sub-pixel 11 is electrically connected to a corresponding pixel driving circuit unit 12, and the pixel driving circuit unit 12 drives the corresponding sub-pixel 11 to emit light, so as to realize image display; likewise, the pixel driving circuit units 12 are arranged in a plurality of rows and columns in an array manner consistent with the arrangement manner of the sub-pixels 11.
Each gate driving circuit comprises a plurality of GOA units 13, each GOA unit 13 is connected with at least one scanning line 14, and the gate driving circuit is connected to a GOA bus through a signal lead led out of the gate driving circuit. The driving signals of the gate driving array display panel are input from the signal input ends and transmitted to the signal lead wires of the GOA units 13 connected with the driving signals through the GOA bus, and then reach the clock signal input ends of the GOA units 13, so that the signal driving of the GOA units 13 is realized.
It will be appreciated that, for the sub-pixel unit, the sub-pixel 11 is disposed on one side of the pixel driving circuit unit 12, the sub-pixel 11 and the pixel driving circuit unit 12 are disposed in a stacked manner, that is, the sub-pixel 11 is disposed on the top layer of the sub-pixel unit, and the pixel driving circuit unit 12 is disposed on the bottom layer of the sub-pixel unit. Since the bottom space of the sub-pixel unit has a part of line sparse area, namely the line sparse area 1001a, besides the pixel driving circuit unit 12, the GOA unit 13 located in the non-display area 100b in the prior art is moved to the display area 100a, so that the width of the left and right frames of the display panel can be significantly reduced, and the goal of frame-free display panel can be realized.
Specifically, the GOA unit 13 may be disposed between two adjacent pixel driving circuit units 12 located in the same row, or may be disposed between two adjacent pixel driving circuit units 12 located in the same column.
Note that, in the embodiment of the present invention, the line sparse region 1001a does not mean a region where no wiring of the pixel driving circuit unit 12 is provided, but means a region where the transistor and the storage capacitor of the pixel driving circuit unit 12 are avoided, and compared with a region where the transistor and the storage capacitor are provided, the line density of the region is smaller, and enough space can be left for placing the GOA unit 13.
In an embodiment, the pixel driving circuit unit 12 may be reduced in size to reduce the occupied space of the pixel driving circuit unit 12 in the sub-pixel unit, so as to make a part of the space, which is the line thinning region 1001a in the present invention. In particular, this can be achieved by arranging the transistors and storage capacitances of the pixel driving circuit unit 12 in a relatively dense manner.
In another embodiment, the size of the sparse region 1001a may be increased by rearranging the traces originally disposed in the sparse region 1001a, so that enough space can be left for placing the GOA units 13.
Specifically, the display panel includes a plurality of signal lines extending in a row direction or a column direction of the plurality of sub-pixel units, the signal lines being configured to transmit driving signals to the plurality of pixel driving circuit units 12 located in the same row or the same column, respectively, two adjacent signal lines being located between two adjacent pixel driving circuit units 12 located in the same row or the same column, and two signal line windings forming the line thinning region 1001a.
Specifically, when the signal line extends in the row direction of the plurality of sub-pixel units, for example, the signal line may be an EM signal line or the scanning line 14, in which case the line thinning-out region 1001a is located between two of the pixel driving circuit units 12 in the same column; when the signal line extends in the column direction of the plurality of sub-pixel units, for example, the signal line may be the data line 15 or a high-level voltage signal line VDD, in which case the line thinning-out region 1001a is located between two of the pixel driving circuit units 12 of the same row.
In order to clearly explain the technical solution provided by the present invention, the embodiment of the present invention uses the signal line as the data line 15 for illustration, but other technical solutions adopting the present invention concept are all within the protection scope of the present invention.
Specifically, the plurality of signal lines include a plurality of data lines 15, the plurality of data lines 15 extend along a column direction of the plurality of sub-pixel units, the data lines 15 are configured to respectively transmit data driving signals to the plurality of pixel driving circuit units 12 located in the same column, two adjacent data lines 15 are located between two adjacent pixel driving circuit units 12 in the same column, and the two data lines 15 are wound to form the line sparse region 1001a.
The data line 15 includes a plurality of body segments 151 and a plurality of wire-wound segments 152 that are connected, the wire-wound segments 152 are disposed between two adjacent body segments 151, the body segments 151 extend along the column direction of the plurality of sub-pixel units, and the wire-wound segments 152 extend along the extending direction of the edge of the line sparse region 1001a.
Specifically, two ends of the wire-wound segment 152 are respectively connected to two main body segments 151, the wire-wound segment 152 is closer to the corresponding pixel driving circuit unit 12 than the main body segments 151, the wire-wound segment 152 may be a straight line segment or a curved line segment, and when the wire-wound segment 152 is a straight line segment, the wire-wound segment 152 may be in a shape of or コ; when the winding section 152 is a curved section, the winding section 152 may be any one of a semi-elliptical shape and a semi-circular shape.
It can be understood that, in the embodiment of the present invention, two adjacent data lines 15 driving two adjacent columns of the pixel driving circuit units 12 respectively pass through a corresponding column of the pixel driving circuit units 12, compared with the prior art, in which two adjacent data lines 15 driving two adjacent columns of the pixel driving circuit units 12 are moved between two adjacent columns of the pixel driving circuit units 12, and the data lines 15 are wound, and other signal lines are adaptively rearranged, for example, scan signal lines Scan (n-1) of the n-1 th level originally passing through the line sparse region 1001a are broken at two sides of the line sparse region 1001a to form a plurality of Scan line segments, and an auxiliary connection line 16 is introduced to connect two ends of the two adjacent Scan line segments, the auxiliary connection line 16 is located at the periphery of the line sparse region 1001a, so that the line sparse region 1001a is left between the two adjacent data lines 15 for placing the GOA unit 13.
Each of the pixel driving circuit units 12 includes at least two second transistors 121 and a second capacitor 122, and optionally, the pixel driving circuit unit 12 is any one of 2T1C, 3T1C, 5T1C and 7T1C, and in order to clearly explain the technical solution provided by the present invention, the embodiment of the present invention is illustrated by taking the pixel driving circuit unit 12 as 7T1C as an example.
Specifically, referring to fig. 2, the pixel driving circuit unit 12 further includes an n-1-th Scan signal line Scan (n-1), an n-th Scan signal line Scan (n), a low-potential voltage line VI, a high-power positive voltage signal line VDD and an EM signal line, wherein the n-1-th Scan signal line Scan (n-1), the n-th Scan signal line Scan (n), the low-potential voltage line VI and the EM signal line extend along the row direction of the plurality of sub-pixel units, the high-power positive voltage signal line VDD extends along the column direction of the plurality of sub-pixel units, the n-1-th Scan signal line Scan (n-1) and the n-th Scan signal line Scan (n) are located on the first metal layer, and the high-power positive voltage signal line VDD and the data line are located on the first source drain metal layer.
Referring to fig. 2 and fig. 4, fig. 4 is an equivalent circuit diagram of a pixel driving circuit unit according to an embodiment of the invention. The pixel driving circuit unit 12 includes 7 second transistors and 1 second capacitor, the 7 second transistors are respectively T1 to T7, the first capacitor is C1, the gate of T3 is connected to the Scan signal line Scan (n) of the nth stage, the source of T3 is connected to a Data signal line Data, and the drain of T3 is connected to the drain of T1 and the drain of T5. The grid electrode of the T5 is connected with the EM signal line, the source electrode of the T5 is connected with the high power source positive voltage signal line VDD, and the drain electrode of the T5 is connected with the drain electrode of the T1. The gate of T1 is connected to node Q and the gate of T1 is connected to the source of T6. The grid electrode of the T6 is connected with an EM signal line, and the drain electrode of the T6 is connected with the anode electrode of the sub-pixel 11. The grid electrode of the T2 is connected with the scanning signal line Scan (n) of the nth stage, the T2 is a double-grid switch tube, the source electrode of the T2 is connected with the source electrode of the T6, and the drain electrode of the T2 is connected with the node Q. The gate of T4 is connected to the Scan signal line Scan (n-1) of the n-1 th stage, the drain of T4 is connected to the node Q, the source of T4 is connected to the low potential voltage line VI, and the cathode of the sub-pixel 11 is connected to the low power negative voltage signal line VSS.
In one embodiment, when the line sparse region 1001a is large enough in size, the line sparse region 1001a places the entire GOA unit 13.
With the development of display technology, the pixel density of the display panel is increased, resulting in a smaller size of the line sparse region 1001a where the sub-pixel units exist, and each GOA unit 13 includes a plurality of GOA devices 131, where each GOA device 131 includes at least one first transistor 132 or one first capacitor 133, so that the GOA unit 13 is larger in size, and the line sparse region 1001a is not large enough to accommodate the whole GOA unit 13. Specifically, at least part of the line sparse regions 1001a are provided with the GOA devices 131, and each line sparse region 1001a may be provided with one or more GOA devices 131.
Referring to fig. 5 and 6, fig. 5 is an equivalent circuit diagram of a GOA unit according to an embodiment of the present invention; fig. 6 is a schematic diagram of a wiring structure of a GOA unit according to an embodiment of the present invention. The GOA unit 13 includes 8 first transistors 132 and 2 first capacitors 133 as an example. The 8 first transistors 132 are T8 to T15, the 2 first capacitors 133 are C2 and C3, the gate of T8 and the gate of T10 are connected to the first clock signal XCK, the source of T8 is connected to the VGL voltage signal, the drain of T8 is connected to the drain of T10 and the gate of T12, the gate of T14 and the first electrode of C3, the source of T9 is connected to the Scan signal Scan (n-1) of the n-1 th stage, the drain of T9 is connected to the source of T13, the gate of T10 is connected to the source of T15, the gate of T11 and the source of T13 are connected to the second clock signal CK, the source of T11 is connected to the drain of T12, the gate of T15 is connected to the VGL voltage signal, the drain of T15 is connected to the first electrode of T13, the drain of T13 is connected to the second electrode of C2 and the Scan signal Scan (n) of the n-th stage, the drain of T14 is connected to the second electrode of C2 and the Scan signal Scan (n) of the n-th stage, and the source of T14 is connected to the second electrode of C12 and the second electrode of VGH voltage signal. The VGL voltage signal is a voltage signal for controlling the switching tube to be turned off, the VGH voltage is a voltage for controlling the switching tube to be turned on, and a certain voltage difference exists between the VGH voltage value and the VGL voltage, for example, the voltage difference between VGH and VGL may be set to be greater than 25V.
Specifically, the multiple GOA devices 131 of one GOA unit 13 are disposed in multiple columns of the sub-pixel units or multiple rows of the sub-pixel units, so that the multiple GOA devices 131 are densely disposed, which can reduce the connection difficulty between the GOA devices 131.
Further, the GOA unit 13 is disposed at an edge region of the display area 100a to facilitate wiring.
Further, if the single GOA device 131 cannot meet the requirements of high output and large capacitance, a multi-device parallel connection mode may be adopted, and specifically, the GOA device 131 is formed by a plurality of first sub-transistors connected in parallel, and the size of the first sub-transistors is smaller than that of the GOA device.
Further, referring to fig. 7, fig. 7 is a schematic cross-sectional structure of a display panel according to an embodiment of the invention. The second transistor 121 and the second capacitor 122 are arranged on the same layer as the GOA device 131 in the cross section of the display panel, and thus, the GOA unit 13 and the pixel driving circuit unit 12 are fabricated at the same time.
Specifically, the display panel includes a substrate 101, a driving circuit layer, and a plurality of sub-pixels 11, where the driving circuit layer is disposed on the substrate 101, and the driving circuit layer includes the pixel driving circuit unit 12 and the GOA unit 13; a plurality of the sub-pixels 11 are disposed on the driving circuit layer.
The driving circuit layer includes a semiconductor layer 103, a first gate insulating layer 104, a first metal layer 105, a second gate insulating layer 106, a second metal layer 107, a first interlayer dielectric layer 108, and a first source drain metal layer 109. Specifically, the semiconductor layer 103 is disposed on the substrate 101, and the semiconductor layer 103 includes a first semiconductor 1031 and a second semiconductor 1032; the first gate insulating layer 104 is covered on the semiconductor layer 103; the first metal layer 105 is disposed on the first gate insulating layer 104, and the first metal layer 105 includes a first gate 1051 and a second gate 1052; the second gate insulating layer 106 is covered on the first metal layer 105; the second metal layer 107 is disposed on the second gate insulating layer 106, and the second metal layer 107 includes a third gate 1071; the first interlayer dielectric layer 108 is covered on the second metal layer 107; the first source-drain metal layer 109 is disposed on the first interlayer dielectric layer 108, and the first source-drain metal layer 109 includes a first source 1091, a first drain 1092, a second source 1093, and a second drain 1094.
The first semiconductor 1031, the first gate insulating layer 104, the first gate 1051, the second gate insulating layer 106, the first interlayer dielectric layer 108, the first source 1091, and the first drain 1092 constitute the first transistor 132, and the second semiconductor 1032, the first gate insulating layer 104, the second gate 1052, the second gate insulating layer 106, the third gate 1071, the first interlayer dielectric layer 108, the second source 1093, and the second drain 1094 constitute the second transistor 121.
Further, the display panel further includes a buffer layer 102, and the buffer layer 102 is disposed between the semiconductor layer 103 and the substrate 101.
Further, the display panel further includes a second interlayer dielectric layer 110 and a second source drain metal layer 111, where the second interlayer dielectric layer 110 is covered on the first source drain metal layer 109, the second source drain metal layer 111 is disposed on the second interlayer dielectric layer 110, the second source drain metal layer 111 includes a first connection line 1111 and a second connection line 1112, the first connection line 1111 is electrically connected to two adjacent GOA devices 131 through a first via hole and a second via hole penetrating the second interlayer dielectric layer 110, and the first connection line 1111 forms a bridge structure through the first via hole and the second via hole, so that a short circuit with a wiring in the pixel driving circuit unit 12 when the two adjacent GOA devices 131 are connected can be avoided; the second connection line 1112 electrically connects the sub-pixel 11 and one of the second source electrode 1093 and the second drain electrode 1094 through a third via penetrating the second interlayer dielectric layer 110.
Further, the first source-drain metal layer 109 further includes a high-level power signal line VDD, and the second source-drain metal layer 111 further includes a third connection line, where the third connection line is electrically connected to the high-level power signal line VDD through a fourth via penetrating the second interlayer dielectric layer 110, so that the high-level power signal line VDD and the third connection line are connected in parallel, and a voltage drop of the high-level power signal line VDD can be reduced.
Further, the display panel further includes a planarization layer 112, the planarization layer 112 is covered on the second source-drain metal layer 111 and is used for planarizing the second source-drain metal layer 111, the second connection line 1112 is electrically connected to the anode 113 of the sub-pixel 11 through a fifth via penetrating through the planarization layer 112, and the anode 113 is disposed on the planarization layer 112.
The embodiment of the invention also provides a display device which comprises the display panel in the embodiment, and the display device can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
The display device also comprises a touch panel, wherein the touch panel is combined with the display panel in a built-in or externally-hung mode, so that the display device has a touch function.
The beneficial effects are as follows: compared with the prior art, the display panel and the display device provided by the embodiment of the invention have the advantages that the GOA units in the gate driving circuits are arranged in the line sparse area between the two adjacent pixel driving circuit units, and compared with the prior art, the gate driving circuits in the invention are arranged in the display area without being arranged in the frame areas on the left side and the right side of the display area, so that the width of the left frame and the right frame of the display panel can be obviously reduced, and the goal of borderless display panel can be realized.
In summary, although the present invention has been described in terms of the preferred embodiments, the preferred embodiments are not limited to the above embodiments, and various modifications and changes can be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention is defined by the appended claims.
Claims (11)
1. A display panel, comprising a display area and a non-display area located at the periphery of the display area; the display area comprises a plurality of sub-pixel units which are arranged in a multi-row multi-column array, each sub-pixel unit comprises a sub-pixel and a pixel driving circuit unit used for driving the sub-pixel, and a line sparse area is arranged between two adjacent pixel driving circuit units;
the display panel further comprises a gate driving circuit, wherein the gate driving circuit comprises a plurality of cascaded GOA units, and the GOA units are positioned in the line sparse region;
the display area further comprises a plurality of scanning lines parallel to the row direction of the sub-pixel units, at least part of the scanning lines are broken at two sides of the line sparse area to form a plurality of scanning line segments, two ends of two adjacent scanning line segments are connected through an auxiliary connecting line, and the auxiliary connecting line is located at the periphery of the line sparse area.
2. The display panel according to claim 1, wherein the display panel includes a plurality of signal lines extending in a row direction or a column direction of the plurality of sub-pixels, the signal lines being configured to transmit driving signals to the plurality of pixel driving circuit units located in the same row or the same column, respectively, two adjacent signal lines being located in between the two adjacent pixel driving circuit units in the same row or the same column, the two signal lines being wound to form the line sparse region.
3. The display panel according to claim 2, wherein the plurality of signal lines include a plurality of data lines extending in a column direction of the plurality of sub-pixel units, the data lines are configured to transmit data driving signals to the plurality of pixel driving circuit units located in the same column, respectively, two adjacent data lines are located in a middle of two adjacent pixel driving circuit units in the same column, and two data line windings form the line sparse area.
4. A display panel according to claim 3, wherein the data line comprises a plurality of body segments and a plurality of wire-wound segments connected, the wire-wound segments being disposed between two adjacent body segments, the body segments extending in a column direction of the plurality of sub-pixel units, the wire-wound segments extending in an extending direction of an edge of the line-thinning-out region.
5. The display panel of claim 1, wherein the GOA unit comprises a plurality of GOA devices connected, each of the line-thinning-out regions being provided with at least one of the GOA devices, the GOA devices comprising a first transistor or a first capacitor.
6. The display panel of claim 5, wherein each pixel driving circuit unit comprises at least two second transistors and a second capacitor, the second transistors and the second capacitors being disposed on the same layer as the GOA device.
7. The display panel of claim 6, wherein the display panel comprises:
a substrate;
the driving circuit layer is arranged on the substrate and comprises the pixel driving circuit unit and the GOA unit; and
a plurality of sub-pixels disposed on the driving circuit layer;
wherein the driving circuit layer includes:
a semiconductor layer disposed on the substrate and including a first semiconductor and a second semiconductor;
a first gate insulating layer overlying the semiconductor layer;
the first metal layer is arranged on the first grid insulation layer and comprises a first grid and a second grid;
a second gate insulating layer overlying the first metal layer;
the second metal layer is arranged on the second grid insulation layer and comprises a third grid electrode;
the first interlayer dielectric layer is covered on the second metal layer; and
the first source-drain metal layer is arranged on the first interlayer dielectric layer and comprises a first source electrode, a first drain electrode, a second source electrode and a second drain electrode;
the first semiconductor, the first gate insulating layer, the first gate, the second gate insulating layer, the first interlayer dielectric layer, the first source electrode and the first drain electrode form the first transistor, and the second semiconductor, the first gate insulating layer, the second gate insulating layer, the third gate, the first interlayer dielectric layer, the second source electrode and the second drain electrode form the second transistor.
8. The display panel of claim 7, further comprising:
the second interlayer dielectric layer is covered on the first source drain electrode metal layer; and
the second source drain electrode metal layer is arranged on the second interlayer dielectric layer and comprises a first connecting wire and a second connecting wire, and the first connecting wire is respectively and electrically connected with two adjacent GOA devices through a first via hole and a second via hole which penetrate through the second interlayer dielectric layer; the second connection line electrically connects the sub-pixel and one of the second source electrode and the second drain electrode through a third via hole penetrating the second interlayer dielectric layer.
9. The display panel of claim 5, wherein at least one of the first transistors of the GOA unit is formed of a plurality of first sub-transistors connected in parallel.
10. The display panel according to claim 1, wherein the pixel driving circuit is any one of 2T1C, 3T1C, 5T1C, and 7T 1C.
11. A display device comprising the display panel according to any one of claims 1 to 10.
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