CN114664250A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN114664250A CN114664250A CN202210369176.9A CN202210369176A CN114664250A CN 114664250 A CN114664250 A CN 114664250A CN 202210369176 A CN202210369176 A CN 202210369176A CN 114664250 A CN114664250 A CN 114664250A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
Abstract
The invention discloses a display panel and a display device, wherein the display panel comprises a display area and a non-display area, the display area comprises a plurality of sub-pixel units, each sub-pixel unit comprises a sub-pixel and a pixel driving circuit unit, a line sparse area is arranged between every two adjacent pixel driving circuit units, and a plurality of cascaded GOA units of a grid driving circuit are positioned in the line sparse area.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a display device.
Background
An Active-matrix organic light-emitting diode (AMOLED) display screen is rapidly developed in recent years, and an important application scene of the AMOLED display screen is a display screen of a mobile terminal such as a mobile phone screen, and such a mobile terminal seeks a narrower frame. However, the left and right frames of the AMOLED display generally include a crack prevention region, a package edge region, a power signal line routing region, and a GOA (line driver and scanning circuit) region, where the GOA region occupies a large area, which is not favorable for realizing a narrow frame.
Disclosure of Invention
The embodiment of the invention provides a display panel and a display device, and aims to solve the technical problem that GOA areas of the existing display panel and the display device are positioned on left and right frames and are not beneficial to realizing narrow frames.
In order to solve the above problems, the technical scheme provided by the invention is as follows:
the invention provides a display panel, which comprises a display area and a non-display area positioned at the periphery of the display area; the display area comprises a plurality of sub-pixel units which are arranged in a multi-row and multi-column array manner, each sub-pixel unit comprises a sub-pixel and a pixel driving circuit unit for driving the sub-pixel, and a line sparse area is arranged between every two adjacent pixel driving circuit units;
the display panel further comprises a gate driving circuit, wherein the gate driving circuit comprises a plurality of cascaded GOA units, and the GOA units are located in the line sparse area.
According to the display panel provided by the invention, the display panel comprises a plurality of signal lines, the signal lines extend along the row direction or the column direction of a plurality of sub-pixels, the signal lines are configured to transmit driving signals to a plurality of pixel driving circuit units positioned in the same row or the same column respectively, two adjacent signal lines are positioned between two adjacent pixel driving circuit units positioned in the same row or the same column, and two signal lines form the line sparse area in a winding manner.
According to the display panel provided by the invention, the plurality of signal lines comprise a plurality of data lines, the plurality of data lines extend along the column direction of the plurality of sub-pixel units, the data lines are configured to transmit data driving signals to the plurality of pixel driving circuit units in the same column respectively, two adjacent data lines are positioned between two adjacent pixel driving circuit units in the same column, and the two data lines form the line sparse area in a winding manner.
According to the display panel provided by the invention, the data line comprises a plurality of main body segments and a plurality of winding segments which are connected, the winding segments are arranged between two adjacent main body segments, the main body segments extend along the column direction of a plurality of sub-pixel units, and the winding segments extend along the extending direction of the edge of the line sparse area.
According to the display panel provided by the invention, the GOA unit comprises a plurality of connected GOA devices, each line sparse area is provided with at least one GOA device, and each GOA device comprises a first transistor or a first capacitor.
According to the display panel provided by the invention, each pixel driving circuit unit comprises at least two second transistors and a second capacitor, and the second transistors, the second capacitors and the GOA devices are arranged at the same layer.
According to the present invention, there is provided a display panel including:
a substrate;
the driving circuit layer is arranged on the substrate and comprises the pixel driving circuit unit and the GOA unit; and
the plurality of sub-pixels are arranged on the driving circuit layer;
wherein the driving circuit layer includes:
a semiconductor layer disposed on the substrate, including a first semiconductor and a second semiconductor;
a first gate insulating layer overlying the semiconductor layer;
the first metal layer is arranged on the first grid electrode insulating layer and comprises a first grid electrode and a second grid electrode;
a second gate insulating layer overlying the first metal layer;
the second metal layer is arranged on the second grid electrode insulating layer and comprises a third grid electrode;
the first interlayer dielectric layer covers the second metal layer; and
the first source drain metal layer is arranged on the first interlayer dielectric layer and comprises a first source electrode, a first drain electrode, a second source electrode and a second drain electrode;
wherein the first semiconductor, the first gate insulating layer, the first gate, the second gate insulating layer, the first interlayer dielectric layer, the first source, and the first drain constitute the first transistor, and the second semiconductor, the first gate insulating layer, the second gate insulating layer, the third gate, the first interlayer dielectric layer, the second source, and the second drain constitute the second transistor.
According to the display panel provided by the present invention, the display panel further comprises:
the second interlayer dielectric layer covers the first source drain metal layer; and
the second source-drain metal layer is arranged on the second interlayer dielectric layer and comprises a first connecting line and a second connecting line, and the first connecting line is respectively and electrically connected with two adjacent GOA devices through a first via hole and a second via hole which penetrate through the second interlayer dielectric layer; the second connecting line is electrically connected with the sub-pixel and one of the second source electrode and the second drain electrode through a third via hole penetrating through the second interlayer dielectric layer.
According to the display panel provided by the invention, at least one first transistor of the GOA unit is formed by a plurality of first sub-transistors connected in parallel.
According to the display panel provided by the invention, the pixel driving circuit is any one of 2T1C, 3T1C, 5T1C and 7T 1C.
The invention provides a display device which comprises the display panel.
The invention has the beneficial effects that: according to the display panel and the display device provided by the invention, the GOA unit in the gate drive circuit is arranged in the line sparse area between the two adjacent pixel drive circuit units, compared with the prior art, the gate drive circuit is arranged in the display area without being arranged in the frame areas at the left side and the right side of the display area, so that the width of the left frame and the right frame of the display panel can be obviously reduced, and the frameless target of the display panel is favorably realized.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic plan view of a display panel according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a wiring structure of a display panel according to an embodiment of the present invention;
FIG. 3 is a simplified structural diagram of a display panel according to an embodiment of the present invention;
fig. 4 is an equivalent circuit diagram of a pixel driving circuit unit according to an embodiment of the present invention;
fig. 5 is an equivalent circuit diagram of a GOA unit according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a wiring structure of a GOA unit according to an embodiment of the present invention;
fig. 7 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present invention.
Description of the reference numerals:
100a, a display area; 100b, a non-display area; 1001a, a line sparse area;
11. a sub-pixel; 12. a pixel driving circuit unit; 121. a second transistor; 122. a second capacitor; 13. a GOA unit; 131. a GOA device; 132. a first transistor; 133. a first capacitor; 14. scanning a line; 15. a data line; 151. a main body section; 152. winding the wire section; 16. an auxiliary connecting line;
101. a substrate; 102. a buffer layer; 103. a semiconductor layer; 1031. a first semiconductor; 1032. a second semiconductor; 104. a first gate insulating layer; 105. a first metal layer; 1051. a first gate electrode; 1052. a second gate electrode; 106. a second gate insulating layer; 107. a second metal layer; 1071. a third gate electrode; 108. a first interlayer dielectric layer; 109. a first source drain metal layer; 1091. a first source electrode; 1092. a first drain electrode; 1093. a second source electrode; 1094. a second drain electrode; 110. a second interlayer dielectric layer; 111. a second source drain metal layer; 1111. a first connection line; 1112. a second connecting line; 112. a planarization layer; 113. and an anode.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention. Furthermore, it should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, and are not intended to limit the present invention. In the present invention, unless otherwise specified, the use of directional terms such as "upper" and "lower" generally means upper and lower in the actual use or operation of the device, particularly in the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
Referring to fig. 1, fig. 1 is a schematic plan view of a display panel according to an embodiment of the present invention. An embodiment of the present invention provides a display panel, which includes an OLED display panel and the like, for example, an AMOLED display panel. The display panel includes a display area 100a and a non-display area 100b located at the periphery of the display area 100a, wherein the display area 100a is an Active area (Active area) of the display panel for displaying a picture, and the non-display area 100b surrounds the outer periphery of the display area 100a as a layout space for circuits and related traces.
Referring to fig. 2 and fig. 3, fig. 2 is a schematic diagram of a wiring structure of a display panel according to an embodiment of the present invention; fig. 3 is a schematic plan view of a simplified structure of a display panel according to an embodiment of the present invention. The display area 100a comprises a plurality of sub-pixel units arranged in a multi-row and multi-column array, each sub-pixel unit comprises a sub-pixel 11 and a pixel driving circuit unit 12 for driving the sub-pixel 11, and a line sparse area 1001a is arranged between every two adjacent pixel driving circuit units 12; the display panel further includes a gate driving circuit, the gate driving circuit includes a plurality of cascaded GOA units 13, and the GOA units 13 are located in the line thinning-out region 1001 a.
Specifically, the display area 100a further includes a plurality of scan lines 14 and a plurality of data lines 15, an extending direction of the scan lines 14 is parallel to a row direction of the sub-pixel units, an extending direction of the data lines 15 is parallel to a column direction of the sub-pixel units, the plurality of scan lines 14 and the plurality of data lines 15 are arranged in a crossing manner to define a plurality of sub-pixel units arranged in a matrix form, a number of rows of the sub-pixel units is equal to a number of the scan lines 14, a number of columns of the sub-pixel units is equal to a number of the data lines 15, the sub-pixels 11 located in the same row are electrically connected to a corresponding scan line 14, and the sub-pixels 11 located in the same column are electrically connected to a corresponding data line 15.
Each sub-pixel 11 is electrically connected to a corresponding pixel driving circuit unit 12, and the pixel driving circuit unit 12 drives the corresponding sub-pixel 11 to emit light, thereby realizing image display; similarly, the pixel driving circuit units 12 are also arranged in a multi-row and multi-column array, and the arrangement manner of the pixel driving circuit units is consistent with that of the sub-pixels 11.
Each gate driving circuit comprises a plurality of GOA units 13, each GOA unit 13 is connected with at least one scanning line 14, and the gate driving circuits are connected to a GOA bus through signal leads led out from the gate driving circuits. The driving signals of the gate driver array type display panel are input from the signal input terminals, and are transmitted to the signal leads of the GOA units 13 connected thereto through the GOA bus, and further reach the clock signal input terminals of the GOA units 13, so as to realize signal driving of the GOA units 13.
It is understood that, for the sub-pixel unit, the sub-pixel 11 is disposed on one side of the pixel driving circuit unit 12, and the sub-pixel 11 and the pixel driving circuit unit 12 are stacked up and down, that is, the sub-pixel 11 is located on the top layer of the sub-pixel unit, and the pixel driving circuit unit 12 is located on the bottom layer of the sub-pixel unit. In the present invention, the GOA unit 13 located in the non-display area 100b in the prior art is moved to the display area 100a, so that the widths of the left and right frames of the display panel can be significantly reduced, which is beneficial to achieving the frameless target of the display panel.
Specifically, the GOA unit 13 may be disposed between two adjacent pixel driving circuit units 12 in the same row, or disposed between two adjacent pixel driving circuit units 12 in the same column.
It should be noted that the line sparse region 1001a in the embodiment of the present invention does not mean a region where the wiring of the pixel driving circuit unit 12 is not completely disposed, but means a region where the transistor and the storage capacitor of the pixel driving circuit unit 12 are avoided, and the line density of the region is smaller than that of the region where the transistor and the storage capacitor are disposed, so that a sufficient space for placing the GOA unit 13 can be reserved.
In an embodiment, the pixel driving circuit unit 12 may be reduced in size to reduce the occupied space of the pixel driving circuit unit 12 in the sub-pixel unit, so as to make a part of the space, and it is understood that the made part of the space is the line sparse region 1001a in the present invention. In particular, this can be achieved by arranging the transistors and storage capacitors of the pixel driving circuit unit 12 in a denser manner.
In another embodiment, the size of the sparse line area 1001a may be increased by rearranging the routing lines originally disposed in the sparse line area 1001a, so as to leave enough space for placing the GOA unit 13.
Specifically, the display panel includes a plurality of signal lines extending in a row direction or a column direction of the plurality of sub-pixel units, the signal lines are configured to transmit driving signals to the plurality of pixel driving circuit units 12 located in the same row or the same column, respectively, two adjacent signal lines are located between two adjacent pixel driving circuit units 12 located in the same row or the same column, and the two signal lines form the line thinning-out region 1001a by winding.
Specifically, when the signal line extends in the row direction of a plurality of the sub-pixel units, for example, the signal line may be an EM signal line or the scan line 14, in which case the line thinning-out region 1001a is located between two of the pixel driving circuit units 12 in the same column; when the signal line extends in the column direction of a plurality of the sub-pixel units, for example, the signal line may be the data line 15 or the high-level voltage signal line VDD, in which case the line thinning-out region 1001a is located between two of the pixel driving circuit units 12 in the same row.
In order to clearly explain the technical solutions provided by the present invention, the embodiment of the present invention takes the signal line as the data line 15 as an example for explanation, but other technical solutions adopting the inventive concept are within the protection scope of the present invention.
Specifically, the plurality of signal lines include a plurality of data lines 15, the plurality of data lines 15 extend in a column direction of the plurality of sub-pixel units, the data lines 15 are configured to transmit data driving signals to the plurality of pixel driving circuit units 12 located in the same column, respectively, two adjacent data lines 15 are located between two adjacent pixel driving circuit units 12 located in the same column, and the two data lines 15 are wound to form the line thinning-out region 1001 a.
The data line 15 includes a plurality of main body segments 151 and a plurality of line winding segments 152 connected to each other, the line winding segments 152 are disposed between two adjacent main body segments 151, the main body segments 151 extend in a column direction of a plurality of sub-pixel units, and the line winding segments 152 extend in an extending direction of an edge of the line thinning-out region 1001 a.
Specifically, two ends of the winding segment 152 are respectively connected to the two main segments 151, the winding segment 152 is closer to the corresponding pixel driving circuit unit 12 than the main segments 151, the winding segment 152 may be a straight line segment or a curved line segment, and when the winding segment 152 is a straight line segment, the winding segment 152 may be "Contraband" shaped or "コ" shaped; when the winding wire section 152 is a curved section, the winding wire section 152 may be any one of a semi-elliptical shape and a semi-circular shape.
It can be understood that, in the prior art, two adjacent data lines 15 driving two adjacent columns of pixel driving circuit units 12 respectively pass through one corresponding column of pixel driving circuit units 12, compared with the prior art, in the embodiment of the present invention, two adjacent data lines 15 driving two adjacent columns of pixel driving circuit units 12 are moved to between two adjacent columns of pixel driving circuit units 12, and by performing a wire winding design on the data lines 15 and performing adaptive rearrangement on other signal lines, for example, a scanning signal line Scan (n-1) originally passing through the n-1 th stage of the line sparse region 1001a is broken at two sides of the line sparse region 1001a to form a plurality of scanning line segments, and an auxiliary connection line 16 is introduced to connect two ends of two adjacent scanning line segments, the auxiliary connection line 16 is located at the periphery of the line sparse region 1001a, so that the line sparse area 1001a is left between two adjacent data lines 15 for placing the GOA unit 13.
Each of the pixel driving circuit units 12 includes at least two second transistors 121 and a second capacitor 122, and optionally, the pixel driving circuit unit 12 is any one of 2T1C, 3T1C, 5T1C and 7T1C, and in order to clearly explain the technical solution provided by the present invention, the embodiment of the present invention takes the pixel driving circuit unit 12 as 7T1C for illustration.
Specifically, referring to fig. 2, the pixel driving circuit unit 12 further includes an n-1 th Scan signal line Scan (n-1), an n-th Scan signal line Scan (n), a low-voltage line VI, a high-power positive voltage signal line VDD, and an EM signal line, wherein the n-1 th Scan signal line Scan (n-1), the n-th Scan signal line Scan (n), the low-voltage line VI, and the EM signal line extend along the row direction of the plurality of sub-pixel units, the high-power positive voltage signal line VDD extends along the column direction of the plurality of sub-pixel units to the n-1 th Scan signal line Scan (n-1) and the n-th Scan signal line Scan (n) are located in the first metal layer, and the high-power positive voltage signal line VDD and the data line are located in the first source-drain metal layer.
Referring to fig. 2 and fig. 4, fig. 4 is an equivalent circuit diagram of a pixel driving circuit unit according to an embodiment of the present invention. The pixel driving circuit unit 12 includes 7 second transistors and 1 second capacitor, the 7 second transistors are respectively T1-T7, the first capacitor is C1, the gate of T3 is connected to the scan signal line scan (n) of the nth stage, the source of T3 is connected to a Data signal line Data, and the drain of T3 is connected to the drain of T1 and the drain of T5. The gate of T5 is connected to the EM signal line, the source of T5 is connected to the high power supply positive voltage signal line VDD, and the drain of T5 is connected to the drain of T1. The gate of T1 is connected to node Q, and the gate of T1 is connected to the source of T6. The gate of T6 is connected to the EM signal line, and the drain of T6 is connected to the anode of the sub-pixel 11. The grid of T2 is connected with the scan signal line Scan (n) of the nth stage, T2 is a double-grid switch tube, the source of T2 is connected with the source of T6, and the drain of T2 is connected with the node Q. The gate of T4 is connected to Scan signal line Scan (n-1) of the (n-1) th stage, the drain of T4 is connected to node Q, the source of T4 is connected to low-potential voltage line VI, and the cathode of the sub-pixel 11 is connected to low-power negative voltage signal line VSS.
In an embodiment, when the size of the line thinning-out region 1001a is large enough, the line thinning-out region 1001a places the whole GOA unit 13.
With the development of display technology, the pixel density of the display panel is increased more and more, which results in that the size of the line sparse region 1001a of the sub-pixel unit is smaller, and each of the GOA units 13 includes a plurality of GOA devices 131, and each of the GOA devices 131 includes at least one of the first transistor 132 or the first capacitor 133, so that the size of the GOA unit 13 is larger, and the size of the line sparse region 1001a is not enough to place the whole GOA unit 13. Specifically, the GOA devices 131 are disposed in at least a portion of the line thinning-out regions 1001a, and one or more GOA devices 131 may be disposed in each of the line thinning-out regions 1001 a.
For example, please refer to fig. 5 and fig. 6, fig. 5 is an equivalent circuit diagram of a GOA unit according to an embodiment of the present invention; fig. 6 is a schematic diagram of a wiring structure of a GOA unit according to an embodiment of the present invention. The GOA unit 13 includes 8 first transistors 132 and 2 first capacitors 133 for illustration. The 8 first transistors 132 are respectively T8-T15, the 2 first capacitors 133 are respectively C2 and C3, the gates of T8 and T10 are connected with a first clock signal XCK, the source of T8 is connected with a VGL voltage signal, the drain of T8 is connected with the drain of T10 and the gate of T12, a gate of T14 and a first electrode of C3, a source of T9 is connected to Scan signal Scan (n-1) of the n-1 th stage, a drain of T9 is connected to a source of T13, a gate of T10 is connected to a source of T15, a gate of T11 and a source of T13 are connected to second clock signal CK, a source of T11 is connected to a drain of T12, a gate of T15 is connected to VGL voltage signal, a drain of T15 is connected to a gate of T13 and a first electrode of C2, a drain of T13 is connected to a second electrode of C2 and Scan signal Scan (Scan) of the n-th stage, a drain of T14 is connected to a second electrode of C2 and Scan signal Scan (n) of the n-th stage, and a source of T14 and a source of T12 are connected to a second electrode of C3 and VGH voltage signal. The VGL voltage signal is a voltage signal for controlling the switching tube to be turned off, the VGH voltage is a voltage for controlling the switching tube to be turned on, and a certain voltage difference exists between the VGH voltage value and the VGL voltage, for example, the voltage difference between the VGH and the VGL can be set to be more than 25V.
Specifically, the plurality of GOA devices 131 of one GOA unit 13 are disposed in a plurality of columns of sub-pixel units or a plurality of rows of sub-pixel units, so that the plurality of GOA devices 131 are densely disposed, and the connection difficulty between the plurality of GOA devices 131 can be reduced.
Further, the GOA units 13 are disposed in the edge region of the display area 100a for convenient wiring.
Further, if the single placed GOA device 131 cannot meet the requirements of high output and large capacitance, a multi-device parallel connection mode may be adopted, specifically, the GOA device 131 is formed by a plurality of first sub-transistors connected in parallel, and the size of the first sub-transistors is smaller than that of the GOA device.
Further, please refer to fig. 7, fig. 7 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present invention. In a cross-sectional view of the display panel, the second transistor 121 and the second capacitor 122 are disposed on the same layer as the GOA device 131, so that the GOA unit 13 and the pixel driving circuit unit 12 are manufactured at the same time.
Specifically, the display panel includes a substrate 101, a driving circuit layer and a plurality of sub-pixels 11, the driving circuit layer is disposed on the substrate 101, and the driving circuit layer includes the pixel driving circuit unit 12 and the GOA unit 13; the plurality of sub-pixels 11 are disposed on the driving circuit layer.
The driving circuit layer comprises a semiconductor layer 103, a first gate insulating layer 104, a first metal layer 105, a second gate insulating layer 106, a second metal layer 107, a first interlayer dielectric layer 108 and a first source/drain metal layer 109. Specifically, the semiconductor layer 103 is disposed on the substrate 101, and the semiconductor layer 103 includes a first semiconductor 1031 and a second semiconductor 1032; the first gate insulating layer 104 covers the semiconductor layer 103; the first metal layer 105 is disposed on the first gate insulating layer 104, the first metal layer 105 includes a first gate 1051 and a second gate 1052; the second gate insulating layer 106 covers the first metal layer 105; the second metal layer 107 is disposed on the second gate insulating layer 106, and the second metal layer 107 includes a third gate 1071; the first interlayer dielectric layer 108 covers the second metal layer 107; the first source-drain metal layer 109 is disposed on the first interlayer dielectric layer 108, and the first source-drain metal layer 109 includes a first source 1091, a first drain 1092, a second source 1093, and a second drain 1094.
Wherein the first semiconductor 1031, the first gate insulating layer 104, the first gate 1051, the second gate insulating layer 106, the first interlayer dielectric layer 108, the first source 1091, and the first drain 1092 constitute the first transistor 132, and the second semiconductor 1032, the first gate insulating layer 104, the second gate 1052, the second gate insulating layer 106, the third gate 1071, the first interlayer dielectric layer 108, the second source 1093, and the second drain 1094 constitute the second transistor 121.
Further, the display panel further includes a buffer layer 102, and the buffer layer 102 is disposed between the semiconductor layer 103 and the substrate 101.
Further, the display panel further includes a second interlayer dielectric layer 110 and a second source/drain metal layer 111, the second interlayer dielectric layer 110 covers the first source/drain metal layer 109, the second source/drain metal layer 111 is disposed on the second interlayer dielectric layer 110, the second source/drain metal layer 111 includes a first connection line 1111 and a second connection line 1112, the first connection line 1111 is electrically connected to two adjacent GOA devices 131 through a first via hole and a second via hole penetrating through the second interlayer dielectric layer 110, and the first connection line 1111 forms a bridge structure through the first via hole and the second via hole, so as to avoid a short circuit between the two adjacent GOA devices 131 and the wiring in the pixel driving circuit unit 12 when connected; the second connection line 1112 electrically connects the sub-pixel 11 and one of the second source 1093 and the second drain 1094 through a third via penetrating through the second interlayer dielectric layer 110.
Further, the first source-drain metal layer 109 further includes a high-level power signal line VDD, and the second source-drain metal layer 111 further includes a third connection line electrically connected to the high-level power signal line VDD through a fourth via hole penetrating through the second interlayer dielectric layer 110, so that the high-level power signal line VDD and the third connection line are connected in parallel, which can reduce a voltage drop of the high-level power signal line VDD.
Further, the display panel further includes a planarization layer 112, the planarization layer 112 covers the second source/drain metal layer 111 for planarizing the second source/drain metal layer 111, the second connection line 1112 is electrically connected to the anode 113 of the sub-pixel 11 through a fifth via hole penetrating through the planarization layer 112, and the anode 113 is disposed on the planarization layer 112.
The embodiment of the invention also provides a display device, which comprises the display panel in the embodiment, and the display device can be any product or part with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
The display device also comprises a touch panel, and the touch panel is combined with the display panel in an internal or external mode so as to enable the display device to have a touch function.
The beneficial effects are that: according to the display panel and the display device provided by the embodiment of the invention, the GOA units in the gate drive circuit are arranged in the line sparse area between the two adjacent pixel drive circuit units, compared with the prior art, the gate drive circuit is arranged in the display area without being arranged in the frame areas at the left side and the right side of the display area, so that the width of the left frame and the right frame of the display panel can be obviously reduced, and the frameless target of the display panel is favorably realized.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (11)
1. A display panel is characterized by comprising a display area and a non-display area positioned at the periphery of the display area; the display area comprises a plurality of sub-pixel units which are arranged in a multi-row and multi-column array manner, each sub-pixel unit comprises a sub-pixel and a pixel driving circuit unit for driving the sub-pixel, and a line sparse area is arranged between every two adjacent pixel driving circuit units;
the display panel further comprises a gate driving circuit, wherein the gate driving circuit comprises a plurality of cascaded GOA units, and the GOA units are located in the line sparse area.
2. The display panel according to claim 1, wherein the display panel includes a plurality of signal lines extending in a row direction or a column direction of the plurality of sub-pixels, the signal lines being configured to transmit driving signals to a plurality of the pixel driving circuit units located in a same row or a same column, respectively, two adjacent signal lines being located in between two adjacent pixel driving circuit units located in a same row or a same column, the two signal lines forming the line thinning-out region around a line.
3. The display panel according to claim 2, wherein the plurality of signal lines include a plurality of data lines extending in a column direction of the plurality of sub-pixel units, the data lines are configured to transmit data driving signals to the plurality of pixel driving circuit units located in a same column, respectively, two adjacent data lines are located in between two adjacent pixel driving circuit units located in the same column, and two data lines form the line thinning-out region around the lines.
4. The display panel according to claim 3, wherein the data line includes a plurality of main body segments and a plurality of winding segments connected, the winding segments being disposed between adjacent two of the main body segments, the main body segments extending in a column direction of the plurality of sub-pixel units, and the winding segments extending in an extending direction of an edge of the line thinning-out region.
5. The display panel according to claim 1, wherein the GOA unit comprises a plurality of connected GOA devices, each of the line thinning regions is provided with at least one GOA device, and the GOA device comprises a first transistor or a first capacitor.
6. The display panel according to claim 5, wherein each of the pixel driving circuit units comprises at least two second transistors and a second capacitor, and the second transistors and the second capacitors are disposed in the same layer as the GOA device.
7. The display panel according to claim 6, characterized in that the display panel comprises:
a substrate;
the driving circuit layer is arranged on the substrate and comprises the pixel driving circuit unit and the GOA unit; and
the plurality of sub-pixels are arranged on the driving circuit layer;
wherein the driving circuit layer includes:
a semiconductor layer disposed on the substrate, including a first semiconductor and a second semiconductor;
a first gate insulating layer overlying the semiconductor layer;
the first metal layer is arranged on the first grid electrode insulating layer and comprises a first grid electrode and a second grid electrode;
a second gate insulating layer overlying the first metal layer;
the second metal layer is arranged on the second grid electrode insulating layer and comprises a third grid electrode;
the first interlayer dielectric layer covers the second metal layer; and
the first source drain metal layer is arranged on the first interlayer dielectric layer and comprises a first source electrode, a first drain electrode, a second source electrode and a second drain electrode;
the first semiconductor, the first gate insulating layer, the first gate, the second gate insulating layer, the first interlayer dielectric layer, the first source, and the first drain constitute the first transistor, and the second semiconductor, the first gate insulating layer, the second gate insulating layer, the third gate, the first interlayer dielectric layer, the second source, and the second drain constitute the second transistor.
8. The display panel according to claim 7, characterized by further comprising:
the second interlayer dielectric layer covers the first source drain electrode metal layer; and
the second source drain metal layer is arranged on the second interlayer dielectric layer and comprises a first connecting line and a second connecting line, and the first connecting line is respectively and electrically connected with two adjacent GOA devices through a first via hole and a second via hole which penetrate through the second interlayer dielectric layer; the second connecting line is electrically connected with the sub-pixel and one of the second source electrode and the second drain electrode through a third via hole penetrating through the second interlayer dielectric layer.
9. The display panel according to claim 5, wherein at least one of the first transistors of the GOA unit is formed of a plurality of first sub-transistors connected in parallel.
10. The display panel according to claim 1, wherein the pixel driving circuit is any one of 2T1C, 3T1C, 5T1C, and 7T 1C.
11. A display device comprising the display panel according to any one of claims 1 to 10.
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