CN113764461A

CN113764461A - Display panel and display device

Info

Publication number: CN113764461A
Application number: CN202010498518.8A
Authority: CN
Inventors: 黄耀; 黄炜赟; 龙跃; 王彬艳; 杨国波; 王本莲
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2020-06-04
Filing date: 2020-06-04
Publication date: 2021-12-07
Anticipated expiration: 2040-06-04
Also published as: US20240114731A1; EP4106001A1; JP2023529038A; CN117396032A; EP4106001A4; US20230189596A1; US20230091142A1; WO2021244279A1

Abstract

A display panel and a display device, the display panel including: a first display area; a second display area at least located at one side of the first display area; the pixel units in the first display area are lower in density than the pixel units in the second display area and comprise pixel circuits; and a first power supply line configured to supply a first voltage signal to the pixel circuit; the first power line includes a plurality of first conductive lines extending from the second display region to the first display region, a plurality of second conductive lines located at the first display region and between adjacent first conductive lines, the second conductive lines extending in a first direction, the third conductive lines extending in a second direction, the first direction intersecting the second direction, the third conductive lines extending from the second display region to the first display region, and adjacent second conductive lines spaced apart from each other in the first direction, the second conductive lines connected to the first conductive lines through the third conductive lines.

Description

Display panel and display device

Technical Field

At least one embodiment of the present disclosure relates to a display panel and a display device.

Background

Based on the design of the under-screen camera, the display panel usually includes a high pixel density (Pixels Per inc, PPI) region and a low PPI region, however, the light transmittance of the general display panel in the low PPI region is low, which is not favorable for improving the display effect of the camera in the imaging region.

Disclosure of Invention

At least one embodiment of the present disclosure provides a display panel including: a first display area; a second display area located at least on one side of the first display area;

a plurality of pixel units located in the first display area and the second display area, the density of the pixel units of the first display area being less than the density of the pixel units of the second display area, the pixel units including pixel circuits; and a first power supply line configured to supply a first voltage signal to the pixel circuit; the first power line includes a plurality of first conductive lines extending from the second display region to the first display region, a plurality of second conductive lines located at the first display region and between adjacent first conductive lines, the second conductive lines extending in a first direction, and a plurality of third conductive lines extending in a second direction, the first direction intersecting the second direction, the third conductive lines extending from the second display region to the first display region, and adjacent second conductive lines spaced apart from each other in the first direction, the second conductive lines being connected to the first conductive lines through the third conductive lines.

According to some embodiments of the present disclosure, there is provided a display panel, wherein the plurality of second conductive lines are sequentially arranged along the first direction.

According to some embodiments of the present disclosure, there is provided a display panel, wherein the adjacent second conductive lines are not directly connected.

According to some embodiments of the present disclosure, there is provided a display panel, wherein a length of a portion of the first conductive line located in the first display region in the first direction is greater than a length of the second conductive line in the first direction.

According to some embodiments of the present disclosure, there is provided a display panel, wherein the first conductive line includes portions located at different layers, and the portions located at different layers are connected by a via penetrating through an insulating layer.

According to some embodiments of the present disclosure, there is provided a display panel, in which the first power line further includes a fourth conductive line extending in the second direction, the second conductive line is connected to the first conductive line through the fourth conductive line, and a length of the fourth conductive line in the second direction is less than or equal to a length of the third conductive line in the second direction.

According to some embodiments of the present disclosure, there is provided a display panel including a plurality of fourth conductive lines between adjacent third conductive lines, the plurality of fourth conductive lines being sequentially arranged along the second direction, and adjacent fourth conductive lines being spaced apart from each other in the second direction.

According to some embodiments of the present disclosure, there is provided a display panel, wherein a portion of the first conductive line and the third conductive line are located at the same layer, and the fourth conductive line and the third conductive line are located at the same layer.

According to the display panel provided by some embodiments of the present disclosure, the pixel units located in the first display area constitute a plurality of pixel islands, the pixel islands include at least two pixel units located in two adjacent rows, and the first conducting lines and the second conducting lines respectively overlap with the two pixel units located in the two adjacent rows.

According to some embodiments of the present disclosure, there is provided a display panel, the pixel unit further includes a light emitting element, the pixel circuit includes a first transistor and a second transistor, the first transistor is connected to the second transistor, the second transistor is connected to the light emitting element, the first transistor includes a first channel and a second channel, the first channel and the second channel are connected by a conductive portion, the second wire further includes a connection arm, the connection arm and the conductive portion of one of the pixel islands which overlaps with the second wire are spaced apart from each other in a third direction which is perpendicular to the first direction and perpendicular to the second direction, and partially overlap in the third direction.

According to some embodiments of the present disclosure, there is provided a display panel, wherein the shape of the connection arm includes a C-shape.

According to some embodiments of the present disclosure, there is provided a display panel, wherein the first conductive line has a branch which is spaced apart from the conductive portion of one pixel cell of the pixel island overlapping the first conductive line in the third direction and partially overlaps in the third direction.

According to some embodiments of the present disclosure, there is provided the display panel, wherein the first direction is perpendicular to the second direction.

According to some embodiments of the present disclosure, there is provided a display panel, wherein the first power line further includes a fifth conductive line extending along the first direction, the fifth conductive line being located in the second display region, the fifth conductive line being located between adjacent first conductive lines, and the fifth conductive line and a second conductive line adjacent thereto being spaced apart from each other along the first direction.

According to some embodiments of the present disclosure, there is provided a display panel further including an initialization signal line configured to provide an initialization signal to the pixel circuit, the second conductive line being surrounded by a portion of the initialization signal line.

According to some embodiments of the present disclosure, there is provided a display panel, wherein the first conductive line includes a first portion and a second portion, the first portion of the first conductive line is located at the same layer as the second conductive line, the second portion of the first conductive line is not located at the same layer as the second conductive line, and the first portion of the first conductive line is surrounded by a portion of the initialization signal line.

According to some embodiments of the present disclosure, there is provided a display panel, wherein the first portion of the first conductive line has a first sub-portion extending in the first direction and a second sub-portion extending in the second direction, the second sub-portion having a branch, the branch extending in the first direction.

According to some embodiments of the present disclosure, there is provided the display panel, wherein a length of the branch in the first direction is smaller than a length of the first sub-section in the first direction.

According to some embodiments of the present disclosure, there is provided a display panel, the pixel unit further includes a light emitting element, the pixel circuit includes a first transistor and a second transistor, the first transistor is connected to the second transistor, the second transistor is connected to the light emitting element, the first transistor includes a first channel and a second channel, the first channel and the second channel are connected through a conductive portion, the branch and the conductive portion of one of the pixel units overlapping the first conductive line in the pixel island are spaced apart from each other in the third direction and partially overlap in the third direction, and the third direction is perpendicular to the first direction and perpendicular to the second direction.

According to some embodiments of the present disclosure, there is provided a display panel, in which the second conductive line further includes a connection arm that is spaced apart from and partially overlaps in a third direction with the conductive portion of one pixel cell of the pixel island that overlaps the second conductive line.

According to some embodiments of the present disclosure, there is provided a display panel, further including a substrate and data lines configured to supply data signals to the pixel circuits, the data lines including first data lines, wherein the first data lines extend from the first display region to the second display region, and the first data lines overlap with a forward projection portion of the third conductive lines on the substrate.

According to some embodiments of the present disclosure, there is provided a display panel, wherein the first data line includes a first portion and a second portion, the first portion of the first data line overlaps the third conductive line, the second portion of the first data line does not overlap the third conductive line, and the first portion of the first data line and the second portion of the first data line are respectively located at different layers.

According to some embodiments of the present disclosure, there is provided a display panel having a light transmission region between adjacent pixel islands, and the first portion of the first data line is positioned between the adjacent pixel islands.

According to the display panel provided by some embodiments of the present disclosure, two first data lines are provided, the two first data lines are respectively connected to two adjacent columns of pixel units, and the two first data lines overlap with an orthographic projection part of the same third conducting wire on the substrate.

According to some embodiments of the present disclosure, the display panel further includes a gate line configured to provide a scan signal to a row of pixel units, the gate line including a first gate line extending from the second display region to the first display region, and the light-transmitting region is surrounded by two adjacent first gate lines and two adjacent first data lines.

Some embodiments of the present disclosure also provide a display device including any one of the above display panels.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

Fig. 1A to 1C are schematic views of a display panel provided in some embodiments of the present disclosure;

fig. 2 is a schematic diagram of a second display area of a display panel according to an embodiment of the disclosure;

fig. 3 is a schematic diagram of a first display area of a display panel according to an embodiment of the disclosure;

fig. 4 is a schematic diagram of a pixel unit and a signal line for providing a signal to the pixel unit in a display panel according to an embodiment of the disclosure;

FIG. 5 is a schematic view of a display panel;

fig. 6A to 6E are schematic views of a display panel according to some embodiments of the present disclosure;

fig. 7A is a schematic view of a display panel according to an embodiment of the disclosure;

fig. 7B is a schematic diagram of a display panel according to an embodiment of the disclosure;

fig. 8 is a schematic diagram of a pixel circuit of a display panel according to an embodiment of the disclosure;

fig. 9 is a plan view of a semiconductor pattern in a display panel according to an embodiment of the present disclosure;

fig. 10 is a plan view of a first conductive pattern layer in a display panel according to an embodiment of the present disclosure;

fig. 11 is a plan view of a second conductive pattern layer in a display panel according to an embodiment of the disclosure;

fig. 12 is a plan view of a first insulating layer in a display panel according to an embodiment of the present disclosure;

fig. 13 is a plan view of a third conductive pattern layer in a display panel according to an embodiment of the disclosure;

fig. 14 is a plan view of a second insulating layer in a display panel according to an embodiment of the present disclosure;

fig. 15 is a plan view of a pixel electrode layer in a display panel according to an embodiment of the present disclosure;

fig. 16 is a plan view of a pixel defining layer in a display panel according to an embodiment of the disclosure;

fig. 17 is a schematic diagram illustrating an active layer of a thin film transistor formed in a display panel according to an embodiment of the present disclosure;

fig. 18 is a schematic plan view illustrating a display panel according to an embodiment of the present disclosure after forming a second conductive pattern layer and a first insulating layer;

fig. 19 is a schematic plan view illustrating a display panel according to an embodiment of the present disclosure after a third conductive pattern layer is formed;

fig. 20 is a schematic plan view illustrating a display panel according to an embodiment of the present disclosure after a second insulating layer is formed;

fig. 21 is a schematic plan view illustrating a display panel after a pixel electrode layer is formed according to an embodiment of the present disclosure;

fig. 22 is a schematic plan view illustrating a display panel after a pixel definition is formed according to an embodiment of the present disclosure;

fig. 23 is a schematic plan view illustrating a pixel island adjacent to the first display region in the second direction in a display panel according to an embodiment of the disclosure;

fig. 24 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure; and

fig. 25 is a schematic cross-sectional view of a display panel according to an embodiment of the disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

In a typical display panel, the first power line has a mesh structure in both a high PPI region and a low PPI region. In order to improve the light transmittance of the low PPI region and improve the display effect of the camera in the imaging region, the display panel provided by the embodiment of the disclosure optimizes the signal lines of the low PPI region to achieve a higher transmittance, for example, the embodiment of the disclosure optimizes the wires arranged in the transverse and longitudinal directions of the mesh-shaped first power line.

Fig. 1A to 1C are schematic views of a display panel according to some embodiments of the present disclosure. As shown in fig. 1A to 1C, the display panel includes a first display region R1 and a second display region R2. The first display region R1 is a high pixel density (PPI) region, and the second display region R2 is a low PPI region. The second display region R2 is a partially light-transmitting region. As shown in fig. 1A to 1C, the second display region R2 is located at least at one side of the first display region R1. The display panel shown in fig. 1A and 1B further includes a third region R3. A sensor such as a camera may be provided in the first display region R1 (as shown in fig. 1C), or in the first display region R1 and the third region R3 (as shown in fig. 1A and 1B). The third region R3 shown in fig. 1A and 1B may be a dug region, that is, the material at the position corresponding to the third region R3 is removed to form a through hole. The sensor may receive ambient light. Use the sensor as the camera for example, realize camera under the screen for when normally using the screen, the first display area that the sensor corresponds can normally show the picture, and when carrying out the camera shooting, first display area can see through ambient light, supports normal use. For example, the sensor is disposed on the non-display side of the display panel. The sensor may also be referred to as an off-screen device.

Fig. 1A also shows a plurality of gate lines 113 and a plurality of data lines 313. The plurality of gate lines 113 includes a first gate line GL1, and the plurality of data lines 313 includes a first data line DL 1. The first gate line GL1 extends from the second display region R2 to the first display region R1. The first data line DL1 extends from the first display region R1 to the second display region R2. In the embodiment of the present disclosure, an element extending from the first display region R1 to the second display region R2 may be understood as being located in the first display region R1 and the second display region R2, and may be said as an element extending from the second display region R2 to the first display region R1. For clarity of illustration, fig. 1A schematically shows several gate lines 113 and several data lines 313, and the number of the gate lines 113 and the data lines 313 may be determined as needed. The plurality of gate lines 113 and the plurality of data lines 313 cross each other and are insulated from each other.

Fig. 2 is a schematic diagram of a second display area of a display panel according to an embodiment of the disclosure. Fig. 3 is a schematic diagram of a first display area of a display panel according to an embodiment of the disclosure. As shown in fig. 2 and 3, the display panel includes a plurality of pixel units P0, and a plurality of pixel units P0 includes a first pixel unit 101, a second pixel unit 102, a third pixel unit 103, and a fourth pixel unit 104. One first pixel unit 101, one second pixel unit 102, one third pixel unit 103, and one fourth pixel unit 104 constitute the pixel group P1. For example, one pixel group P1 includes two pixels, and in the pixel group P1, one first pixel unit 101 and one second pixel unit 102 constitute one pixel, and one third pixel unit 103 and one fourth pixel unit 104 constitute one pixel. One pixel group P1 forms two virtual pixels to improve the display effect. For example, one pixel group P1 is a repeating unit and is arranged in an array in the second display region R2. As shown in fig. 3, in the first display region R1, one pixel group P1 is referred to as one pixel island a 1. The first display region R1 includes a plurality of light transmission regions R0; the light transmission region R0 is located between adjacent pixel islands a 1. The light transmitting region R0 is transparent to ambient light. For example, the light-transmitting region R0 may include a substrate and a transparent insulating layer on the substrate, and the light-transmitting region R0 has no light-shielding structure, e.g., no metal traces. For example, the light-transmitting region R0 is located in a region surrounded by four adjacent pixel islands a1, but is not limited thereto. For example, as shown in fig. 3, adjacent pixel islands a1 are spaced apart.

In the embodiment of the disclosure, the first pixel unit 101 is a red pixel unit, the second pixel unit 102 is a green pixel unit, the third pixel unit 103 is a blue pixel unit, and the fourth pixel unit 104 is a green pixel unit. Of course, in other embodiments, the arrangement of the plurality of pixel units P0 in the display panel is not limited to that shown in fig. 2 and 3.

Referring to fig. 2 and 3, a plurality of pixel units P0 are positioned in the first display region R1 and the second display region R2, and the density of the pixel units of the first display region R1 is less than that of the pixel units of the second display region R2. In other words, the density of the pixels of the first display region R1 is less than the density of the pixels of the second display region R2. The density of the pixel cells in the first display region R1 shown in fig. 3 is one fourth of the density of the pixel cells in the second display region R2. That is, the density of the pixels in the first display region R1 shown in fig. 3 is one-fourth of the density of the pixels in the second display region R2. The arrangement of the light-transmitting region R0 and the pixel unit in the first display region R1 is not limited to that shown in fig. 3, and may be set as needed. For example, in other embodiments, the density of the pixel cells in the first display region R1 is a value other than one-fourth, such as one-half, one-third, one-sixth, or one-eighth, of the density of the pixel cells in the second display region R2.

For example, as shown in fig. 1A and 3, the display panel further includes a gate line 113 and a data line 313. The gate line 113 and the data line 313 are insulated from each other. Each gate line 113 connects a row of pixel cells, and each data line 313 connects a column of pixel cells. For example, the gate line 113 is configured to supply a scan signal to a row of pixel units.

For example, as shown in fig. 1A and 3, the data line 313 includes a first data line DL 1. The first data line DL1 is located at least in the first display region R1. For example, the first data line DL1 extends from the first display region R1 to the second display region R2.

For example, as shown in fig. 1A and 3, the gate lines include a first gate line GL1, and the first gate line GL1 extends from the second display region R2 to the first display region R1. As shown in fig. 3, the light-transmitting region R0 is surrounded by two adjacent first gate lines GL1 and two adjacent first data lines DL1, but is not limited thereto.

Fig. 4 is a schematic diagram of a pixel unit and a signal line for providing a signal to the pixel unit in a display panel according to an embodiment of the disclosure. As shown in fig. 4, the display panel includes: a plurality of pixel units P0, each pixel unit P0 including a light emitting element EMC, which may be an electroluminescent element, for example, an Organic Light Emitting Diode (OLED), and a pixel circuit 10 providing a driving current for the light emitting element EMC.

As shown in fig. 4, the display panel further includes an initialization signal line 210, a light emission control signal line 110, a data line 313, a first power line 311, and a second power line 312. For example, the gate line 113 is configured to supply a SCAN signal SCAN to the pixel circuit 10. The emission control signal line 110 is configured to supply an emission control signal EM to the pixel unit P0. The DATA line 313 is configured to supply the DATA signal DATA to the pixel circuit 10, the first power line 311 is configured to supply a constant first voltage signal ELVDD to the pixel circuit 10, the second power line 312 is configured to supply a constant second voltage signal ELVSS to the pixel circuit 10, and the first voltage signal ELVDD is greater than the second voltage signal ELVSS. The initialization signal line 210 is configured to supply an initialization signal Vint to the pixel circuit 10. The initialization signal Vint is a constant voltage signal, and may have a magnitude between the first voltage signal ELVDD and the second voltage signal ELVSS, for example, but is not limited thereto, and may be less than or equal to the second voltage signal ELVSS, for example. For example, the pixel circuit 10 outputs a driving current to drive the light emitting element EMC to emit light under the control of signals of the SCAN signal SCAN, the DATA signal DATA, the initialization signal Vint, the first voltage signal ELVDD, the second voltage signal ELVSS, the light emission control signal EM, and the like. As shown in fig. 4, the light emitting element EMC includes a pixel electrode E1 and a common electrode E2. The pixel electrode E1 is connected to the pixel circuit 10, and the common electrode E2 is connected to the second power line 312.

Fig. 5 is a schematic view of a display panel. As shown in fig. 5, the first power line 3110 is in a mesh structure regardless of whether it is in the first display region R1 or the second display region R2, and a lateral portion of the first power line 3110 is directly connected and a vertical portion of the first power line 3110 is directly connected. However, the first power supply line of such a mesh structure is wired in such a manner that the light transmittance of the first display region R1 is low.

Fig. 6A to 6E are schematic views of display panels according to some embodiments of the present disclosure. As shown in fig. 6A to 6E, the first power line 311 includes a plurality of first conductive lines L1, a plurality of second conductive lines L2, and a plurality of third conductive lines L3, the first conductive lines L1 extend from the second display region R2 to the first display region R1, the plurality of second conductive lines L2 are located in the first display region R1 and are located between adjacent first conductive lines L1, each of the second conductive lines L2 extends in the first direction D1, the third conductive lines L3 are located at least in the first display region R1, for example, the third conductive lines L3 extend from the second display region R2 to the first display region R1, the third conductive lines L6959 extend in the second direction D2, the first direction D1 intersects the second direction D2, and adjacent second conductive lines L2 are spaced apart from each other in the first direction D1, and the second conductive lines L2 are connected to the first conductive lines L1 through the third conductive lines L3687458. For example, the first direction D1 is perpendicular to the second direction D2, but is not limited thereto. For example, the first wire L1 extends in the first direction D1. For example, in the embodiment of the present disclosure, the second wire L2 is located only in the first display region R1. In the embodiments of the present disclosure, the element extending along a certain direction is not necessarily a straight line, and may have a portion of a curved line or a broken line, for example, the extending direction of a certain element refers to a general extending tendency of the element, for example, each portion of the element does not necessarily extend along the direction.

According to the display panel provided by the embodiment of the disclosure, the structure of the first power line in the first display area is adjusted, which is equivalent to removing a part of the first power line arranged along the second direction in a common display panel, so that the first power line in the first display area is simplified, and the light transmittance of the first display area is improved.

For example, as shown in fig. 6A to 6E, the first conductive line L1 and the second conductive line L2 respectively connect two adjacent rows of pixel cells in one pixel island a1, but are not limited thereto, and in other embodiments, the pixel island a1 may further include more than two rows of pixel cells. For example, as shown in fig. 6A to 6E, the pixel island a1 includes at least two pixel cells located in two adjacent rows, and the first and second conductive lines L1 and L2 overlap the two pixel cells located in the two adjacent rows, respectively. For example, as shown in fig. 6A to 6E, the first conductive line L1 overlaps the first pixel cell 101, and the second conductive line L2 overlaps the third pixel cell 103. For example, as shown in fig. 6A to 6E, the first conductive line L1 also overlaps the second pixel cell 102, and the second conductive line L2 also overlaps the fourth pixel cell 104.

For example, as shown in fig. 6A to 6E, the plurality of second conductive lines L2 are sequentially arranged in the first direction D1. For example, as shown in fig. 6A to 6E, adjacent second conductive lines L2 are not directly connected, and a plurality of second conductive lines L2 that are not directly connected are formed by removing a portion of the first power supply line disposed in the first direction.

For example, as shown in fig. 6A to 6E, in order to improve the light transmittance of the first display region, the length of the portion of the first conductive line L1 located in the first display region R1 in the first direction D1 is greater than the length of the second conductive line L2 in the first direction D1.

For example, as shown in fig. 6A to 6E, the first power line 311 further includes a fourth conductive line L4, the fourth conductive line L4 extends along the second direction D2, the second conductive line L2 is connected to the first conductive line L1 through the fourth conductive line L4, and a length of the fourth conductive line L4 in the second direction D2 is less than or equal to a length of the third conductive line L3 in the second direction D2. In the display panel shown in fig. 6A, 6B and 6E, the length of the fourth conductive line L4 in the second direction D2 is less than the length of the third conductive line L3 in the second direction D2. In the display panel shown in fig. 6C, the length of the fourth conductive line L4 in the second direction D2 is equal to the length of the third conductive line L3 in the second direction D2.

For example, as shown in fig. 6A to 6E, in order to further improve the light transmittance of the first display region, a plurality of fourth conductive lines L4 are provided, the plurality of fourth conductive lines L4 are sequentially arranged in the second direction D2, and adjacent fourth conductive lines L4 are spaced apart from each other in the second direction D2. For example, as shown in fig. 6A, a plurality of fourth conductive lines L41 are positioned between the third conductive line L31 and the third conductive line L32, and the third conductive line L31 and the third conductive line L32 are adjacent third conductive lines L3. Fig. 6A shows three fourth conductive lines L41, but the number of the fourth conductive lines L4 positioned between the adjacent third conductive lines L3 is not limited to that shown in the drawing and may be determined as needed. Since the plurality of fourth conductive lines L4 are spaced apart from each other in the second direction D2, a portion of the first power line disposed in the second direction in a typical display panel is removed, thereby reducing wiring, optimizing a routing space, and improving light transmittance.

For example, as shown in fig. 6A to 6E, the first power line 311 further includes a fifth conductive line L5, the fifth conductive line L5 extends in the first direction D1, the fifth conductive line L5 is located in the second display region R2, the fifth conductive line L5 is located between adjacent first conductive lines L1, and the fifth conductive line L5 and the second conductive line L2 adjacent thereto are spaced apart from each other in the first direction D1. Therefore, the wiring is reduced at the boundary position between the first display region and the second display region, and the transmittance of light is improved.

In the display panel shown in fig. 6E, each pixel island includes two rows and three columns of pixel units. In the embodiment of the present disclosure, the number of the pixel units included in each pixel island and the arrangement manner of the pixel units are not limited, and the arrangement manner of the first power lines provided by the embodiment of the present disclosure may be adopted as long as the number of the pixel units included in each pixel island is greater than or equal to two rows.

As shown in fig. 6A and 6B, in the display panel, the first power line 311 further includes a plurality of sixth conductive lines L6, the sixth conductive line L6 is located in the second display region R2, and the sixth conductive line L6 extends in the second direction D2. In the second display region R2, a plurality of fifth conductive lines L5 and a plurality of sixth conductive lines L6 are disposed to cross. In the embodiment of the present disclosure, both the fifth wire L5 and the sixth wire L6 are located only in the second display region R2.

Fig. 7A is a schematic view of a display panel according to an embodiment of the disclosure. As shown in fig. 7A, the same gate line 113 connects the pixel cells in the second display region located at both sides of the first display region R1 and the pixel cells in the first display region R1 to form a row of pixel cells. The embodiment of the present disclosure does not limit the form of the first conductive line as long as it can extend from the second display region R2 to the first display region R1. The first power line in fig. 7A may also be replaced with the first power line in other embodiments of the present disclosure. Also, the extending manner of the gate line 113 is not limited to that shown in fig. 7A, as long as the gate line 113 is arranged in such a manner that the pixels in the second display region R2 are connected to the pixels in the first display region R1.

Fig. 7B is a schematic diagram of a display panel according to an embodiment of the disclosure. Compared with the display panel shown in fig. 7A, the display panel shown in fig. 7B adjusts the arrangement position of a portion of the gate lines located in the first display region. That is, in the display panel shown in fig. 7B, one gate line is disposed above and below the pixel island, respectively. In the display panel shown in fig. 7A, two gate lines are disposed under the pixel islands.

Fig. 6A to 6E, 7A, and 7B exemplify that the second wire is connected to one of two adjacent first wires, and is not directly connected to the other. In the display panel shown in fig. 6A to 6E, 7A and 7B, the fourth conductive line is in contact with one of two adjacent first conductive lines, for example, through a via hole penetrating an insulating layer.

For example, in the embodiment of the present disclosure, a row of pixel units is a pixel unit connected to the same gate line 113, and a column of pixel units is a pixel unit connected to the same data line 313. In the embodiment of the present disclosure, the first wire L1, the second wire L2, and the fifth wire L5 all extend in the row direction, and the third wire L3, the fourth wire L4, and the sixth wire L6 extend in the column direction, but the present disclosure is not limited thereto. In other embodiments, the first conductive line L1, the second conductive line L2, and the fifth conductive line L5 may extend in the column direction, the third conductive line L3, the fourth conductive line L4, and the sixth conductive line L6 may extend in the row direction, and accordingly, the second direction D2 and the first direction D1 may be replaced with each other.

Fig. 6A to 6E take the pixel island including two rows of pixel units as an example, in other embodiments, the pixel island may further include three or more rows of pixel units, in which case, the plurality of second conductive lines may be understood as second conductive lines connected to the same row of pixel units. In the case where the first conductive line L1, the second conductive line L2, and the fifth conductive line L5 all extend in the column direction, and the third conductive line L3, the fourth conductive line L4, and the sixth conductive line L6 extend in the row direction, the plurality of second conductive lines described above may be understood as second conductive lines connected to pixel cells of the same column.

Some embodiments of the present disclosure are described below in conjunction with fig. 8-25. Fig. 8 to 24 illustrate a pixel circuit of 7T1C as an example.

Fig. 8 is a schematic diagram of a pixel circuit of a display panel according to an embodiment of the disclosure. Fig. 9 is a plan view of a semiconductor pattern in a display panel according to an embodiment of the present disclosure. Fig. 10 is a plan view of a first conductive pattern layer in a display panel according to an embodiment of the present disclosure. Fig. 11 is a plan view of a second conductive pattern layer in a display panel according to an embodiment of the disclosure. Fig. 12 is a plan view of a first insulating layer in a display panel according to an embodiment of the disclosure. Fig. 13 is a plan view of a third conductive pattern layer in a display panel according to an embodiment of the disclosure. Fig. 14 is a plan view of a second insulating layer in a display panel according to an embodiment of the disclosure. Fig. 15 is a plan view of a pixel electrode layer in a display panel according to an embodiment of the present disclosure. Fig. 16 is a plan view of a pixel definition layer in a display panel according to an embodiment of the disclosure. Fig. 17 is a schematic diagram illustrating an active layer of a thin film transistor formed in a display panel according to an embodiment of the present disclosure. Fig. 18 is a schematic plan view illustrating a display panel according to an embodiment of the present disclosure after forming a second conductive pattern layer and a first insulating layer. Fig. 19 is a schematic plan view illustrating a display panel after a third conductive pattern layer is formed in the display panel according to an embodiment of the disclosure. Fig. 20 is a schematic plan view illustrating a display panel after a second insulating layer is formed according to an embodiment of the present disclosure. Fig. 21 is a schematic plan view illustrating a display panel after a pixel electrode layer is formed according to an embodiment of the present disclosure. Fig. 22 is a schematic plan view illustrating a display panel after a pixel definition is formed according to an embodiment of the disclosure. Fig. 23 is a schematic plan view illustrating adjacent pixel islands in the second direction in the first display region of the display panel according to an embodiment of the disclosure. Fig. 24 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure. Fig. 25 is a schematic cross-sectional view of a display panel according to an embodiment of the disclosure. In the embodiments of the present disclosure, for clarity of illustration, the insulating layer is shown in a form of a via hole in a plan view, and the insulating layer itself is subjected to a transparentization process.

For example, referring to fig. 8, the gate line 113 is configured to supply a SCAN signal SCAN to the pixel circuit 10. The emission control signal line 110 is configured to supply an emission control signal EM to the pixel unit P0. The DATA line 313 is configured to supply the DATA signal DATA to the pixel circuit 10, the first power line 311 is configured to supply a constant first voltage signal ELVDD to the pixel circuit 10, the second power line 312 is configured to supply a constant second voltage signal ELVSS to the pixel circuit 10, and the first voltage signal ELVDD is greater than the second voltage signal ELVSS. The initialization signal line 210 is configured to supply an initialization signal Vint to the pixel circuit 10. The initialization signal Vint is a constant voltage signal, and may have a magnitude between the first voltage signal ELVDD and the second voltage signal ELVSS, for example, but is not limited thereto, and may be less than or equal to the second voltage signal ELVSS, for example. For example, the pixel circuit outputs a driving current to drive the light emitting element 20 to emit light under the control of signals of the SCAN signal SCAN, the DATA signal DATA, the initialization signal Vint, the first voltage signal ELVDD, the second voltage signal ELVSS, the light emission control signal EM, and the like. The light emitting element 20 emits red light, green light, blue light, or white light or the like under the drive of its corresponding pixel circuit 10.

As shown in fig. 8, the pixel circuit 10 includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a first reset transistor T6, a second reset transistor T7, and a storage capacitor C1. The driving transistor T1 is electrically connected to the light emitting element 20 and outputs a driving current to drive the light emitting element 20 to emit light under the control of signals of the SCAN signal SCAN, the DATA signal DATA, the first voltage signal ELVDD, the second voltage signal ELVSS, and the like.

For example, the display panel provided by the embodiment of the present disclosure further includes: a data driving circuit and a scan driving circuit. The DATA driving circuit is configured to supply the DATA signal DATA to the pixel unit P0 according to an instruction of the control circuit; the SCAN drive circuit is configured to supply signals such as a light emission control signal EM, a SCAN signal SCAN, and a RESET control signal RESET to the pixel unit P0 in accordance with an instruction of the control circuit. For example, the control circuit includes an external Integrated Circuit (IC), but is not limited thereto. For example, the scan driving circuit is a goa (gate driver On array) structure mounted On the display panel, or a driving chip (IC) structure bound (bonded) with the display panel. For example, it is also possible to use different driving circuits to supply the emission control signal EM and the SCAN signal SCAN, respectively. For example, the display panel further includes a power supply (not shown in the figure) to supply the above-mentioned voltage signals, which may be a voltage source or a current source as needed, configured to supply the first voltage signal ELVDD, the second power voltage ELVSS, the initialization signal Vint, and the like to the pixel unit P0 through the first power line 311, the second power line 312, and the initialization signal line 210, respectively.

As shown in fig. 8, the second pole C12 of the storage capacitor C1 is electrically connected to the first power line 311, and the first pole C11 of the storage capacitor C1 is electrically connected to the second pole T32 of the threshold compensation transistor T3. The gate T20 of the data writing transistor T2 is electrically connected to the gate line 113, and the first electrode T21 and the second electrode T22 of the data writing transistor T2 are electrically connected to the data line 313 and the first electrode T11 of the driving transistor T1, respectively. The gate T30 of the threshold compensation transistor T3 is electrically connected to the gate line 113, the first pole T31 of the threshold compensation transistor T3 is electrically connected to the second pole T12 of the driving transistor T1, and the second pole T32 of the threshold compensation transistor T3 is electrically connected to the gate T10 of the driving transistor T1.

For example, as shown in fig. 8, the gate T40 of the first light emission controlling transistor T4 and the gate T50 of the second light emission controlling transistor T5 are both connected to the light emission control signal line 110.

For example, as shown in fig. 8, the first pole T41 and the second pole T42 of the first light emitting control transistor T4 are electrically connected to the first power line 311 and the first pole T11 of the driving transistor T1, respectively. The first electrode T51 and the second electrode T52 of the second light-emitting control transistor T5 are electrically connected to the second electrode T12 of the driving transistor T1 and the pixel electrode E1 (which may be an anode of an OLED) of the light-emitting element 20, respectively. The common electrode E2 (which may be a common electrode of an OLED, such as a cathode) of the light emitting element 20 is electrically connected to the second power line 312.

For example, as shown in fig. 8, the gate T60 of the first reset transistor T6 is electrically connected to the first reset control signal line 111, the first pole T61 of the first reset transistor T6 is electrically connected to the initialization signal line 210 (first initialization signal line 211), and the second pole T62 of the first reset transistor T6 is electrically connected to the gate T10 of the driving transistor T1. The gate T70 of the second reset transistor T7 is electrically connected to the second reset control signal line 112, the first pole T71 of the second reset transistor T7 is electrically connected to the initialization signal line 210 (second initialization signal line 212), and the second pole T72 of the second reset transistor T7 is electrically connected to the pixel electrode E1 of the light emitting element 20.

Fig. 9 illustrates the semiconductor pattern SCP, and fig. 10 illustrates the first conductive pattern layer LY1 with the first gate insulating layer disposed between the first conductive pattern layer LY1 and the semiconductor pattern SCP. The semiconductor pattern SCP is doped with the first conductive pattern LY1 as a mask so that a region of the semiconductor pattern SCP not covered with the first conductive pattern LY1 retains semiconductor characteristics to form a channel of the thin film transistor, and a region of the semiconductor pattern SCP covered with the first conductive pattern LY1 is silicided to form a source or a drain of the thin film transistor. The active layer ALT formed after the semiconductor pattern SCP has been partially conductorized is shown as 17.

As shown in fig. 10, the first conductive pattern layer LY1 includes a first reset control signal line 111, a second reset control signal line 112, a light emission control signal line 110, a gate line 113, and a first electrode C11 of a storage capacitor C1. Fig. 10 also shows a first portion DL11 (conductive line 114) of the first data line DL 1. Fig. 10 also shows a gate line GL0, the gate line GL0 being a portion of the gate line extending from the second display region to the first display region. For example, referring to fig. 19, in the embodiment of the present disclosure, the first reset control signal line 111 and the second reset control signal line 112 are connected.

Fig. 11 shows the second conductive pattern layer LY2 with the second gate insulating layer disposed between the second conductive pattern layer LY2 and the first conductive pattern layer LY 1. The second conductive pattern layer LY2 includes a stopper BK0, a stopper BK1, an initialization signal line 210, and a second pole C12 of the storage capacitor C1. The second pole C12 of the storage capacitor C1 has an opening OPN. The initialization signal line 210 includes a first initialization signal line 211 and a second initialization signal line 212. As shown in fig. 11, the second conductive pattern layer LY2 includes a first portion L11 and a third portion L13 of the first conductive line L1. As shown in fig. 11, a stopper BK0 extends from the first wire L1. Fig. 12 illustrates a pattern of the first insulating layer ISL1, in which dots are via holes in the first insulating layer ISL1, and the first insulating layer ISL1 includes at least one of a first gate insulating layer, a second gate insulating layer, and an interlayer insulating layer. The interlayer insulating layer is positioned between the second conductive pattern layer LY2 and the third conductive pattern layer LY 3. Referring to fig. 24 and 25, with respect to the first, second and interlayer insulating layers, the first, second and third conductive pattern layers LY1, LY2 and LY3, may be illustrated. Fig. 18 shows a schematic plan view after forming the first insulating layer ISL 1.

Fig. 13 shows the third conductive pattern layer LY3, and the third conductive pattern layer LY3 includes a third conductive line L3 (a portion of the first power line 311), a second portion DL12 of the data line (a portion of the data line 313), a first connection electrode 31a, a second connection electrode 31b, a third connection electrode 31c, and a fourth connection electrode 31 d. As shown in fig. 13, the third conductive pattern layer LY3 further includes a second portion L12 of the first conductive line L1. The first portion L11 and the third portion L13 of the first wire L1 are connected by a second portion L12.

Referring to fig. 13, 17, 18 and 19, the data line 313 is electrically connected to the first pole T21 of the data write transistor T2 through the via V4, the first power line 311 is electrically connected to the first pole T41 of the first light emission control transistor T4 through the via V3, the first power line 311 is electrically connected to the second pole C12 of the storage capacitor C1 through the via V6, and the first power line 311 is electrically connected to the conductive block BK1 through the via V5. One end of the first connection electrode 31a is electrically connected to the first initialization signal line 211 through the via V11, and the other end of the first connection electrode 31a is connected to the first pole T61 of the first reset transistor T6 through the via V12, so that the first pole T61 of the first reset transistor T6 is electrically connected to the first initialization signal line 211. One end of the second connection electrode 31b is electrically connected to the second pole T62 of the first reset transistor T6 through the via V21, and the other end of the second connection electrode 31b is electrically connected to the gate T10 of the driving transistor T1 (i.e., the first pole C11 of the storage capacitor C1) through the via V22, so that the second pole T62 of the first reset transistor T6 is electrically connected to the gate T10 of the driving transistor T1 (i.e., the first pole C11 of the storage capacitor C1). One end of the third connection electrode 31c is electrically connected to the second initialization signal line 212 through the via V31, and the other end of the third connection electrode 31c is connected to the first pole T71 of the second reset transistor T7 through the via V32, so that the first pole T71 of the second reset transistor T7 is electrically connected to the first initialization signal line 211. The fourth connection electrode 31d is electrically connected to the second diode T52 of the second light emission controlling transistor T5 through a via hole V1. The fourth connection electrode 31d may be used to be electrically connected to a pixel electrode E1 (see fig. 8) of the light emitting element 20 to be formed later.

Fig. 14 shows a second insulation layer ISL2, and the dots in fig. 14 are vias V1 in the second insulation layer ISL 2. As shown in fig. 14, the via V1 includes a via V10, a via V20, a via V30, and a via V40. Fig. 20 is a plan view after forming a second insulating layer.

Fig. 15 shows the electrode layer ETL. The electrode layer ETL includes a plurality of pixel electrodes E1. The electrode layer ETL includes a pixel electrode E11 of the first pixel unit 101, a pixel electrode E12 of the second pixel unit 102, a pixel electrode E13 of the third pixel unit 103, and a pixel electrode E14 of the fourth pixel unit 104. The pixel electrode E11 of the first pixel unit 101 is connected to the corresponding fourth connection electrode 31d through the via V10, the pixel electrode E12 of the second pixel unit 102 is connected to the corresponding fourth connection electrode 31d through the via V20, the pixel electrode E13 of the third pixel unit 103 is connected to the corresponding fourth connection electrode 31d through the via V30, and the pixel electrode E14 of the fourth pixel unit 104 is connected to the corresponding fourth connection electrode 31d through the via V40. Fig. 21 is a plan view of the display panel after the electrode layer is formed.

Referring to fig. 15 and 22, the pixel electrode E14 of the fourth pixel unit 104 includes a supplement portion E0, and an orthogonal projection of the supplement portion E0 on the substrate may cover an orthogonal projection of the common electrodes (the second pole T22 of the data write transistor T2 and the second pole T42 of the first light emission control transistor T4) of the data write transistor T2 and the first light emission control transistor T4 on the substrate, so as to improve stability and lifespan of the data write transistor T2 and the first light emission control transistor T4, so that long-term light emission stability and lifespan of the display panel may be improved.

Fig. 16 shows a plan view of the pixel defining layer. As shown in fig. 16, the pixel definition layer PDL includes a plurality of openings including an opening OPN1, an opening OPN2, an opening OPN3, and an opening OPN 4. Fig. 22 shows a schematic view of the display panel after the pixel defining layer is formed. As shown in fig. 22, the opening OPN1 exposes a portion of the pixel electrode E11, the opening OPN2 exposes a portion of the pixel electrode E12, the opening OPN3 exposes a portion of the pixel electrode E13, and the opening OPN4 exposes a portion of the pixel electrode E14. In the subsequent processes, a light emitting function layer and a common electrode are formed, and further, a light emitting element EMC is formed.

It should be noted that the transistors used in an embodiment of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics. The source and drain of the transistor used herein may be symmetrical in structure, so that there may be no difference in structure between the source and drain. In an embodiment of the present disclosure, in order to distinguish two poles of a transistor except for a gate, one of the poles is directly described as a first pole, and the other pole is directly described as a second pole, so that the first pole and the second pole of all or part of the transistors in the embodiment of the present disclosure can be interchanged as needed. For example, the first pole of the transistor according to the embodiment of the present disclosure may be a source, and the second pole may be a drain; alternatively, the first pole of the transistor is the drain and the second pole is the source.

Further, the transistors may be classified into N-type and P-type transistors according to their characteristics. The embodiments of the present disclosure are described by taking P-type transistors as examples of transistors. Based on the description and teaching of this implementation manner in the present disclosure, a person skilled in the art can easily think of an implementation manner in which at least some of the transistors in the pixel circuit of the embodiment of the present disclosure are N-type transistors, that is, N-type transistors or a combination of N-type transistors and P-type transistors, without making creative work, and therefore, these implementation manners are also within the protection scope of the present disclosure.

Fig. 8 to 25 illustrate the pixel circuit of 7T1C as an example, but the embodiments of the disclosure include but are not limited thereto. In addition, the number of thin film transistors and the number of capacitors included in the pixel circuit are not limited in the embodiments of the present disclosure. For example, in some other embodiments, the pixel circuit of the display base panel may also have a structure including another number of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, which is not limited by the embodiments of the present disclosure.

Fig. 25 is a schematic cross-sectional view of a display panel according to an embodiment of the disclosure. For example, as shown in fig. 25, the display panel includes a thin film transistor 50 and a storage capacitor C1. The thin film transistor 50 includes an active layer ATL1 on the substrate BS, a first gate insulating layer GI1 on a side of the active layer ATL1 away from the substrate BS, and a gate electrode GE on a side of the first gate insulating layer GI1 away from the substrate BS. The display panel further includes a second gate insulating layer GI2 located on a side of the gate electrode GE away from the substrate BS, an interlayer insulating layer ILD located on a side of the second gate insulating layer GI2 away from the substrate BS, and a connection electrode CNE1 located on a side of the interlayer insulating layer ILD away from the substrate BS. The active layer ATL1 includes a channel CN11, and a first pole ET1 and a second pole ET2 respectively located at both sides of the channel CN11, and the connection electrode CNE1 is connected to the second pole ET2 through a via hole penetrating through the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer ILD. The storage capacitor C1 includes a first pole C11 and a second pole C12, the first pole C11 and the gate electrode GE are located at the same layer and are both located on the first conductive pattern layer LY1, and the second pole C12 is located between the second gate insulating layer GI2 and the interlayer insulating layer ILD and is located on the second conductive pattern layer LY 2. One of the first and second poles ET1 and ET2 is a source, and the other of the first and second poles ET1 and ET2 is a drain. The connection electrode CNE1 is located at the third conductive pattern layer LY 3. The display panel further includes a passivation layer PVX and a planarization layer PLN. For example, the connection electrode CNE1 may be the fourth connection electrode 31d, and the thin film transistor 50 may be the second emission control transistor T5.

As shown in fig. 25, the display panel further includes a light emitting element EMC including a pixel electrode E1, a light emitting function layer EML, and a common electrode E2, and the pixel electrode E1 is connected to a connection electrode CNE1 through a via hole penetrating the passivation layer PVX and the planarization layer PLN. The display panel further comprises an encapsulation layer CPS comprising a first encapsulation layer CPS1, a second encapsulation layer CPS2 and a third encapsulation layer CPS 3. For example, the first and third encapsulation layers CPS1, CPS3 are inorganic material layers, and the second encapsulation layer CPS2 is an organic material layer. For example, the pixel electrode E1 is an anode, and the common electrode E2 is a cathode, but is not limited thereto.

The light emitting element EMC includes, for example, an organic light emitting diode. The light emitting function layer is positioned between the common electrode E2 and the pixel electrode E1. The light emitting functional layer EML includes at least a light emitting layer, and may further include at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer.

As shown in fig. 25, the display panel further includes a pixel defining layer PDL and spacers PS. The pixel defining layer PDL has an opening configured to define a light emitting area (light emitting area, effective light emitting area) of the pixel unit, and the spacer PS is configured to support the fine metal mask when the light emitting function layer EML is formed. Fig. 25 shows that spacers PS are provided on both opposite sides of the light emitting element, but not limited thereto.

For example, the data line is configured to input a data signal to the pixel unit, and the first power supply signal line is configured to input a first power supply voltage to the driving transistor. The second power supply signal line is configured to input a second power supply voltage to the pixel unit. The first power voltage is a constant voltage, and the second power voltage is a constant voltage, for example, the first power voltage is a positive voltage, and the second power voltage is a negative voltage, but not limited thereto. For example, in some embodiments, the first power supply voltage is a positive voltage and the second power supply signal line is grounded.

Referring to fig. 25, in an embodiment of the present disclosure, the first insulating layer ISL1 includes at least one of a first gate insulating layer GI1, a second gate insulating layer GI2, and an interlayer insulating layer ILD, and the second insulating layer ISL2 includes a planarization layer PLN.

For example, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, the passivation layer PVX, the planarization layer PLN, the pixel defining layer PDL, and the spacer PS are made of insulating materials. For example, the materials of the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, and the passivation layer PVX include at least one of SiOx and SiNx, but are not limited thereto. For example, the planarization layer PLN, the pixel defining layer PDL, and the spacer PS may be made of an organic insulating material, for example, a resin, but not limited thereto.

Referring to fig. 17, the threshold compensation transistor T3 includes a first channel CN1 and a second channel CN2, and the first channel CN1 and the second channel CN2 are connected by a conductive part CP. Referring to fig. 18, the second wire L2 further includes a connection arm L21. The threshold compensation transistor T3 is a double-gate transistor, the conductive part CP is in a floating (floating) state when the threshold compensation transistor T3 is turned off, and is susceptible to jumping due to the influence of the voltage of the peripheral line, and the voltage jumping of the conductive part CP affects the leakage current of the threshold compensation transistor T3, and further affects the light emitting luminance of the pixel cell, so that the voltage of the conductive part CP needs to be kept stable. The stopper BK0, the stopper BK, and the connecting arm L21 mentioned in the embodiments of the present disclosure all play a role of stabilizing the voltage of the conductive portion CP.

Referring to fig. 24, the connection arm L21 partially overlaps the conductive portion CP of the threshold compensation transistor T3 to form a capacitor C0, and a first gate insulating layer GI1 and a second gate insulating layer GI2 are provided between the connection arm L21 and the conductive portion CP. Fig. 24 also shows a second channel CN 2. Capacitor C0 may be referred to as a stabilization capacitor, and the connecting arm L21 and conductive portion CP are the two plates of capacitor C0. As shown in fig. 24, the gate electrode GE2 overlaps the second channel CN2 in a direction perpendicular to the substrate base plate BS. The gate GE2 is a gate of the threshold compensation transistor T3. As shown in fig. 24, the second connection electrode 31b is connected to the second pole T32 of the threshold compensation transistor T3.

Referring to fig. 19, the second wire L2 further includes a connection arm L21, the connection arm L21 and the conductive portion CP being spaced apart from each other in the third direction D3 and partially overlapping in the third direction D3 (refer to fig. 24). For example, the shape of the connecting arm L21 includes a C-shape. It should be noted that the link arm L21 may be substantially C-shaped, and of course, the link arm L21 may have another shape as long as it can function to stabilize the threshold compensating transistor T3.

For example, the third direction D3 is perpendicular to the first direction D1 and perpendicular to the second direction D2, the third direction D3 is a direction perpendicular to the substrate base plate BS, and the first gate insulating layer GI1 and the second gate insulating layer GI2 are provided between the connection arm L21 and the conductive portion CP. For example, the first direction D1 and the second direction D2 are directions parallel to the main surface of the base substrate BS, and the third direction D3 is a direction perpendicular to the main surface of the base substrate BS. Various elements are fabricated on the main surface of the base substrate BS.

Referring to fig. 11, 19 and 24, the first portion L11 includes a first sub-portion La extending in the first direction D1 and a second sub-portion Lb extending in the second direction, the second sub-portion Lb having branches extending in the first direction D1, and the stopper BK0 is a branch of the second sub-portion Lb. Referring to fig. 17, 19, and 24, the branch (the stopper BK0) of the second sub-portion Lb and the conductive portion of one pixel cell of the pixel island overlapping the first conductive line L1 are spaced apart from each other in the third direction D3 and partially overlap in the third direction D3. Referring to fig. 17, 19, and 24, the branch (the stopper BK0) of the second sub-portion Lb and the conductive portion CP of one pixel cell (the pixel cell at the upper left corner in fig. 24) of the pixel island overlapping the first conductive line L1 are spaced apart from each other in the third direction D3 and partially overlap in the third direction D3. For example, the length of the branch (the stopper BK0) in the first direction D1 is smaller than the length of the first sub-portion La in the first direction D1.

For example, referring to fig. 8, 17, 19, and 24, the pixel circuit 10 includes a first transistor and a second transistor, the first transistor being connected to the second transistor, the second transistor being connected to the light emitting element, the first transistor including a first channel CN1 and a second channel CN2, the first channel CN1 and the second channel CN2 being connected through the conductive portion CP, the second wire L2 further including a connection arm L21, the connection arm L21 being spaced apart from each other in the third direction D3 and partially overlapping in the third direction D3 with the CP of one pixel cell (the pixel cell located at the lower left corner in fig. 19) of the pixel island overlapping with the second wire L2. For example, the first transistor and the second transistor described above are a threshold value compensation transistor T3 in the pixel circuit 10 and a light emission control transistor connected to a light emitting element, respectively. The light emission controlling transistor connected to the light emitting element is, for example, the second light emission controlling transistor T5 described above. Of course, in other embodiments of the present disclosure, the stopper or the connecting arm forming the capacitor with the conductive portion CP in the first transistor in the pixel island may also take other forms, which is not limited herein.

For example, referring to fig. 19, in the embodiment of the present disclosure, the block BK0 (branch of the second sub-portion Lb) and the connecting arm L21 are both connected to the third conductive line L3 of the present column of pixel cells, and the block BK is connected to the third conductive line of the adjacent column of pixel cell columns in which the conductive portion shielded by the block BK is located. That is, as shown in fig. 19, the stopper BK0 (branch of the second sub-portion Lb), the connecting arm L21, and the stopper BK are all connected to the same third wire L3.

For example, as shown in fig. 11, the initialization signal line 210 includes a plurality of hollow areas HP, the second conductive line L2 is located in one hollow area HP and surrounded by a portion of the initialization signal line surrounding the hollow area HP, and the second conductive line L2 does not overlap with the portion of the initialization signal line surrounding the hollow area HP. That is, the second wire L2 is completely surrounded by the portion of the initialization signal line surrounding the hollowed-out area HP. In the embodiment of the disclosure, the hollow area HP corresponds to a position of a portion of the film removed when the initialization signal line 210 is manufactured.

For example, referring to fig. 11, 13, and 19, the first wire L1 includes a first portion L11 and a second portion L12, the first portion L11 of the first wire L1 is located at the same layer as the second wire L2, the second portion L12 of the first wire L1 is not located at the same layer as the second wire L2, and the second portion L12 of the first wire L1 at least partially overlaps the initialization signal line 210. Referring to fig. 11, 13 and 19, the first portion L11 of the first conductive line L1 and the second conductive line L2 are located at the second conductive pattern layer LY2, and the second portion L12 of the first conductive line L1 is located at the third conductive pattern layer LY 3.

For example, referring to fig. 11, 13 and 19, the second wire L2 is surrounded by a portion of the initialization signal line 210, and the first portion L11 of the first wire L1 is surrounded by a portion of the initialization signal line 210. Referring to fig. 11, 13 and 19, the second wire L2 is surrounded by the portion 210a of the initialization signal line 210 at the lower side, and the first portion L11 of the first wire L1 is surrounded by the portion 210b of the initialization signal line 210 at the upper side.

For example, referring to fig. 3 and 19, the data line 313 includes a first data line DL1, the first data line DL1 extends from the first display region R1 to the second display region R2, and the first data line DL1 overlaps with an orthographic projection of the third conductive line L3 on the substrate base plate BS. The arrangement mode is favorable for reducing the wiring area and improving the light transmittance.

For example, referring to fig. 13, 18, and 19, the first data line DL1 includes a first portion DL11 and a second portion DL12, the first portion DL11 of the first data line DL1 partially overlaps the third conductive line L3, the second portion DL12 of the first data line DL1 does not overlap the third conductive line L4, and the first portion DL11 of the first data line DL1 and the second portion DL12 of the first data line DL1 are located at different layers, respectively. For example, the first portion DL11 (conductive line 214) of the first data line DL1 on the left side in fig. 19 is located in the second conductive pattern layer, the second portion DL12 of the first data line DL1 on the left side is located in the third conductive pattern layer, the first portion DL11 (conductive line 114) of the first data line DL1 on the right side in fig. 19 is located in the first conductive pattern layer, and the second portion DL12 of the first data line DL1 on the right side is located in the third conductive pattern layer. For example, referring to fig. 3, 19 and 23, the first portion DL11 of the first data line DL1 is located between adjacent pixel islands a 1.

For example, referring to fig. 13 and 19, two first data lines DL1 are provided, two first data lines DL1 are respectively connected to two adjacent columns of pixel cells, and two first data lines DL1 overlap with an orthographic projection portion of the same third conductive line L3 on the substrate base BS. The arrangement mode enables the data line positioned between the pixel islands in the two adjacent columns of pixel units to be hidden under the third conducting wire, thereby reducing the wiring area and improving the light transmittance.

For example, the first wire L1 includes portions located at different layers, and the portions located at different layers are connected by a via hole penetrating the insulating layer. Referring to fig. 19, the first wire L1 includes a first portion L11, a second portion L12, and a third portion L13. The first and third portions L11 and L13 are located at the second conductive pattern layer LY2, and the second portion L12 is located at the third conductive pattern layer LY 3. The first portion L11 and the second portion L12 are connected by a via V41 penetrating through the insulating layer, and the third portion L13 and the second portion L12 are connected by a via V42 penetrating through the insulating layer. Referring to fig. 24 and 25, an interlayer dielectric layer ILD is disposed between the second conductive pattern layer LY2 and the third conductive pattern layer LY3, that is, the via V41 penetrates the interlayer dielectric layer ILD, and the via V42 penetrates the interlayer dielectric layer ILD.

For example, referring to fig. 19, a portion of the first conductive line L1 (the second portion L12) is located at the same layer as the third conductive line L3, and is located at the third conductive pattern layer LY 3. The fourth conductive line L4 is located at the same layer as the third conductive line L3, and is located at the third conductive pattern layer LY 3.

At least one embodiment of the present disclosure further provides a display device including any one of the display panels described above. For example, the display device may be a display device such as an Organic Light-Emitting Diode (OLED) display, and any product or component having a display function such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, and a navigator including the display device.

For example, in the embodiment of the present disclosure, the first conductive line L1 may include a portion located at the first conductive pattern layer and a portion located at the second conductive pattern layer, the second conductive line L2 is configured only by the portion located at the second conductive pattern layer, the third conductive line L3 is configured only by the portion located at the third conductive pattern layer, the fourth conductive line L43 is configured only by the portion located at the third conductive pattern layer, and the fifth conductive line L5 may include a portion located at the first conductive pattern layer and a portion located at the second conductive pattern layer, but is not limited thereto and may be provided as needed.

For example, referring to fig. 11 and 19, in an embodiment of the present disclosure, the second pole C12 of the storage capacitor C1 of the pixel cell P0 is a portion of the second conductive line L2 or a portion of the first conductive line L1.

The following points need to be explained:

(1) unless otherwise defined, like reference numerals refer to like meanings in the embodiments of the present disclosure and the drawings.

(2) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are referred to, and other structures may refer to general designs.

(3) In the drawings used to describe embodiments of the present disclosure, the thickness of a layer or region is exaggerated for clarity. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

(4) Features of the same embodiment of the disclosure and of different embodiments may be combined with each other without conflict.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A display panel, comprising:

a first display area;

a second display area located at least on one side of the first display area;

a plurality of pixel units located in the first display area and the second display area, the density of the pixel units of the first display area being less than the density of the pixel units of the second display area, the pixel units including pixel circuits; and

a first power line configured to supply a first voltage signal to the pixel circuit,

wherein the first power line includes a plurality of first conductive lines extending from the second display region to the first display region, a plurality of second conductive lines located at the first display region and between adjacent first conductive lines, the second conductive lines extending in a first direction, the third conductive lines extending in a second direction, the first direction crossing the second direction, and a plurality of third conductive lines extending from the second display region to the first display region, and

adjacent second conductive lines are spaced apart from each other along the first direction, and the second conductive lines are connected to the first conductive lines through the third conductive lines.

2. The display panel according to claim 1, wherein the plurality of second conductive lines are sequentially arranged in the first direction.

3. The display panel of claim 1, wherein the adjacent second conductive lines are not directly connected.

4. The display panel according to claim 1, wherein a length of a portion of the first conductive line in the first direction, which is located in the first display region, is greater than a length of the second conductive line in the first direction.

5. The display panel according to claim 1, wherein the first conductive line includes portions located at different layers, and the portions located at different layers are connected by a via penetrating an insulating layer.

6. The display panel according to claim 1, wherein the first power supply line further comprises a fourth conductive line extending in the second direction, the second conductive line being connected to the first conductive line through the fourth conductive line, a length of the fourth conductive line in the second direction being less than or equal to a length of the third conductive line in the second direction.

7. The display panel of claim 1, comprising a plurality of fourth conductive lines between adjacent third conductive lines, the plurality of fourth conductive lines being sequentially arranged along the second direction, adjacent fourth conductive lines being spaced apart from each other in the second direction.

8. The display panel according to claim 6, wherein a part of the first conductive line is located at the same layer as the third conductive line, and wherein the fourth conductive line is located at the same layer as the third conductive line.

9. The display panel according to any one of claims 1 to 8, wherein the pixel units located in the first display region constitute a plurality of pixel islands including at least two pixel units located in two adjacent rows, and the first conductive line and the second conductive line overlap the two pixel units located in the two adjacent rows, respectively.

10. The display panel according to claim 9, wherein the pixel unit further comprises a light-emitting element, wherein the pixel circuit comprises a first transistor and a second transistor, wherein the first transistor is connected to the second transistor, wherein the second transistor is connected to the light-emitting element, wherein the first transistor comprises a first channel and a second channel, wherein the first channel and the second channel are connected by a conductive portion, wherein the second wire further comprises a connection arm, wherein the connection arm and the conductive portion of one of the pixel islands which overlaps with the second wire are spaced apart from each other in a third direction which is perpendicular to the first direction and perpendicular to the second direction, and partially overlap in the third direction.

11. The display panel of claim 10, wherein the shape of the connecting arm comprises a C-shape.

12. The display panel according to claim 10, wherein the first conductive line has a branch which is spaced from and partially overlaps in the third direction with the conductive portion of one pixel cell of the pixel island which overlaps the first conductive line.

13. The display panel of any of claims 1-8, wherein the first direction is perpendicular to the second direction.

14. The display panel of claim 1, wherein the first power line further comprises a fifth conductive line extending in the first direction, the fifth conductive line being positioned in the second display region, the fifth conductive line being positioned between adjacent first conductive lines, the fifth conductive line and a second conductive line adjacent thereto being spaced apart from each other in the first direction.

15. The display panel according to claim 9, further comprising an initialization signal line configured to supply an initialization signal to the pixel circuit, wherein the second wire is surrounded by a part of the initialization signal line.

16. The display panel according to claim 15, wherein the first conductive line includes a first portion and a second portion, the first portion of the first conductive line is located at the same layer as the second conductive line, the second portion of the first conductive line is not located at the same layer as the second conductive line, and the first portion of the first conductive line is surrounded by a part of the initialization signal line.

17. The display panel of claim 16, wherein the first portion of the first conductive line has a first sub-portion extending in the first direction and a second sub-portion extending in the second direction, the second sub-portion having a branch extending in the first direction.

18. The display panel of claim 17, wherein a length of the branch in the first direction is less than a length of the first sub-section in the first direction.

19. The display panel according to claim 16, wherein the pixel unit further comprises a light emitting element, wherein the pixel circuit comprises a first transistor and a second transistor, wherein the first transistor is connected to the second transistor, wherein the second transistor is connected to the light emitting element, wherein the first transistor comprises a first channel and a second channel, wherein the first channel and the second channel are connected by a conductive portion, wherein the branch and the conductive portion of one of the pixel units overlapping with the first wire in the pixel island are spaced apart from each other in the third direction and partially overlap in the third direction, and wherein the third direction is perpendicular to the first direction and perpendicular to the second direction.

20. The display panel according to claim 19, wherein the second conductive line further comprises a connection arm that is spaced apart from and partially overlaps in a third direction with the conductive portion of one of the pixel cells in the pixel island that overlaps the second conductive line.

21. The display panel of claim 9, further comprising a substrate and data lines, wherein the data lines are configured to provide data signals to the pixel circuits, the data lines including first data lines, wherein the first data lines extend from the first display region to the second display region, the first data lines overlapping with a forward projection portion of the third conductive lines on the substrate.

22. The display panel of claim 21, wherein the first data line includes a first portion and a second portion, the first portion of the first data line partially overlaps the third conductive line, the second portion of the first data line does not overlap the third conductive line, and the first portion of the first data line and the second portion of the first data line are respectively located at different layers.

23. The display panel of claim 22, wherein adjacent pixel islands have a light-transmitting region therebetween, and the first portion of the first data line is positioned between the adjacent pixel islands.

24. The display panel according to any one of claims 21 to 23, wherein two first data lines are provided, the two first data lines are respectively connected to two adjacent columns of pixel cells, and the two first data lines overlap with an orthographic projection part of the same third conductive line on the substrate.

25. The display panel according to any one of claims 21 to 23, further comprising gate lines, wherein the gate lines are configured to supply a scan signal to a row of pixel units, the gate lines include a first gate line extending from the second display region to the first display region, and the light-transmitting region is surrounded by two adjacent first gate lines and two adjacent first data lines.

26. A display device comprising the display panel of any one of claims 1-25.