WO2021000751A1 - 锁相环电路及其设置方法、通信设备 - Google Patents

锁相环电路及其设置方法、通信设备 Download PDF

Info

Publication number
WO2021000751A1
WO2021000751A1 PCT/CN2020/097225 CN2020097225W WO2021000751A1 WO 2021000751 A1 WO2021000751 A1 WO 2021000751A1 CN 2020097225 W CN2020097225 W CN 2020097225W WO 2021000751 A1 WO2021000751 A1 WO 2021000751A1
Authority
WO
WIPO (PCT)
Prior art keywords
phase
locked loop
circuit
delay unit
main circuit
Prior art date
Application number
PCT/CN2020/097225
Other languages
English (en)
French (fr)
Inventor
刘俊
韦兆碧
王珊
段沛
雷梦毕
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Priority to US17/624,063 priority Critical patent/US11750200B2/en
Priority to EP20835431.6A priority patent/EP3989442A4/en
Publication of WO2021000751A1 publication Critical patent/WO2021000751A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
    • H03L1/02—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
    • H03L1/022—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
    • H03L1/02—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
    • H03L1/02—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
    • H03L1/04—Constructional details for maintaining temperature constant
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present invention relates to the field of communication technology, in particular to a phase-locked loop circuit and its setting method, and communication equipment.
  • the machine is a multi-channel transceiver 4G and 5G (5 th -Generation, 5th generation) communication technology is typically applied; 5G in communication, space division multiplexing (Space Division Multiple Access (SDMA) is an important example of the application of multiple input multiple output (Maximum Input Minimum Output, Massive MIMO) technology.
  • SDMA uses beamforming technology to concentrate the signal energy in a specific direction to increase spectrum utilization efficiency and reduce interference to other receivers. Beamforming has strict requirements on the phase difference between the multiple channels of the transceiver. For example, the phase difference between the multiple channels of the sub 6G 5G base station transceiver should be less than 5°.
  • the present disclosure provides a phase-locked loop circuit, a setting method thereof, and a communication device, which solves how to fundamentally realize multi-channel phase synchronization.
  • the present disclosure provides a phase-locked loop circuit, including a phase-locked loop main circuit and a phase temperature compensation circuit.
  • the phase temperature compensation circuit includes at least one phase delay unit, and at least one phase delay unit The unit is connected to the main circuit of the phase-locked loop, and the phase shift produced by the phase delay unit connected to the main circuit of the phase-locked loop with temperature changes is the same as the phase of the main circuit of the phase-locked loop with temperature changes. The offsets cancel each other out.
  • the present disclosure also provides a communication device including at least one phase-locked loop circuit as described above.
  • phase offset caused by the change is offset; thereby ensuring that the phase-locked loop circuit does not produce phase shift or phase shift in a small range with the temperature change during the working process; this way the phase-locked loop circuit is applied to multi-channel
  • the phase-locked loop circuit of each channel does not produce phase shift or phase shift in a small range with the temperature change during the working process, it can ensure that the phase difference before each channel is exhausted at any time. It may be small, so that it can better meet the needs of phase synchronization in multi-channel communication; and the phase detection and alignment control operations between the channels can be omitted, so resource utilization and energy consumption can be improved at the same time.
  • FIG. 1 is a schematic diagram of the structure of a phase-locked loop circuit according to the first embodiment of the disclosure
  • FIG. 2 is a schematic diagram of the main circuit structure of a phase-locked loop in the first embodiment of the disclosure
  • FIG. 3 is a schematic diagram of the phase delay of the main circuit of the phase-locked loop in the first embodiment of the disclosure
  • FIG. 5 is a schematic flowchart of a method for setting a phase-locked loop circuit according to the second embodiment of the disclosure
  • FIG. 7 is a first structural diagram of a phase delay unit of the second embodiment of the disclosure.
  • Fig. 8-1 is a second structural diagram of the phase delay unit of the second embodiment of the disclosure.
  • phase delay unit control module 9 is a schematic structural diagram of a phase delay unit control module according to the second embodiment of the disclosure.
  • FIG. 10 is a schematic diagram of the calibration process of the phase-locked loop circuit of the second embodiment of the disclosure.
  • 11-1 is a schematic diagram of the phase change with temperature when the phase is not compensated in the second embodiment of the disclosure
  • Figure 11-2 is a schematic diagram of under-compensation in the second embodiment of the disclosure.
  • Figure 11-3 is a schematic diagram of overcompensation in the second embodiment of the disclosure.
  • Fig. 11-4 is a schematic diagram of ideal compensation in the second embodiment of the disclosure.
  • 13-2 is a schematic diagram of K1 of the reference signal input path in application scenario 1 of the third embodiment of the disclosure.
  • 13-4 is a schematic diagram of K3 of the feedback signal transmission path in application scenario 1 of the third embodiment of the disclosure.
  • 13-5 is a schematic diagram of Kc3 of the feedback signal transmission path of the phase delay unit in the application scenario 1 of the third embodiment of the disclosure;
  • Fig. 13-6 is a schematic diagram of comparison of application scenario 1 of the third embodiment of the disclosure.
  • 13-7 is a schematic diagram of Klast in application scenario 1 of the third embodiment of the disclosure.
  • 14-1 is a schematic diagram of the structure of a phase-locked loop circuit in an application scenario two of the third embodiment of the disclosure.
  • 14-3 is a schematic diagram of K2 of the signal output path in application scenario 2 of the third embodiment of the disclosure.
  • 14-5 is a schematic diagram of Kc1 in the feedback signal transmission path of the phase delay unit in the second application scenario of the third embodiment of the disclosure;
  • 15-1 is a schematic diagram of K1 of the reference signal input path in application scenario 3 of the third embodiment of the disclosure.
  • 15-2 is a schematic diagram of K2 of the signal output path in application scenario 3 of the third embodiment of the disclosure.
  • 15-3 is a schematic diagram of K3 of the feedback signal transmission path in application scenario 3 of the third embodiment of the disclosure.
  • 15-4 is a schematic diagram of Kc1 of the feedback signal transmission path of the phase delay unit in the third application scenario of the third embodiment of the disclosure.
  • Fig. 15-5 is a schematic diagram of comparison of application scenario 3 of embodiment 3 of the disclosure.
  • 15-6 is a schematic diagram of Klast in application scenario 3 of the third embodiment of the disclosure.
  • 16-1 is a schematic diagram of the structure of a phase-locked loop circuit in an application scenario two of the third embodiment of the disclosure.
  • 16-2 is a schematic diagram of K1 of the reference signal input path in the fourth application scenario of the third embodiment of the disclosure.
  • 16-3 is a schematic diagram of K2 of the signal output path in application scenario 4 of the third embodiment of the disclosure.
  • 16-4 is a schematic diagram of K3 of the feedback signal transmission path in the fourth application scenario of the third embodiment of the disclosure.
  • 16-5 is a schematic diagram of Kc2 in the feedback signal transmission path of the phase delay unit in the fourth application scenario of the third embodiment of the disclosure.
  • 16-6 is a schematic diagram of comparison of application scenario 4 of embodiment 3 of the disclosure.
  • 16-7 is a schematic diagram of Klast in application scenario 4 of Embodiment 3 of the disclosure.
  • Figure 17 is a schematic structural diagram of a base station according to Embodiment 4 of the disclosure.
  • the phase-locked loop circuit in this embodiment includes a phase-locked loop main circuit 1 and a phase temperature compensation circuit 2.
  • the phase temperature compensation circuit 2 includes at least one phase delay unit 21, and at least one phase delay unit 21
  • the time unit 21 is connected to the main circuit of the phase-locked loop 1, and the phase shift produced by the phase delay unit 21 of the main circuit of the phase-locked loop 1 with temperature changes is the same as the phase of the main circuit of the phase-locked loop 1 with temperature changes.
  • phase-locked loop circuit does not produce phase shifts or phase shifts in a small range as the temperature changes during the working process; in this way, when the phase-locked loop circuit is applied to a multi-channel scene, due to the phase-locked loop of each channel
  • the circuit does not produce phase shift or phase shift in a small range as the temperature changes during the working process, so it can ensure that the phase difference before each channel is as small as possible at any time, which is fundamentally better It meets the needs of phase synchronization for multi-channel communication; and can omit the control operation of detecting and aligning the phases between channels, so that resource utilization and energy consumption can be improved at the same time.
  • phase temperature compensation circuit 2 can be set according to, but not limited to, the phase shift produced by the phase-locked loop main circuit 1 with temperature changes.
  • the unit 21 is connected to the main circuit 1 of the phase-locked loop, and the specific positions in the main circuit 1 of the phase-locked loop can be set flexibly.
  • the main circuit of the phase-locked loop 1 in this embodiment can be various circuits that can realize the functions of the main circuit of the phase-locked loop.
  • the following description of the present embodiment uses an example phase-locked loop main circuit 1, but it should be understood that the structure of the phase-locked loop main circuit 1 in this embodiment is not limited to the following exemplary structure.
  • the main circuit 1 of the phase-locked loop in this example includes:
  • the frequency discriminator 11 is configured to detect the phase difference and frequency difference between the external reference signal f ref and the feedback signal f b output by the programmable frequency divider 15.
  • the implementation circuit of the frequency discriminator 11 can be flexibly set; for example, in an example, the frequency discriminator 11 can be composed of two D-edge flip-flops and an AND gate;
  • the charge pump 12 is mainly set to convert the logic level representing the phase difference information output by the frequency discriminator 11 into a current signal, and charge and discharge the loop filter 13 under the action of the control switch, so that the loop filter 13
  • the voltage-controlled oscillator tuning voltage Vtune on the capacitor increases or decreases;
  • the loop filter 13 may be, but is not limited to, a passive filter in an example.
  • the loop filter 13 is set to filter out the high frequency components of the output signal of the charge pump 12, and output an approximate DC voltage Vtune, which is used as the control signal of the VCO (Voltage Controlled Oscillator); the realization circuit of the loop filter 13 It can also be set flexibly.
  • the loop filter 13 can be composed of a capacitor and a resistor.
  • the voltage controlled oscillator 14 is a circuit module that controls the output oscillation frequency through the voltage signal input by the loop filter 13.
  • the voltage-controlled oscillator 14 can convert DC power into AC power through but not limited to self-oscillation, and continuously generate AC signals, the frequency of which is controlled by the voltage-controlled voltage.
  • the programmable frequency divider 15 is set to reduce the output signal frequency of the oscillator, so that the output frequency of the oscillator is reduced to one-Nth and compared with the reference signal frequency to realize the phase-locked loop frequency multiplication function.
  • phase-locked loop main circuit 1 in FIG. 2 can be flexibly adjusted or set, and the specific implementation circuits of each module in Figure 2 can also be flexibly set.
  • phase-locked loop main circuit 1 shown in Fig. 2 When the phase-locked loop main circuit 1 shown in Fig. 2 is used by a channel, the phase-locked loop main circuit 1 will have a phase shift with temperature changes; when multiple channels each use a phase-locked loop main circuit 1, the The temperature changes, the phase difference between each channel is relatively large, can not meet the needs of phase synchronization between the channels. Therefore, in this embodiment, a corresponding number of phase delay units 21 can be connected to the corresponding position of the phase-locked loop main circuit 1 shown in FIG.
  • the phase shift is to offset the phase shift of the main phase-locked loop circuit 1 with temperature changes, so that the final output phase shift of the main phase-locked loop circuit 1 at different temperatures is 0 or slightly greater than 0, that is,
  • the output phase of the main circuit of the phase-locked loop 1 is stable within a range allowed by the phase synchronization requirements; the realization circuit is simple, easy to operate, and the circuit cost is small, and the output phase of the phase-locked loop is significantly improved with temperature characteristics; and
  • the phase-locked loop circuit provided by the embodiment is applied to multiple channels, it is not necessary to detect the phases between the channels and perform alignment control operations, so that resource utilization and energy consumption can be improved at the same time.
  • phase-temperature change slope to characterize the phase shift as an example.
  • This characteristic of phase change with temperature is called the slope of phase and temperature change in this embodiment, which is represented by the parameter K, and its unit is ps/°C.
  • K the total output phase and temperature change slope
  • Koutc the total output phase and temperature change slope Kout of the transmission path itself on the phase-locked loop main circuit 1 and the total output phase and temperature of the phase delay unit 21 connected to the phase-locked loop main circuit 1 on the transmission path
  • the change slope Koutc satisfies:
  • Klast —Kout+Koutc— ⁇ K0.
  • K0 in this embodiment can be flexibly set according to specific application scenarios and application requirements.
  • the value of K0 can be between 0ps/°C and 0.5ps/°C, and the specific value can be flexibly set according to specific needs.
  • the signal transmission phase of each module in the PLL main circuit 1 will change with temperature.
  • the PLL main circuit 1 can be divided into four parts: reference signal input path, feedforward path, and feedback signal transmission Path, signal output path.
  • the change in the transmission phase of the feedforward path with temperature will not be reflected in the final output signal of the phase-locked loop, and the negative feedback mechanism of the phase-locked loop will be calibrated from time to time.
  • the additional delay caused by the temperature change of the phase of the reference signal input path, the feedback signal transmission path, and the signal output path is represented by the first phase delay, the second phase delay, and the third phase delay, respectively.
  • the phases of the reference signal input path, the feedback signal transmission path, and the signal output path also increase with the increase of temperature, that is, the phase is linearly proportional to the temperature.
  • the phase of the phase delay unit 21 is also linearly proportional to the temperature.
  • the phase and temperature change slope of the reference signal input path, the feedback signal transmission path, and the signal output path, and the total output phase and temperature change slope of the phase delay unit currently connected to the main circuit of the phase-locked loop on the transmission path are respectively K1, K2, K3, Koutc.
  • K1 of the reference signal input path and K2 of the signal output path superimpose the final output phase temperature change
  • K3 of the feedback signal transmission path plays a subtractive effect; therefore, in this example, the main circuit 1 of the phase-locked loop
  • the total output phase and temperature change slope of the transmission path itself Kout K1+K2-K3;
  • phase and temperature change slopes of the phase delay unit 21 connected to the phase-locked loop main circuit 1 on the reference signal input path, signal output path, and feedback signal transmission path are Kc1, Kc2, and Kc2, respectively.
  • Kc3 the total output phase and temperature change slope of the phase delay unit currently connected to the main circuit of the phase-locked loop on the transmission path
  • Koutc Kc1+Kc2-Kc3.
  • Kout K1+K2-K3 is greater than 0.5
  • Klast —Kout+Koutc— ⁇ K0, when the value of K0 is small, for example, when it is a value near 0, Then the expression can also be: —Kout+Koutc— ⁇ 0.
  • Koutc is used to achieve first-order compensation for Kout, so that the final Klast output is 0 or a smaller positive or negative value.
  • phase delay unit 21 is not connected to at least one of the output paths.
  • the corresponding path may not be provided with the phase delay unit 21 or set the corresponding number of phase delay units 21 but not connected; thereby reducing the phase delay
  • the use of unit 21 improves resource utilization, reduces cost and control complexity.
  • both Kc1 and Kc2 can be set to 0, that is, the phase delay unit 21 is not connected to the reference signal input path and the signal output path (in this case, the phase delay unit 21 may not be set corresponding to these two paths. 21 or set a corresponding number of phase delay units 21 but not connected), at this time, only the phase delay unit 21 is connected to the feedback signal transmission path, and the number of phase delay units 21 connected can be determined according to The values of Kout and K0 are flexibly set.
  • K1+K2 when K1+K2 is much smaller than K3, it can also be characterized and determined by setting the corresponding adjustment threshold here.
  • Koutc can also realize the first-order compensation for Kout, so that the final output Klast is 0 or a smaller positive or negative value.
  • Kc3 can be set to 0 in an example, that is, no phase delay unit is connected to the feedback signal transmission path 21 (corresponding to this path at this time, the phase delay unit 21 may not be set or the corresponding number of phase delay units 21 may be set but not connected), thereby reducing the use of the phase delay unit 21, improving resource utilization, reducing cost and control Complexity.
  • any one of Kc1 and Kc2 can be set to 0, that is, the phase delay unit 21 is not connected to the reference signal input path or the signal output path, and at this time, it can be connected to the feedback signal transmission path.
  • the phase delay unit 21 may not be connected to the phase delay unit 21; of course, in some examples, the phase delay unit 21 may also be provided on the reference signal input path, signal output path, and feedback signal transmission path at the same time (this When the values of Kc1, Kc2, and Kc3 are all greater than 0), and the number of phase delay units 21 connected can be flexibly set according to the values of Kout and K0, as long as the value of Koutc meets the above conditions.
  • the phase-locked loop circuit may further include a phase delay unit control module 3, which is set to control the corresponding number of phase delay units according to the phase delay unit control parameters.
  • the time unit 21 is connected to the main circuit 1 of the phase-locked loop; wherein the control parameter of the phase-delay unit is determined according to the phase shift produced by the main circuit of the phase-locked loop 1 with temperature changes; for example, in an example, the need can be flexibly determined according to Kout On which of the reference signal input path, the signal output path, and the feedback signal transmission path, the phase delay unit 21 is connected. And the number of phase delay units 21 connected on each path; thus, the phase shift caused by the temperature change of the phase delay unit connected to the phase temperature compensation circuit is used for the phase-locked loop main circuit with the temperature change.
  • the generated phase shift is offset; thereby ensuring that the phase-locked loop circuit does not produce a phase shift or produce a phase shift within a small range as the temperature changes during the working process.
  • the phase-locked loop circuit provided in this embodiment is applied to a multi-channel scenario, since the phase-locked loop circuit of each channel does not produce a phase shift or produces a phase shift within a small range as the temperature changes during the working process, It can ensure that the phase difference before each channel is as small as possible at any time, so as to fundamentally better meet the needs of multi-channel communication phase synchronization; and the phase detection and alignment control operations between the channels can be omitted, Therefore, resource utilization and energy consumption can be improved at the same time.
  • this embodiment will exemplify the setting method of the phase-locked loop circuit shown in the first embodiment on the basis of the above-mentioned first embodiment. Please refer to FIG. 5, including:
  • phase delay unit control parameters include which paths need to be connected to the phase delay unit 21 and the number of phase delay units 21 connected to each path Number
  • S503 Control the corresponding number of phase delay units to be connected to the main circuit of the phase-locked loop according to the phase delay unit control parameters.
  • control parameters of the phase delay unit can include high and low levels.
  • the high and low levels are connected to the corresponding phase delay unit lock in the phase temperature compensation circuit through the control switch, so as to realize the corresponding number in the corresponding position in the simulation stage.
  • the phase delay unit can include high and low levels.
  • phase delay unit 21 and the phase delay unit control module 3 in this embodiment can be flexibly set according to requirements.
  • phase temperature compensation circuit is shown in FIG. 6, which includes a plurality of phase delay units 21, and the plurality of phase delay units 21 are connected to the circuit through transmission gate logic to form a phase temperature compensation circuit.
  • Each phase delay unit 21 can be composed of two or more stages of inverter circuits, as shown in FIG. 7. It can also be composed of circuits such as transmission gate unit, RC delay unit, simple resistance unit, etc. Please refer to Figure 8-1, Figure 8-2 and Figure 8-3 for several composition methods; of course, other circuits can also be used Structure realization.
  • the structure of the phase delay unit control module 3 is shown in FIG. 9, which includes a decoding circuit and a transmission gate control logic circuit.
  • the decoding circuit can input signals such as v1, v2...vn, etc. Converted into 2 n high and low level control signals such as ctrl1, ctrl2...ctrl2 n , these control signals are connected to the transmission gate control logic directly or after passing through an inverter to control the phase delay unit 21 of the phase temperature compensation circuit to access PLL main circuit.
  • the calibration process provided in this embodiment may include:
  • the final phase offset Klast it is determined that it is necessary to increase or decrease the number m of phase delay units connected to the main circuit of the phase-locked loop, and correspondingly increase m phase delay units to be connected to the main circuit of the phase-locked loop, or from the current connection In the phase delay unit of the main circuit of the phase-locked loop, m phase delay units 21 are disconnected.
  • the above-mentioned calibration process may be, but not limited to, performing test calibration during the chip factory stage.
  • the following description of the present embodiment is based on the process of testing and calibrating the chip at the factory stage, as shown in Figure 10, including:
  • S1002 —Klast— ⁇ K0? (That is, whether —Klast— is less than or equal to K0); if yes, go to S1003; otherwise, go to S1004.
  • S1005 Decrease the corresponding number of phase delay units connected on the reference signal input path and/or signal output path according to the —Klast— value; or increase the corresponding number of phase delay units connected on the feedback signal transmission path , And then go to S1001.
  • S1006 Add a corresponding number of phase delay units to the reference signal input path and/or signal output path according to the —Klast— value; or reduce the corresponding number of phase delay units to be connected to the feedback signal transmission path ; Then go to S1001.
  • the calibration process shown in FIG. 10 can be performed.
  • the Klast of the current phase of the phase-locked loop circuit can be tested separately at high and low temperatures, and then judge whether the —Klast— value is small enough and meet the application requirements, if it is satisfied, the calibration ends, if not, it is further judged whether the Klast value is greater than 0.
  • the number of phase delay units connected to the reference signal input path and/or output path should be appropriately reduced according to the —Klast— value, or the number of phase delay units connected to the feedback signal transmission path should be increased; if Klast If the value is less than 0, increase the number of phase delay units on the reference signal input path and/or output path according to the value of —Klast—, or reduce the number of phase delay units on the feedback signal transmission path; then repeat the above verification steps until —Klast— value meets the requirements.
  • a phase-locked loop circuit for a phase-locked loop circuit, based on the phase and temperature change slope corresponding to the highest temperature and lowest temperature interval in its working environment, a phase-locked loop circuit can be obtained through the process shown in FIG. 5 and FIG. 10 A fixed set of phase delay unit control parameters.
  • the phase delay unit control parameters include which paths need to be connected to the phase delay unit and the number of phase delay units to be connected to each path.
  • the phase delay unit control module can control the corresponding number of phase delay units to be connected to the corresponding path based on the fixed phase delay unit control parameter, and it can be unchanged after leaving the factory.
  • a phase-locked loop circuit can be divided into multiple temperature ranges based on the maximum temperature and minimum temperature in its working environment, and a set of phases corresponding to each temperature range can be obtained based on the test results.
  • Delay unit control parameters that is, a set of phase delay unit control parameters corresponding to a temperature range; in the working process, the phase delay unit control module can obtain the current temperature, and determine that the current temperature falls into another target temperature During the interval, based on the phase delay unit control parameter corresponding to the target temperature interval, the corresponding number of phase delay units are dynamically controlled to be connected on the corresponding path.
  • Klast is a smaller value greater than 0, and the final output phase of the phase-locked loop circuit slightly increases with the increase in temperature;
  • Klast is a small value less than 0, and the final output phase of the phase-locked loop circuit decreases slightly with the increase of temperature;
  • Klast is a value equal to 0.
  • the increase in the phase delay of the feedback signal transmission path of the phase-locked loop circuit will cause the output phase delay of the phase-locked loop circuit to decrease
  • the inherent characteristics can be simulated and off-line calibration.
  • phase delay unit (also can be connected to the phase delay unit according to demand); the output phase of the connected phase delay unit increases with the increase of temperature, because the phase delay of the reference signal input path of the phase-locked loop circuit will increase
  • the simulation calibration and offline calibration shown in Figure 5 and Figure 10 can be used to control the corresponding number of phase delay units to access the reference signal input path through the phase delay unit control module to achieve the adjustment of the coefficient Kc1 .
  • the signal output path and feedback signal transmission path are currently not connected to the phase delay unit (The phase delay unit can also be connected according to demand); the output phase of the connected phase delay unit increases with the increase of temperature, and the increase of the phase delay of the reference signal input path of the phase locked loop circuit will cause the phase locked loop circuit
  • the inherent characteristics of increased output phase delay can be simulated and offline calibration.
  • the simulation calibration and offline calibration shown in Figure 5 and Figure 10 can be used to control the corresponding number of phase delay units to access the reference signal input path through the phase delay unit control module to achieve the adjustment of the coefficient Kc1 .
  • the comparison chart of K1, K2, K3, Kc1 is shown in Figure 15-5, and the Klast obtained after offsetting is shown in Figure 15-6 (Schematic diagram of over compensation) as shown.
  • the output phase of the phase-locked loop decreases slightly as the temperature rises.
  • phase delay unit (also can be connected to the phase delay unit according to demand); the output phase of the connected phase delay unit increases with the increase of temperature, because the phase delay of the reference signal input path of the phase-locked loop circuit will increase
  • the simulation calibration and offline calibration shown in Figure 5 and Figure 10 can be used to control the corresponding number of phase delay units to access the signal output path through the phase delay unit control module to achieve the adjustment of the coefficient Kc2.
  • the communication device may be, but is not limited to, a base station or various transceivers, which includes at least one phase-locked loop circuit shown in the foregoing embodiments.
  • the communication device adopts multi-channel communication, one phase-locked loop circuit can be used for one channel, or one phase-locked loop circuit can be shared by multiple channels.
  • the base station in this embodiment uses a communication device as a base station for illustration.
  • the base station in this embodiment may be a cabinet macro base station, a distributed base station or a multi-mode base station.
  • the base station in this example includes a baseband unit (Building Baseband Unit, BBU) 171, a radio remote unit (RRU) 172, and an antenna 173, among which:
  • BBU Building Baseband Unit
  • RRU radio remote unit
  • the baseband unit 171 is responsible for centralized control and management of the entire base station system, completes uplink and downlink baseband processing functions, and provides physical interfaces with radio frequency units and transmission networks to complete information exchange.
  • the baseband unit 171 may include a baseband processing unit 1712, a main control unit 1711, a transmission interface unit 1713, and the like.
  • the main control unit 1711 mainly implements baseband unit control management, signaling processing, data transmission, interactive control, system clock provision and other functions;
  • the baseband processing unit 1712 is set to complete baseband protocol processing such as signal encoding and modulation, resource scheduling, and data encapsulation.
  • the transmission interface unit 1713 is responsible for providing the transmission interface connected to the core network.
  • the above-mentioned logical function units can be distributed on different physical boards, or integrated on the same board.
  • the baseband unit 171 can adopt a baseband master control integrated type, or a baseband master control separated type.
  • the baseband master control integrated type the master control, transmission, and baseband integrated design, that is, the baseband processing unit, the master control unit, and the transmission interface unit are integrated on a physical board.
  • the architecture has higher reliability and lower cost. Delay, higher resource sharing and scheduling efficiency, while lower power consumption.
  • the baseband processing unit and the master control unit are distributed on different boards, corresponding to the baseband board and the master control board.
  • the separated architecture supports free combination between boards and facilitates flexible expansion of the baseband. Specific settings can be flexibly adopted according to requirements.
  • the remote radio unit 172 communicates with the BBU through the baseband radio frequency interface to complete the conversion between the baseband signal and the radio frequency signal.
  • an exemplary radio remote unit 172 mainly includes an interface unit 1721, an uplink signal processing unit 1724, a downlink signal processing unit 1722, a power amplifier unit 1723, a low noise amplifier unit 1725, a duplexer unit 1726, etc. Form the downlink signal processing link and the uplink signal processing link.
  • the interface unit 1721 provides a fronthaul interface with the baseband unit to receive and send baseband IQ signals;
  • the downlink signal processing unit 1722 completes signal processing functions such as signal up-conversion, digital-to-analog conversion, and radio frequency modulation;
  • the uplink signal processing unit 1724 mainly completes Signal filtering, mixing, analog-to-digital conversion, down-conversion and other functions;
  • the power amplifier unit 1723 is set to amplify the downlink signal and then sent through the antenna 173;
  • the low-noise amplifier unit 1725 is set to amplify the uplink signal received by the antenna 173 and send it
  • the uplink signal processing unit 1724 is processed;
  • the duplexer unit 1726 supports multiplexing of received and received signals and filters the received and received signals.
  • the base station in this embodiment can also adopt a CU (Central Unint, Central Unit)-DU (Distributed Unit) architecture, where DU is a distributed access point and is responsible for completing the underlying baseband protocol. And radio frequency processing function, CU is the central unit, responsible for processing high-level protocol functions and centralized management of multiple DUs. CU and DU jointly complete the baseband and radio frequency processing functions of the base station.
  • CU Central Unint, Central Unit
  • DU distributed access point and is responsible for completing the underlying baseband protocol.
  • radio frequency processing function CU is the central unit, responsible for processing high-level protocol functions and centralized management of multiple DUs.
  • CU and DU jointly complete the baseband and radio frequency processing functions of the base station.
  • communication media usually contain computer-readable instructions, data structures, computer program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium. Therefore, the present invention is not limited to any specific combination of hardware and software.
  • the phase-locked loop circuit includes a phase-locked loop main circuit and a phase temperature compensation circuit.
  • the phase temperature compensation circuit can be set according to the phase shift produced by the phase-locked loop main circuit with temperature changes.
  • At least one phase delay unit is connected to the main circuit of the phase-locked loop, and the phase shift caused by the temperature change of the phase-delay unit connected to the phase temperature compensation circuit is used to correct the phase deviation of the main circuit of the phase-locked loop with the temperature change.
  • phase-locked loop circuit does not produce phase shift or phase shift in a small range as the temperature changes during the working process; in this way, when the phase-locked loop circuit is applied to a multi-channel scene, because each channel The phase-locked loop circuit in the working process does not produce phase shift or phase shift in a small range as the temperature changes, so it can ensure that the phase difference before each channel is as small as possible at any time, thus fundamentally It better meets the needs of phase synchronization for multi-channel communication; and can omit phase detection and alignment control operations between channels, so resource utilization and energy consumption can be improved at the same time.

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

本公开提供一种锁相环电路及其设置方法、通信设备，其中，锁相环电路包括：锁相环主体电路以及相位温度补偿电路，可根据锁相环主体电路随温度变化所产生的相位偏移，设置相位温度补偿电路的至少一个相位延时单元接入锁相环主体电路，利用接入相位温度补偿电路的相位延时单元随温度变化所产生的相位偏移，对锁相环主体电路随温度变化所产生的相位偏移进行抵消；从而保证锁相环电路在工作过程中随着温度的变化不产生相位偏移或在很小范围内产生相位偏移；应用于多通道通信时，由于各通道的锁相环电路随温度的变化不产生相位偏移或在很小范围内产生相位偏移，因此可保证各通道之前的相位差异在任何时刻都尽可能小，从根本上满足同步的需求。

Description

锁相环电路及其设置方法、通信设备 技术领域
本发明涉及通信技术领域，尤其涉及一种锁相环电路及其设置方法、通信设备。
背景技术
且随着通信技术的发展，多阵列天线基站、多收发通道整机是4G以及5G(5 th-Generation，第5代)通讯技术中的典型应用；在5G通信中，空分复用(Space Division Multiple Access，SDMA)是多输入多输出(Maximum Input Minimum Output，Massive MIMO)技术应用的一个重要例子。SDMA使用波束形成beamforming技术使信号能量集中在特定的方向传播，从而增大频谱利用效率，减小对其它接收机的干扰。beamforming对收发信机多通道之间信号的相位差异有着严苛的要求，例如sub 6G的5G基站收发信机多通道间的相位差异应小于5°。由于受成本及单板面积等限制，目前一般一个通道对应使用一个锁相环电路，由于锁相环电路具有随着温度变化而产生相位偏移的特性，导致多个通道之间的相位偏差随着温度变化增大。这对该问题，为满足多通道之间的相位差异小于设定值(例如5°)的要求，目前的做法是无线基站系统采用一系列相位检测及调整措施来减小通道间的相位误差，进而对齐多通道信号的相位；例如每间隔30分钟进行一次相位检测及对齐控制，这种相位检测对齐处理方式需要占用大量的系统资源以及产生较大的功耗，且也不能保证在检测时间间隔内多个通道之间的相位差异小于设定值的要求。因此，如何从根本上保证多通道相位同步是基站应用的一大技术瓶颈。
发明内容
本公开提供的一种锁相环电路及其设置方法、通信设备，解决如何从根本上实现多通道相位同步。
为解决上述技术问题，本公开提供一种锁相环电路，包括锁相环主体电路以及相位温度补偿电路，所述相位温度补偿电路包括至少一个相位延时单元，且至少一个所述相位延时单元接入所述锁相环主体电路，接入所述锁相环主体电路的相位延时单元随温度变化所产生的相位偏移，与所述锁相环主体电路随温度变化所产生的相位偏移相互抵消。
为解决上述技术问题，本公开还提供一种如上所述的锁相环电路设置方法，包括：通过仿真得到所述锁相环主体电路随温度变化所产生的相位偏移；根据所述相位偏移确定相位延时单元控制参数；根据所述相位延时单元控制参数控制相应个数的所述相位延时单元接入所述锁相环主体电路。
为解决上述技术问题，本公开还提供一种通信设备，包括至少一个如上所述的锁相环电路。
根据本公开提供的锁相环电路及其设置方法、通信设备，锁相环电路包括锁相环主体电路以及相位温度补偿电路，可根据锁相环主体电路随温度变化所产生的相位偏移，设置相位温度补偿电路的至少一个相位延时单元接入锁相环主体电路，利用接入相位温度补偿电路的相位延时单元随温度变化所产生的相位偏移，对锁相环主体电路随温度变化所产生的相位偏移进行抵消；从而保证锁相环电路在工作过程中随着温度的变化不产生相位偏移或在很小范围内产生相位偏移；这样锁相环电路应用到多通道场景时，由于各通道的锁相环电路在工作过程中随着温度的变化不产生相位偏移或在很小范围内产生相位偏移，因此可保证各通道之前的相位差异在任何时刻都尽可能小，从而从根本上更好的满足多通道通信相位同步的需求；且可省略对各通道之间的相位进行检测以及对齐的控制操作，因此可同时 提升资源利用率以及节省能耗。
本发明其他特征和相应的有益效果在说明书的后面部分进行阐述说明，且应当理解，至少部分有益效果从本发明说明书中的记载变的显而易见。
附图说明
图1为本公开实施例一的锁相环电路结构示意图；
图2为本公开实施例一的锁相环主体电路结构示意图；
图3为本公开实施例一的锁相环主体电路的相位延时示意图；
图4为本公开实施例一的另一锁相环电路结构示意图；
图5为本公开实施例二的锁相环电路的设置方法流程示意图；
图6为本公开实施例二的相位温度补偿电路结构示意图；
图7为本公开实施例二的相位延时单元结构示意图一；
图8-1为本公开实施例二的相位延时单元结构示意图二；
图8-2为本公开实施例二的相位延时单元结构示意图三；
图8-3为本公开实施例二的相位延时单元结构示意图四；
图9为本公开实施例二的一种相位延时单元控制模块结构示意图；
图10为本公开实施例二的锁相环电路的校准过程示意图；
图11-1为本公开实施例二的未补偿时的相位随温度变化示意图；
图11-2为本公开实施例二的欠补偿示意图；
图11-3为本公开实施例二的过补偿示意图；
图11-4为本公开实施例二的理想补偿示意图；
图12为本公开实施例二的欠补偿与未补偿的对比示意图；
图13-1为本公开实施例三应用场景一的锁相环电路结构示意图；
图13-2为本公开实施例三应用场景一的参考信号输入路径之K1示意图；
图13-3为本公开实施例三应用场景一的信号输出路径之K2示意图；
图13-4为本公开实施例三应用场景一的反馈信号传输路径之K3示意图；
图13-5为本公开实施例三应用场景一的相位延时单元在反馈信号传输路径之Kc3示意图；
图13-6为本公开实施例三应用场景一的比较示意图；
图13-7为本公开实施例三应用场景一的Klast示意图；
图14-1为本公开实施例三应用场景二的应用场景一锁相环电路结构示意图；
图14-2为本公开实施例三应用场景二的参考信号输入路径之K1示意图；
图14-3为本公开实施例三应用场景二的信号输出路径之K2示意图；
图14-4为本公开实施例三应用场景二的反馈信号传输路径之K3示意图；
图14-5为本公开实施例三应用场景二的相位延时单元在反馈信号传输路径之Kc1示意图；
图14-6为本公开实施例三应用场景二的比较示意图；
图14-7为本公开实施例三应用场景二的Klast示意图；
图15-1为本公开实施例三应用场景三的参考信号输入路径之K1示意 图；
图15-2为本公开实施例三应用场景三的信号输出路径之K2示意图；
图15-3为本公开实施例三应用场景三的反馈信号传输路径之K3示意图；
图15-4为本公开实施例三应用场景三的相位延时单元在反馈信号传输路径之Kc1示意图；
图15-5为本公开实施例三应用场景三的比较示意图；
图15-6为本公开实施例三应用场景三的Klast示意图；
图16-1为本公开实施例三应用场景二的应用场景一锁相环电路结构示意图；
图16-2为本公开实施例三应用场景四的参考信号输入路径之K1示意图；
图16-3为本公开实施例三应用场景四的信号输出路径之K2示意图；
图16-4为本公开实施例三应用场景四的反馈信号传输路径之K3示意图；
图16-5为本公开实施例三应用场景四的相位延时单元在反馈信号传输路径之Kc2示意图；
图16-6为本公开实施例三应用场景四的比较示意图；
图16-7为本公开实施例三应用场景四的Klast示意图；
图17为本公开实施例四的基站结构示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，下面通过具体 实施方式结合附图对本公开作进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
实施例一：
针对由于锁相环电路具有随着温度变化而产生相位偏移的特性，导致使用多个锁相环电路的多个通道随着温度的变化，通道之间的相位偏差也逐渐增大的问题；本公开提供了一种能从根本上实现多通道的相位同步锁相环电路。请参见图1所示，本实施例中的锁相环电路包括锁相环主体电路1以及相位温度补偿电路2，其中相位温度补偿电路2包括至少一个相位延时单元21，且至少一个相位延时单元21接入锁相环主体电路1，接入锁相环主体电路1的相位延时单元21随温度变化所产生的相位偏移，与锁相环主体电路1随温度变化所产生的相位偏移相互抵消。从而保证锁相环电路在工作过程中随着温度的变化不产生相位偏移或在很小范围内产生相位偏移；这样锁相环电路应用到多通道场景时，由于各通道的锁相环电路在工作过程中随着温度的变化不产生相位偏移或在很小范围内产生相位偏移，因此可保证各通道之前的相位差异在任何时刻都尽可能小，从而从根本上更好的满足多通道通信相位同步的需求；且可省略对各通道之间的相位进行检测以及对齐的控制操作，因此可同时提升资源利用率以及节省能耗。
应当理解的是，在本实施例的一些应用场景中，可以根据但不限于锁相环主体电路1随温度变化所产生的相位偏移，设置相位温度补偿电路2的相应个数的相位延时单元21接入锁相环主体电路1，且在锁相环主体电路1中具体设置的位置也都可灵活设定。
应当理解的是，本实施例中的锁相环主体电路1可以为各种能实现锁相环主体电路功能的各种电路。为了便于理解，本实施例下面以一种示例的锁相环主体电路1进行说明，但应当理解的是本实施例中锁相环主体电 路1的结构并不限于下面示例的结构。
请参见图2所示，本示例中的锁相环主体电路1包括：
鉴频鉴相器11，设置为检测外部参考信号f ref和可编程分频器15输出的反馈信号f b之间的相位差和频率差。鉴频鉴相器11的实现电路可以灵活设置；例如一种示例中，鉴频鉴相器11可由两个D边缘触发器和一个与门构成；
电荷泵12，主要设置为将鉴频鉴相器11输出的代表相位差信息的逻辑电平转化为电流信号，在控制开关的作用下对环路滤波器13进行充放电，使得环路滤波器13电容上的压控振荡器调谐电压Vtune升高或者降低；
环路滤波器13，一种示例中可为但不限于无源滤波器。环路滤波器13设置为滤除电荷泵12输出信号的高频分量，输出一个近似直流电压Vtune，作为VCO(Voltage Controlled Oscillator，压控振荡器)的控制信号；环路滤波器13的实现电路也可以灵活设置，例如一种示例中，环路滤波器13可由电容和电阻组成。
压控振荡器14，为通过环路滤波器13输入的电压信号控制输出振荡频率的电路模块。在一种示例中，压控振荡器14可通过但不限于自激振荡的方式，将直流电能转换为交流电能，源源不断的产生交流信号，其频率值由压控电压控制。
可编程分频器15，设置为降低振荡器的输出信号频率，方便振荡器输出频率缩小到N分之一之后与参考信号频率相比较，实现锁相环倍频功能。
应当理解的是，图2中锁相环主体电路1的结构可以灵活调整或设置，且图2中各模块的具体实现电路也都可灵活设置。
图2所示的锁相环主体电路1在被通道应用时，锁相环主体电路1随着温度变化而产生相位偏移；当多条通道各自使用一个锁相环主体电路1 时，随着温度的变化，各通道之间的相位差异较大，不能满足通道之间相位同步的需求。因此，在本实施例中，可在图2所示的锁相环主体电路1的相应位置接入对应个数的相位延时单元21，利用接入的相位延时单元21随温度变化而产生相位偏移，对锁相环主体电路1随温度变化而产生相位偏移进行抵消，从而使得锁相环主体电路1在不同温度下最终输出的相位偏移为0或略微大于0，也即使得锁相环主体电路1的输出相位稳定在一个符合相位同步需求所允许的范围内；实现电路简单，易操作性强，电路代价小，对锁相环输出相位随温度变化特性改善明显；且本实施例提供的锁相环电路应用于多通道时，不需要对通道之间的相位进行检测以及进行对齐控制操作，因此还可同时提升资源利用率以及节省能耗。
经试验研究，锁相环主体电路1中各部分的相位与温度之间的整体线性比例关系，因此为了便于理解，本实施例下面以相位温度变化斜率表征相位偏移情况为示例进行说明。这种相位随温度变化的特性本实施例称之为相位与温度变化斜率，用参数K来表示，其单位为ps/℃。在本示例中，锁相环主体电路1上的传输路径自身的总输出相位与温度变化斜率Kout与接入锁相环主体电路1的相位延时单元21在传输路径上的总输出相位与温度变化斜率Koutc之间满足：
Kout的值为负时，Koutc的值为正，Kout的值为正时，Koutc的值为负，且Kout与Koutc之和的绝对值小于等于阈值K0；这样可以保证通过接入锁相环主体电路1的相位延时单元21的补偿之后，锁相环电路最终的相位与温度变化斜率Klast维持在0左右，也即：
Klast＝︱Kout+Koutc︱≤K0。
应当理解的是，本实施例中K0的取值可以根据具体应用场景和应用需求灵活设置。例如，K0的取值可介于0ps/℃到0.5ps/℃之间，具体取值 可根据具体需求灵活设置。
根据上述分析可知，锁相环主体电路1中各模块的信号传输相位会随着温度变化，锁相环主体电路1主要可分为四个部分：参考信号输入路径、前馈路径、反馈信号传输路径、信号输出路径。其中前馈路径传输相位随温度变化不会体现体现在锁相环最终输出信号上，锁相环自身的负反馈机理会将其时时校准。如图3所示，参考信号输入路径、反馈信号传输路径、信号输出路径的相位随温度变化造成的额外延时分别用第一相位延时、第二相位延时，第三相位延时来表示，参考信号输入路径、反馈信号传输路径、信号输出路径的相位也都随着温度的升高而升高，也即相位与温度成线性正比关系。相位延时单元21的相位与温度之间也成线性正比关系。对应的，参考信号输入路径、反馈信号传输路径、信号输出路径的相位与温度变化斜率以及当前接入锁相环主体电路的相位延时单元在传输路径上的总输出相位与温度变化斜率分别为K1、K2、K3、Koutc。
在本实施例中，参考信号输入路径的K1与信号输出路径的K2对最终输出相位温度变化起叠加作用，反馈信号传输路径的K3起相减作用；因此在本示例中锁相环主体电路1传输路径自身的总输出相位与温度变化斜率Kout＝K1+K2-K3；
相应的，在本实施例中设接入锁相环主体电路1的相位延时单元21在参考信号输入路径、信号输出路径以及反馈信号传输路径上的相位与温度变化斜率分别为Kc1、Kc2、Kc3，当前接入锁相环主体电路的相位延时单元在传输路径上的总输出相位与温度变化斜率Koutc＝Kc1+Kc2-Kc3。
Kout的值为负时，Koutc的值为正，Kout的值为正时，Koutc的值为负，从而Kout与Koutc之间相互抵消。
例如，在一种场景中，K1+K2比K3大的较多时，此处可通过设置对 应的调整阈值，当K1+K2比K3大的部分大于等于该调整阈值时，例如大于0.5，Kout＝K1+K2-K3大于0.5，此时Koutc＝Kc1+Kc2-Kc3则需要为负数，且Klast＝︱Kout+Koutc︱≤K0，当K0的取值较小，例如为0附近的取值时，则该表达式还可为：︱Kout+Koutc︱≈0。在本应用场景中，Kc1+Kc2小于Kc3，从而使得Koutc的取值为负，此时Klast＝Kout+Koutc。例如一种示例中假设Kout＝0.7，Koutc＝-0.5，则Klast＝0.7+(-0.5)＝0.2；又例如另一种示例中，假设Kout＝0.7，Koutc＝-0.7，则Klast＝0.7+(-0.7)＝0，此时为最佳的效果；又例如另一种示例中，假设Kout＝0.7，Koutc＝-0.8，则Klast＝0.7+(-0.8)＝-0.1。这样通过Koutc对Kout实现一阶补偿，使得最终输出的Klast为0或为一个较小的正值或负值。
在本应用场景中，Kout为正时，也即Kout为大于0且需要进行补偿的值时，一种示例中可设置Kc1、Kc2中的至少一个为0，也即在参考信号输入路径和信号输出路径中的至少一个路径上不接入相位延时单元21，此时对应该路径可不设置相位延时单元21或设置相应个数的相位延时单元21但不接入；从而减少相位延时单元21的使用，提升资源利用率，降低成本和控制的复杂程度。在另一些示例中，可设置Kc1、Kc2都为0，也即在参考信号输入路径和信号输出路径上都不接入相位延时单元21(此时对应这两个路径可不设置相位延时单元21或设置相应个数的相位延时单元21但不接入)，此时则仅在反馈信号传输路径上接入相位延时单元21，且所接入相位延时单元21的个数可根据Kout以及K0的取值灵活设定。
又例如，在另一种场景中，K1+K2比K3小的较多时，此处也可通过设置对应的调整阈值进行表征确定，当K3比K1+K2大的部分大于等于该调整阈值，例如大于1，则Kout＝K1+K2-K3小于-1，此时Koutc＝Kc1+Kc2-Kc3则需要为正，且Klast＝︱Kout+Koutc︱≤K0，当K0 的取值较小，例如为0附近的取值时，则该表达式还可为：︱Kout︱-︱Koutc︱≈0。在本应用场景中，Kc1+Kc2大于Kc3，从而使得Koutc的取值为正，此时Klast＝Kout+Koutc。例如一种示例中假设Kout＝-1，Koutc＝0.8，则Klast＝-1+0.8＝-0.2；又例如另一种示例中，假设Kout＝-1，Koutc＝1，则Klast＝-1+1＝0，此时为最佳的效果；又例如另一种示例中，假设Kout＝-1，Koutc＝1.1，则Klast＝-1+1.1＝0.1。这样通过Koutc也能实现对Kout进行一阶补偿，使得最终输出的Klast为0或为一个较小的正值或负值。
在本应用场景中，Kout为负时，也即Kout为小于0且需要进行补偿的值时，一种示例中可设置Kc3为0，也即在反馈信号传输路径上不接入相位延时单元21(此时对应这个路径可不设置相位延时单元21或设置相应个数的相位延时单元21但不接入)，从而减少相位延时单元21的使用，提升资源利用率，降低成本和控制的复杂程度。在另一些示例中，可设置Kc1和Kc2中的任意一个为0，也即在参考信号输入路径或信号输出路径上不接入相位延时单元21，此时在反馈信号传输路径上可接入相位延时单元21，也可不接入相位延时单元21；当然，在一些示例中，还可同时在参考信号输入路径、信号输出路径和反馈信号传输路径上都设置相位延时单元21(此时Kc1、Kc2、Kc3的取值都大于0)，且所接入相位延时单元21的个数可根据Kout以及K0的取值灵活设定，只要满足Koutc的取值符合上述条件即可。
根据上述分析可知，本实施例中，为消除相位偏移，锁相环主体电路1所需接入的相位延时单元21个数，以及相位延时单元21在锁相环主体电路1中接入的位置，可以根据具体应用场景和需求灵活设置。因此，请参见图4所示，在本实施例的一些示例中，锁相环电路还可包括相位延时单元控制模块3，设置为根据相位延时单元控制参数，控制相应个数的相 位延时单元21接入锁相环主体电路1；其中相位延时单元控制参数根据锁相环主体电路1随温度变化所产生的相位偏移确定；例如，一种示例中，可根据Kout灵活确定需要在参考信号输入路径、信号输出路径和反馈信号传输路径中的哪些路径上接入相位延时单元21。以及在各路径上接入的相位延时单元21的个数；从而利用接入相位温度补偿电路的相位延时单元随温度变化所产生的相位偏移，对锁相环主体电路随温度变化所产生的相位偏移进行抵消；进而保证锁相环电路在工作过程中随着温度的变化不产生相位偏移或在很小范围内产生相位偏移。本实施例提供的锁相环电路应用到多通道场景时，由于各通道的锁相环电路在工作过程中随着温度的变化不产生相位偏移或在很小范围内产生相位偏移，因此可保证各通道之前的相位差异在任何时刻都尽可能小，从而从根本上更好的满足多通道通信相位同步的需求；且可省略对各通道之间的相位进行检测以及对齐的控制操作，因此可同时提升资源利用率以及节省能耗。
实施例二：
为了便于理解，本实施例下面在上述实施例一基础上，对实施例一所示的锁相环电路的设置方法进行示例说明，请参见图5所示，包括：
S501：通过仿真得到锁相环主体电路1随温度变化所产生的相位偏移。
例如，一种示例中，可基于采集到的数据仿真得到参考信号输入路径、反馈信号传输路径、信号输出路径的相位与温度变化斜率K1、K2、K3，从而得到锁相环主体电路1传输路径自身的总输出相位与温度变化斜率Kout＝K1+K2-K3。
S502：根据得到的相位偏移确定相位延时单元控制参数。
例如一种示例中，可根据Kout＝K1+K2-K3确定需要在参考信号输入路径、信号输出路径和反馈信号传输路径中的哪些路径上接入相位延时单元21；以及在各路径上接入的相位延时单元21的个数；也即一种示例中 相位延时单元控制参数包括需要在哪些路径上接入相位延时单元21以及在各路径上接入的相位延时单元21的个数
S503：根据相位延时单元控制参数控制相应个数的相位延时单元接入锁相环主体电路。
例如可通过相位延时单元控制参数可以包括高低电平，高低电平通过控制开关控制连入相位温度补偿电路中相应的相位延时单元锁，从而在仿真阶段实现在相应位置接入相应个数的相位延时单元。
应当理解的是，本实施例中相位延时单元21和相位延时单元控制模块3的具体结构以及设置的总数可以根据需求灵活设定。
例如，一种示例的相位温度补偿电路请参见图6所示，其包括多个相位延时单元21，多个相位延时单元21通过传输门逻辑连入电路中，组成相位温度补偿电路。每个相位延时单元21可以由两级或多级反相器电路组成，如图7所示。也可由由传输门单元、RC延时单元、简单电阻单元等电路组成，如几种组成方式请分别参见图8-1、图8-2和图8-3所示；当然也可通过其他电路结构实现。
又例如，一种示例中，相位延时单元控制模块3的结构参见图9所示，其包括译码电路以及传输门控制逻辑电路，译码电路可以将v1、v2...vn等输入信号转换成ctrl1、ctrl2...ctrl2 n等2 n个高低电平控制信号，这些控制信号直接或通过反相器之后连接传输门控制逻辑，进而控制相位温度补偿电路的相位延时单元21接入锁相环主体电路。
在本实施例的另一些应用场景中，基于上述仿真结果设置好锁相环电路之后，还可包括以下校准过程，以进一步提升控制的准确性和可靠性。本实施例提供的校准过程可包括：
获取接入锁相环主体电路的相位延时单元随温度变化所产生的相位偏移，与锁相环主体电路随温度变化所产生的相位偏移相互抵消后输出的 最终的相位与温度变化斜率Klast。
根据最终相位偏移Klast确定需要增加或减少接入锁相环主体电路的相位延时单元的个数m，并对应增加m个相位延时单元接入锁相环主体电路，或从当前接入锁相环主体电路的相位延时单元中，断开m个相位延时单元21。
本实施例的中上述校准过程可以为但不限于在芯片出厂阶段进行测试校准。为了便于理解，本实施例下面以芯片出厂阶段进行测试校准的过程进行说明，请参见图10所示，包括：
S1001：测试锁相环电路最终的相位与温度变化斜率Klast。
S1002：︱Klast︱≤K0？(也即︱Klast︱是否小于等于K0)；如是，转至S1003；否则，转至S1004。
S1003：︱Klast︱满足要求，测试校验结束。
S1004：Klast＞0？(也即Klast是否大于0)；如是，转至S1005；否则，转至S1006；
S1005：根据︱Klast︱值在参考信号输入路径和/或信号输出路径上减少接入的相应个数的相位延时单元；或在反馈信号传输路径上增加相应个数的相位延时单元接入，然后转至S1001。
S1006：根据︱Klast︱值在参考信号输入路径和/或信号输出路径上增加相应个数的相位延时单元接入；或在反馈信号传输路径上减少接入的相应个数的相位延时单元；然后转至S1001。
在一种应用场景中，当锁相环电路设置于芯片内或以分离器件形式出厂时，可执行图10所示的校准过程。例如可分别测试在高温和低温下测试获得锁相环电路当前相的Klast，然后判断︱Klast︱值是否足够小且满足应用要求，如果满足则校准结束，如果不满足则进一步判断Klast值是 否大于0。如果Klast值大于0，则根据︱Klast︱值适当减少参考信号输入路径和/或输出路径接入的相位延时单元数目，或者增加反馈信号传输路径上接入的相位延时单元数目；如果Klast值小于0，则根据︱Klast︱值适当增加参考信号输入路径和/或输出路径上相位延时单元数目，或者减少反馈信号传输路径上的相位延时单元数目；之后重复上述校验步骤，直到︱Klast︱值满足要求。
在本实施例的一种示例中，针对一个锁相环电路，可基于其工作环境下的最高温度和最低温度区间对应的相位与温度变化斜率，通过图5和图10所示的过程得到一组固定的相位延时单元控制参数，该相位延时单元控制参数包括需要在哪些路径上接入相位延时单元以及在各路径上需要接入的相位延时单元的个数。在本示例中，相位延时单元控制模块可基于该固定的相位延时单元控制参数控制相应个数的相位延时单元在相应路径上接入，且在出厂之后可不变。
在本实施例的另一种示例中，针对一个锁相环电路，可基于其工作环境下的最高温度和最低温度划分成多个温度区间，并基于测试结果得到各温度区间对应的一组相位延时单元控制参数，也即一个温度区间对应的一组相位延时单元控制参数；在工作过程中，相位延时单元控制模块可获取当前的温度，并在确定当前温度落入另一目标温度区间时，基于目标温度区间对应的相位延时单元控制参数动态的控制相应个数的相位延时单元在相应路径上接入。
另外，为了便于理解，本实施例下面以修正前后的几种情况进行比对为示例，对本实施例提供的锁相环电路为结构进行示例说明。
请参见图11-1所示，该图所示为锁相环主体电路未进行补偿时输出相位随着温度变化的情况；从该图中可以看出相位随温度变化的幅度较大，不能满足通信要求。通过本实施例提供的锁相环电路输出的波形相位随温 度变化的情况可能存在以下三种：
欠补偿情况，请参见图11-2所示，此时Klast为一个较小的大于0的值，锁相环电路最终输出相位随温度升高的略微增大；
过补偿情况，请参见图11-3所示，此时Klast为一个较小的小于0的值，锁相环电路最终输出相位随温度升高的略微减小；
理想补偿情况，请参见图11-4所示，此时Klast为一个等于0的值，此时温度升高或降低时，锁相环电路输出相位不变。
下面以图11-1和图11-2所述的两种情况对应的锁相环电路最终输出的相位与温度变化斜率的对比为示例进行说明，请参见图12所示，图12中左边的坐标系为图11-1对应的相位与温度变化斜率，右边的坐标系为图11-2对应的相位与温度变化斜率。可见经过校准后的输出相位随温度变化的斜率远小于未经校准的锁相环电路结构。
实施例三：
为了便于理解，本实施例下面以几种具体的应用场景为示例进行说明。
应用场景一：
在本应用场景中，请参见图13-2至图13-4所示，参考信号输入路径、信号输出路径以及反馈信号传输路径的相位与温度变化斜率关系为K1+K2-K3＞0，如果不接入相位延时单元，锁相环电路最终输出相位随温度升高而增大。本实施例中在反馈信号传输路径上接入相应个数的相位延时单元产生对应的Kc3，请参见图13-1和图13-5所示，参考信号输入路径、信号输出路径当前不接入相位延时单元；接入的相位延时单元输出相位随温度升高而增大，由于锁相环电路反馈信号传输路径的相位延时增大会导致锁相环电路输出相位延时减小的固有特性，可借助仿真校准和离线校准，接入的相位延时单元最终使得锁相环输出相位随温度升高而增大的特性减小，即Klast＝K1+K2-K3-Kc3。在本应用场景中，可借助图5和图 10所示的仿真校准和离线校准，通过相位延时单元控制模块控制相应个数的相位延时单元接入反馈信号传输路径，实现系数Kc3的调整。在Kc3的作用下，实现Klast＝K1+K2-K3-Kc3≈0，其中K1、K2、K3、Kc3的对比图请参见图13-6所示，抵消之后得到的Klast请参见图13-7所示，此时锁相环电路输出相位随温度升高略微增大，但远小于K1+K2-K3。
应用场景二：
在本应用场景中，请参见图14-2至图14-4所示，参考信号输入路径、信号输出路径以及反馈信号传输路径的相位与温度变化斜率关系为K1+K2-K3＜0，如果不接入相位延时单元，锁相环电路最终输出相位随温度升高而减小。本实施例中在参考信号输入路径上接入相应个数的相位延时单元产生对应的Kc1，请参见图14-1和图14-5所示，信号输出路径、反馈信号传输路径当前不接入相位延时单元(也可根据需求接入相位延时单元)；接入的相位延时单元输出相位随温度升高而增大，由于锁相环电路参考信号输入路径的相位延时增大会导致锁相环电路输出相位延时增大的固有特性，可借助仿真校准和离线校准，接入的相位延时单元最终使得锁相环输出相位随温度升高而减小的特性减小，即Klast＝K1+K2-K3+Kc1。在本应用场景中，可借助图5和图10所示的仿真校准和离线校准，通过相位延时单元控制模块控制相应个数的相位延时单元接入参考信号输入路径，实现系数Kc1的调整。在Kc1的作用下，实现Klast＝K1+K2-K3+Kc1≈0，其中K1、K2、K3、Kc1的对比图请参见图14-6所示，抵消之后得到的Klast请参见图14-7(为欠补偿的示意图)所示。
应用场景三：
在本应用场景中，请参见图15-1至图15-3所示，参考信号输入路径、信号输出路径以及反馈信号传输路径的相位与温度变化斜率关系为 K1+K2-K3＜0，如果不接入相位延时单元，锁相环电路最终输出相位随温度升高而减小。本实施例中在参考信号输入路径上接入相应个数的相位延时单元产生对应的Kc1，请参见图15-4所示，信号输出路径、反馈信号传输路径当前不接入相位延时单元(也可根据需求接入相位延时单元)；接入的相位延时单元输出相位随温度升高而增大，由于锁相环电路参考信号输入路径的相位延时增大会导致锁相环电路输出相位延时增大的固有特性，可借助仿真校准和离线校准，接入的相位延时单元最终使得锁相环输出相位随温度升高而减小的特性减小，即Klast＝K1+K2-K3+Kc1。在本应用场景中，可借助图5和图10所示的仿真校准和离线校准，通过相位延时单元控制模块控制相应个数的相位延时单元接入参考信号输入路径，实现系数Kc1的调整。在Kc1的作用下，实现Klast＝K1+K2-K3+Kc1≈0，其中K1、K2、K3、Kc1的对比图请参见图15-5所示，抵消之后得到的Klast请参见图15-6(为过补偿的示意图)所示。此时锁相环输出相位随温度升高略微减小。
应用场景四：
在本应用场景中，请参见图16-2至图16-4所示，参考信号输入路径、信号输出路径以及反馈信号传输路径的相位与温度变化斜率关系为K1+K2-K3＜0，如果不接入相位延时单元，锁相环电路最终输出相位随温度升高而减小。本实施例中在信号输出路径上接入相应个数的相位延时单元产生对应的Kc2，请参见图16-1和图16-5所示，参考信号输入路径、反馈信号传输路径当前不接入相位延时单元(也可根据需求接入相位延时单元)；接入的相位延时单元输出相位随温度升高而增大，由于锁相环电路参考信号输入路径的相位延时增大会导致锁相环电路输出相位延时增大的固有特性，可借助仿真校准和离线校准，接入的相位延时单元最终使得锁相环输出相位随温度升高而减小的特性减小，即Klast＝K1+K2-K3+Kc2。在本应用场景中，可借助图5和图10所示的仿真 校准和离线校准，通过相位延时单元控制模块控制相应个数的相位延时单元接入信号输出路径，实现系数Kc2的调整。在Kc2的作用下，实现Klast＝K1+K2-K3+Kc2≈0，其中K1、K2、K3、Kc2的对比图请参见图16-6所示，抵消之后得到的Klast请参见图16-7所示。此时锁相环输出相位随温度升高略微增大，但远小于K1+K2-K3。
实施例四：
本实施例还提供了一种通信设备，该通信设备可以为但不限于基站或各种收发机，其包括至少一个上述各实施例所示的锁相环电路。在一种示例中，通信设备采用多通道通信时，可一个通道对应使用一个锁相环电路，也可多个通道共用一个锁相环电路。
为了便于理解，本实施例的一种示例中以通信设备为基站进行示例说明。且应当理解的是，本实施例中的基站可以为机柜式宏基站、分布式基站或多模基站。请参见图17所示，本示例中的基站包括基带单元(Building Base band Unit，BBU)171和射频拉远单元(Radio Remote Unit，RRU)172以及天线173，其中：
基带单元171负责集中控制与管理整个基站系统，完成上下行基带处理功能，并提供与射频单元、传输网络的物理接口，完成信息交互。按照逻辑功能的不同，请参见图17所示，基带单元171可包括基带处理单元1712、主控单元1711、传输接口单元1713等。其中，主控单元1711主要实现基带单元的控制管理、信令处理、数据传输、交互控制、系统时钟提供等功能；基带处理单元1712设置为完成信号编码调制、资源调度、数据封装等基带协议处理，提供基带单元和射频拉远单元间的接口；传输接口单元1713负责提供与核心网连接的传输接口。在本示例中，上述各逻辑功能单元可分布在不同的物理板卡上，也可以集成在同一块板卡上。且可选的，基带单元171可采用基带主控集成式，也可采用基带主控分离式。 对于基带主控集成式，主控、传输、基带一体化设计，即基带处理单元与主控单元、传输接口单元集成在一块物理板卡上，该架构具有更高的可靠性、更低的低延、更高的资源共享及调度效率，同时功耗更低。对于基带主控分离式，基带处理单元与主控单元分布在不同的板卡上，对应于基带板、主控板，分离式架构支持板卡间自由组合、便于基带灵活扩容。具体可根据需求灵活采用设置。
射频拉远单元172通过基带射频接口与BBU通信，完成基带信号与射频信号的转换。参见图17所示，一种示例的射频拉远单元172主要包括接口单元1721、上行信号处理单元1724、下行信号处理单元1722、功放单元1723、低噪放单元1725、双工器单元1726等，构成下行信号处理链路与上行信号处理链路。其中，接口单1721提供与基带单元之间的前传接口，接收和发送基带IQ信号；下行信号处理单元1722完成信号上变频、数模转换、射频调制等信号处理功能；上行信号处理单元1724主要完成信号滤波、混频、模数转换、下变频等功能；功放单元1723设置为对下行信号进行放大后通过天线173发出；低噪放单元1725设置为对天线173接收到的上行信号进行放大后发给上行信号处理单元1724进行处理；双工器单元1726支持收发信号复用并对收发信号进行滤波。
另外，应当理解的是，本实施例中的基站还可采用CU(Central Unint，中央单元)-DU(Distributed Unit，分布式单元)架构，其中DU是分布式接入点，负责完成底层基带协议及射频处理功能，CU是中央单元，负责处理高层协议功能并集中管理多个DU。CU和DU共同完成基站的基带及射频处理功能。
可见，本领域的技术人员应该明白，上文中所公开方法中的全部或某些步骤、系统、装置中的功能模块/单元可以被实施为软件(可以用计算装置可执行的计算机程序代码来实现)、固件、硬件及其适当的组合。在硬 件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些物理组件或所有物理组件可以被实施为由处理器，如中央处理器、数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。
此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、计算机程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。所以，本发明不限制于任何特定的硬件和软件结合。
以上内容是结合具体的实施方式对本公开所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。
工业实用性
基于本发明实施例提供的上述技术方案，锁相环电路包括锁相环主体电路以及相位温度补偿电路，可根据锁相环主体电路随温度变化所产生的相位偏移，设置相位温度补偿电路的至少一个相位延时单元接入锁相环主体电路，利用接入相位温度补偿电路的相位延时单元随温度变化所产生的相位偏移，对锁相环主体电路随温度变化所产生的相位偏移进行抵消；从而保证锁相环电路在工作过程中随着温度的变化不产生相位偏移或在很小范围内产生相位偏移；这样锁相环电路应用到多通道场景时，由于各通道的锁相环电路在工作过程中随着温度的变化不产生相位偏移或在很小范围内产生相位偏移，因此可保证各通道之前的相位差异在任何时刻都尽可能小，从而从根本上更好的满足多通道通信相位同步的需求；且可省略对各通道之间的相位进行检测以及对齐的控制操作，因此可同时提升资源利用率以及节省能耗。

Claims (11)

  1. 一种锁相环电路，包括锁相环主体电路以及相位温度补偿电路，所述相位温度补偿电路包括至少一个相位延时单元，且至少一个所述相位延时单元接入所述锁相环主体电路，接入所述锁相环主体电路的相位延时单元随温度变化所产生的相位偏移，与所述锁相环主体电路随温度变化所产生的相位偏移相互抵消。
  2. 如权利要求1所述的锁相环电路，其中，所述锁相环主体电路上的传输路径自身的总输出相位与温度变化斜率Kout与接入所述锁相环主体电路的相位延时单元在所述传输路径上的总输出相位与温度变化斜率Koutc之间满足：
    所述Kout的值为负时，所述Koutc的值为正，所述Kout的值为正时，所述Koutc的值为负，且所述Kout与所述Koutc之和的绝对值小于等于阈值K0。
  3. 如权利要求2所述的的锁相环电路，其中，所述传输路径包括参考信号输入路径、信号输出路径以及反馈信号传输路径，所述参考信号输入路径、信号输出路径以及反馈信号传输路径的相位与温度变化斜率分别为K1、K2和K3，所述Kout＝K1+K2-K3；
    接入所述锁相环主体电路的相位延时单元在所述参考信号输入路径、信号输出路径以及反馈信号传输路径上的相位与温度变化斜率分别为Kc1、Kc2、Kc3，所述Koutc＝Kc1+Kc2-Kc3。
  4. 如权利要求3所述的锁相环电路，其中，所述Kout的值为正时，所述Kc1、Kc2中的至少一个为0。
  5. 如权利要求4所述的锁相环电路，其中，所述Kout的值为正时，所述Kc1、Kc2都为0。
  6. 如权利要求3至5任一项所述的锁相环电路，其中，所述Kout的值为负时，所述Kc3为0。
  7. 如权利要求3至5任一项所述的锁相环电路，其中，所述Kout的值为负时，所述Kc1或Kc2为0。
  8. 如权利要求1至5任一项所述的锁相环电路，其中，还包括相位延时单元控制模块，设置为根据相位延时单元控制参数，控制相应个数的相位延时单元接入所述锁相环主体电路；所述相位延时单元控制参数根据所述锁相环主体电路随温度变化所产生的相位偏移确定。
  9. 一种如权利要求1至8任一项所述的锁相环电路设置方法，包括：
    通过仿真得到所述锁相环主体电路随温度变化所产生的相位偏移；
    根据所述相位偏移确定相位延时单元控制参数；
    根据所述相位延时单元控制参数控制相应个数的所述相位延时单元接入所述锁相环主体电路。
  10. 如权利要求9所述的锁相环电路设置方法，其中，根据所述相位延时单元控制参数控制相应个数的所述相位延时单元接入所述锁相环主体电路之后，还包括以下校准过程：
    获取接入所述锁相环主体电路的相位延时单元随温度变化所产生的相位偏移，与所述锁相环主体电路随温度变化所产生的相位偏移相互抵消后输出的最终相位偏移；
    根据所述最终相位偏移确定需要增加或减少接入所述锁相环主体电路的相位延时单元的个数m，并对应增加m个相位延时单元接入所述锁相环主体电路，或从当前接入所述锁相环主体电路的相位延时单元中，断 开m个相位延时单元。
  11. 一种通信设备，包括至少一个如权利要求1至9任一项所述的锁相环电路。
PCT/CN2020/097225 2019-07-02 2020-06-19 锁相环电路及其设置方法、通信设备 WO2021000751A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US17/624,063 US11750200B2 (en) 2019-07-02 2020-06-19 Phase-locked loop circuit, configuration method therefor, and communication apparatus
EP20835431.6A EP3989442A4 (en) 2019-07-02 2020-06-19 PHASE LOCKED CIRCUIT, CONFIGURATION METHOD THEREOF AND COMMUNICATION DEVICE

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910591540.4 2019-07-02
CN201910591540.4A CN112187255A (zh) 2019-07-02 2019-07-02 锁相环电路及其设置方法、通信设备

Publications (1)

Publication Number Publication Date
WO2021000751A1 true WO2021000751A1 (zh) 2021-01-07

Family

ID=73914370

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/097225 WO2021000751A1 (zh) 2019-07-02 2020-06-19 锁相环电路及其设置方法、通信设备

Country Status (4)

Country Link
US (1) US11750200B2 (zh)
EP (1) EP3989442A4 (zh)
CN (1) CN112187255A (zh)
WO (1) WO2021000751A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006000611A1 (en) * 2004-06-24 2006-01-05 Nokia Corporation Frequency synthesizer
CN1968006A (zh) * 2005-11-17 2007-05-23 中国科学院半导体研究所 具有温度补偿效应的环路压控振荡器
CN101662260A (zh) * 2008-08-28 2010-03-03 株式会社瑞萨科技 半导体集成电路
CN104135277A (zh) * 2014-07-25 2014-11-05 深圳大学 一种片上基准时钟产生电路及方法
CN105629772A (zh) * 2014-10-30 2016-06-01 深圳艾科创新微电子有限公司 一种延时控制装置
CN108988854A (zh) * 2018-07-04 2018-12-11 西安电子科技大学 锁相环电路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4679005A (en) * 1985-01-23 1987-07-07 Sony Corporation Phase locked loop with frequency offset
US8866556B2 (en) 2009-02-27 2014-10-21 Analog Bits, Inc. Phase shift phase locked loop
US9966661B2 (en) 2012-08-24 2018-05-08 City University Of Hong Kong Phased array, a coherent source array, an antenna array and a system for controlling thereof
JP6263906B2 (ja) * 2013-08-28 2018-01-24 富士通株式会社 電子回路および制御方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006000611A1 (en) * 2004-06-24 2006-01-05 Nokia Corporation Frequency synthesizer
CN1968006A (zh) * 2005-11-17 2007-05-23 中国科学院半导体研究所 具有温度补偿效应的环路压控振荡器
CN101662260A (zh) * 2008-08-28 2010-03-03 株式会社瑞萨科技 半导体集成电路
CN104135277A (zh) * 2014-07-25 2014-11-05 深圳大学 一种片上基准时钟产生电路及方法
CN105629772A (zh) * 2014-10-30 2016-06-01 深圳艾科创新微电子有限公司 一种延时控制装置
CN108988854A (zh) * 2018-07-04 2018-12-11 西安电子科技大学 锁相环电路

Also Published As

Publication number Publication date
US11750200B2 (en) 2023-09-05
EP3989442A4 (en) 2022-08-03
EP3989442A1 (en) 2022-04-27
US20220360267A1 (en) 2022-11-10
CN112187255A (zh) 2021-01-05

Similar Documents

Publication Publication Date Title
JP7377603B2 (ja) 位相変動補償装置及び方法
US6993107B2 (en) Analog unidirectional serial link architecture
CN103297366B (zh) 调制系统、调相系统和用于减轻调制误差的方法
US11387833B1 (en) Differential digital-to-time converter for even-order INL cancellation and supply noise/disturbance rejection
US10831220B2 (en) Methods and apparatuses for voltage regulation using precharge rails
US11595028B2 (en) Frequency doubler with duty cycle correction
US11212017B2 (en) Phase-locked loop (PLL) calibration
US11258451B2 (en) Apparatus and method for generating an oscillation signal, mobile communication systems and mobile device
AU2020439938A1 (en) Timing difference determination method and apparatus, device and storage medium
USRE49805E1 (en) Apparatus and circuit for processing carrier aggregation
WO2021000751A1 (zh) 锁相环电路及其设置方法、通信设备
US11841738B2 (en) Multi-phase clock signal phase difference detection and calculation circuit and method and digital phase modulation system
US9414262B2 (en) Interference suppression method and apparatus
EP4213391A1 (en) Clock synchronization circuit, control method, printed circuit board and communication device
US8417198B1 (en) Selection of closed-loop/open-loop power control in user equipment
EP3243277B1 (en) Method and radio network node for compensation for local oscillator pulling or pushing
CN103686981A (zh) 多待或多通移动终端及其频偏调整方法
CN113472373B (zh) 一种射频信号输出自动均衡的方法
CN100550872C (zh) 通讯系统与方法
US11588612B2 (en) Communication chip
JP2011259423A (ja) 無線通信のエミッション抑制のための送信元、方法及び位相同期回路
RU2292659C2 (ru) Способ и устройство адаптивной предварительной коррекции
TW202423057A (zh) 相位追蹤與校正架構
TW202015343A (zh) 用於全數位鎖相迴路的裝置和方法
CN105763188A (zh) 改善发射机射频指标的方法和装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20835431

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2020835431

Country of ref document: EP

Effective date: 20220118