WO2020259523A1 - 与fpga通信的主机及方法、fpga接口芯片 - Google Patents

与fpga通信的主机及方法、fpga接口芯片 Download PDF

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Publication number
WO2020259523A1
WO2020259523A1 PCT/CN2020/097858 CN2020097858W WO2020259523A1 WO 2020259523 A1 WO2020259523 A1 WO 2020259523A1 CN 2020097858 W CN2020097858 W CN 2020097858W WO 2020259523 A1 WO2020259523 A1 WO 2020259523A1
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fpga
interface
host
cable
communicating
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PCT/CN2020/097858
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English (en)
French (fr)
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冯展鹏
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深圳市紫光同创电子有限公司
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Priority to JP2020568804A priority Critical patent/JP7041285B2/ja
Publication of WO2020259523A1 publication Critical patent/WO2020259523A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/321—Interlayer communication protocols or service data unit [SDU] definitions; Interfaces between layers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2212/00—Encapsulation of packets

Definitions

  • This application relates to the field of programmable logic devices, and more specifically, to a host and method for communicating with FPGA, and an FPGA interface chip.
  • FPGA Field Programmable Gate Array
  • an on-chip control system is integrated. This on-chip control system allows users to configure, debug, and read and write soft and hard core data on the FPGA through interfaces such as JTAG (Joint Test Action Group) and SPI (Serial Peripheral Interface).
  • JTAG Joint Test Action Group
  • SPI Serial Peripheral Interface
  • the upper computer can use different channels to communicate with the FPGA.
  • an interface chip responsible for receiving and sending messages from the host and used to directly interact with the FPGA.
  • the subsystem composed of this interface chip is generally called a downloader (Cable).
  • the host and method for communicating with FPGA, and the FPGA interface chip provided by the embodiments of the application mainly solve the technical problem that the existing host interface software design has poor scalability and cannot use multiple communication resources in parallel to communicate with the FPGA interface chip. The problem.
  • an embodiment of the present application provides a host communicating with an FPGA.
  • the host communicating with the FPGA includes a software interface module for defining a calling interface exposed to an upper-layer application, and the calling interface is used to determine transmission data.
  • the resource management module is used to manage the host interface chip cable object, allowing parallel access to at least two cable objects at the same time.
  • the cable object obtains the transmission data through the calling interface, and sends the transmission data to Protocol packet module.
  • the protocol encapsulation module is used to receive the transmission data, encapsulate the transmission data to obtain a data packet according to the interface protocol of the FPGA and the channel protocol corresponding to the cable object, and send the data packet to the host channel interface Module.
  • the host channel interface module is configured to receive the data packet, package the data packet in a preset data format agreed with the FPGA interface chip, and send it through the channel.
  • embodiments of the present application provide an FPGA interface chip, the FPGA interface chip is configured to receive the data packet sent by the host communicating with the FPGA according to any one of claims 1-9, and transfer the data packet It is converted into the communication signal required by FPGA and communicates directly with FPGA.
  • an embodiment of the present application provides a method for communicating with an FPGA, including: a software interface module of a host communicating with the FPGA defines a calling interface exposed to an upper-layer application, and the calling interface can determine the transmission data.
  • the resource management module of the host communicating with the FPGA manages the host interface chip cable object, allowing parallel access to at least two cable objects at the same time.
  • the cable object obtains the transmission data through the call interface, and transfers all The transmission data is sent to the protocol packet module of the host communicating with the FPGA.
  • the protocol encapsulation module receives the transmission data, encapsulates the transmission data to obtain a data packet according to the interface protocol of the FPGA and the channel protocol corresponding to the cable object, and sends the data packet to the communication with FPGA
  • the host channel interface module of the host receives the data packet, encapsulates the data packet in a preset data format agreed with the FPGA interface chip, and sends it to the FPGA interface chip through the channel.
  • the FPGA interface chip receives the data packet, converts the data packet into a communication signal required by the FPGA, and communicates directly with the FPGA.
  • This application provides a host and FPGA interface chip that communicate with FPGA.
  • the definition of the software interface module of this application The call interface exposed to the upper application; the resource management module manages the host interface chip cable object, and allows parallel access to at least two cable objects at the same time, the cable object is common to the call interface; the protocol package module is based on the FPGA interface protocol, The channel protocol corresponding to the cable object encapsulates the transmission data to obtain the data packet; the host channel interface module encapsulates the data packet according to the preset data format agreed with the FPGA interface chip, and sends it through the channel; that is, by layering the interface software Setting, you can access multiple interface resources in parallel, and use the same software interface, suitable for FPGA cluster resource management; strong portability, completely hierarchical, transplant to different platforms, only the host channel interface is different, and the operation process does not need to be changed , Improve the overall
  • FIG. 1 is a schematic structural diagram of a host communicating with FPGA provided by the first embodiment of this application;
  • FIG 2-1 is a schematic diagram of the host communicating with the FPGA and the FPGA interface chip connected via Ethernet according to the first embodiment of the application;
  • Figure 2-2 is a schematic diagram of the host communicating with the FPGA and the FPGA interface chip provided by the first embodiment of the application connected through a cable such as USB or LPT;
  • Figure 2-3 is a schematic diagram of the host communicating with the FPGA and the FPGA interface chip connected through a wireless network provided by the first embodiment of the application;
  • FIG. 3 is a schematic diagram of the host communicating with the FPGA provided by the first embodiment of the application implementing communication with the FPGA interface chip via Ethernet;
  • FIG. 4 is a schematic diagram of the preset data format provided by the first embodiment of the application.
  • FIG. 5 is a schematic diagram of the connection between the FPGA interface chip and the FPGA provided by the second embodiment of the application;
  • FIG. 6 is a schematic diagram of the software hierarchy structure provided by the second embodiment of this application.
  • FIG. 7 is a schematic diagram of the communication process between the host communicating with the FPGA and the FPGA provided by the third embodiment of the application.
  • FIG. 8 is a schematic flowchart of a method for communicating with an FPGA provided by the third embodiment of the application.
  • the communication interface software developed by existing FPGA manufacturers has certain limitations.
  • the USB interface Cable of the machine can only be used to communicate with FPGA, because multiple resources cannot be used in parallel at the same time, it can only support one user at a time, and the scalability is not good.
  • some FPGA manufacturers also propose the concept of virtual cable, such as Xilinx Virtual Cable, which allows users to virtualize a cable locally (in fact, access the FPGA on the circuit board through the Ethernet interface) as a normal
  • the cable of the USB cable is used, but the specific software is separate. In this case, when writing the communication flow code of a certain on-chip interface of the FPGA, it may be necessary to write separately for different channels, which causes a waste of development resources and increases maintenance costs.
  • Fig. 1 is a host for communicating with FPGA provided in this embodiment.
  • the host includes but is not limited to a computer, a notebook, and the like.
  • the host includes: a software interface module 101, a resource management module 102, a protocol closure module 103, and a host channel interface module 104;
  • the software interface module 101 is used to define a calling interface exposed to upper-layer applications, and the calling interface is used to determine transmission data.
  • the resource management module 102 is used to manage the host interface chip cable object, allowing parallel access to at least two cable objects at the same time, the cable object obtains transmission data through the calling interface, and sends the transmission data to the protocol packet module 103.
  • the protocol encapsulation module 103 is configured to receive transmission data, encapsulate the transmission data to obtain a data packet according to the interface protocol of the FPGA and the channel protocol corresponding to the cable object, and send the data packet to the host channel interface module 104.
  • the host channel interface module 104 is configured to receive data packets, package the data packets in a preset data format agreed with the FPGA interface chip, and send them through the channel.
  • the call interface exposed to the user through the software interface module 101 can determine the transmission data; the resource management module 102 determines the cable object communicating with the FPGA interface chip, and then the cable object obtains the transmission data through the call interface and sends it to the protocol The packet module 103; the protocol packet module 103 encapsulates the transmission data to obtain a data packet according to the interface protocol of the FPGA and the channel protocol corresponding to the cable object, and sends the data packet to the host channel interface module 104.
  • the cable object is different, and the corresponding channel is different.
  • the cable object includes the cable connected to the USB (Universal Serial Bus) cable, the cable connected to the circuit board through the Ethernet port, and the cable connected to the PCIE (peripheral component).
  • Interconnect Express a high-speed serial computer expansion bus standard
  • the corresponding channels are USB, Ethernet port, PCIE, and printer parallel port.
  • the host channel interface module 104 is only responsible for channel-related processing, implementing data packets, and then sending data, it needs to agree on the necessary data packet format with the FPGA interface chip, and send the data packets according to the protocol rules used by the channel. For FPGA interface chips, the agreed data packet format is also different.
  • the software interface module 101 serves as an interface software library of the host communicating with the FPGA, including an interface exposed to the user, and the calling interface includes a basic software interface for communicating with the FPGA.
  • the host communicating with the FPGA and the FPGA interface chip can be connected via cables such as Ethernet, USB or LPT, and Wi-Fi (wireless network). It is understandable that for different FPGA interface chip types, such as USB, Ethernet, WIFI, etc., the communication process based on it is basically the same, and it must be initialized, connected, read and write data to each other, and finally released.
  • Figure 3 shows the communication process between the host communicating with FPGA and the FPGA interface chip through Ethernet.
  • FPGA interface chip monitors a certain port and waits for connection; the host communicating with FPGA is based on IP (Internet Protocol, The network protocol) address initializes the socket (socket) connection. When the connection is successful, the host communicating with the FPGA reads and writes data through the socket. The FPGA interface chip unpacks the data in the socket and converts the data into the signals required by the FPGA. After that, the host communicating with the FPGA is released and the socket is disconnected; the FPGA interface chip monitors a certain port again.
  • IP Internet Protocol, The network protocol
  • the software interface module 101 is unified and abstracted to form a fixed basic software interface for communication between different types of FPGA interface chips and the host communicating with the FPGA, that is, for the upper layer software, it communicates with each FPGA interface chip.
  • the basic software interface in this embodiment includes an initialization (Init) interface, a write data (Write) interface, a read data (Read) interface and a release (Release) interface.
  • the initialization is to use the TCP (Transmission Control Protocol)/IP protocol, and use the system socket to try to connect with the remote FPGA interface chip.
  • the request object in the process of transferring the transmission data to the above-mentioned basic software interface, the request object needs to be defined.
  • the request object is a structure. Therefore, the structure of the transmission data includes the request object, and the request object includes a predefined operation code. At least one of data, object, callback function, and extended void (no type) pointer, allowing upper-level code to access the basic software interface in a unified form.
  • the resource management module 102 manages all available cable objects.
  • the cable objects can be real, such as a cable connected by a USB cable, or virtual, such as a circuit board connected to an Ethernet port. Or the interface chip on the PCIE board connected to PCIE.
  • the resource management module 102 specifically manages the specific number and occupancy of various types of cable objects, and allows parallel access to at least two cable objects at the same time. Of course, the at least two cable objects do not conflict.
  • each cable object instance is assigned a unique MAC address and type identifier to facilitate distinction, and the resource management module 102 can uniquely determine the cable object.
  • the type identifier assigned to the cable object is used to define the type attribute of the cable object.
  • the type identifier can be customized by the host communicating with the FPGA. For example, when the cable object is USB Cable, the corresponding type identifier It can be USB; when the cable object is an Ethernet virtual cable, the corresponding type identification can be Ethernet. In some embodiments, as long as the cable type can be indicated, the type identification may also be in the form of a custom number or the like.
  • a unique MAC address will be assigned to the cable as a unique resource identifier.
  • the MAC address is the serial number recorded in the EEPROM of the USB;
  • the MAC address is the IP of the Ethernet virtual cable Address or the real MAC address of the FPGA interface chip;
  • the MAC address is the address of the PCIE bus or the serial number in the interface chip on the PCIE bus;
  • the MAC address is a parallel port address.
  • the user can select any cable object connected to the FPGA interface chip.
  • the resource management module 102 scans the accessible cable objects to form a list, and provides the list to the user.
  • the calling interface includes obtaining a Probe interface that can access the cable object, and the Probe interface can detect the current usage of the accessible cable object.
  • the resource management module 102 forms a list, it returns to the all users through the Probe interface.
  • the upper-layer application is the user, so that the upper-layer application can determine the access cable object that communicates with the FPGA.
  • the protocol encapsulation module 103 mainly encapsulates the received transmission data according to the interface protocol of the FPGA and the protocol used by the channel.
  • the hardware and software cores in FPGA generally support JTAG (Joint Test Action Group), I2C (Inter-Integrated Circuit, two-wire serial bus), SPI (Serial Peripheral Interface, serial peripheral interface) ), slave and other interfaces, these interface protocols sometimes need to be specially processed at the application layer based on protocol-related information.
  • the JTAG protocol if there is a JTAG chain, there will actually be many devices on this chain, some of which may be FPGAs, and some may not. In this way, the JTAG protocol software needs some processing when needed. For example, when writing JTAG commands, you need to write the necessary bypass commands according to the chain situation first, and when writing JTAG data, you must also fill in 1 and so on.
  • the protocol encapsulation module 103 When the transmission data is being transferred, the protocol encapsulation module 103 will also re-encapsulate the transmission data according to the protocol used by the channel. For example, when the channel corresponding to the Ethernet is used, the transmission data will be re-encapsulated according to the TCP/IP protocol to obtain the transmission.
  • the data packet to the host channel interface module 104; and then the FPGA interface information parses the TCP/IP data, and then the extracted content is the agreed preset data packet format.
  • a certain format of data needs to be agreed upon between the host channel interface module 104 and the FPGA interface chip.
  • the agreed preset data format and FPGA interface The implementation of the chip is related, so the host channel interface module 104 agrees with the FPGA interface chip on the preset data format according to the implementation of the FPGA interface chip.
  • the host channel interface module 104 agrees with the FPGA interface chip on the preset data format according to the implementation of the FPGA interface chip.
  • it is to agree on a certain format for binary data, and then send the binary data according to this format.
  • the preset data format includes a packet header and data
  • the packet header is composed of a command code and a data length.
  • the 32bits (bit) command code determines the operations that the FPGA interface chip needs to perform, such as the state jump of the JTAG protocol, setting some attributes, and reading and writing JTAG data.
  • the data length of 32bits indicates how much data is behind.
  • the FPGA interface chip is implemented as an MCU (Microcontroller Unit) with an Ethernet port chip. Since the FPGA interface chip can be programmed, the network data packet received by the FPGA interface chip can be agreed upon The content format of, both parties can unpack according to the corresponding agreement.
  • MCU Microcontroller Unit
  • the host that communicates with the FPGA provided in this embodiment includes a hierarchical interface software design mode.
  • the software interface module 101, the resource management module 102, the protocol packet module 103 and the host channel interface module 104 Through the software interface module 101, the resource management module 102, the protocol packet module 103 and the host channel interface module 104, the operations of the FPGA communication interfaces It is completely abstracted, so that the upper-layer code of the interface software does not need to care about the channel, the receiving end Cable, and the interface protocol, but only needs to focus on the communication process of a certain interface of the specific FPGA, which improves the scalability and availability of the overall software. Maintainability.
  • the FPGA interface chip includes an FPGA-side channel interface module.
  • the FPGA-side channel interface module is used to receive data packets sent by a host communicating with the FPGA.
  • the preset data format agreed by the host channel interface module 104 of the host communicating with the FPGA parses the data packet, converts the data packet into a communication signal required by the FPGA, and directly communicates with the FPGA.
  • the FPGA-side channel interface module analyzes data, which is a chip-level behavior, that is, read data directly from the channel, and after analysis, it is directly converted into communication signals such as JTAG and SPI required by the FPGA, and directly communicates with the FPGA.
  • the interface chip is a USB Cable
  • the data of the host communicating with the FPGA is obtained through the USB cable, and then converted into protocol signals such as JTAG to communicate with the FPGA.
  • the FPGA interface chip includes a USB interface chip of FT2232H
  • the preset data format includes packet header and data.
  • the packet header is composed of a command code and a data length.
  • the command code determines the operations that the receiver interface chip needs to perform, such as performing state jumps in the JTAG protocol, setting some attributes, reading and writing JTAG data, etc.
  • the data length indicates how much data is behind.
  • This embodiment provides an interface design for communicating with FPGA, and the interface software is realized by layering. As shown in Fig. 6, the interface design includes:
  • Software interface Define the interface exposed to the upper application, including the resource application release interface, the Probe interface to obtain the resource list, the read and write interface and the initialization interface of each protocol directly related to the FPGA, and these basic interfaces are defined.
  • the interface of the host that communicates with the FPGA is abstracted into an operating unit (operator).
  • Each type of operator implements the corresponding function; these operators are only responsible for the direct reading and writing of data, or translation, the initialization and release of interfaces, and the collection of resource conditions; different operators can implement custom functions according to their own characteristics, But the upper function only cares about these basic interfaces.
  • Resource management implement resource management, responsible for managing cable resources, allowing parallel access to multiple communication resources at the same time.
  • the resource management layer coordinates and manages all available cable resources, including the specific number and occupation of various resources.
  • the resource application release mechanism is implemented in the resource management layer.
  • the user obtains handle objects when applying for objects, and then uses these handle objects to operate.
  • the resource management layer needs to be able to automatically scan the currently available resources and provide a list to the user. In the Probe function interface, the list of related resources is returned; after the user selects, he can concurrently access the corresponding cable resource; each cable resource can be accessed through MAC, type, etc. are uniquely distinguished. For a process, this resource management object class is a singleton.
  • the Cable object here can be real, such as a cable connected by a USB cable, or virtual, such as an interface chip on a circuit board connected through an Ethernet port, or a PCIE board connected through PCIE The interface chip on the card.
  • the purpose of the cable object is to integrate the various operators supported by the current type of cable, and to implement a unified Handle software interface, so that the upper layer can only pass the opcode to achieve data reading and writing.
  • the Cable object also needs to provide basic interfaces such as initialization and release. These interface methods are actually calling the relevant operator for resource application and release.
  • Protocol packet This layer mainly combines the JTAG, SPI and other protocol-related data used by the FPGA into a data packet according to certain rules, and sends it to the underlying operator object for processing.
  • the bottom-level operator only deals with the details related to the channel.
  • some protocol operators need to be implemented to package the lower-level operators.
  • the processing in this layer of protocol operators is essentially Split or reassemble the protocol-related data packets passed by the user, and then call the basic read-write interface in turn for processing.
  • the operator of the protocol needs the bottom operator, and basically all the bottom operators share the same protocol-related operator.
  • Host channel interface This layer mainly implements the bottom-layer operators that call the drive interface of the system, and re-encapsulates the data passed by the upper layer according to the channel requirements, and then sends it out. Different channels may require different encoding methods. Related to the interface on the FPGA side. After the data is sent out according to the channel requirements, it is received by the FPGA-side channel interface. Since different receivers have different data packet requirements, the upper-layer software does not care about the specific packet conditions. It only needs to be agreed for different receiver platforms; and then according to these agreements, realize each independent Operator.
  • FPGA-side channel interface There is an interface chip on the FPGA side.
  • this is a Cable with an interface chip. It obtains the data of the host communicating with the FPGA through the USB cable, and then converts it into JTAG and other protocol signals. Communicate with FPGA.
  • Different interface chips need to do different processing, which means that it needs to cooperate with the host side of FPGA communication, but in most cases, it is only the difference in how to combine the packaged data.
  • the interface hardware selected by the receiving end can be more flexible.
  • the host communicating with the FPGA can encapsulate the data according to the hardware requirements of the receiving end. At this time, the interface hardware chip needs to be able to support the unpacking of the data and transform it into what the FPGA needs
  • the communication signal communicates directly with the FPGA.
  • the hierarchical interface software design mode makes upper-layer applications no longer need to care about any interface chip, FPGA's own interface protocol and other special processing details, which enhances scalability. Regardless of the channel, interface resources are exposed to the upper layer. Applications are fixed; they can be concurrent. They can be accessed and used in parallel for non-conflicting interface resources. They are suitable for use as a server process. If an interconnection structure such as Ethernet can be introduced, certain distributed characteristics can also be realized.
  • the same software interface can be used, which is suitable for FPGA cluster resource management; strong portability, completely hierarchical, transplant to different platforms, only the host channel interface is different Therefore, the code migration can be realized by replacing each operator of this layer, and the operation flow of the upper layer does not need to be changed; the usage scenario is more flexible, and it supports wireless, wired and other methods to communicate with the FPGA.
  • This embodiment also describes the communication process of the host communicating with the FPGA and the FPGA, as shown in FIG. 7.
  • the host side communicating with the FPGA determines the cable resource for communicating with the FPAG according to the Probe interface.
  • the Probe interface mainly detects the total number of accessible resources of the current type, forms a list, and returns it to the upper software for the user to decide which cable resource to use to communicate with FPAG.
  • the cable resource is assigned a MAC Address and type identification to distinguish each cable resource. Assume that it is determined that the cable connected by the USB cable and the cable of the Ethernet simulation communicate with the FPAG.
  • the host terminal communicating with the FPGA is connected to the FPAG interface chip of the FPAG through the initialization interface.
  • the initialization is to use the TCP/IP protocol, and the socket of the system is used to try to connect with the remote receiving end; for the case of USB, the initialization is to call the system interface to apply for the USB device and perform the initialization operation.
  • the host side communicating with the FPGA combines the data related to the interface protocol used by the FPGA into a data packet according to a certain rule.
  • the host side communicating with the FPGA organizes the data packet according to the preset data format, and then sends it to the FPAG interface chip through the channel corresponding to the cable resource.
  • the FPAG interface chip includes the USB interface chip of FT2232H, the preset data format is composed of packet header and data, and the packet header is composed of command code and data length.
  • the command code determines the operations that the receiver interface chip needs to perform, such as the state jump of the JTAG protocol, setting some attributes, reading and writing JTAG data, etc.
  • the data length indicates how much data is behind.
  • the FPAG interface chip also includes an MCU with an Ethernet port chip. Since the Ethernet port chip can be programmed, the content format of the network data packet received by the Ethernet port chip can be agreed. Of course, when using Ethernet, when data is transmitted, the TCP/IP protocol used will also re-encapsulate the data and then transmit it to the Ethernet port chip.
  • the FPAG interface chip reads and parses the data packet from the channel, converts it into the communication signal required by the FPGA, and communicates directly with the FPGA.
  • the FPAG interface chip parses the data according to the preset data format.
  • the FPAG interface chip sends data back to the host side communicating with the FPGA, it also performs packetization according to the preset data format.
  • S706 The host terminal communicating with the FPGA disconnects the connection with the FPAG interface chip through the release interface.
  • the embodiment of the present application also provides a method for communicating with FPGA, as shown in FIG. 8, which can be implemented through the following steps:
  • the software interface module 101 of the host communicating with the FPGA defines a calling interface exposed to upper-layer applications, and the calling interface can determine the transmission data.
  • the resource management module 102 of the host communicating with the FPGA manages the host interface chip cable object, allowing parallel access to at least two cable objects at the same time.
  • the cable object obtains the transmission data by calling the interface, and sends the transmission data to the FPGA
  • the protocol packet module 103 of the communicating host is the protocol packet module 103 of the communicating host.
  • the protocol packet module 103 receives the transmission data, encapsulates the transmission data to obtain a data packet according to the FPGA interface protocol and the channel protocol corresponding to the cable object, and sends the data packet to the host channel interface of the host communicating with the FPGA Module 104.
  • the host channel interface module 104 receives the data packet, packetizes the data packet according to a preset data format agreed with the FPGA interface chip, and sends it to the FPGA interface chip through the channel.
  • the FPGA interface chip receives the data packet, converts the data packet into a communication signal required by the FPGA, and communicates directly with the FPGA.
  • the method of communicating with the FPGA further includes: the host communicating with the FPGA disconnects the connection with the FPAG interface chip through the release interface.
  • the method of the above embodiments can be implemented by means of software plus the necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is better. ⁇
  • the technical solution of this application essentially or the part that contributes to the existing technology can be embodied in the form of a software product, and the computer software product is stored in a storage medium (such as ROM/RAM, magnetic disk, The optical disc) includes a number of instructions to enable a device (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the method of each embodiment of the present application.

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Abstract

本申请公开了一种与FPGA通信的主机及方法、FPGA接口芯片，软件接口模块定义暴露给上层应用的调用接口，调用接口用于确定传输数据；资源管理模块对主机接口芯片cable对象进行管理，并允许并行化地同时访问至少两个cable对象，cable对象通过调用接口获取传输数据，并将传输数据发送至协议封包模块；协议封包模块接收所述传输数据，根据FPGA的接口协议、与cable对象对应的信道协议，对传输数据进行封装得到数据包，并将数据包发送至主机信道接口模块；主机信道接口模块接收所述数据包，将数据包按与FPGA接口芯片约定的预设数据格式进行封包，通过信道发送。解决了现有接口软件设计中，扩展性差，无法并行使用多种通信资源与FPGA接口芯片进行通信的问题。

Description

与FPGA通信的主机及方法、FPGA接口芯片
相关申请的交叉引用
本申请要求于2019年06月28日提交中国专利局的申请号为201910580647.9、名称为“一种与FPGA通信的主机、FPGA接口芯片”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及可编程逻辑器件领域，更具体地说，涉及一种与FPGA通信的主机及方法、FPGA接口芯片。
背景技术
FPGA(Field Programmable Gate Array，现场可编程门阵列)是一种可编程逻辑器件。在FPGA芯片中，一般都会集成一个片上控制系统。这个片上控制系统允许用户通过JTAG(Joint Test Action Group，联合测试行动小组)、SPI(Serial Peripheral Interface，串行外设接口)等接口对FPGA进行配置、调试以及读写软硬核数据等操作。在通信过程中，上位机可以使用不同的信道来与FPGA进行通信。在接收端，一般有个接口芯片负责接收和发送主机的消息，并用来和FPGA进行直接交互。这个接口芯片构成的子系统一般称为下载器(Cable)。
发明内容
本申请实施例提供的一种与FPGA通信的主机及方法、FPGA接口芯片，主要解决的技术问题在于现有主机接口软件设计中，扩展性差，无法并行使用多种通信资源与FPGA接口芯片进行通信的问题。
第一方面，本申请实施例提供一种与FPGA通信的主机，该与FPGA通信的主机包括：软件接口模块，用于定义暴露给上层应用的调用接口，所述调用接口用于确定传输数据。资源管理模块，用于对主机接口芯片cable对象进行管理，允许并行化地同时访问至少两个cable对象，所述cable对象通过所述调用接口获取所述传输数据，并将所述传输数据发送至协议封包模块。所述协议封包模块，用于接收所述传输数据，根据FPGA的接口协议、与所述cable对象对应的信道协议，对传输数据进行封装得到数据包，并将所述数据包发送至主机信道接口模块。所述主机信道接口模块，用于接收所述数据包，将所述数据包 按与FPGA接口芯片约定的预设数据格式进行封包，通过所述信道发送。
第二方面，本申请实施例提供一种FPGA接口芯片，所述FPGA接口芯片，用于接收权利要求1-9任一项所述的与FPGA通信的主机发送的数据包，将所述数据包转化为FPGA所需的通信信号，与FPGA进行直接通信。
第三方面，本申请实施例提供一种与FPGA通信的方法，包括：与FPGA通信的主机的软件接口模块定义暴露给上层应用的调用接口，所述调用接口可确定传输数据。所述与FPGA通信的主机的资源管理模块对主机接口芯片cable对象进行管理，允许并行化地同时访问至少两个cable对象，所述cable对象通过所述调用接口获取所述传输数据，并将所述传输数据发送至所述与FPGA通信的主机的协议封包模块。所述协议封包模块接收所述传输数据，根据FPGA的接口协议、与所述cable对象对应的信道协议，对传输数据进行封装得到数据包，并将所述数据包发送至所述与FPGA通信的主机的主机信道接口模块。所述主机信道接口模块接收所述数据包，将所述数据包按与FPGA接口芯片约定的预设数据格式进行封包，通过所述信道发送至FPGA接口芯片。所述FPGA接口芯片接收所述数据包，将所述数据包转化为FPGA所需的通信信号，与FPGA进行直接通信。
有益效果
本申请提供一种与FPGA通信的主机、FPGA接口芯片，针对现有主机接口软件设计中，扩展性差，无法并行使用多种通信资源与FPGA接口芯片进行通信的问题，本申请的软件接口模块定义暴露给上层应用的调用接口；资源管理模块对主机接口芯片cable对象进行管理，并允许并行化地同时访问至少两个cable对象，cable对象通用所述调用接口；协议封包模块根据FPGA的接口协议、与cable对象对应的信道协议对传输数据进行封装得到数据包；主机信道接口模块将所述数据包按与FPGA接口芯片约定的预设数据格式进行封包，通过信道发送；即通过将接口软件分层设置，可以并行访问多个接口资源，且使用同样的软件接口，适合FPGA集群资源管理；可移植性强，完全分层后，移植到不同平台，只是主机信道接口不同，而操作流程不需要改变，提升整体的扩展性和可维护性；把FPGA各项通信接口的操作完全抽象化，使得调用接口软件的上层代码不用关心信道、接收端Cable、接口协议的任何细节，而只需要关注于具体FPGA的某个接口的通信流程即可。
附图说明
下面将结合附图及实施例对本申请作进一步说明，附图中：
图1为本申请第一实施例提供的与FPGA通信的主机的结构示意图；
图2-1为本申请第一实施例提供的与FPGA通信的主机和FPGA接口芯片通过以太网连接的示意图；
图2-2为本申请第一实施例提供的与FPGA通信的主机和FPGA接口芯片通过USB或者LPT等线缆连接的示意图；
图2-3为本申请第一实施例提供的与FPGA通信的主机和FPGA接口芯片通过无线网连接的示意图；
图3为本申请第一实施例提供的与FPGA通信的主机通过以太网实现与FPGA接口芯片通信的示意图；
图4为本申请第一实施例提供的预设数据格式的示意图；
图5为本申请第二实施例提供的FPGA接口芯片与FPGA的连接示意图；
图6为本申请第二实施例提供的软件层次结构示意图；
图7为本申请第三实施例提供的与FPGA通信的主机与FPGA进行通信的流程示意图。
[根据细则91更正 24.08.2020]　
图8为本申请第三实施例提供的与FPGA通信的方法的流程示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，下面通过具体实施方式结合附图对本申请实施例作进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
现有的FPGA厂商开发的通信接口软件，都具有一定的局限性。比如只能使用本机的USB接口Cable来与FPGA通信、因不能同时并行地使用多种资源而导致一次只支持一个用户使用、可扩展性不佳等等。虽然有些FPGA厂商也有提出虚拟Cable的概念，比如：Xilinx虚拟连接(Xilinx Virtual Cable)，来让用户在本地虚拟出一个Cable(实际上是通过以太网接口来访问电路板上的FPGA)来当成普通的USB线缆的Cable来使用，但是具体实现的软件却是分开的。这样的话，在书写FPGA某个片上接口的通信流程代码的时候，可能就需要针对 不同的信道分别编写，造成了开发资源的浪费，提升了维护成本。
基于上述，本申请实施例提供了以下方案：
实施例一
本申请实施例通过把FPGA各项通信接口的操作完全抽象化，使得调用接口软件的上层代码不用关心信道、接收端FPGA接口芯片Cable、接口协议的任何细节，而只需要关注于具体FPGA的某个接口的通信流程即可，提升整体软件的扩展性和可维护性。如图1所示，图1为本实施例提供的与FPGA通信的主机，该主机包括但不限于电脑、笔记本等。该主机包括：软件接口模块101，资源管理模块102，协议封闭模块103，主机信道接口模块104；
软件接口模块101，用于定义暴露给上层应用的调用接口，调用接口用于确定传输数据。
资源管理模块102，用于对主机接口芯片cable对象进行管理，允许并行化地同时访问至少两个cable对象，所述cable对象通过所述调用接口获取传输数据，并将传输数据发送至协议封包模块103。
协议封包模块103，用于接收传输数据，根据FPGA的接口协议、与所述cable对象对应的信道协议，对传输数据进行封装得到数据包，并将数据包发送至主机信道接口模块104。
主机信道接口模块104，用于接收数据包，将数据包按与FPGA接口芯片约定的预设数据格式进行封包，通过所述信道发送。
在一些实施例中，通过软件接口模块101暴露给用户的调用接口可确定传输数据；通过资源管理模块102确定与FPGA接口芯片通信的cable对象，进而cable对象通过调用接口获取传输数据，发给协议封包模块103；协议封包模块103根据FPGA的接口协议、与所述cable对象对应的信道协议，对传输数据进行封装得到数据包，并将所述数据包发给主机信道接口模块104。
其中，cable对象不同，对应的信道不同，cable对象包括与USB(Universal Serial Bus，通用串行总线)线缆连接的cable、通过以太网口连接到的电路板上的cable、通过PCIE(peripheral component interconnect express，高速串行计算机扩展总线标准)连接到的PCIE板卡上的cable、与打印机并口连接的cable中的至少一种，其对应的信道分别为USB、以太网口、PCIE、打印机并口。主机信道 接口模块104只负责与信道相关的处理，实现数据封包，然后发送数据的时候，其中需要和FPGA接口芯片约定必要的数据包格式，并按照信道所用的协议规则发送数据包，针对不同的FPGA接口芯片，约定的数据包格式也不同。
在一些实施例中，软件接口模块101作为与FPGA通信的主机的接口软件库，包括暴露给用户的接口，调用接口包括与FPGA进行通信的基本软件接口。如图2-1、图2-2、图2-3所示，与FPGA通信的主机与FPGA接口芯片可以通过以太网、USB或LPT等线缆、Wi-Fi(无线网络)连接。可以理解的是，对于不同的FPGA接口芯片类型，例如USB、以太网、WIFI等，基于的通信流程基本一致，必须需要初始化，进行连接，然后互相读写数据，最后释放。如图3所示，图3为与FPGA通信的主机通过以太网实现与FPGA接口芯片通信流程，可以为：FPGA接口芯片监听某个端口，等待连接；与FPGA通信的主机依据IP(Internet Protocol，网络协议)地址初始化socket(套接字)连接，当连接成功后，与FPGA通信的主机通过socket进行读写数据，FPGA接口芯片解包socket中的数据，并按照数据转化为FPGA所需的信号，之后与FPGA通信的主机释放，socket断开连接；FPGA接口芯片重新监听某个端口。
因此本实施例中，通过软件接口模块101统一抽象形成固定的基本软件接口，用于不同类型的FPGA接口芯片和与FPGA通信的主机通信，即对于上层软件来说，和各个FPGA接口芯片进行通信时，可以使用同样的基本软件接口，因此本实施例中的基本软件接口包括初始化(Init)接口、写入数据(Write)接口、读取数据(Read)接口和释放(Release)接口。例如当与FPGA通信的主机使用以太网与FPGA接口芯片通信时，初始化即使用TCP(Transmission Control Protocol传输控制协议)/IP协议，利用系统的socket，尝试和远程的FPGA接口芯片连接，连接成功后，发送一些数据包进行一定的初始化操作，接口返回。释放也就是断开连接，写入即为往套接字写入二进制数据，读取即为从socket中读取数据。当与FPGA通信的主机使用USB与FPGA接口芯片通信时，初始化即为调用系统接口申请USB设备，并进行初始化操作，释放即为把资源释放给系统，读、写也就是使用系统接口进行数据的读、写。当然，上述在与FPGA通信的主机与FPGA接口芯片间传输的数据都是按照约定的预设数据格式进行封包。
在一些实施例中，在传输数据传递到上述基本软件接口的过程中，需要定义请求对象，请求对象是一个结构体，因此传输数据的结构包括请求对象，所述请求对象包括预定义的操作码、数据、对象、回调函数和扩展的void(无类 型)指针中的至少一种，允许上层代码以统一的形式访问基本软件接口。
在一些实施例中，资源管理模块102管理着所有可用的cable对象，该cable对象可以是真实的，比如USB线缆连接的cable；也可以是虚拟的，比如通过以太网口连接到的电路板上的接口芯片；或者是通过PCIE连接到的PCIE板卡上的接口芯片。资源管理模块102具体对各类cable对象的具体数目，被占用情况进行管理，且允许并行化地同时访问至少两个cable对象，当然该至少两个cable对象并不冲突。在本实施例中，为便于管理各个cable对象，每个cable对象实例都会被分配唯一的MAC地址以及类型标识，以便于区分，进而资源管理模块102可以唯一确定cable对象。
在一些实施例中，为cable对象分配的类型标识用于定义该cable对象的类型属性，该类型标识可以由与FPGA通信的主机自定义设置，例如当cable对象为USB Cable时，对应的类型标识可以是USB；cable对象为以太网虚拟Cable时，对应的类型标识可以是以太网。在一些实施例中，只要能表明cable的类型，类型标识也可以是自定义数字等形式。
其中，不管cable本身有没有真实的MAC，都会给cable分配唯一的MAC地址作为唯一的资源标识。具体的，当所述cable对象为USB Cable时，所述MAC地址为USB的EEPROM中记录的序列号；当所述cable对象为以太网虚拟Cable时，所述MAC地址为以太网虚拟Cable的IP地址或FPGA接口芯片真实MAC地址；当所述cable对象为PCIE板上的Cable时，所述MAC地址为PCIE总线的地址或者是PCIE总线上接口芯片里的序列号；当所述cable对象为打印机并口时，所述MAC地址为并口地址。
此处，可以由用户选择与FPGA接口芯片连接的任意cable对象，具体由资源管理模块102扫描可访问cable对象形成列表后，并提供列表给用户。
在一些实施例中，调用接口包括获取可访问cable对象的探测器(Probe)接口，该Probe接口可探测当前可访问cable对象的使用情况；资源管理模块102形成列表后，通过Probe接口返回给所述上层应用即用户，以便于所述上层应用确定与所述FPGA进行通信的访问cable对象。
在一些实施例中，协议封包模块103主要根据FPGA的接口协议、信道所用协议，对接收的传输数据进行封装。其中，FPGA中的软硬核，一般支持JTAG(Joint Test Action Group，联合测试工作组)、I2C(Inter－Integrated Circuit， 两线式串行总线)、SPI(Serial Peripheral Interface，串行外设接口)、从并等接口，这些接口协议，有时候需要依据协议相关的信息来在应用层进行特殊处理。
比如对于JTAG协议来说，如果存在JTAG链，那么实际上这条链上就会有很多个设备，有些可能是FPGA，有些可能不是。这样，JTAG协议软件在需要的时候，需进行一些处理。比如在写JTAG命令的时候，需要先依据链的情况，写入必要的bypass指令，在写JTAG数据的时候，也要适当补1等等。当传输数据在传递的时候，协议封包模块103也会根据信道所用的协议对传输数据进行再封装，例如使用以太网对应的信道时，则根据TCP/IP协议对传输数据进行再封装，得到发送到主机信道接口模块104的数据包；进而FPGA接口信息把TCP/IP的数据进行解析，然后提取出的内容即为约定的预设数据包格式。
在一些实施例中，主机信道接口模块104与FPGA接口芯片之间，需要约定一定格式的数据，为了便于FPGA接口芯片接收到数据包，并且能解析数据包，约定的预设数据格式与FPGA接口芯片的实现方式相关，因此主机信道接口模块104根据所述FPGA接口芯片的实现方式与所述FPGA接口芯片约定所述预设数据格式。对于电子元件之间的数字信号的通信来说，就是对二进制数据约定一定的格式，然后按照这种格式发送二进制数据。
此处，当所述FPGA接口芯片包括FT2232H的USB接口芯片，所述预设数据格式包括包头和数据，所述包头由命令码与数据长度组成。如图4所示，其中32bits(比特)的命令码决定FPGA接口芯片需要执行的操作，比如进行JTAG协议的状态跳转、设置一些属性、读写JTAG数据等。32bits的数据长度表示后边有多少数据。
在一些实施例中，FPGA接口芯片的实现方式为一个MCU(Microcontroller Unit，微控制单元)配合以太网口芯片，由于FPGA接口芯片可以编程，那么就可以约定FPGA接口芯片收到的网路数据包的内容格式，双方按照对应的约定解包即可。
本实施例提供的与FPGA通信的主机，包括分层的接口软件设计模式，通过软件接口模块101、资源管理模块102、协议封包模块103和主机信道接口模块104，把FPGA各项通信接口的操作完全抽象化，使得调用接口软件的上层代码不用关心信道、接收端Cable、接口协议的任何细节，而只需要关注于具体FPGA的某个接口的通信流程即可，提升整体软件的扩展性和可维护性。
实施例二
本实施例提供一种FPGA接口芯片，如图5所示，该FPGA接口芯片包括FPGA端信道接口模块，FPGA端信道接口模块用于接收与FPGA通信的主机发送的数据包，FPGA接口芯片按与所述与FPGA通信的主机的主机信道接口模块104约定的预设数据格式解析所述数据包，将所述数据包转化为FPGA所需的通信信号，与FPGA进行直接通信。
其中FPGA端信道接口模块解析数据，是芯片级别的行为，也就是直接从信道中读取数据，解析后，就直接转化为FPGA所需的JTAG、SPI等通信信号，与FPGA直接进行通信。
例如，接口芯片为USB Cable，通过USB线获取与FPGA通信的主机的数据，然后转化成JTAG等协议信号，从而和FPGA通信。其中当所述FPGA接口芯片包括FT2232H的USB接口芯片，所述预设数据格式包括包头和数据。所述包头由命令码与数据长度组成，命令码决定接收端接口芯片需要执行的操作，比如进行JTAG协议的状态跳转、设置一些属性、读写JTAG数据等，数据长度表示后边有多少数据。
本实施例提供一种与FPGA通信的接口设计，通过分层来实现接口软件，如图6所示，该接口设计包括：
软件接口：定义暴露给上层应用的接口，包含资源的申请释放接口，获取资源列表的Probe接口，和FPGA直接相关的各个协议的读写接口、初始化接口等，定义了这些基本的接口，就可以把与FPGA通信的主机的接口抽象化为一个个操作单元(operator)。每种类型的operator都实现对应的功能；这些operator只负责数据的直接读写，或者是转译，接口的初始化释放，以及资源情况收集；不同的operator可以依据各自的特点，实现自定义的功能，但是上层函数只关心这些基本的接口。
资源管理：实现资源管理类，负责对cable资源进行管理，允许并行化地同时访问多个通信资源。资源管理层统筹管理所有可用的cable资源，包括各类资源的具体数目，被占用情况等。在资源管理层实现资源申请释放机制，用户申请对象的时候获得句柄对象，往后使用这些句柄对象进行操作。资源管理层需要能够自动扫描当前可用资源，并提供列表给用户，在Probe函数接口中，返回 的就是相关的资源列表；用户选择后，即可并发的访问对应的cable资源；各个cable资源可以通过MAC，类型等唯一区分。对于一个进程来说，这个资源管理对象类是个单例。
Cable对象：这里的Cable对象可以是真实的，比如USB线缆连接的cable，也可以是虚拟的，比如通过以太网口连接到的电路板上的接口芯片，或者是通过PCIE连接到的PCIE板卡上的接口芯片。在软件设计层面，这些都需要抽象化成一个cable对象，Cable对象的目的是整合当前类型cable支持的各类operator，并实现统一的Handle软件接口，这样上层仅传递操作码即可实现数据的读写。Cable对象也需要提供初始化，释放等基本接口，这些接口方法实际上就是调用相关的operator进行资源的申请和释放。
协议封包：这一层主要是把FPGA使用的JTAG，SPI等协议相关的数据按照一定的规则组合成数据包，并发送给底层的operator对象处理。底层的operator只处理和信道相关的细节问题，对于FPGA相关的某些协议操作，则需要实现一些协议operator来包装更为底层的operator来实现，在这一层协议operator中的处理，本质上即把用户传递过来的协议相关的数据包进行拆分或者是重组，然后依次调用基本的读写接口，进行处理。协议的operator需要底层operator，基本所有的底层operator都共用同一个协议相关的operator。
主机信道接口：这一层主要是实现调用系统的驱动接口的一个个底层operator，并按照信道要求把上层传递过来的数据再次封装，然后发送出去，不同的信道可能需要不同的编码方式，这个也和FPGA端的接口相关。数据按照信道要求发送出去后，被FPGA端信道接口接收。由于不同的接收端会有不同的数据封包需求，不过具体的封包情况，其实上层软件并不关心，只需要针对于不同的接收端平台，分别约定即可；然后依据这些约定，实现一个个独立的operator。
FPGA端信道接口：FPGA那一端有接口芯片，比如对USB Cable来说，这个就是带有接口芯片的Cable，它通过USB线获取与FPGA通信的主机的数据，然后转化成JTAG等协议信号，从而和FPGA通信。不同的接口芯片需要做的处理是不同的，这也就是需要与FPGA通信的主机端进行配合，但是大多数情况下，只是如何组合封装数据的差异。接收端所选用的接口硬件可以比较灵活，与FPGA通信的主机端可以按照接收端的硬件自身的要求来封装数据，此时接口硬件芯片需要能够支持对数据进行解包，并转化为FPGA所需的通信信号， 与FPGA进行直接通信。
在本实施例中，分层的接口软件设计模式，使得上层应用不需要再关心任何接口芯片，FPGA自身接口协议等特殊处理的细节，增强了可扩展性，不管信道如何，接口资源暴露给上层应用都是固定的；可并发，对于不冲突的接口资源可以并行访问使用，适合作为Server进程启用，如果能够引入以太网等互联结构，也可以实现一定的分布式特性。对于上层软件而言，和网络中的各个FPGA资源进行通信，可以使用同样的软件接口，适合FPGA集群资源管理；可移植性强，完全分层后，移植到不同平台，只是主机信道接口不同而已，所以替换这一层的各个operator即可实现代码移植，上层的操作流程不需要改变；使用场景更为灵活，支持无线、有线等方式来与FPGA进行通信。
实施例三：
本实施例还对与FPGA通信的主机与FPGA进行通信的通信过程进行说明，如图7所示。
S701、与FPGA通信的主机端根据Probe接口确定与FPAG进行通信的cable资源。
在本实施例中，Probe接口主要是探测当前类型的可访问资源的总数，形成列表，并返回给上层软件，供用户决定使用哪一个cable资源与FPAG进行通信，其中cable资源被分配了一个MAC地址以及类型标识，以区分各个cable资源。假设确定使用USB线缆连接的cable和以太网模拟的cable与FPAG进行通信，其中。
S702、与FPGA通信的主机端通过初始化接口与FPAG的FPAG接口芯片连接。
对于使用以太网的情况，初始化即使用TCP/IP协议，利用系统的socket，尝试和远程的接收端连接；对于USB的情况，初始化即调用系统接口申请USB设备，并进行初始化操作。
S703、当使用写数据接口写入二进制数据时，与FPGA通信的主机端把FPGA使用的接口协议相关的数据按照一定的规则组合成数据包。
对于使用以太网的情况，即往socket写入二进制数据；对于USB的情况， 使用系统接口进行二进制数据的写入；之后使用JTAG、SPI等协议相关的数据，按照一定的规则，将二进制数据组合成数据包。
S704、与FPGA通信的主机端按照预设数据格式组织数据包，然后通过与cable资源对应的信道发送给FPAG接口芯片。
在本实施例中，假设FPAG接口芯片包括FT2232H的USB接口芯片，预设数据格式由包头和数据组成，包头由命令码和数据长度组成。命令码决定接收端接口芯片需要执行的操作，比如进行JTAG协议的状态跳转、设置一些属性、读写JTAG数据等，数据长度表示后边有多少数据。FPAG接口芯片还包括MCU配合以太网口芯片，由于以太网口芯片可以编程，那么就可以约定以太网口芯片收到的网路数据包的内容格式。当然在用以太网时，数据包括传递的时候，使用到的TCP/IP协议也会对数据包括也会进行再封装，然后传递到太网口芯片。
S705、FPAG接口芯片从信道中读取并解析数据包，转化为FPGA所需的通信信号，与FPGA直接进行通信。
FPAG接口芯片按照预设数据格式解析数据包括，当然FPAG接口芯片发送数据回与FPGA通信的主机端时，也按照预设的预设数据格式进行封包。
S706，与FPGA通信的主机端通过释放接口断开与FPAG接口芯片的连接。
本申请实施例还提供一种与FPGA通信的方法，如图8所示，可通过如下步骤实现：
S11、与FPGA通信的主机的软件接口模块101定义暴露给上层应用的调用接口，调用接口可确定传输数据。
S12、与FPGA通信的主机的资源管理模块102对主机接口芯片cable对象进行管理，允许并行化地同时访问至少两个cable对象，cable对象通过调用接口获取传输数据，并将传输数据发送至与FPGA通信的主机的协议封包模块103。
S13、协议封包模块103接收所述传输数据，根据FPGA的接口协议、与cable对象对应的信道协议，对传输数据进行封装得到数据包，并将数据包发送至与FPGA通信的主机的主机信道接口模块104。
S14、主机信道接口模块104接收所述数据包，将数据包按与FPGA接口芯片约定的预设数据格式进行封包，通过信道发送至FPGA接口芯片。
S15、FPGA接口芯片接收数据包，将数据包转化为FPGA所需的通信信号， 与FPGA进行直接通信。
在此基础上，在FPGA接口芯片接收数据包之后，与FPGA通信的方法还包括：与FPGA通信的主机通过释放接口断开与FPAG接口芯片的连接。
本申请实施例提出的与FPGA通信的方法的解释说明和有益效果，均与前述实施例所述的与FPGA通信的主机的解释说明和有益效果相同，在此不再赘述。需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台装置(可以是手机，计算机，服务器，空调器，或者网络设备等)执行本申请各个实施例的方法。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，这些均属于本申请的保护之内。
以上所述仅为本申请的优选实施例而已，并不用于限制本申请，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。
以上所述仅为本申请的优选实施例而已，并不用于限制本申请，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则 之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种与FPGA通信的主机，其特征在于，所述主机包括：
    软件接口模块，用于定义暴露给上层应用的调用接口，所述调用接口用于确定传输数据；
    资源管理模块，用于对主机接口芯片cable对象进行管理，允许并行化地同时访问至少两个cable对象，所述cable对象通过所述调用接口获取所述传输数据，并将所述传输数据发送至协议封包模块；
    所述协议封包模块，用于接收所述传输数据，根据FPGA的接口协议、与所述cable对象对应的信道协议，对传输数据进行封装得到数据包，并将所述数据包发送至主机信道接口模块；
    所述主机信道接口模块，用于接收所述数据包，将所述数据包按与FPGA接口芯片约定的预设数据格式进行封包，通过所述信道发送。
  2. 如权利要求1所述的与FPGA通信的主机，其特征在于，所述与FPGA通信的主机还包括释放接口模块；所述释放接口模块，用于在所述主机信道接口模块发出所述数据包后，使与FPGA通信的主机和FPAG接口芯片断开连接。
  3. 如权利要求1所述的与FPGA通信的主机，其特征在于，所述调用接口包括与FPGA进行通信的基本软件接口，所述基本软件接口包括初始化Init接口、写入数据Write接口、读取数据Read接口和释放Release接口。
  4. 如权利要求1所述的与FPGA通信的主机，其特征在于，所述cable对象包括请USB线缆连接的cable、通过以太网口连接到的电路板上的cable、通过PCIE连接到的PCIE板卡上的cable、打印机并口的至少一种。
  5. 如权利要求4所述的与FPGA通信的主机，其特征在于，所述cable对 象被分配用于区分唯一的MAC地址以及类型标识。
  6. 如权利要求5所述的与FPGA通信的主机，其特征在于，当所述cable对象为USB Cable时，所述MAC地址为USB的EEPROM中记录的序列号；
    当所述cable对象为以太网虚拟Cable时，所述MAC地址为以太网虚拟Cable的IP地址或FPGA接口芯片真实MAC地址；
    当所述cable对象为PCIE板上的Cable时，所述MAC地址为PCIE总线的地址或者是PCIE总线上接口芯片里的序列号；
    当所述cable对象为打印机并口时，所述MAC地址为并口地址。
  7. 如权利要求4所述的与FPGA通信的主机，其特征在于，所述资源管理模块，还用于扫描允许访问的cable对象，并形成列表。
  8. 如权利要求7所述的与FPGA通信的主机，其特征在于，所述调用接口还包括获取可访问cable对象的Probe接口；
    所述资源管理模块扫描访问cable对象形成列表后，通过所述Probe接口返回给所述上层应用，以便于所述上层应用确定与所述FPGA进行通信的访问cable对象。
  9. 如权利要求1-8任一项所述的与FPGA通信的主机，其特征在于，所述主机信道接口模块根据所述FPGA接口芯片的实现方式与所述FPGA接口芯片约定所述预设数据格式。
  10. 如权利要求9所述的与FPGA通信的主机，其特征在于，当所述FPGA接口芯片包括FT2232H的USB接口芯片时，所述预设数据格式包括包头和数据，所述包头由命令码与数据长度组成。
  11. 一种FPGA接口芯片，其特征在于，所述FPGA接口芯片，用于接收权利要求1-10任一项所述的与FPGA通信的主机发送的数据包，将所述数据包转化为FPGA所需的通信信号，与FPGA进行直接通信。
  12. 如权利要求11所述的FPGA接口芯片，其特征在于，所述FPGA接口芯片包括以太网、USB、LTP、无线网络。
  13. 如权利要求12所述的FPGA接口芯片，其特征在于，当所述FPGA接口芯片包括FT2232H的USB接口芯片，所述预设数据格式包括包头和数据，所述包头由命令码与数据长度组成。
  14. 如权利要求11所述的FPGA接口芯片，其特征在于，所述FPGA芯片通过初始化接口和所述与FPGA通信的主机连接。
  15. 如权利要求11所述的FPGA接口芯片，其特征在于，所述FPGA支持的接口协议包括JTAG、I2C、SPI、从并接口。
  16. 如权利要求11所述的FPGA接口芯片，其特征在于，所述FPGA接口芯片包括信道接口模块；所述信道接口模块，用于接收权利要求1-9任一项所述的与FPGA通信的主机发送的数据包。
  17. 一种与FPGA通信的方法，其特征在于，包括：
    与FPGA通信的主机的软件接口模块定义暴露给上层应用的调用接口，所述调用接口可确定传输数据；
    所述与FPGA通信的主机的资源管理模块对主机接口芯片cable对象进行管理，允许并行化地同时访问至少两个cable对象，所述cable对象通过所述调用接口获取所述传输数据，并将所述传输数据发送至所述与FPGA通信的主机的 协议封包模块；
    所述协议封包模块接收所述传输数据，根据FPGA的接口协议、与所述cable对象对应的信道协议，对传输数据进行封装得到数据包，并将所述数据包发送至所述与FPGA通信的主机的主机信道接口模块；
    所述主机信道接口模块接收所述数据包，将所述数据包按与FPGA接口芯片约定的预设数据格式进行封包，通过所述信道发送至FPGA接口芯片；
    所述FPGA接口芯片接收所述数据包，将所述数据包转化为FPGA所需的通信信号，与FPGA进行直接通信。
  18. 如权利要求15所述的与FPGA通信的方法，其特征在于，在所述FPGA接口芯片接收所述数据包之后，所述与FPGA通信的方法还包括：
    所述与FPGA通信的主机通过释放接口断开与所述FPAG接口芯片的连接。
  19. 如权利要求17或18所述的与FPGA通信的主机，其特征在于，所述资源管理模块对主机接口芯片cable对象进行管理，包括：
    所述资源管理模块扫描允许访问的cable对象，并形成列表。
  20. 如权利要求19所述的与FPGA通信的主机，其特征在于，所述调用接口还包括获取可访问cable对象的Probe接口；
    所述资源管理模块对主机接口芯片cable对象进行管理，还包括：
    所述资源管理模块扫描访问cable对象形成列表后，通过所述Probe接口返回给所述上层应用，以便于所述上层应用确定与所述FPGA进行通信的访问cable对象。
PCT/CN2020/097858 2019-06-28 2020-06-24 与fpga通信的主机及方法、fpga接口芯片 WO2020259523A1 (zh)

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