WO2020258843A1 - 显示装置及其驱动方法 - Google Patents

显示装置及其驱动方法 Download PDF

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Publication number
WO2020258843A1
WO2020258843A1 PCT/CN2020/071218 CN2020071218W WO2020258843A1 WO 2020258843 A1 WO2020258843 A1 WO 2020258843A1 CN 2020071218 W CN2020071218 W CN 2020071218W WO 2020258843 A1 WO2020258843 A1 WO 2020258843A1
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data
original data
sub
buffer
display
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PCT/CN2020/071218
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English (en)
French (fr)
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解红军
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昆山国显光电有限公司
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Publication of WO2020258843A1 publication Critical patent/WO2020258843A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0457—Improvement of perceived resolution by subpixel rendering

Definitions

  • the embodiments of the present application relate to the field of display technology, for example, to a display device and a driving method thereof.
  • the sub-pixel rendering (SPR) technology can effectively increase the number of pixels per inch of the display device.
  • the display area of the display panel is divided into multiple display areas driven by multiple drive chips accordingly.
  • the client cannot provide the driver chip with redundant data of the display area adjacent to the display area corresponding to the driver chip, which causes the driver chip to fail to perform the normal SPR algorithm, and split screens will appear near the border between adjacent display areas Problems or problems with bright or dark lines.
  • the present application provides a display device and a driving method thereof, so that the first driving chip and the second driving chip can perform a normal algorithm corresponding to the first sub-pixel arrangement, which effectively avoids when the sub-pixels in the display panel follow the first sub-pixel arrangement.
  • the adjacent display areas corresponding to different drive chips have abnormal display problems such as split screen or bright lines.
  • the embodiment of the present application provides a display device, including:
  • a display panel the sub-pixels of the display panel are arranged in a first sub-pixel arrangement, the display panel includes a plurality of display areas arranged along the row direction of the sub-pixel arrangement, the first display area and the second display area are Two adjacent display areas are provided with a first boundary area located in the first display area and a first boundary area located in the second display area around the boundary between the first display area and the second display area. 2. Border zone;
  • a first driving chip and a second driving chip connected to the display panel
  • a programmable device is electrically connected to the first driving chip and the second driving chip, and the programmable device is configured to include the first original data and the first corresponding to the second boundary area Sending first data of a redundant data to the first driver chip, and sending second data including the second original data and second redundant data corresponding to the first boundary area to the second driver chip;
  • the first original data, the second original data, the first redundant data, and the second redundant data are all image data with a second sub-pixel arrangement;
  • a motherboard the motherboard is electrically connected to the programmable device, and is configured to send first original data corresponding to the first display area and second original data corresponding to the second display area to the programmable device;
  • the first driving chip is configured to drive the first display area for display according to the algorithm corresponding to the first sub-pixel arrangement and the first data
  • the second driving chip is configured to display according to the algorithm corresponding to the first sub-pixel arrangement.
  • the algorithm of the sub-pixel arrangement and the second data drive the second display area for display.
  • the embodiment of the present application also provides a method for driving a display device, which is executed by the display device according to any embodiment of the present application, and the driving method includes:
  • the main board sends the first original data corresponding to the first display area and the second original data corresponding to the second display area to the programmable device;
  • the programmable device sends the first data including the first original data and the first redundant data corresponding to the second boundary area to the first driving chip, and sends the first data including the second original data and the corresponding first data Sending the second data of the second redundant data of a boundary area to the second driving chip;
  • the first driving chip drives the first display area for display according to the algorithm corresponding to the first sub-pixel arrangement and the first data
  • the second driving chip according to the algorithm corresponding to the first sub-pixel arrangement
  • the second data drives the second display area for display.
  • FIG. 1 is a schematic structural diagram of a display device provided by an embodiment of the application.
  • FIG. 2 is a schematic structural diagram of a programmable device provided by an embodiment of the application.
  • FIG. 3 is a schematic structural diagram of another programmable device provided by an embodiment of the application.
  • FIG. 4 is a schematic flowchart of a method for driving a display device according to an embodiment of the application.
  • the embodiment of the application provides a display device, including a motherboard, a programmable device, a display panel, and a plurality of driving chips.
  • the sub-pixels of the display panel are arranged in a first sub-pixel arrangement, and the display panel includes a row direction along the sub-pixels.
  • a plurality of display areas are set, the first display area and the second display area are two adjacent display areas, and a first boundary located in the first display area is arranged around the boundary between the first display area and the second display area Area and a second border area located in the second display area.
  • the main board is electrically connected to the programmable device, and is configured to send the first original data corresponding to the first display area and the second original data corresponding to the second display area to the programmable device.
  • the programmable device is electrically connected to a plurality of driving chips and is set to Send the first data including the first original data and the first redundant data corresponding to the second boundary area to the first driver chip, and send the first data including the second original data and the second redundant data corresponding to the first boundary area
  • the second data is sent to the second driver chip; wherein, the first original data, the second original data, the first redundant data and the second redundant data are all image data with a second sub-pixel arrangement, and the first driver
  • the chip is electrically connected to the display panel, and is configured to drive the first display area for display according to the algorithm corresponding to the first sub-pixel arrangement and the first data
  • the second driving chip is electrically connected to the display panel, and is configured to arrange according to the corresponding first sub-pixel
  • the algorithm of the method and the second data drive the second display area for display.
  • SPR Sub-pixel Rendering
  • a single driver chip cannot support the display of the display device.
  • Two or more driver chips are required, and the display area of the display panel is divided into multiple displays driven by multiple driver chips. area.
  • the driver chip needs to obtain the redundant data of the display area adjacent to the display area corresponding to the driver chip to implement the SPR algorithm, but the client cannot provide the driver chip with the corresponding driver chip
  • the driver chip cannot obtain the redundant data of the display area adjacent to the display area corresponding to the driver chip, which causes the driver chip to fail to perform the normal SPR algorithm.
  • a specially customized driver chip can be used to realize the transmission of redundant data between the driver chips corresponding to adjacent display areas.
  • a serial peripheral interface Serial Peripheral Interface, SPI
  • an integrated circuit bus Inter-Integrated Circuit, The I 2 C
  • SPI Serial Peripheral Interface
  • I 2 C Inter-Integrated Circuit
  • the drive chip corresponding to the adjacent display area of the display area provides redundant data, and the client cannot provide the corresponding redundant data for the drive chip.
  • the display panel with SPR pixel arrangement it is impossible to avoid between adjacent display areas. There will be split screen problems or bright or dark lines near the border of.
  • the display device uses a programmable device to enable the first driver chip to obtain the first data including the first redundant data corresponding to the second boundary area, and enable the second driver chip to obtain the first data including the corresponding first
  • the second data of the second redundant data in the boundary area in turn enables the first driver chip and the second driver chip to perform normal algorithms corresponding to the first sub-pixel arrangement, which effectively avoids when the sub-pixels in the display panel follow the
  • the adjacent display areas corresponding to different driving chips have abnormal display problems such as split screens or bright lines.
  • FIG. 1 is a schematic structural diagram of a display device provided by an embodiment of the application.
  • the display device includes a main board 1, a programmable device 2, a display panel 3, and a plurality of driving chips.
  • FIG. 1 only exemplarily shows that the display device includes a first driving chip 41 and a second driving chip 42.
  • the driver chip, the sub-pixels of the display panel 3 are arranged according to the first sub-pixel arrangement.
  • the display panel 3 includes a plurality of display areas arranged along the row direction of the sub-pixel arrangement.
  • the first display area A1 and the second display area A2 are adjacent Around the boundary a between the first display area A1 and the second display area A2, there are a first boundary area B1 located in the first display area A1 and a second boundary area B2 located in the second display area A2. .
  • the main board 1 is electrically connected to the programmable device 2, and is configured to send the first original data corresponding to the first display area A1 and the second original data corresponding to the second display area A2 to the programmable device 2.
  • the arrow d1 in Figure 1 represents the main board 1 is the first original data sent, arrow d2 represents the second original data sent by the main board 1.
  • the programmable device 2 is electrically connected to the first driving chip 41 and the second driving chip 42, and is set to contain the first original data d1 and
  • the first data d10 corresponding to the first redundant data of the second boundary area B2 is sent to the first driving chip 41, and the second data d10 that contains the second original data d2 and the second redundant data corresponding to the first boundary area B1
  • the data d20 is sent to the second driving chip 42, and the first original data d1, the second original data d2, the first redundant data, and the second redundant data are all image data with a second sub-pixel arrangement.
  • the first sub-pixel arrangement can be set to SPR arrangement, that is, there is a sub-pixel borrowing relationship between pixels.
  • three adjacent pixels include R pixels and G pixels, B pixels and R pixels, and G pixels.
  • B pixels adjacent pixels are related to each other
  • the second sub-pixel arrangement can be set to Real RGB arrangement, that is, each pixel is composed of three sub-pixels of R pixel, G pixel and B pixel.
  • the first original data d1 and the second original data d2 are image data with a second sub-pixel arrangement, that is, the first original data d1 is image data corresponding to the first display area A1 and corresponding to the sub-pixels arranged in Real RGB, and the second The original data d2 is image data corresponding to the second display area A2 and corresponding to the sub-pixels arranged in Real RGB.
  • the first redundant data and the second redundant data are also image data with a second sub-pixel arrangement.
  • the first redundant data is image data corresponding to the second boundary area B2 and corresponding to the sub-pixels arranged in Real RGB.
  • the second redundant data is image data corresponding to the first boundary area B1 and corresponding to the sub-pixels arranged in Real RGB.
  • the programmable device 2 may use a field programmable gate array (Field Programmable Gate Array, FPGA) chip or a complex programmable logic device (Complex Programmable Logic Device, CPLD) chip, which can combine the first redundant data with the second The redundant data is burned in the programmable device 2 in advance.
  • FPGA Field Programmable Gate Array
  • CPLD Complex Programmable Logic Device
  • the programmable device 2 receives the first original data d1 and the second original data d2 sent by the main board 1, and the programmable device 2 provides the first data d10 to the first driving chip 41 And when the second data d20 is provided to the second driving chip 42, the programmable device 2 can call the corresponding first redundant data and second redundant data so that the first data d10 contains the first data corresponding to the first display area A1
  • the second data d20 includes the second original data d2 corresponding to the second display area A2 and the second redundant data corresponding to the first border area B1 .
  • the first driving chip 41 is electrically connected to the display panel 3, and is configured to drive the first display area A1 for display according to the algorithm corresponding to the first sub-pixel arrangement, that is, the SPR algorithm and the first data d10, and the second driving chip 42 and the display panel 3 Electrical connection, set to drive the second display area A2 for display according to the algorithm corresponding to the first sub-pixel arrangement, that is, the SPR algorithm and the second data d20.
  • the drive chips are connected in cascade mode.
  • One drive chip is the main control drive chip, and the timing controller (TCON) function is enabled, and the rest are driven
  • the chip is a slave driving chip, which turns off the TCON function and receives the synchronization signal sent by the master driving chip, that is, all slave driving chips follow the driving sequence of the active driving chip.
  • the embodiment of the present application compares the first driving chip 41 and the second driving chip 42 Which drive chip is the master drive chip is not limited.
  • the first driving chip 41 receives the first original data d1 corresponding to the first display area A1 in the Real RGB format and the first data d10 corresponding to the first redundant data of the second boundary area B2, and adopts The SPR algorithm converts the first data d10 in the Real RGB format into image data in the SPR format, and sends light-emitting drive signals to the sub-pixels in the first display area A1 of the display panel 3 corresponding to the converted image data.
  • the second driving chip 42 receives the second original data d2 corresponding to the second display area A2 in the Real RGB format and the second data d20 corresponding to the second redundant data of the first boundary area B1, and adopts SPR
  • the algorithm converts the second data d20 in the Real RGB format into image data in the SPR format, and sends light-emitting drive signals to the sub-pixels in the second display area A2 of the display panel 3 corresponding to the converted image data.
  • the setting of the programmable device 2 enables the first driver chip 41 to obtain the first redundant data corresponding to the second boundary area B2, and enables the second driver chip 42 to obtain the second redundant data corresponding to the first boundary area B1, thereby
  • the first driver chip 41 and the second driver chip 42 can perform the normal SPR algorithm, that is, the first driver chip 41 and the second driver chip 42 can convert the image data in the Real RGB format into the image data in the SPR format, which solves the problem of the motherboard
  • the driver chip cannot provide the redundant data of the display area adjacent to the display area corresponding to the driver chip, and the driver chip cannot obtain the redundant data of the display area adjacent to the display area corresponding to the driver chip, thereby causing the driver
  • the chip cannot perform the normal SPR algorithm, and there will be a split screen problem or a bright or dark line problem near the border between adjacent display areas. At the same time, there is no need to use a specially customized driver chip. Only a conventional driver chip can achieve the relative performance. The acquisition of the redundant data corresponding to the adjacent
  • FIG. 1 only exemplarily provides that the display device includes two driver chips, a first driver chip 41 and a second driver chip 42, and the display panel 3 includes two display areas, a first display area A1 and a second display area A2.
  • the display panel includes more display areas and drive chips.
  • the first display area A1 and the second display area A2 can represent any two adjacent display areas, and the first drive chip 41 and the second drive chip 42 correspond to any of the foregoing Driver chips for two adjacent display areas.
  • the portion of the boundary area located in the first display area A1 is defined as the first boundary area B1, and the boundary area is located
  • the department of the second display area A2 is defined as the second boundary area B2.
  • the size of the boundary area depends on the pixel format conversion of the first driver chip 41 and the second driver chip 42, namely Real RGB format original data and redundancy
  • the number of pixels that need to be borrowed when the data is converted into the image data in the SPR format the embodiment of the present application does not limit the size of the border area.
  • Real RGB format image data is converted into SPR format image data through algorithms.
  • FIG. 2 is a schematic structural diagram of a programmable device provided by an embodiment of the application. With reference to Figures 1 and 2, it can be set that the programmable device 2 includes two buffers, a first buffer 21 and a second buffer 22.
  • the first buffer 21 is set to receive the first original data sent by the motherboard 1 in the first period of time.
  • the first driving chip 41 in the second time period including the first original data d1 received by the first buffer 21 in the first time period and the first redundant data corresponding to the second boundary area B2 The first data d10 of the first data d10, and the second drive chip 42 that includes the second original data d2 received by the first buffer 21 in the first time period and the second redundant data corresponding to the first boundary area B1.
  • the second buffer 22 is configured to receive the first original data d1 and the second original data d2 sent by the main board 1 in the second time period, and send to the first driver chip 41 in the third time period including the second buffer 22 in the second time period.
  • the received first original data d1 and the first data d10 corresponding to the first redundant data of the second boundary area B2, and the transmission to the second driving chip 42 in the third period includes the second buffer 22 received in the second period
  • the corresponding redundant data can be programmed into each buffer in advance.
  • the first buffer 21 receives the first original data d1 and the second original data sent by the main board 1.
  • the first buffer 21 sends to the first driver chip 41 the first data containing the first original data d1 received by the first buffer 21 in the first period and the first redundant data corresponding to the second boundary area B2.
  • the second buffer 22 receives the first original data d1 and the second original data d2 sent by the main board 1. In the third period, the second buffer 22 sends to the first driver chip 41 the first data containing the first original data d1 received by the second buffer 22 in the second period and the first redundant data corresponding to the second boundary area B2. A data d10 and second data d20 including the second original data d2 received by the second buffer 22 in the second period and the second redundant data corresponding to the first boundary area B1 are sent to the second driving chip 42.
  • one of the two buffers receives the original data sent by the main board 1, and the other buffer sends the original data received in the previous period and the corresponding redundant data to the corresponding
  • the driver chip drives the sub-pixels in the display panel 3 for display.
  • the transceiver functions of the two buffers are reversed, that is, the buffer that realized the receiving function in the previous period will contain the original data received in the previous period and the first data of the corresponding redundant image data or
  • the second data is sent to the corresponding driving chip, and the driving chip drives the sub-pixels in the display panel 3 to display accordingly.
  • the buffer that realized the sending function in the previous period receives the original data sent by the main board 1 during this period.
  • Each buffer adopts a ping-pong working mode, that is, at different time periods, the receiving and sending functions of the two buffers are inverted, and the alternating period of the image data receiving and sending period can correspond to the display period corresponding to one frame of display screen, which realizes the display function of the display panel 3, and
  • the programmable device 2 enables the first driver chip 41 to obtain the first redundant data corresponding to the second boundary area B2, and enables the second driver chip 42 to obtain the second redundant data corresponding to the first boundary area B1, which effectively avoids
  • the adjacent display areas corresponding to different driving chips may be split-screen or bright lines and other abnormal display problems may occur.
  • both the first buffer 21 and the second buffer 22 can be set to be line buffers, and the first buffer 21 is set to receive the first buffer corresponding to the i-th row of sub-pixels sent by the main board 1 in the first time period.
  • the original data d1 and the second original data d2, and the first original data d1 corresponding to the sub-pixels in the i-th row and the first redundant data corresponding to the sub-pixels in the i-th row are sent to the first driving chip 41 in the second period
  • the first data d10 and the second data d20 containing the second original data d2 corresponding to the sub-pixels in the i-th row and the second redundant data corresponding to the sub-pixels in the i-th row are sent to the second driving chip 42 in the second period.
  • the second buffer 22 is configured to receive the first original data d1 and the second original data d2 corresponding to the sub-pixels in the i+1th row sent by the main board 1 in the second period, and send to the first driving chip 41 in the third period. Contains the first original data d1 corresponding to the sub-pixels in the i+1th row and the first data d10 corresponding to the first redundant data of the sub-pixels in the i+1th row, and sends to the second driving chip 42 in the third time interval containing There are second original data d2 corresponding to the sub-pixels in the i+1th row and second data d20 corresponding to the second redundant data of the sub-pixels in the i+1th row, and i is a positive integer.
  • the first buffer 21 may receive, for example, the first original data d1 and the second original data d2 corresponding to the first row of sub-pixels in the display panel 3 sent by the main board 1, that is, the first buffer 21 is in the first period The original data corresponding to the sub-pixels in the first row of the display panel 3 is received.
  • the first original data d1 and the second original data d2 corresponding to the first row of sub-pixels in the display panel 3 both include H sub-pixel data
  • the first original The data d1 is H sub-pixel data corresponding to the first row of sub-pixels in the first display area A1
  • the second original data d2 is H sub-pixel data corresponding to the first row of sub-pixels in the second display area A2.
  • the first buffer 21 sends to the first driver chip 41 the first original data d1 containing the first row of sub-pixels corresponding to the first display area A1 received by the first buffer 21 in the first period and the corresponding The first data d10 of the first redundant data of the first row of sub-pixels in the second boundary area B2 and the corresponding second display area A2 received by the first buffer 21 in the first period are sent to the second driving chip 42
  • the second original data d2 of the first row of sub-pixels and the second data d20 corresponding to the second redundant data of the first row of sub-pixels in the first boundary area B1 that is, the first buffer 21 realizes the corresponding The transmission of image data corresponding to the first row of sub-pixels of the driver chip.
  • the second buffer 22 receives the first original data d1 and the second original data d2 corresponding to the second row of sub-pixels in the display panel 3 sent by the main board 1, that is, the second buffer 22 realizes the correspondence in the second period The raw data of the sub-pixels in the second row of the display panel 3 is received.
  • the sub-pixels arranged in SPR are in adjacent display areas.
  • the number of sub-pixels borrowed between the first display area A1 and the second display area A3 is For example, x, x may be the smallest unit 6 borrowed by sub-pixels, then the first redundant data corresponding to the second boundary area B1 includes 6 pixel data, and the second redundant data set corresponding to the first boundary area B2 also includes 6 Pixel data, the first data d10 sent by the first buffer 21 to the first driver chip 41 in the second period includes H plus 6 pixel data, and the first buffer 21 sent to the second driver chip 42 in the second period The second data d20 includes H plus 6 pixel data.
  • the second buffer 22 sends to the first driver chip 41 the first raw data d1 containing the second row of sub-pixels corresponding to the first display area A1 received by the second buffer 22 in the second period and the corresponding The first data d10 of the first redundant data of the second row of sub-pixels in the second boundary area B2 and the corresponding second display area A2 received by the second buffer 22 in the second period are sent to the second driving chip 42
  • the second original data d2 of the second row of sub-pixels and the second data d20 corresponding to the second redundant data of the second row of sub-pixels in the first boundary area B1 that is, the second buffer 22 realizes the corresponding The driver chip corresponding to the second row of sub-pixel data transmission.
  • the first data d10 sent by the second buffer 22 to the first driver chip 41 in the third period includes H plus 6 pixel data
  • the second buffer 22 sends the first data to the second driver chip 42 in the third period.
  • the second data d20 includes H plus 6 pixel data.
  • the first buffer 21 and the second buffer 22 are both line buffers, and in the same period, one of the two line buffers receives the original data corresponding to the i-th row sub-pixels sent by the main board 1, and one The row buffer sends the first data or second data containing the original data corresponding to the sub-pixels of the i-1th row and the redundant data corresponding to the i-1th row received in the previous period to the corresponding driving chip, and the driving chip Accordingly, the sub-pixels in the i-1th row in the display panel 3 are driven for display.
  • the transceiver functions of the two line buffers are inverted, that is, the line buffer that realizes the receiving function in the previous period will contain the original data corresponding to the i-th row of sub-pixels received in the previous period and the corresponding
  • the first data or the second data of the redundant image data of the i line is sent to the corresponding driving chip, and the driving chip drives the sub-pixels in the i-th row of the display panel 3 to display, and the line buffer that realizes the sending function in the previous period
  • the original data corresponding to the sub-pixels of the i+1th row sent by the main board 1 is received.
  • the two row buffers adopt the ping-pong mode of operation, that is, in different periods, the transceiver functions of the two row buffers are reversed, which realizes
  • Each row of sub-pixels in the display panel 3 is driven row by row, and the programmable device 2 is used to enable the first driving chip 41 to obtain the first redundant data corresponding to the second boundary area B2, and to enable the second driving chip 42 to obtain Corresponding to the second redundant data of the first boundary area B1, so that the first driving chip 41 and the second driving chip 42 can perform the normal algorithm corresponding to the first sub-pixel arrangement, effectively avoiding the problem of sub-pixels in the display panel.
  • the adjacent display areas corresponding to different driving chips have abnormal display problems such as split screens or bright lines.
  • FIG. 3 is a schematic structural diagram of another programmable device provided by an embodiment of the application.
  • the programmable device 2 may also include a plurality of first interfaces 5 and a plurality of second interfaces 6, and the two buffers are both electrically connected to the plurality of first interfaces 5 and the plurality of second interfaces 6.
  • the multiple first interfaces 5 are electrically connected to the main board 1, and the multiple second interfaces 6 are electrically connected to multiple driving chips.
  • Figure 3 exemplarily sets the display device to include two drive chips, a first drive chip 41 and a second drive chip 42.
  • the drive chips are arranged in one-to-one correspondence with the first interface 5, and the first interface 5 and the second interface 6 are arranged in one-to-one correspondence That is, it is exemplarily set that the programmable device 2 includes two first interfaces 5 and two second interfaces 6, the first buffer 21 is electrically connected to the two first interfaces 5 and the two second interfaces 6, and the second The buffer 22 is electrically connected to the two first interfaces 5 and the two second interfaces 6, the two first interfaces 5 are electrically connected to the motherboard 1, and the two second interfaces 6 are electrically connected to the first driving chip 41 and the second driving chip. 42 electrical connection.
  • the two first interfaces 5 are configured to receive the first original data d1 and the second original data d2 sent by the main board 1, decode the first original data d1 and the second original data d2, and send them to the corresponding buffers.
  • the first interface 51 receives the first original data d1 corresponding to the first display area A1 sent by the main board 1, and decodes the first original data d1 and sends it to the corresponding buffer.
  • the first interface 52 receives the first original data d1 sent by the main board 1.
  • the corresponding buffer may refer to the first buffer 21 and the second buffer 22 in the period A buffer that implements the receiving function.
  • the two second interfaces 6 are configured to receive the first data d10 and the second data d20 sent by the corresponding buffers, encode the first data d10 and the second data d20, and then send them to the corresponding drive chip.
  • the corresponding buffers can be Refers to the buffers in the first buffer 21 and the second buffer 22 that implement the sending function in this period.
  • the second interface 61 receives the first data d10 corresponding to the first display area A1 sent by the corresponding buffer, decodes the first data d10 and sends it to the first driver chip 41, and the second interface 62 receives the corresponding buffer
  • the second data d20 corresponding to the second display area A2 sent by the driver and decoded the second data d20 are sent to the second driving chip 42.
  • the two first interfaces 5 decode the first original data d1 and the second original data d2 in line units, and the decoded ones will correspond to one line.
  • the decoded first original data d1 and second original data d2 of the pixel are sent to the buffer that performs the receiving function in this period, and the two second interfaces 6 also receive the first data sent by the buffer that performs the sending function in this period in line units.
  • Data d10 and second data d20 and send the encoded first data d10 and second data d20 corresponding to one row of sub-pixels to the corresponding driving chip.
  • the first interface 5 may adopt a Mobile Industry Processor (MIPI) interface, a Low Voltage Differential Signaling (LVDS) interface, or a High Definition Multimedia (High Definition Multimedia) interface.
  • MIPI Mobile Industry Processor
  • LVDS Low Voltage Differential Signaling
  • High Definition Multimedia High Definition Multimedia
  • HDMI High Definition Multimedia
  • the second interface 6 adopts one of MIPI interface, LVDS interface or HDMI interface
  • the first interface 5 and the second interface 6 are of the same type, for example, the first interface 5 and the second interface 6 can all be MIPI interfaces, or all LVDS interfaces, or all HDMI interfaces
  • Figure 3 exemplarily sets the first interface 5 and the second interface 6 to adopt MIPI interfaces
  • the second original data d2 the first data d10
  • the second data d20 all include five signals CLK and D0 to D3 corresponding to the MIPI interface shown in FIG.
  • the motherboard 1 can be provided with corresponding MIPI interfaces to connect with the two first interfaces 5 to realize the transmission of original data without redundant data.
  • the drive chip is also equipped with corresponding MIPI interfaces to connect with the corresponding two second interfaces 6 to realize The first data d10 and the second data d20 with redundant data corresponding to the display area are received.
  • the display device may also include a flexible circuit board (not shown in FIGS. 1 to 3), a plurality of driving chips provide display signals to the sub-pixels in the display panel 3 through the flexible circuit board, and the programmable device 2 It is set on the main board 1, and the programmable device 2 can also be set on the flexible circuit board to prevent the programmable device 2 from affecting the frame width of the display panel 3.
  • a flexible circuit board not shown in FIGS. 1 to 3
  • a plurality of driving chips provide display signals to the sub-pixels in the display panel 3 through the flexible circuit board
  • the programmable device 2 It is set on the main board 1, and the programmable device 2 can also be set on the flexible circuit board to prevent the programmable device 2 from affecting the frame width of the display panel 3.
  • the driver chip may further include an initialization port c1, and the main board 1 initializes the driver chip through the initialization port.
  • the motherboard 1 can write reference values to the registers in the driver chip through the initialization port of the driver chip, without signal processing, so the initialization port of the driver chip is directly electrically connected to the motherboard 1, without going through the programmable device 2. This port can use SPI interface to realize signal transmission.
  • the display device may be an organic light-emitting display device or a liquid crystal display device.
  • the display device may be a mobile phone, or may be an electronic device such as a computer or a wearable device.
  • the embodiment of the present application does not limit the form of the display device.
  • FIG. 4 is a schematic flowchart of a method for driving a display device provided by an embodiment of this application.
  • the driving method can be executed by the display device of the above-mentioned embodiment, as shown in FIG.
  • the driving method of the display device includes:
  • the main board sends the first original data corresponding to the first display area and the second original data corresponding to the second display area to the programmable device.
  • the programmable device sends the first data including the first original data and the first redundant data corresponding to the second boundary area to the first driving chip, and sends the first data including the second original data and the first redundant data corresponding to the first boundary area.
  • the second data of the second redundant data is sent to the second driving chip.
  • the programmable device 2 includes two buffers, a first buffer 21 and a second buffer 22.
  • the first buffer 21 receives the first original buffer sent by the main board 1.
  • the first buffer 21 sends to the first driver chip 41 the first data containing the first original data d1 received by the first buffer 21 in the first period and the first redundant data corresponding to the second boundary area B2.
  • the second buffer 22 receives the first original data d1 and the second original data d2 sent by the main board 1. In the third period, the second buffer 22 sends to the first driver chip 41 the first data containing the first original data d1 received by the second buffer 22 in the second period and the first redundant data corresponding to the second boundary area B2. A data d10 and second data d20 including the second original data d2 received by the second buffer 22 in the second period and the second redundant data corresponding to the first boundary area B1 are sent to the second driving chip 42.
  • the first buffer 21 and the second buffer 22 are both line buffers.
  • the first buffer 21 receives the i-th row of sub-pixels sent by the main board 1.
  • the first buffer 21 sends to the first driving chip 41 the first data d10 containing the first original data d1 corresponding to the i-th row of sub-pixels and the first redundant data corresponding to the i-th row of sub-pixels, And sending to the second driving chip 42 the second data d20 including the second original data d2 corresponding to the sub-pixels in the i-th row and the second redundant data corresponding to the sub-pixels in the i-th row, and the second buffer 22 receives the transmission from the main board 1.
  • the first original data d1 and the second original data d2 corresponding to the sub-pixels in the i+1th row.
  • the second buffer 22 sends to the first driver chip 41 the first original data d1 corresponding to the sub-pixels in the i+1th row and the first redundant data corresponding to the sub-pixels in the i+1th row.
  • i is a positive integer.
  • the first driving chip drives the first display area to display according to the algorithm corresponding to the first sub-pixel arrangement and the first data
  • the second driving chip drives the second display according to the algorithm corresponding to the first sub-pixel arrangement and the second data. Area to display.
  • the display device uses a programmable device to enable the first driver chip to obtain the first data including the first redundant data corresponding to the second boundary area, and enable the second driver chip to obtain the first data including the corresponding first
  • the second data of the second redundant data in the boundary area in turn enables the first driver chip and the second driver chip to perform normal algorithms corresponding to the first sub-pixel arrangement, which effectively avoids when the sub-pixels in the display panel follow the
  • the adjacent display areas corresponding to different driving chips have abnormal display problems such as split screens or bright lines.
  • the programmable device sends the first data including the first original data and the first redundant data corresponding to the second boundary area to the first driving chip, and sends the first data including the second original data
  • the sending of data and second data corresponding to the second redundant data of the first boundary area to the second driver chip includes: in the first period, the first buffer of the programmable device receives the first original data sent by the main board Data and second original data; in the second period, the first buffer sends to the first driver chip the first original data and the corresponding second data received by the first buffer in the first period The first data of the first redundant data in the boundary area, and sending to the second driver chip the second original data received by the first buffer in the first period and the first data corresponding to the first boundary area
  • the second data of the second redundant data, the second buffer of the programmable device receives the first original data and the second original data sent by the main board; in the third period, the second buffer sends the A driver chip sends first data including the first original data received by the second buffer in the second period and the first redundant
  • the first buffer of the programmable device receives the first original data and the second original data sent by the main board, including: in the first period, the The first buffer receives the first original data and the second original data corresponding to the sub-pixels in the i-th row sent by the main board.
  • the first buffer sends to the first driver chip the first original data received by the first buffer in the first time period and the first data corresponding to the second boundary area.
  • the second data, the second buffer of the programmable device receiving the first original data and the second original data sent by the main board includes: in the second period, the first buffer sends the first driver chip Sending the first data including the first original data corresponding to the i-th row of sub-pixels and the first redundant data corresponding to the i-th row of sub-pixels, and sending to the second driving chip the first data containing the corresponding The second original data of the sub-pixels in the i-th row and the second data corresponding to the second redundant data of the sub-pixels in the i-th row, the second buffer of the programmable device receives the corresponding i+th data sent by the main board
  • the second buffer sends to the first driver chip the first original data received by the second buffer in the second period and the data corresponding to the second boundary area.
  • the first data of the first redundant data and sending to the second driver chip the second original data received by the second buffer in the second period and the second corresponding to the first boundary area
  • the second data of the redundant data includes: in the third period, the second buffer sends to the first driver chip the first original data containing the sub-pixels corresponding to the i+1th row and the The first data of the first redundant data of the sub-pixels in the (i+1)th row, and sending to the second driving chip the second original data containing the sub-pixels in the (i+1)th row and corresponding to the i-th The second data of the second redundant data of the +1 row of sub-pixels; where i is a positive integer.

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Abstract

一种显示装置及其驱动方法，显示装置包括：显示面板(3)，显示面板(3)的子像素按照第一子像素排列方式排列；与显示面板(3)连接的第一驱动芯片(41)与第二驱动芯片(42)；主板(1)，主板(1)设置为向可编程器件(2)发送对应第一显示区(A1)的第一原始数据(d1)和对应第二显示区(A2)的第二原始数据(d2)；可编程器件(2)，可编程器件(2)设置为将包含有第一原始数据(d1)和对应第二边界区(B2)的第一冗余数据的第一数据(d10)发送至第一驱动芯片(41)，将包含有第二原始数据(d2)和对应第一边界区(B1)的第二冗余数据的第二数据(d20)发送至第二驱动芯片(42)；第一原始数据(d1)、第二原始数据(d2)、第一和第二冗余数据均为具有第二子像素排列方式的图像数据；第一驱动芯片(41)和第二驱动芯片(42)设置为根据对应第一子像素排列方式的算法以及对应数据驱动第一显示区(A1)和第二显示区(A2)进行显示。

Description

显示装置及其驱动方法
本申请要求在2019年06月24日提交中国专利局、申请号为201910551230.X的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及显示技术领域，例如涉及一种显示装置及其驱动方法。
背景技术
子像素渲染(Sub-pixel Rendering，SPR)技术与真正红绿蓝(Real Red-Green-Blue，Real RGB)子像素排列相比，SPR子像素排列可以有效提高显示装置的每英寸所拥有的像素数目(Pixel Per Inch，PPI)，以及减少驱动芯片的通道数，因而SPR技术已经得到了广泛的应用。
针对中大尺寸的显示装置，需要采用两个或者更多的驱动芯片，并相应地将显示面板的显示区划分为由多个驱动芯片驱动的多个显示区域。客户端无法向驱动芯片提供与该驱动芯片对应的显示区相邻的显示区的冗余数据，进而导致驱动芯片无法进行正常的SPR算法，在相邻显示区之间的边界附近会出现分屏问题或者出现亮线或者暗线问题。
发明内容
本申请提供一种显示装置及其驱动方法，使得第一驱动芯片以及第二驱动芯片能够进行正常的对应第一子像素排列方式的算法，有效避免了当显示面板中的子像素按照第一子像素排列方式排列时，对应不同驱动芯片的相邻显示区出现分屏或者出现亮线等异常显示问题。
本申请实施例提供了一种显示装置，包括：
显示面板，所述显示面板的子像素按照第一子像素排列方式排列，所述显示面板包括沿所述子像素排列的行方向设置的多个显示区，第一显示区和第二显示区为相邻的两个显示区，围绕所述第一显示区与所述第二显示区之间的边界设置有位于所述第一显示区的第一边界区和位于所述第二显示区的第二边界区；
与所述显示面板连接的第一驱动芯片与第二驱动芯片；
可编程器件，所述可编程器件与所述第一驱动芯片和第二驱动芯片电连接，所述可编程器件设置为将包含有所述第一原始数据和对应所述第二边界区的第 一冗余数据的第一数据发送至第一驱动芯片，以及将包含有所述第二原始数据和对应所述第一边界区的第二冗余数据的第二数据发送至第二驱动芯片；其中，所述第一原始数据、所述第二原始数据、所述第一冗余数据和所述第二冗余数据均为具有第二子像素排列方式的图像数据；
主板，所述主板与所述可编程器件电连接，设置为向所述可编程器件发送对应所述第一显示区的第一原始数据和对应所述第二显示区的第二原始数据；
所述第一驱动芯片设置为根据对应所述第一子像素排列方式的算法以及所述第一数据驱动所述第一显示区进行显示，所述第二驱动芯片设置为根据对应所述第一子像素排列方式的算法以及所述第二数据驱动所述第二显示区进行显示。
本申请实施例还提供了一种显示装置的驱动方法，由本申请任意实施例所述的显示装置执行，所述驱动方法包括：
主板向可编程器件发送对应第一显示区的第一原始数据和对应第二显示区的第二原始数据；
所述可编程器件将包含有所述第一原始数据和对应第二边界区的第一冗余数据的第一数据发送至第一驱动芯片，以及将包含有所述第二原始数据和对应第一边界区的第二冗余数据的第二数据发送至第二驱动芯片；
所述第一驱动芯片根据对应第一子像素排列方式的算法以及所述第一数据驱动所述第一显示区进行显示，所述第二驱动芯片根据对应所述第一子像素排列方式的算法以及所述第二数据驱动所述第二显示区进行显示。
附图说明
图1为本申请实施例提供的一种显示装置的结构示意图；
图2为本申请实施例提供的一种可编程器件的结构示意图；
图3为本申请实施例提供的另一种可编程器件的结构示意图；
图4为本申请实施例提供的一种显示装置的驱动方法的流程示意图。
具体实施方式
下面结合附图和实施例对本申请进行说明。本文所描述的具体实施例仅仅用于解释本申请，而非对本申请的限定。为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。贯穿本文中，相同或相似的附图标号代表相同或相似的结构、元件或流程。本申请实施例提供了一种显示装置，包括主板、 可编程器件、显示面板和多个驱动芯片，显示面板的子像素按照第一子像素排列方式排列，显示面板包括沿子像素排列的行方向设置的多个显示区，第一显示区和第二显示区为相邻的两个显示区，围绕第一显示区与第二显示区之间的边界设置有位于第一显示区的第一边界区和位于第二显示区的第二边界区。主板与可编程器件电连接，设置为向可编程器件发送对应第一显示区的第一原始数据和对应第二显示区的第二原始数据，可编程器件与多个驱动芯片电连接，设置为将包含有第一原始数据和对应第二边界区的第一冗余数据的第一数据发送至第一驱动芯片，以及将包含有第二原始数据和对应第一边界区的第二冗余数据的第二数据发送至第二驱动芯片；其中，第一原始数据、第二原始数据、第一冗余数据和第二冗余数据均为具有第二子像素排列方式的图像数据，第一驱动芯片与显示面板电连接，设置为根据对应第一子像素排列方式的算法以及第一数据驱动第一显示区进行显示，第二驱动芯片与显示面板电连接，设置为根据对应第一子像素排列方式的算法以及第二数据驱动第二显示区进行显示。
SPR(Sub-pixel Rendering，子像素渲染)技术与Real RGB子像素排列相比，SPR子像素排列可以有效提高显示装置的PPI，以及减少驱动芯片的通道数，因而SPR技术已经得到了广泛的应用。
针对中大尺寸的显示装置，单个驱动芯片无法支持显示装置的显示，需要采用两个或者更多的驱动芯片，并相应地将显示面板的显示区划分为由多个驱动芯片驱动的多个显示区域。对于SPR像素排列的显示面板，驱动芯片要实现SPR算法，需要获取到与该驱动芯片对应的显示区相邻的显示区的冗余数据，但是客户端无法向驱动芯片提供与该驱动芯片对应的显示区相邻的显示区的冗余数据，驱动芯片也就无法获取与该驱动芯片对应的显示区相邻的显示区的冗余数据，进而导致驱动芯片无法进行正常的SPR算法，在相邻显示区之间的边界附近会出现分屏问题或者出现亮线或者暗线问题。
可以利用专门定制的驱动芯片实现相邻显示区对应的驱动芯片之间冗余数据的传输，例如可以利用串行外设接口(Serial Peripheral Interface，SPI)接口或者集成电路总线(Inter-Integrated Circuit，I 2C)接口实现驱动芯片之间冗余数据的传输，但是这种专门定制的驱动芯片价格昂贵，无疑增加了显示装置的生产成本，而常规的驱动芯片又无法为与该驱动芯片对应的显示区相邻的显示区所对应的驱动芯片提供冗余数据，客户端也无法为驱动芯片提供相应的冗余数据，对于SPR像素排列的显示面板，也就无法避免在相邻显示区之间的边界附近会出现分屏问题或者出现亮线或者暗线问题。
本申请实施例提供的显示装置利用可编程器件使得第一驱动芯片能够获取包含有对应第二边界区的第一冗余数据的第一数据，以及使得第二驱动芯片能 够获取包含有对应第一边界区的第二冗余数据的第二数据，进而使得第一驱动芯片以及第二驱动芯片能够进行正常的对应第一子像素排列方式的算法，有效避免了当显示面板中的子像素按照第一子像素排列方式排列时，对应不同驱动芯片的相邻显示区出现分屏或者出现亮线等异常显示问题。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。图1为本申请实施例提供的一种显示装置的结构示意图。如图1所示，显示装置包括主板1、可编程器件2、显示面板3和多个驱动芯片，图1仅示例性地示出显示装置包括第一驱动芯片41和第二驱动芯片42两个驱动芯片，显示面板3的子像素按照第一子像素排列方式排列，显示面板3包括沿子像素排列的行方向设置的多个显示区，第一显示区A1和第二显示区A2为相邻的两个显示区，围绕第一显示区A1与第二显示区A2之间的边界a设置有位于第一显示区A1的第一边界区B1和位于第二显示区A2的第二边界区B2。
主板1与可编程器件2电连接，设置为向可编程器件2发送对应第一显示区A1的第一原始数据和对应第二显示区A2的第二原始数据，图1中的箭头d1表示主板1发送的第一原始数据，箭头d2表示主板1发送的第二原始数据，可编程器件2与第一驱动芯片41和第二驱动芯片42电连接，设置为将包含有第一原始数据d1和对应第二边界区B2的第一冗余数据的第一数据d10发送至第一驱动芯片41，以及将包含有第二原始数据d2和对应第一边界区B1的第二冗余数据的第二数据d20发送至第二驱动芯片42，第一原始数据d1、第二原始数据d2、第一冗余数据和第二冗余数据均为具有第二子像素排列方式的图像数据。
可选的，可以设置第一子像素排列方式为SPR排列，即像素之间存在子像素的借用关系，例如相邻的三个像素分别包括R像素和G像素、B像素和R像素以及G像素和B像素，相邻的像素彼此关联，可以设置第二子像素排列方式为Real RGB排列，即每个像素由R像素、G像素和B像素三个子像素组成。第一原始数据d1和第二原始数据d2为具有第二子像素排列方式的图像数据，即第一原始数据d1为对应第一显示区A1且对应Real RGB排列的子像素的图像数据，第二原始数据d2为对应第二显示区A2且对应Real RGB排列的子像素的图像数据。第一冗余数据和第二冗余数据同样均为具有第二子像素排列方式的图像数据，第一冗余数据为对应第二边界区B2且对应Real RGB排列的子像素的图像数据，第二冗余数据为对应第一边界区B1且对应Real RGB排列的子像素的图像数据。
示例性地，可编程器件2可以采用现场可编程门阵列(Field Programmable Gate Array，FPGA)芯片或者复杂可编程逻辑器件(Complex Programmable Logic Device，CPLD)芯片，可以将第一冗余数据和第二冗余数据提前烧录在可编程 器件2中，可编程器件2接收主板1发送的第一原始数据d1和第二原始数据d2，在可编程器件2向第一驱动芯片41提供第一数据d10以及向第二驱动芯片42提供第二数据d20时，可编程器件2则可以调用相应的第一冗余数据和第二冗余数据使得第一数据d10包含有对应第一显示区A1的第一原始数据d1以及对应第二边界区B2的第一冗余数据，以及使得第二数据d20包含有对应第二显示区A2的第二原始数据d2和对应第一边界区B1的第二冗余数据。
第一驱动芯片41与显示面板3电连接，设置为根据对应第一子像素排列方式的算法，即SPR算法以及第一数据d10驱动第一显示区A1进行显示，第二驱动芯片42与显示面板3电连接，设置为根据对应第一子像素排列方式的算法，即SPR算法以及第二数据d20驱动第二显示区A2进行显示。
可选的，针对多个驱动芯片驱动显示装置进行显示的情况，驱动芯片之间采用级联的方式，一个驱动芯片为主控驱动芯片，启用时序控制器(Timing Controller，TCON)功能，其余驱动芯片为从属驱动芯片，关闭TCON功能并接收主控驱动芯片发出的同步信号，即所有从属驱动芯片遵从主动驱动芯片的驱动时序，本申请实施例对第一驱动芯片41和第二驱动芯片42中哪个驱动芯片为主控驱动芯片不作限定。
可选的，第一驱动芯片41接收到包含有Real RGB格式的对应第一显示区A1的第一原始数据d1以及对应第二边界区B2的第一冗余数据的第一数据d10，并采用SPR算法将Real RGB格式的第一数据d10转换为SPR格式的图像数据，并对应转换后的图像数据向显示面板3的第一显示区A1中的子像素发送发光驱动信号。同样的，第二驱动芯片42接收到包含有Real RGB格式的对应第二显示区A2的第二原始数据d2以及对应第一边界区B1的第二冗余数据的第二数据d20，并采用SPR算法将Real RGB格式的第二数据d20转换为SPR格式的图像数据，并对应转换后的图像数据向显示面板3的第二显示区A2中的子像素发送发光驱动信号。
可编程器件2的设置使得第一驱动芯片41能够获取对应第二边界区B2的第一冗余数据，以及使得第二驱动芯片42能够获取对应第一边界区B1的第二冗余数据，进而使得第一驱动芯片41以及第二驱动芯片42能够进行正常的SPR算法，即第一驱动芯片41和第二驱动芯片42能够将Real RGB格式的图像数据转换为SPR格式的图像数据，解决了主板无法向驱动芯片提供与该驱动芯片对应的显示区相邻的显示区的冗余数据，驱动芯片也就无法获取与该驱动芯片对应的显示区相邻的显示区的冗余数据，进而导致驱动芯片无法进行正常的SPR算法，在相邻显示区之间的边界附近会出现分屏问题或者出现亮线或者暗线问题的同时，无需使用专门定制的驱动芯片，仅需常规驱动芯片即可实现相邻显 示区域对应的冗余数据的获取，降低了显示装置实现SPR技术的成本。
图1仅示例性地设置显示装置包括第一驱动芯片41和第二驱动芯片42两个驱动芯片，且显示面板3包括第一显示区A1和第二显示区A2两个显示区，也可以设置显示面板包括更多的显示区和驱动芯片，第一显示区A1和第二显示区A2可以表示任意两个相邻的显示区，第一驱动芯片41和第二驱动芯片42则为对应前述任意两个相邻显示区的驱动芯片。另外，第一显示区A1与第二显示区A2之间具有边界a，围绕该边界a限定出一个边界区，边界区位于第一显示区A1的部分定义为第一边界区B1，边界区位于第二显示区A2的部门定义为第二边界区B2，边界区的尺寸取决于第一驱动芯片41以及第二驱动芯片42在执行像素格式的转换时，即将Real RGB格式的原始数据以及冗余数据转换为SPR格式的图像数据时需要借用的像素个数，本申请实施例对边界区的尺寸不作限定。将Real RGB格式的图像数据通过算法转换为SPR格式的图像数据。
图2为本申请实施例提供的一种可编程器件的结构示意图。结合图1和图2，可以设置可编程器件2包括第一缓存器21和第二缓存器22两个缓存器，第一缓存器21设置为在第一时段接收主板1发送的第一原始数据d1和第二原始数据d2，在第二时段向第一驱动芯片41发送包含有第一缓存器21在第一时段接收的第一原始数据d1和对应第二边界区B2的第一冗余数据的第一数据d10，以及在第二时段向第二驱动芯片42发送包含有第一缓存器21在第一时段接收的第二原始数据d2和对应第一边界区B1的第二冗余数据的第二数据d20。第二缓存器22设置为在第二时段接收主板1发送的第一原始数据d1和第二原始数据d2，在第三时段向第一驱动芯片41发送包含有第二缓存器22在第二时段接收的第一原始数据d1和对应第二边界区B2的第一冗余数据的第一数据d10，以及在第三时段向第二驱动芯片42发送包含有第二缓存器22在第二时段接收的第二原始数据d2和对应第一边界区B1的第二冗余数据的第二数据d20。
可选的，结合图1和图2，可以提前向每个缓存器烧录对应的冗余数据，在第一时段，第一缓存器21接收主板1发送的第一原始数据d1和第二原始数据d2。在第二时段，第一缓存器21向第一驱动芯片41发送包含有第一缓存器21在第一时段接收的第一原始数据d1和对应第二边界区B2的第一冗余数据的第一数据d10，以及向第二驱动芯片42发送包含有第一缓存器21在第一时段接收的第二原始数据d2和对应第一边界区B1的第二冗余数据的第二数据d20，第二缓存器22接收主板1发送的第一原始数据d1和第二原始数据d2。在第三时段，第二缓存器22向第一驱动芯片41发送包含有第二缓存器22在第二时段接收的第一原始数据d1和对应第二边界区B2的第一冗余数据的第一数据d10，以及向第二驱动芯片42发送包含有第二缓存器22在第二时段接收的第二原始数据d2和对应第一边界区B1的第二冗余数据的第二数据d20。
可选的，在同一时段，两个缓存器中的一个缓存器接收主板1发送的原始数据，另一个缓存器将包含有上一时段接收的包含有原始数据以及对应的冗余数据发送至对应的驱动芯片，驱动芯片据此驱动显示面板3中的子像素进行显示。在下一时段，两个缓存器的收发功能倒置，即上一时段实现接收功能的缓存器在这一时段将包含有上一时段接收到的原始数据以及对应的冗余图像数据的第一数据或者第二数据发送至对应的驱动芯片，驱动芯片据此驱动显示面板3中的子像素进行显示，上一时段实现发送功能的缓存器在这一时段则接收主板1发送的原始数据，这样，两个缓存器采用乒乓工作方式，即不同时段，两个缓存器的收发功能倒置，图像数据的收发时段的交替周期可以对应一帧显示画面对应的显示周期，实现了显示面板3的显示功能，且可编程器件2使得第一驱动芯片41能够获取对应第二边界区B2的第一冗余数据，以及使得第二驱动芯片42能够获取对应第一边界区B1的第二冗余数据，有效避免了当显示面板中的子像素按照第一子像素排列方式排列时，对应不同驱动芯片的相邻显示区出现分屏或者出现亮线等异常显示问题。
可选地，可以设置第一缓存器21和第二缓存器22均为行缓存器，则第一缓存器21是设置为在第一时段接收主板1发送的对应第i行子像素的第一原始数据d1和第二原始数据d2，以及在第二时段向第一驱动芯片41发送包含有对应第i行子像素的第一原始数据d1和对应第i行子像素的第一冗余数据的第一数据d10，以及在第二时段向第二驱动芯片42发送包含有对应第i行子像素的第二原始数据d2和对应第i行子像素的第二冗余数据的第二数据d20。第二缓存器22是设置为在第二时段接收主板1发送的对应第i+1行子像素的第一原始数据d1和第二原始数据d2，以及在第三时段向第一驱动芯片41发送包含有对应第i+1行子像素的第一原始数据d1和对应第i+1行子像素的第一冗余数据的第一数据d10，以及在第三时段向第二驱动芯片42发送包含有对应第i+1行子像素的第二原始数据d2和对应所述第i+1行子像素的第二冗余数据的第二数据d20，i为正整数。
在第一时段，第一缓存器21例如可以接收主板1发送的对应显示面板3中第一行子像素的第一原始数据d1和第二原始数据d2，即第一缓存器21在第一时段实现对应显示面板3第一行子像素的原始数据的接收。
示例性地，例如可以设置显示面板3中一行有2H个子像素，则对应显示面板3中第一行子像素的第一原始数据d1和第二原始数据d2均包括H个子像素数据，第一原始数据d1为对应第一显示区A1的第一行子像素的H个子像素数据，第二原始数据d2为对应第二显示区A2的第一行子像素的H个子像素数据。
在第二时段，第一缓存器21向第一驱动芯片41发送包含有第一缓存器21 在第一时段接收的对应第一显示区A1的第一行子像素的第一原始数据d1以及对应第二边界区B2的第一行子像素的第一冗余数据的第一数据d10，以及向第二驱动芯片42发送包含有第一缓存器21在第一时段接收的对应第二显示区A2的第一行子像素的第二原始数据d2以及对应第一边界区B1的第一行子像素的第二冗余数据的第二数据d20，即第一缓存器21在第二时段实现向对应驱动芯片的对应第一行子像素的图像数据的发送。在第二时段，第二缓存器22接收主板1发送的对应显示面板3中第二行子像素的第一原始数据d1和第二原始数据d2，即第二缓存器22在第二时段实现对应显示面板3第二行子像素的原始数据的接收。
示例性地，可以设置针对显示面板3中的每行子像素，SPR排列的子像素在相邻显示区，例如第一显示区A1和第二显示区A3之间借用的子像素的个数为x，x例如可以为子像素借用的最小单位6，则对应第二边界区B1的第一冗余数据包含6个像素数据，对应第一边界区B2设置的第二冗余数据同样包含6个像素数据，则第一缓存器21在第二时段向第一驱动芯片41发送的第一数据d10包括H加6个像素数据，第一缓存器21在第二时段向第二驱动芯片42发送的第二数据d20包括H加6个像素数据。
在第三时段，第二缓存器22向第一驱动芯片41发送包含有第二缓存器22在第二时段接收的对应第一显示区A1的第二行子像素的第一原始数据d1以及对应第二边界区B2的第二行子像素的第一冗余数据的第一数据d10，以及向第二驱动芯片42发送包含有第二缓存器22在第二时段接收的对应第二显示区A2的第二行子像素的第二原始数据d2以及对应第一边界区B1的第二行子像素的第二冗余数据的第二数据d20，即第二缓存器22在第三时段实现向对应的驱动芯片的对应第二行子像素的数据的发送。
同理，第二缓存器22在第三时段向第一驱动芯片41发送的第一数据d10包括H加6个像素数据，第二缓存器22在第三时段向第二驱动芯片42发送的第二数据d20包括H加6个像素数据。
设置第一缓存器21以及第二缓存器22均为行缓存器，且在同一时段，两个行缓存器中的一个行缓存器接收主板1发送的对应第i行子像素的原始数据，一个行缓存器将包含有上一时段接收的对应第i-1行子像素的原始数据以及对应第i-1行的冗余数据的第一数据或第二数据发送至对应的驱动芯片，驱动芯片据此驱动显示面板3中的第i-1行子像素进行显示。在下一时段，两个行缓存器的收发功能倒置，即上一时段实现接收功能的行缓存器在这一时段将包含有上一时段接收到的对应第i行子像素的原始数据以及对应第i行的冗余图像数据的第一数据或第二数据发送至对应的驱动芯片，驱动芯片据此驱动显示面板3中的 第i行子像素进行显示，上一时段实现发送功能的行缓存器在这一时段则接收主板1发送的对应第i+1行子像素的原始数据，这样，两个行缓存器采用乒乓工作方式，即不同时段，两个行缓存器的收发功能倒置，实现了对显示面板3中每一行子像素的逐行驱动，且利用可编程器件2使得第一驱动芯片41能够获取对应第二边界区B2的第一冗余数据，以及使得第二驱动芯片42能够获取对应第一边界区B1的第二冗余数据，进而使得第一驱动芯片41以及第二驱动芯片42能够进行正常的对应第一子像素排列方式的算法，有效避免了当显示面板中的子像素按照第一子像素排列方式排列时，对应不同驱动芯片的相邻显示区出现分屏或者出现亮线等异常显示问题。
图3为本申请实施例提供的另一种可编程器件的结构示意图。结合图1至图3，可编程器件2还可以包括多个第一接口5和多个第二接口6，两个缓存器均与多个第一接口5以及多个第二接口6电连接，多个第一接口5与主板1电连接，多个第二接口6与多个驱动芯片电连接。图3示例性地设置显示装置包括第一驱动芯片41和第二驱动芯片42两个驱动芯片，驱动芯片与第一接口5一一对应设置，第一接口5与第二接口6一一对应设置，即示例性地设置可编程器件2包括两个第一接口5和两个第二接口6，第一缓存器21与两个第一接口5以及两个第二接口6均电连接，第二缓存器22与两个第一接口5以及两个第二接口6均电连接，两个第一接口5与主板1电连接，两个第二接口6与第一驱动芯片41和第二驱动芯片42电连接。
两个第一接口5设置为接收主板1发送的第一原始数据d1和第二原始数据d2并对第一原始数据d1和第二原始数据d2解码后发送至对应的缓存器。可选的，第一接口51接收主板1发送的对应第一显示区A1的第一原始数据d1并将第一原始数据d1解码后发送至对应的缓存器，第一接口52接收主板1发送的对应第二显示区A2的第二原始数据d2并将第二原始数据d2解码后发送至对应的缓存器，这里对应的缓存器可以指第一缓存器21与第二缓存器22中在该时段实现接收功能的缓存器。
两个第二接口6设置为接收对应的缓存器发送的第一数据d10和第二数据d20并对第一数据d10和第二数据d20编码后发送至对应的驱动芯片，这里对应的缓存器可以指第一缓存器21与第二缓存器22中在该时段实现发送功能的缓存器。可选的，第二接口61接收对应的缓存器发送的对应第一显示区A1的第一数据d10并对第一数据d10解码后发送至第一驱动芯片41，第二接口62接收对应的缓存器发送的对应第二显示区A2的第二数据d20并对第二数据d20解码后发送至第二驱动芯片42。
当第一缓存器21与第二缓存器22均为行缓存器时，两个第一接口5则以 行为单位对第一原始数据d1和第二原始数据d2进行解码，解码后将对应一行子像素的解码后的第一原始数据d1和第二原始数据d2发送至该时段执行接收功能的缓存器，两个第二接口6同样以行为单位接收该时段执行发送功能的缓存器发送的第一数据d10和第二数据d20，并将对应一行子像素的编码后的第一数据d10和第二数据d20发送至对应的驱动芯片。
示例性地，结合图1至图3，第一接口5可以采用移动产业处理器(Mobile Industry Processor Interface，MIPI)接口、低压差分信号(Low Voltage Differential Signaling，LVDS)接口或者高清多媒体(High Definition Multimedia Interface，HDMI)接口中的一种，第二接口6采用MIPI接口、LVDS接口或者HDMI接口中的一种，第一接口5与第二接口6的类型相同，例如第一接口5与第二接口6可以均为MIPI接口，或者均为LVDS接口，或者均为HDMI接口，图3示例性地设置第一接口5和第二接口6均采用MIPI接口，图1以及图2中的第一原始数据d1、第二原始数据d2、第一数据d10以及第二数据d20均包括图2所示的对应MIPI接口的五路信号CLK以及D0至D3。主板1可设置有相应的MIPI接口与两个第一接口5对接，实现无冗余数据的原始数据的传输，驱动芯片同样设置有相应的MIPI接口与对应的两个第二接口6对接，实现对应显示区的带冗余数据的第一数据d10和第二数据d20的接收。
可选地，显示装置还可以包括柔性电路板(图1至图3中未示出)，多个驱动芯片通过柔性电路板向显示面板3中的子像素提供显示信号，可以将可编程器件2设置在主板1上，也可以将可编程器件2设置在柔性电路板上，避免可编程器件2影响显示面板3的边框宽度。
可选地，如图1所示，驱动芯片还可以包括初始化端口c1，主板1通过初始化端口对驱动芯片进行初始化。可选的，主板1可以通过驱动芯片的初始化端口向驱动芯片中的寄存器写入参考值，无需经过信号的处理，因此驱动芯片的初始化端口直接与主板1电连接，无需经过可编程器件2，该端口可以采用SPI接口实现信号的传输。
示例性地，显示装置可以是有机发光显示装置，也可以是液晶显示装置，显示装置可以是手机，或者可以是电脑或可穿戴设备等电子设备，本申请实施例对显示装置的形式不作限定。
本申请实施例还提供了一种显示装置的驱动方法，图4为本申请实施例提供的一种显示装置的驱动方法的流程示意图，该驱动方法可以由上述实施例的显示装置执行，如图4所示，显示装置的驱动方法包括：
S110、主板向可编程器件发送对应第一显示区的第一原始数据和对应第二显示区的第二原始数据。
S120、可编程器件将包含有第一原始数据和对应第二边界区的第一冗余数据的第一数据发送至第一驱动芯片，以及将包含有第二原始数据和对应第一边界区的第二冗余数据的第二数据发送至第二驱动芯片。
可选地，结合图1至图3，可编程器件2包括第一缓存器21和第二缓存器22两个缓存器，在第一时段，第一缓存器21接收主板1发送的第一原始数据d1和第二原始数据d2。在第二时段，第一缓存器21向第一驱动芯片41发送包含有第一缓存器21在第一时段接收的第一原始数据d1和对应第二边界区B2的第一冗余数据的第一数据d10，以及向第二驱动芯片42发送包含有第一缓存器21在第一时段接收的第二原始数据d2和对应第一边界区B1的第二冗余数据的第二数据d20，第二缓存器22接收主板1发送的第一原始数据d1和第二原始数据d2。在第三时段，第二缓存器22向第一驱动芯片41发送包含有第二缓存器22在第二时段接收的第一原始数据d1和对应第二边界区B2的第一冗余数据的第一数据d10，以及向第二驱动芯片42发送包含有第二缓存器22在第二时段接收的第二原始数据d2和对应第一边界区B1的第二冗余数据的第二数据d20。
可选地，结合图1至图3，第一缓存器21和第二缓存器22均为行缓存器，在第一时段，第一缓存器21接收主板1发送的对应第i行子像素的第一原始数据d1和第二原始数据d2。在第二时段，第一缓存器21向第一驱动芯片41发送包含有对应第i行子像素的第一原始数据d1和对应第i行子像素的第一冗余数据的第一数据d10，以及向第二驱动芯片42发送包含有对应第i行子像素的第二原始数据d2和对应第i行子像素的第二冗余数据的第二数据d20，第二缓存器22接收主板1发送的对应第i+1行子像素的第一原始数据d1和第二原始数据d2。在第三时段，第二缓存器22向第一驱动芯片41发送包含有对应第i+1行子像素的第一原始数据d1和对应第i+1行子像素的第一冗余数据的第一数据d10，以及向第二驱动芯片42发送包含有对应第i+1行子像素的第二原始数据d2和对应所述第i+1行子像素的第二冗余数据的第二数据d20；其中，i为正整数。
S130、第一驱动芯片根据对应第一子像素排列方式的算法以及第一数据驱动第一显示区进行显示，第二驱动芯片根据对应第一子像素排列方式的算法以及第二数据驱动第二显示区进行显示。
本申请实施例提供的显示装置利用可编程器件使得第一驱动芯片能够获取包含有对应第二边界区的第一冗余数据的第一数据，以及使得第二驱动芯片能够获取包含有对应第一边界区的第二冗余数据的第二数据，进而使得第一驱动芯片以及第二驱动芯片能够进行正常的对应第一子像素排列方式的算法，有效避免了当显示面板中的子像素按照第一子像素排列方式排列时，对应不同驱动芯片的相邻显示区出现分屏或者出现亮线等异常显示问题。
可选的，所述可编程器件将包含有所述第一原始数据和对应第二边界区的第一冗余数据的第一数据发送至第一驱动芯片，以及将包含有所述第二原始数据和对应第一边界区的第二冗余数据的第二数据发送至第二驱动芯片，包括：在第一时段，所述可编程器件的第一缓存器接收所述主板发送的第一原始数据和第二原始数据；在第二时段，所述第一缓存器向所述第一驱动芯片发送包含有所述第一缓存器在所述第一时段接收的第一原始数据和对应第二边界区的第一冗余数据的第一数据，以及向所述第二驱动芯片发送包含有所述第一缓存器在所述第一时段接收的第二原始数据和对应第一边界区的第二冗余数据的第二数据，所述可编程器件的第二缓存器接收所述主板发送的第一原始数据和第二原始数据；在第三时段，所述第二缓存器向所述第一驱动芯片发送包含有所述第二缓存器在所述第二时段接收的第一原始数据和对应所述第二边界区的第一冗余数据的第一数据，以及向所述第二驱动芯片发送包含有所述第二缓存器在所述第二时段接收的第二原始数据和对应所述第一边界区的第二冗余数据的第二数据。
可选的，所述在第一时段，所述可编程器件的第一缓存器接收所述主板发送的第一原始数据和第二原始数据，包括：在第一时段，所述可编程器件的第一缓存器接收所述主板发送的对应第i行子像素的第一原始数据和第二原始数据。
所述在第二时段，所述第一缓存器向所述第一驱动芯片发送包含有所述第一缓存器在所述第一时段接收的第一原始数据和对应第二边界区的第一冗余数据的第一数据，以及向所述第二驱动芯片发送包含有所述第一缓存器在所述第一时段接收的第二原始数据和对应第一边界区的第二冗余数据的第二数据，所述可编程器件的第二缓存器接收所述主板发送的第一原始数据和第二原始数据，包括：在第二时段，所述第一缓存器向所述第一驱动芯片发送包含有对应所述第i行子像素的第一原始数据和对应所述第i行子像素的第一冗余数据的第一数据，以及向所述第二驱动芯片发送包含有对应所述第i行子像素的第二原始数据和对应所述第i行子像素的第二冗余数据的第二数据，所述可编程器件的第二缓存器接收所述主板发送的对应第i+1行子像素的第一原始数据和第二原始数据。
所述在第三时段，所述第二缓存器向所述第一驱动芯片发送包含有所述第二缓存器在所述第二时段接收的第一原始数据和对应所述第二边界区的第一冗余数据的第一数据，以及向所述第二驱动芯片发送包含有所述第二缓存器在所述第二时段接收的第二原始数据和对应所述第一边界区的第二冗余数据的第二数据，包括：在第三时段，所述第二缓存器向所述第一驱动芯片发送包含有对应所述第i+1行子像素的第一原始数据和对应所述第i+1行子像素的第一冗余数据的第一数据，以及向所述第二驱动芯片发送包含有对应所述第i+1行子像素的 第二原始数据和对应所述第i+1行子像素的第二冗余数据的第二数据；其中，i为正整数。

Claims (13)

  1. 一种显示装置，包括：
    显示面板，所述显示面板的子像素按照第一子像素排列方式排列，所述显示面板包括沿所述子像素排列的行方向设置的多个显示区，第一显示区和第二显示区为相邻的两个显示区，围绕所述第一显示区与所述第二显示区之间的边界设置有位于所述第一显示区的第一边界区和位于所述第二显示区的第二边界区；
    与所述显示面板连接的第一驱动芯片与第二驱动芯片；
    可编程器件，所述可编程器件与所述第一驱动芯片和所述第二驱动芯片电连接，所述可编程器件设置为将包含有所述第一原始数据和对应所述第二边界区的第一冗余数据的第一数据发送至第一驱动芯片，以及将包含有所述第二原始数据和对应所述第一边界区的第二冗余数据的第二数据发送至第二驱动芯片；其中，所述第一原始数据、所述第二原始数据、所述第一冗余数据和所述第二冗余数据均为具有第二子像素排列方式的图像数据；
    主板，所述主板与所述可编程器件电连接，设置为向所述可编程器件发送对应所述第一显示区的第一原始数据和对应所述第二显示区的第二原始数据；
    所述第一驱动芯片设置为根据对应所述第一子像素排列方式的算法以及所述第一数据驱动所述第一显示区进行显示，所述第二驱动芯片设置为根据对应所述第一子像素排列方式的算法以及所述第二数据驱动所述第二显示区进行显示。
  2. 根据权利要求1所述的显示装置，其中，所述可编程器件包括第一缓存器和第二缓存器；
    所述第一缓存器设置为在第一时段接收所述主板发送的第一原始数据和第二原始数据，以及在第二时段向所述第一驱动芯片发送包含有所述第一缓存器在所述第一时段接收的第一原始数据和对应所述第二边界区的第一冗余数据的第一数据，以及在所述第二时段向所述第二驱动芯片发送包含有所述第一缓存器在所述第一时段接收的第二原始数据和对应所述第一边界区的第二冗余数据的第二数据；
    所述第二缓存器设置为在所述第二时段接收所述主板发送的第一原始数据和第二原始数据，以及在第三时段向所述第一驱动芯片发送包含有所述第二缓存器在所述第二时段接收的第一原始数据和对应所述第二边界区的第一冗余数据的第一数据，以及在所述第三时段向所述第二驱动芯片发送包含有所述第二缓存器在所述第二时段接收的第二原始数据和对应所述第一边界区的第二冗余数据的第二数据。
  3. 根据权利要求2所述的显示装置，其中，所述第一缓存器和所述第二缓存器均为行缓存器；
    所述第一缓存器是设置为在第一时段接收所述主板发送的对应第i行子像素的第一原始数据和第二原始数据，以及在第二时段向所述第一驱动芯片发送包含有对应所述第i行子像素的第一原始数据和对应所述第i行子像素的第一冗余数据的第一数据，以及在所述第二时段向所述第二驱动芯片发送包含有对应所述第i行子像素的第二原始数据和对应所述第i行子像素的第二冗余数据的第二数据；
    所述第二缓存器是设置为在所述第二时段接收所述主板发送的对应第i+1行子像素的第一原始数据和第二原始数据，以及在第三时段向所述第一驱动芯片发送包含有对应所述第i+1行子像素的第一原始数据和对应所述第i+1行子像素的第一冗余数据的第一数据，以及在所述第三时段向所述第二驱动芯片发送包含有对应所述第i+1行子像素的第二原始数据和对应所述第i+1行子像素的第二冗余数据的第二数据；其中，i为正整数。
  4. 根据权利要求2或3所述的显示装置，其中，所述可编程器件还包括多个第一接口和多个第二接口，所述第一缓存器和所述第二缓存器均与所述多个第一接口以及所述多个第二接口电连接，所述多个第一接口与所述主板电连接，所述多个第二接口与所述第一驱动芯片和所述第二驱动芯片电连接；
    所述多个第一接口设置为接收所述主板发送的第一原始数据和第二原始数据并将所述第一原始数据和所述第二原始数据解码，将解码后的第一原始数据和解码后的第二原始数据发送至对应的缓存器；
    所述多个第二接口设置为接收对应的缓存器发送的第一数据和第二数据并将所述第一数据和所述第二数据编码，将编码后的第一数据和编码后的第二数据发送至对应的驱动芯片。
  5. 根据权利要求4所述的显示装置，其中，所述第一接口采用移动产业处理器MIPI接口、低压差分信号LVDS接口或者高清多媒体HDMI接口中的一种，所述第二接口采用MIPI接口、LVDS接口或者HDMI接口中的一种。
  6. 根据权利要求1-5中任一项所述的显示装置，还包括：
    柔性电路板，所述第一驱动芯片和所述第二驱动芯片是设置为通过所述柔性电路板向所述显示面板中的子像素提供显示信号，所述可编程器件设置于所述主板上或者设置于所述柔性电路板上。
  7. 根据权利要求1-6中任一项所述的显示装置，其中，所述可编程器件包括现场可编程门阵列FPGA芯片或者复杂可编程逻辑器件CPLD芯片。
  8. 根据权利要求1-7中任一项所述的显示装置，其中，所述第一子像素排列方式为子像素渲染SPR排列方式，所述第二子像素排列方式为真正红绿蓝Real RGB排列方式。
  9. 根据权利要求5所述的显示装置，其中，所述第一接口和所述第二接口的类型相同。
  10. 根据权利要求1-9中任一项所述的显示装置，其中，每个驱动芯片包括初始化端口；
    所述主板还设置为通过每个驱动芯片的初始化端口对所述每个驱动芯片进行初始化。
  11. 一种显示装置的驱动方法，由如权利要求1-10任一项所述的显示装置执行，包括：
    主板向可编程器件发送对应第一显示区的第一原始数据和对应第二显示区的第二原始数据；
    所述可编程器件将包含有所述第一原始数据和对应第二边界区的第一冗余数据的第一数据发送至第一驱动芯片，以及将包含有所述第二原始数据和对应第一边界区的第二冗余数据的第二数据发送至第二驱动芯片；
    所述第一驱动芯片根据对应第一子像素排列方式的算法以及所述第一数据驱动所述第一显示区进行显示，所述第二驱动芯片根据对应所述第一子像素排列方式的算法以及所述第二数据驱动所述第二显示区进行显示。
  12. 根据权利要求11所示的驱动方法，其中，所述可编程器件将包含有所述第一原始数据和对应第二边界区的第一冗余数据的第一数据发送至第一驱动芯片，以及将包含有所述第二原始数据和对应第一边界区的第二冗余数据的第二数据发送至第二驱动芯片，包括：
    在第一时段，所述可编程器件的第一缓存器接收所述主板发送的第一原始数据和第二原始数据；
    在第二时段，所述第一缓存器向所述第一驱动芯片发送包含有所述第一缓存器在所述第一时段接收的第一原始数据和对应第二边界区的第一冗余数据的第一数据，以及向所述第二驱动芯片发送包含有所述第一缓存器在所述第一时段接收的第二原始数据和对应第一边界区的第二冗余数据的第二数据，所述可编程器件的第二缓存器接收所述主板发送的第一原始数据和第二原始数据；
    在第三时段，所述第二缓存器向所述第一驱动芯片发送包含有所述第二缓存器在所述第二时段接收的第一原始数据和对应所述第二边界区的第一冗余数 据的第一数据，以及向所述第二驱动芯片发送包含有所述第二缓存器在所述第二时段接收的第二原始数据和对应所述第一边界区的第二冗余数据的第二数据。
  13. 根据权利要求12所示的驱动方法，其中，所述在第一时段，所述可编程器件的第一缓存器接收所述主板发送的第一原始数据和第二原始数据，包括：
    在第一时段，所述可编程器件的第一缓存器接收所述主板发送的对应第i行子像素的第一原始数据和第二原始数据；
    所述在第二时段，所述第一缓存器向所述第一驱动芯片发送包含有所述第一缓存器在所述第一时段接收的第一原始数据和对应第二边界区的第一冗余数据的第一数据，以及向所述第二驱动芯片发送包含有所述第一缓存器在所述第一时段接收的第二原始数据和对应第一边界区的第二冗余数据的第二数据，所述可编程器件的第二缓存器接收所述主板发送的第一原始数据和第二原始数据，包括：
    在第二时段，所述第一缓存器向所述第一驱动芯片发送包含有对应所述第i行子像素的第一原始数据和对应所述第i行子像素的第一冗余数据的第一数据，以及向所述第二驱动芯片发送包含有对应所述第i行子像素的第二原始数据和对应所述第i行子像素的第二冗余数据的第二数据，所述可编程器件的第二缓存器接收所述主板发送的对应第i+1行子像素的第一原始数据和第二原始数据；
    所述在第三时段，所述第二缓存器向所述第一驱动芯片发送包含有所述第二缓存器在所述第二时段接收的第一原始数据和对应所述第二边界区的第一冗余数据的第一数据，以及向所述第二驱动芯片发送包含有所述第二缓存器在所述第二时段接收的第二原始数据和对应所述第一边界区的第二冗余数据的第二数据，包括：
    在第三时段，所述第二缓存器向所述第一驱动芯片发送包含有对应所述第i+1行子像素的第一原始数据和对应所述第i+1行子像素的第一冗余数据的第一数据，以及向所述第二驱动芯片发送包含有对应所述第i+1行子像素的第二原始数据和对应所述第i+1行子像素的第二冗余数据的第二数据；其中，i为正整数。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110189696A (zh) * 2019-06-24 2019-08-30 昆山国显光电有限公司 一种显示装置及其驱动方法
CN112542117B (zh) * 2019-09-20 2023-04-28 北京小米移动软件有限公司 终端、显示数据发送方法、装置及存储介质
CN112331082A (zh) * 2020-11-17 2021-02-05 武汉华星光电技术有限公司 一种显示面板和显示装置
CN113903281A (zh) * 2021-08-13 2022-01-07 芯颖科技有限公司 一种基于fpga点屏的驱动集成电路验证系统及方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105867867A (zh) * 2016-04-19 2016-08-17 京东方科技集团股份有限公司 显示控制方法、装置及系统
CN106415697A (zh) * 2014-05-21 2017-02-15 三星电子株式会社 显示装置、包括该显示装置的电子设备以及操作该电子设备的方法
US20170186359A1 (en) * 2015-12-24 2017-06-29 Samsung Display Co., Ltd. Display device
CN107633795A (zh) * 2016-08-19 2018-01-26 京东方科技集团股份有限公司 显示装置和显示面板的驱动方法
CN107633809A (zh) * 2017-09-30 2018-01-26 京东方科技集团股份有限公司 消除多ic驱动显示屏暗线的方法、显示屏及显示装置
US20180122283A1 (en) * 2016-11-02 2018-05-03 Samsung Display Co., Ltd. Method of driving display device and display device for performing the same
CN107993608A (zh) * 2018-01-31 2018-05-04 芯颖科技有限公司 基于spr的至少两屏拼接显示方法、装置及驱动显示系统
CN109064987A (zh) * 2018-08-31 2018-12-21 深圳市华星光电技术有限公司 液晶显示面板及具有该液晶显示面板的液晶显示装置
CN110189696A (zh) * 2019-06-24 2019-08-30 昆山国显光电有限公司 一种显示装置及其驱动方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080049034A1 (en) * 2006-07-12 2008-02-28 Daniel Chin Uniform image display for multiple display devices
CN101582244A (zh) * 2008-05-15 2009-11-18 胜华科技股份有限公司 影像处理方法以及显示装置
KR100973561B1 (ko) * 2008-06-25 2010-08-03 삼성전자주식회사 표시장치
JP5542409B2 (ja) * 2009-10-27 2014-07-09 三菱電機株式会社 マルチ画面表示装置
US8704732B2 (en) * 2010-09-29 2014-04-22 Qualcomm Incorporated Image synchronization for multiple displays
KR101964458B1 (ko) * 2012-12-10 2019-04-02 엘지디스플레이 주식회사 유기발광 표시장치 및 그의 열화보상방법
KR102023184B1 (ko) * 2013-02-20 2019-09-20 삼성디스플레이 주식회사 표시장치, 데이터 처리장치 및 그 방법
CN104821147B (zh) * 2015-05-27 2017-06-27 京东方科技集团股份有限公司 一种子像素渲染方法
US10262387B2 (en) * 2016-11-14 2019-04-16 Google Llc Early sub-pixel rendering

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106415697A (zh) * 2014-05-21 2017-02-15 三星电子株式会社 显示装置、包括该显示装置的电子设备以及操作该电子设备的方法
US20170186359A1 (en) * 2015-12-24 2017-06-29 Samsung Display Co., Ltd. Display device
CN105867867A (zh) * 2016-04-19 2016-08-17 京东方科技集团股份有限公司 显示控制方法、装置及系统
CN107633795A (zh) * 2016-08-19 2018-01-26 京东方科技集团股份有限公司 显示装置和显示面板的驱动方法
US20180122283A1 (en) * 2016-11-02 2018-05-03 Samsung Display Co., Ltd. Method of driving display device and display device for performing the same
CN107633809A (zh) * 2017-09-30 2018-01-26 京东方科技集团股份有限公司 消除多ic驱动显示屏暗线的方法、显示屏及显示装置
CN107993608A (zh) * 2018-01-31 2018-05-04 芯颖科技有限公司 基于spr的至少两屏拼接显示方法、装置及驱动显示系统
CN109064987A (zh) * 2018-08-31 2018-12-21 深圳市华星光电技术有限公司 液晶显示面板及具有该液晶显示面板的液晶显示装置
CN110189696A (zh) * 2019-06-24 2019-08-30 昆山国显光电有限公司 一种显示装置及其驱动方法

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