WO2020245697A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2020245697A1
WO2020245697A1 PCT/IB2020/054928 IB2020054928W WO2020245697A1 WO 2020245697 A1 WO2020245697 A1 WO 2020245697A1 IB 2020054928 W IB2020054928 W IB 2020054928W WO 2020245697 A1 WO2020245697 A1 WO 2020245697A1
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Prior art keywords
transistor
circuit
wiring
layer
memory cell
Prior art date
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Ceased
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PCT/IB2020/054928
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English (en)
French (fr)
Japanese (ja)
Inventor
大貫達也
松嵜隆徳
岡本佑樹
山崎舜平
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to US17/613,605 priority Critical patent/US12015012B2/en
Priority to JP2021524493A priority patent/JP7524175B2/ja
Publication of WO2020245697A1 publication Critical patent/WO2020245697A1/ja
Anticipated expiration legal-status Critical
Priority to US18/740,603 priority patent/US12381187B2/en
Priority to JP2024113749A priority patent/JP7711279B2/ja
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
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    • H10B—ELECTRONIC MEMORY DEVICES
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
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    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D87/00—Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
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    • H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
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    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
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    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
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    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip having an integrated circuit, and an electronic component in which the chip is housed in a package are examples of semiconductor devices. Further, the storage device, the display device, the light emitting device, the lighting device, the electronic device, and the like are themselves semiconductor devices, and may have the semiconductor device.
  • IGZO In-Ga-Zn oxides
  • Exo In-Ga-Zn oxides
  • CAAC c-axis aligned crystalline
  • nc nanocrystalline structure
  • Oxide semiconductor transistor or "OS transistor”
  • OS transistor Oxide semiconductor transistor
  • Various semiconductor devices using OS transistors have been manufactured (for example, Non-Patent Documents 3 and 4).
  • Patent Document 1 discloses a configuration in which a plurality of layers of a memory cell array having an OS transistor are laminated on a substrate provided with a Si transistor.
  • One aspect of the present invention includes a silicon substrate having a first circuit, a first element layer having a second circuit, and a second element layer having a third circuit, and the first circuit is a first transistor.
  • the second circuit has a second transistor
  • the third circuit has a memory cell
  • the memory cell has a third transistor and a capacitor
  • the element layer constitutes a laminated block provided by being laminated in a direction perpendicular to or substantially perpendicular to the surface of the silicon substrate, and the laminated block is laminated in a direction perpendicular to or substantially perpendicular to the surface of the silicon substrate.
  • a plurality of laminated blocks are provided, and each of the plurality of laminated blocks has a first wiring provided in a direction perpendicular to or substantially perpendicular to the surface of the silicon substrate, and the first wiring is electrically connected to the plurality of laminated blocks. It is a semiconductor device.
  • the first circuit has a function of outputting a signal for driving the memory cell and data to be written to the memory cell to the first wiring, and amplifies the data read from the memory cell to the first wiring.
  • a semiconductor device having a function is preferable.
  • the second circuit has a function of amplifying the potential of the second wiring electrically connected to the memory cell and transmitting the potential to the first wiring, and a function of transmitting the potential of the first wiring to the second wiring.
  • a semiconductor device having.
  • the second transistor and the third transistor are semiconductor devices each having a semiconductor layer having a metal oxide in a channel forming region.
  • the metal oxide preferably contains a semiconductor device containing In, Ga, and Zn.
  • the layer having a capacitor is preferably a semiconductor device provided above the layer having a third transistor.
  • the layer having a capacitor is preferably a semiconductor device provided in a laminated manner.
  • One form of the present invention can provide a semiconductor device or the like having a new configuration.
  • one aspect of the present invention can provide a semiconductor device having a novel configuration and the like, which can reduce manufacturing costs in a semiconductor device that functions as a storage device using a minimum off-current.
  • one aspect of the present invention can provide a semiconductor device having a novel configuration and excellent low power consumption in a semiconductor device that functions as a storage device using a minimum off-current.
  • one aspect of the present invention can provide a semiconductor device having a novel configuration, which can reduce the size of a semiconductor device that functions as a storage device using a minimum off-current.
  • one aspect of the present invention can provide a semiconductor device having a novel configuration, which has a small fluctuation in the electrical characteristics of a transistor and is excellent in reliability, in a semiconductor device that functions as a storage device using a minimum off-current. ..
  • FIG. 1 is a diagram showing a configuration example of a semiconductor device.
  • FIG. 2 is a diagram showing a configuration example of a semiconductor device.
  • FIG. 3 is a diagram showing a configuration example of a semiconductor device.
  • 4A and 4B are diagrams showing a configuration example of a semiconductor device.
  • FIG. 5 is a diagram showing a configuration example of a semiconductor device.
  • FIG. 6 is a diagram showing a configuration example of a semiconductor device.
  • 7A and 7B are diagrams showing a configuration example of a semiconductor device.
  • FIG. 8 is a diagram showing a configuration example of a semiconductor device.
  • 9A and 9B are diagrams showing a configuration example of a semiconductor device.
  • FIG. 10 is a diagram showing a configuration example of a semiconductor device.
  • FIG. 10 is a diagram showing a configuration example of a semiconductor device.
  • FIG. 11 is a diagram showing a configuration example of a semiconductor device.
  • FIG. 12 is a diagram showing a configuration example of a semiconductor device.
  • FIG. 13 is a schematic cross-sectional view showing a configuration example of the semiconductor device.
  • FIG. 14 is a schematic cross-sectional view showing a configuration example of the semiconductor device.
  • FIG. 15A is a diagram illustrating classification of the crystal structure of IGZO.
  • FIG. 15B is a diagram illustrating an XRD spectrum of a CAAC-IGZO film.
  • FIG. 15C is a diagram for explaining the microelectron diffraction pattern of the CAAC-IGZO film.
  • FIG. 16 is a block diagram illustrating a configuration example of the semiconductor device.
  • FIG. 17 is a conceptual diagram showing a configuration example of a semiconductor device.
  • 18A and 18B are schematic views illustrating an example of an electronic component.
  • FIG. 19 is a diagram showing an example of an electronic device.
  • the ordinal numbers "1st”, “2nd”, and “3rd” are added to avoid confusion of the components. Therefore, the number of components is not limited. Moreover, the order of the components is not limited. Further, for example, the component referred to in “first” in one of the embodiments of the present specification and the like is defined as a component referred to in “second” in another embodiment or in the claims. It is possible. Further, for example, the component referred to in “first” in one of the embodiments of the present specification and the like may be omitted in another embodiment or in the claims.
  • the power supply potential VDD may be abbreviated as potentials VDD, VDD, etc. This also applies to other components (eg, signals, voltages, circuits, elements, electrodes, wiring, etc.).
  • the code is used for identification such as "_1”, “_2”, “[n]", “[m, n]”. May be added and described.
  • the second wiring GL is described as wiring GL [2].
  • a semiconductor device is a device that utilizes semiconductor characteristics, and is a circuit that includes semiconductor elements (transistors, diodes, photodiodes, etc.) and a device that has the same circuit.
  • the semiconductor device described in this embodiment can function as a storage device using a transistor having a minimum off-current.
  • FIG. 1 is a diagram showing a block diagram of a semiconductor device described in the present embodiment.
  • the semiconductor device 10 shown in FIG. 1 has a peripheral circuit 20 provided on a silicon substrate and laminated blocks 30_1 to 30_N (N is a natural number) provided with a plurality of memory cells constituting a memory cell array.
  • the laminated blocks 30_1 to 30_N may be collectively referred to as a laminated block 30.
  • the configuration applicable to the laminated blocks 30_1 to 30_N may be described as the laminated block 30.
  • the silicon substrate refers to a substrate using silicon as a semiconductor material, for example, a single crystal silicon substrate.
  • a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used for the substrate.
  • the peripheral circuit 20 includes a circuit for outputting a signal for driving a memory cell such as a row driver and a column driver.
  • Row drivers and column drivers may simply be referred to as drive circuits or drivers.
  • the row driver and the column driver drive the memory cells at high speed. Therefore, it is preferable that the row driver and the column driver have transistors that operate at high speed.
  • the transistor included in the low driver and the column driver is preferably a transistor (Si transistor) having silicon in the channel forming region, which has excellent field effect mobility.
  • the low driver is a circuit having a function of outputting a signal for driving a memory cell to a word line.
  • the word line has a function of transmitting a word signal to a memory cell.
  • the low driver may be called a word line side drive circuit.
  • the row driver includes a decoder circuit for selecting a word line corresponding to a designated address, a buffer circuit, and the like.
  • the column driver is a circuit having a function of outputting a signal for driving a memory cell to a bit line, a function of outputting data to be written to the memory cell, and a function of amplifying data read from the memory cell to the bit line. ..
  • the bit line BL has a function of transmitting data to a memory cell.
  • the column driver may be referred to as a bit line side drive circuit.
  • the column driver includes a sense amplifier, a precharge circuit, a decoder circuit for selecting a bit line according to a specified address, and the like.
  • the data signal given to the bit line corresponds to the signal written in the memory cell or the signal read from the memory cell.
  • the data signal will be described as a binary signal with a high or low level potential corresponding to data 1 or data 0.
  • the data signal may be a multi-valued data signal having three or more values.
  • the high level potential is VDD
  • the low level potential is VSS, or ground potential (GND).
  • the signal given to the bit line BL includes a data signal, a precharge potential for reading data, and the like.
  • the precharge potential can be VDD / 2.
  • the laminated blocks 30_1 to 30_N have an element layer 40 and an element layer 50, respectively.
  • the element layer 50 has a plurality of memory cells having transistors and capacitors.
  • the memory cell included in the element layer 50 can be called a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) using a transistor having an oxide semiconductor in the channel forming region (hereinafter referred to as an OS transistor) as the memory. Since it can be composed of one transistor and one capacitor, it is possible to realize a high density of memory. Further, by using the OS transistor, the data retention period can be increased.
  • DOSRAM Dynamic Oxide Semiconductor Random Access Memory
  • the leakage current flowing between the source and the drain at the time of off (hereinafter, off current) is extremely low, which is desired.
  • a voltage-dependent charge can be retained in a capacitor on the other side of the source or drain. That is, the data once written can be held in the memory cell for a long time. Therefore, the frequency of data refresh can be reduced and the power consumption can be reduced.
  • a memory cell using an OS transistor data can be rewritten and read by charging or discharging an electric charge, so that the number of times of writing and reading data can be substantially unlimited.
  • a memory cell using an OS transistor is excellent in rewrite resistance because it does not undergo a structural change at the atomic level unlike a magnetic memory or a resistance change type memory.
  • a memory cell using an OS transistor does not show instability due to an increase in electron capture centers even in repeated rewriting operations like a flash memory.
  • a memory cell using an OS transistor can be freely arranged on a silicon substrate having a transistor (hereinafter, Si transistor) whose channel forming region has silicon, or an element layer having an OS transistor, so that it can be integrated. It can be done easily. Further, since the OS transistor can be manufactured by using the same manufacturing apparatus as the Si transistor, it can be manufactured at low cost.
  • the OS transistor can be a 4-terminal semiconductor element if the back gate electrode is included in addition to the gate electrode, the source electrode and the drain electrode.
  • An electric network in which the input and output of signals flowing between the source and the drain can be independently controlled according to the voltage applied to the gate electrode or the back gate electrode can be configured. Therefore, the circuit design can be performed with the same thinking as the LSI.
  • the OS transistor has better electrical characteristics than the Si transistor in a high temperature environment. Specifically, since the ratio of the on current to the off current is large even at a high temperature such as 125 ° C. or higher and 150 ° C. or lower, good switching operation can be performed. Further, the OS transistor operates well in the range of ⁇ 40 ° C. or higher and 190 ° C.
  • the OS transistor has very good heat resistance.
  • This is the heat resistance of the phase change memory (PCM: Phase Change Memory) (-40 ° C or more and 150 ° C or less), and the heat resistance of the resistance change type memory (ReRAM: Resistance Random Access Memory) (-40 ° C or more and 125 ° C or less).
  • PCM Phase Change Memory
  • ReRAM Resistance Random Access Memory
  • the heat resistance is good even when compared with the heat resistance (-40 ° C or higher and 105 ° C or lower) of a magnetic resistance memory (MRAM: Magnetoresistive Random Access Memory).
  • the element layer 40 has a function of amplifying the potential of the bit line connected to the memory cell and transmitting it to the bit line connected to the peripheral circuit 20, and a function of transmitting the potential of the peripheral circuit 20 to the bit line connected to the memory cell.
  • the bit wire connected to the peripheral circuit 20 is shown as a wiring GBL.
  • the bit line connected to the element layer 50 having the memory cell is shown as a wiring LBL.
  • the wiring GBL may be referred to as a global bit line.
  • the wiring LBL may be referred to as a local bit line.
  • the wiring LBL and the wiring GBL have a bit line function for writing or reading data in a memory cell.
  • the wiring LBL and the wiring GBL may be shown by a thick line, a thick dotted line, or the like in order to improve visibility.
  • the schematic diagram shown in FIG. 1 defines the z-axis direction in order to explain the arrangement of each configuration.
  • the z-axis direction may be referred to as a direction perpendicular to the surface of the silicon substrate 11 in the specification.
  • the laminated block 30 or the element layer 40 and the element layer 50 constituting the laminated block 30 are laminated in a direction perpendicular to the surface of the silicon substrate 11 or in a substantially vertical direction.
  • the term "approximately vertical” means a state in which the objects are arranged at an angle of 85 degrees or more and 95 degrees or less.
  • the wiring LBL and the wiring GBL provided on the laminated block 30 are provided in a direction perpendicular to the surface of the silicon substrate 11 or in a substantially vertical direction. With this configuration, the number of memory cells arranged per unit area can be increased, so that the memory density can be increased.
  • FIG. 2 is a circuit diagram of a laminated block 30_1 showing a configuration example of a circuit included in the element layer 40 and a configuration example of a memory cell included in the element layer 50.
  • the memory cell 51_1 has a transistor 52 and a capacitor 53.
  • One of the source and drain of the transistor 52 is connected to the wiring LBL.
  • the gate of the transistor 52 is connected to a wiring (also referred to as a word line WL) that gives a word signal.
  • the transistor 52 is connected to the capacitor 53.
  • the transistor 52 is preferably an OS transistor.
  • the OS transistor has an extremely low off current. Therefore, the electric charge corresponding to the data written in the memory cell 51_1 can be held in the capacitor 53 for a long time. That is, in the memory cells 51_1 to 51_N, the once written data can be held for a long time. Therefore, the frequency of data refresh can be reduced, and the power consumption of the semiconductor device according to one aspect of the present invention can be reduced.
  • the memory cells 51_1 to 51_N using the OS transistor can be freely arranged on the silicon substrate and the element layer having the OS transistor, integration can be easily performed. Therefore, the number of memory cells arranged per unit area can be increased, and the memory density can be increased.
  • the transistor 52 preferably has a back gate electrode. By controlling the potential applied to the back gate electrode, the threshold voltage of the transistor 52 can be controlled. Thereby, for example, the on-current of the transistor 52 can be increased and the off-current can be decreased.
  • the element layer 40 shown in FIG. 2 has transistors 41 to 44.
  • Each of the transistors 41 to 44 can be composed of an OS transistor, and is shown as an n-channel type transistor.
  • the transistor 41 is a transistor for controlling the wiring GBL to a potential corresponding to the potential of the wiring LBL during the period of reading data from the memory cell 51_1.
  • the transistor 42 is a transistor that functions as a switch in which a selection signal MUX is input to a gate and on or off between a source and a drain is controlled according to the selection signal MUX.
  • the transistor 43 is a transistor that functions as a switch in which a write control signal WE is input to a gate and on or off between a source and a drain is controlled according to the write control signal WE.
  • the transistor 44 is a transistor that functions as a switch in which a read control signal RE is input to the gate and on or off between the source and the drain is controlled according to the read control signal RE.
  • a ground potential GND which is a fixed potential, is given to the source side of the transistor 44.
  • element layer 50 shown in FIG. 2 is shown as a single layer, a plurality of element layers 50 may be laminated. The configuration is illustrated in FIG.
  • FIG. 3 is a circuit diagram of a laminated block 30_1 showing a configuration example of a memory cell having element layers 50_1 to 50_p (p is a natural number of 2 or more) as a plurality of element layers 50.
  • the element layers 50_1 to 50_p have memory cells 51_1 to 51_p (also referred to as a memory cell 51) connected to a local bit line LBL provided extending in the z-axis direction.
  • LBL local bit line
  • FIG. 3 shows a configuration in which a plurality of element layers 50_1 to 50_p are stacked as the element layer 50 in the z-axis direction and memory cells are connected by a local bit line LBL provided in the z-axis direction, but as another configuration, May be good.
  • FIG. 4A shows, as an example, a configuration in which transistors 41 to 44 included in the element layer 40 and a plurality of element layers 50_1 to 50_4 are provided in four layers in the z-axis direction.
  • Each of the element layers 50_1 to 50_1 has a memory cell 51.
  • Each memory cell 51 is connected to the gate of the transistor 41 via a local bit line LBL provided in the z-axis direction.
  • the element layer 40 has four transistors 41 to 44.
  • memory cells are stacked and provided in four element layers as shown in FIG. 4A, four memory cells are provided in each layer of the element layer 40. 16 memory cells can be connected to the gate of the transistor 41 via the local bit line LBL.
  • FIG. 4A can be represented as a schematic diagram illustrated in FIG. 4B.
  • FIG. 4B illustrates the memory cell 51 included in the element layers 50_1 to 50_1, the local bit line LBL, and the transistor 41 included in the element layer 40.
  • the memory cells can be arranged at a high density, but the transistors of the element layer 40 also need to be arranged at a high density.
  • the transistor of the element layer 40 is also miniaturized. Since it is necessary to adopt a process having a large number of steps, the manufacturing cost may increase.
  • the transistor included in the element layer 40 has a process different from that of the memory cell, that is, a transistor shape capable of reducing the number of steps, rather than a transistor shape having a large number of steps for miniaturization. That is, the transistor included in the element layer 40 is not a transistor shape that prioritizes miniaturization, but a transistor shape that reduces manufacturing costs, for example, a transistor channel length and channel width, that is, a transistor size that is larger than that of a transistor that the memory cell 51 has. By increasing the value, it is possible to suppress an increase in manufacturing cost.
  • FIG. 5 is a schematic diagram similar to FIG. 4B, and is a diagram showing a configuration example in which the area occupied by the element layer 40 can be increased.
  • the wiring layer 54 has wirings 54_1 and 54_2 connected to the memory cell 51 included in the element layer 50.
  • the wiring 54_1 is connected to the gate of the transistor 41_1 included in the element layer 40_1 constituting the element layer 40.
  • the wiring 54_2 is connected to the gate of the transistor 41_2 included in the element layer 40_2 constituting the element layer 40.
  • the element layer 40_1 and the element have an area occupied by the memory cells 51 provided in the x direction and the y direction.
  • the area occupied by the layer 40_2 can be increased. Therefore, the transistor included in the element layer 40 can be formed into a transistor shape that reduces the manufacturing cost instead of a transistor shape that prioritizes miniaturization, so that an increase in the manufacturing cost can be suppressed.
  • FIG. 6 is a visualization of the schematic diagram shown in FIG. 5 based on the layout diagram of the memory cells.
  • the memory cell 51 has a transistor 52 provided superimposing on the word line WL and a capacitor 53 connected to the transistor 52.
  • the configuration in which the wiring layer 54 and the element layer 50 are provided on the element layer 40 is illustrated.
  • the wiring 54_1 and the wiring 54_2 are connected to a memory cell provided in the y direction at the openings 57_1 and 57_2.
  • the wiring 54_1 and the wiring 54_2 are connected to the element layers 40_1 and 40_2 provided in the y direction at the openings 58_1 and 58_2.
  • the element layer 40_1 and the element have an area occupied by the memory cells 51 provided in the x direction and the y direction.
  • the area occupied by the layer 40_2 can be increased. Therefore, the transistor included in the element layer 40 can be formed into a transistor shape that reduces the manufacturing cost instead of a transistor shape that prioritizes miniaturization, so that an increase in the manufacturing cost can be suppressed.
  • element layer 50_1 shown in FIG. 2 is shown assuming that the transistor and the capacitor are in the same layer, it may be provided in different layers.
  • the configuration is illustrated in FIG. 7B.
  • FIG. 7A is a circuit diagram of a laminated block 30_1 showing a configuration example of a memory cell 51_1 having an element layer 50_A as an element layer 50 provided with a transistor 52 and an element layer 50_B as an element layer 50 provided with a capacitor 53.
  • the device layer 50_A has a transistor 52
  • the device layer 50_B has a capacitor 53.
  • the element layer 50_1 shown in FIG. 2 is shown assuming that a plurality of capacitors are provided in the same layer, it may be provided in different layers. The configuration is illustrated in FIG. 7B.
  • FIG. 7B shows memory cells 51_A and 51_B having an element layer 50_A as the element layer 50 provided with the transistor 52, an element layer 50_B as the element layer 50 provided with the capacitor 53_A, and an element layer 50_C as the element layer 50 provided with the capacitor 53_B.
  • the memory cell 51_A has a transistor 52_A provided in the element layer 50_A and a capacitor 53_A provided in the element layer 50_B.
  • the memory cell 51_B has a transistor 52_B provided in the element layer 50_A and a capacitor 53_B provided in the element layer 50_C.
  • an IC chip that functions as having the semiconductor device 10
  • the semiconductor device 10 can be made into one IC chip by mounting a plurality of dies on a substrate for packaging. 8 and 9A and 9B show an example of the configuration.
  • the schematic cross-sectional view of the IC chip 100 illustrated in FIG. 8 has a silicon substrate 11 and a laminated block in which the element layer 40 and the element layers 50_1 to 50_3 are laminated on the package substrate 101.
  • the package substrate 101 is provided with a solder ball 102 for connecting the IC chip 100 to a printed circuit board or the like.
  • the element layer 40 and the element layers 50_1 to 50_3 can be laminated by repeating the configuration for creating the OS transistor.
  • the peripheral circuits provided on the silicon substrate and each circuit such as the memory cell included in the element layer 40 and the element layers 50_1 to 50_3 may be electrically connected via the through electrode 103 provided so as to penetrate each layer. it can.
  • TSV Three Silicon Via
  • the schematic cross-sectional view of the IC chip 100A shown in FIG. 9A has a silicon substrate 11 and a laminated block in which the element layer 40 and the element layers 50_1 to 50_3 are laminated on the package substrate 101.
  • Peripheral circuits provided on the silicon substrate and circuits such as memory cells included in the element layer 40 and the element layers 50_1 to 50_3 are bonded to each other using the silicon substrate 105.
  • each layer can be electrically connected via a through electrode 103 provided so as to penetrate each layer and a metal bump 104 provided between the layers.
  • the schematic cross-sectional view of the IC chip 100B shown in FIG. 9B has a silicon substrate 11 and a laminated block in which the element layer 40 and the element layers 50_1 to 50_3 are laminated on the package substrate 101.
  • Peripheral circuits provided on the silicon substrate and circuits such as memory cells included in the element layer 40 and the element layers 50_1 to 50_3 are bonded to each other using the silicon substrate 105.
  • each layer can be electrically connected via a through electrode 103 provided so as to penetrate each layer and a metal bump 104 provided between the layers.
  • FIG. 10 is a circuit diagram illustrating a circuit configuration example of the memory cell 51 included in the element layer 50 and a specific circuit configuration example of the peripheral circuit 22 connected to the memory cell described in FIG. ..
  • FIG. 10 illustrates the element layers 50_1 to 50_p.
  • a memory cell 51_p is illustrated as a memory cell of the element layer 50_p connected to the wiring LBL_A.
  • the memory cell 51_p illustrates a transistor 52 and a capacitor 53 whose gate is connected to the word line WL_A.
  • a memory cell 51_c is shown as a memory cell of the element layer 50_p connected to the wiring LBL_B.
  • the memory cell 51_c illustrates a transistor 52B and a capacitor 53B whose gate is connected to the word line WL_B.
  • FIG. 10 illustrates the element layer 40 having the transistors 41_a, 41_b, 42_a, 42_b, 43_a, 43_b, 44_a, 44_b included in the element layer 40.
  • the wirings LBL_A and LBL_B are connected to the gates of transistors 41_a and 41_b.
  • the transistors 42_a, 42_b, 43_a, 43_b included in the element layer 40 are connected to the wiring GBL_A and GBL_B as shown in FIG.
  • the wirings GBL_A and GBL_B are connected to the transistor included in the peripheral circuit 22.
  • control signals WE, RE, and MUX are given to the gates of the transistors 42_a, 42_b, 43_a, 43_b, 44_a, and 44_b of the element layer 40.
  • FIG. 10 shows a precharge circuit 22_A, a precharge circuit 22_B, a sense amplifier 22_C, a switch circuit 22_D, a switch circuit 22_E, and a write / read circuit 29 on the silicon substrate side as circuits included in the peripheral circuit 22.
  • the transistors constituting the precharge circuit 22_A, the precharge circuit 22_B, and the sense amplifier 22_C are composed of Si transistors.
  • the switches 23_A to 23_D constituting the switch circuit 22_D and the switch circuit 22_E can also be composed of Si transistors.
  • One of the source or drain of the transistors 42_a, 42_b, 43_a, 43_b is connected to the transistors constituting the precharge circuit 22_A, the precharge circuit 22_B, the sense amplifier 22_C, and the switch circuit 22_D.
  • the precharge circuit 22_A is composed of n-channel type transistors 24_1 to 24_3.
  • the precharge circuit 22_A is a circuit for precharging the wirings LBL_A and LBL_B to the intermediate potential VPC corresponding to the potential VDD / 2 between VDD and VSS according to the precharge signal given to the precharge line PCL1. ..
  • the precharge circuit 22_B is composed of n-channel type transistors 24_4 to 24_6.
  • the precharge circuit 22_B is a circuit for precharging the wiring GBL_A and the wiring GBL_B to the intermediate potential VPC corresponding to the potential VDD / 2 between VDD and VSS according to the precharge signal given to the precharge line PCL2. is there.
  • the sense amplifier 22_C is composed of p-channel transistors 25_1 and 25_2 and n-channel transistors 25_3 and 25_4 connected to the wiring VHH or wiring VLL.
  • Wiring VHH or Wiring VLL is a wiring having a function of giving VDD or VSS.
  • Transistors 25_1 to 25_1 are transistors that form an inverter loop.
  • the potentials of the wiring GBL_A and the wiring GBL_B can be output to the outside via the write / read circuit 29 via the switch circuit 22_D and the switch circuit 22_E.
  • the wiring LBL_A and LBL_B, and the wiring GBL_A and wiring GBL_B correspond to a bit line pair.
  • the write / read circuit 25 controls the writing of the data signal according to the signal EN_data.
  • the switch circuit 22_D is a circuit for controlling the conduction state between the sense amplifier 22_C and the wiring GBL_A and the wiring GBL_B.
  • the switch circuit 22_D is switched on or off by controlling the switching signal CSEL1.
  • the switches 23_A and 23_B are n-channel transistors, the switching signal CSEL1 is turned on at a high level and turned off at a low level.
  • the switch circuit 22_E is a circuit for controlling the conduction state between the write / read circuit 29 and the bit line pair connected to the sense amplifier 22_C.
  • the switch circuit 22_D is switched on or off by controlling the switching signal CSEL1.
  • the switches 23_C and 23_D may be the same as the switches 23_A and 23_B.
  • FIG. 11 shows a timing chart for explaining the operation of the circuit diagram shown in FIG.
  • the period T11 is the write operation
  • the period T12 is the wiring LBL precharge operation
  • the period T13 is the wiring GBL precharge operation
  • the period T14 is the charge sharing operation
  • the period T15 is the read standby.
  • the operation, period T16 corresponds to the period for explaining the read operation.
  • the word line connected to the gate of the transistor of the memory cell in which the data signal is to be written is set to the high level.
  • the control signal WE and the signal EN_data are set to a high level, and the data signal is written to the memory cell via the wiring GBL and the bit line BL.
  • the precharge line PCL1 is set to a high level while the control signal WE is set to a high level.
  • the bit line BL is precharged to the precharge potential.
  • both the wiring VHH and the wiring VLL that supply the power supply voltage to the sense amplifier 22_C are set to VDD / 2 to suppress the power consumption due to the through current.
  • the precharge line PCL2 is set to a high level in order to precharge the wiring GBL.
  • the wiring GBL is precharged to the precharge potential.
  • control signal WL and the control signal MUX are set to high levels for charge sharing for balancing the charges precharged in the bit line BL and the wiring GBL.
  • the bit wire BL and the wiring GBL are equipotential.
  • both the wiring VHH and the wiring VLL that supply the power supply voltage to the sense amplifier 22_C are set to VDD / 2 to suppress the power consumption due to the through current.
  • the control signal RE is set to a high level. This is a period in which a current flows through the transistor 41 according to the potential of the bit line BL and the potential of the wiring GBL fluctuates according to the amount of the current.
  • the switching signal CSEL1 is set to a low level so that the fluctuation of the potential of the wiring GBL is not affected by the sense amplifier 22_C.
  • Wiring VHH or wiring VLL is similar to period T14.
  • the data signal written in the memory cell is read out by amplifying the fluctuation of the potential of the wiring GBL with the bit line pair connected to the sense amplifier 22_C with the switching signal CSEL1 as the high level.
  • One form of the semiconductor device of the present invention uses an OS transistor having an extremely low off-current as a transistor provided in each element layer.
  • the OS transistor can be laminated on a silicon substrate on which a Si transistor is provided. Therefore, it can be manufactured by repeating the same manufacturing process in the vertical direction, and the manufacturing cost can be reduced. Further, in one embodiment of the present invention, the transistors constituting the memory cell can be arranged in the vertical direction instead of the plane direction to improve the memory density, and the device can be miniaturized.
  • the wiring LBL is connected to the gate of the transistor 41, data can be read out using a slight potential difference of the wiring LBL. Since a circuit such as a sense amplifier using a Si transistor can be miniaturized, the semiconductor device can be miniaturized. Further, it can be operated even if the capacity of the capacitor of the memory cell is reduced.
  • One embodiment of the present invention uses an OS transistor having an extremely low off-current as a transistor provided in each element layer. Therefore, the frequency of refreshing the data held in the memory cell can be reduced, and the semiconductor device can be made with low power consumption.
  • the OS transistors can be stacked and provided, and can be manufactured by repeating the same manufacturing process in the vertical direction, so that the manufacturing cost can be reduced. Further, in one embodiment of the present invention, the transistors constituting the memory cell can be arranged in the vertical direction instead of the plane direction to improve the memory density, and the device can be miniaturized.
  • the OS transistor since the OS transistor has less fluctuation in electrical characteristics than the Si transistor even in a high temperature environment, the fluctuation in electrical characteristics of the transistor when stacked and integrated is small, and the semiconductor device functions as a highly reliable storage device. Can be.
  • the transistor is shown as a transistor having a top gate structure or a bottom gate structure without a back gate electrode, but the structure of the transistor 52 is not limited to this.
  • the transistor included in the memory cell 51 may be a transistor 52 having a back gate electrode connected to the back gate electrode line BGL. With the configuration shown in FIG. 12, it is possible to make it easier to control electrical characteristics such as the threshold voltage of the transistor 52 from the outside.
  • FIG. 13 shows a memory unit 470 (memory unit 470_1 to memory unit 470_m: m is a natural number of 2 or more) on the element layer 411 having a circuit provided on the semiconductor substrate 311.
  • (Shown) is a diagram showing an example of a semiconductor device provided in a laminated manner.
  • a plurality of memory units 470 are laminated on the element layer 411 and the element layer 411.
  • the plurality of memory units 470 include a transistor layer 413 (transistor layer 413_1 to transistor layer 413_m) corresponding to each memory unit 470 on the substrate 450, and a plurality of memory device layers 415 (memory device layer) on each transistor layer 413.
  • n are natural numbers of 2 or more).
  • the transistor layer 413 is provided on the substrate 450 and the memory device layer 415 is provided on the transistor layer 413 is shown, but the present embodiment is not limited to this.
  • a plurality of memory device layers 415 may be provided on the substrate 450, and a transistor layer 413 may be provided on the plurality of memory device layers 415, or memory device layers 415 may be provided above and below the transistor layer 413 on the substrate 450. You may.
  • a material selected from Si, Ge, SiGe, GaAs, GaAlAs, GaN, and InP can be used, respectively.
  • the element layer 411 has a transistor 300 provided on the semiconductor substrate 311 and can function as a circuit of a semiconductor device (sometimes called a peripheral circuit).
  • Examples of circuits include column drivers, row drivers, column decoders, row decoders, sense amplifiers, precharge circuits, amplifier circuits, word line driver circuits, output circuits, control logic circuits, and the like.
  • the transistor layer 413 has a transistor 200T and can function as a circuit for controlling each memory unit 470.
  • the memory device layer 415 has a memory device 420.
  • the memory device 420 shown in this embodiment has a transistor and a capacitance.
  • m is not particularly limited, but is 2 or more and 100 or less, preferably 2 or more and 50 or less, and more preferably 2 or more and 10 or less.
  • n is not particularly limited, but is 2 or more and 100 or less, preferably 2 or more and 50 or less, and more preferably 2 or more and 10 or less.
  • the product of m and n is 4 or more and 256 or less, preferably 4 or more and 128 or less, and more preferably 4 or more and 64 or less.
  • FIG. 13 shows a cross-sectional view of the transistor 200T included in the memory unit and the transistor included in the memory device 420 in the channel length direction.
  • a transistor 300 is provided on the semiconductor substrate 311, and a transistor layer 413 and a memory device layer 415 of the memory unit 470 are provided on the transistor 300, and the transistor layer 413 is provided in one memory unit 470.
  • the transistor 200T included in the memory device layer 415 and the memory device 420 included in the memory device layer 415 are electrically connected by a plurality of conductors 424, and the transistor 300 and the transistor 200T included in the transistor layer 413 in each memory unit 470 are connected to the transistor 426.
  • Conductor 427, and conductor 430 are electrically connected.
  • the conductor 426 is electrically connected to the transistor 200T via a conductor 428 which is electrically connected to any one of the source, drain and gate of the transistor 200T.
  • the conductor 424 is preferably provided in each layer of the memory device layer 415.
  • the conductor 427 is provided on the uppermost layer of each memory unit 470 and is electrically connected to the conductor 426 and the conductor 430.
  • a material selected from Cu, W, Ti, Ta, and Al can be used, respectively.
  • FIG. 13 shows an example in which the substrate 450 of the memory unit 470 is provided on the transistor 300 side, but the present embodiment is not limited to this.
  • the memory unit 470 may be provided so that the memory device layer 415 is provided on the transistor 300 side.
  • the conductor 426 is provided so as to penetrate the memory device layer 415
  • the conductor 430 is provided so as to penetrate the memory device layer 415, the transistor layer 413, and the substrate 450.
  • the conductor 426 is provided so as to penetrate the substrate 450 and the transistor layer 413
  • the conductor 430 is provided so as to penetrate the substrate 450, the transistor layer 413, and the memory device layer 415. ..
  • an insulator such as water or hydrogen or an insulator that suppresses the permeation of oxygen on the side surface of the conductor 424 and the side surface of the conductor 426.
  • an insulator for example, silicon nitride, aluminum oxide, silicon nitride or the like may be used.
  • the memory device 420 has a transistor and a capacitance on the side surface thereof, and the transistor can have a structure similar to that of the transistor 200T included in the transistor layer 413.
  • the transistor 200T uses a metal oxide (hereinafter, also referred to as an oxide semiconductor) that functions as an oxide semiconductor as a semiconductor that includes a region in which a channel is formed (hereinafter, also referred to as a channel formation region). Is preferable.
  • an oxide semiconductor that functions as an oxide semiconductor as a semiconductor that includes a region in which a channel is formed (hereinafter, also referred to as a channel formation region). Is preferable.
  • oxide semiconductors for example, In-M-Zn oxide (element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium). , Neodymium, hafnium, tantalum, tungsten, magnesium, etc. (one or more) and the like may be used. Further, as the oxide semiconductor, indium oxide, In—Ga oxide, or In—Zn oxide may be used. By using an oxide semiconductor having a composition having a high proportion of indium, it is possible to increase the on-current of the transistor, the mobility of the field effect, and the like.
  • the transistor 200T using an oxide semiconductor in the channel formation region has an extremely small leakage current in a non-conducting state, it is possible to provide a semiconductor device with low power consumption. Further, since the oxide semiconductor can be formed into a film by a sputtering method or the like, it can be used for a transistor 200T constituting a highly integrated semiconductor device.
  • a transistor including an oxide semiconductor, impurities and oxygen vacancies in the oxide semiconductor by (V O oxygen vacancy also called), its electrical characteristics are varied, a voltage is applied to normally on (gate electrode Even if there is no channel, there is a characteristic that current flows through the transistor).
  • a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • impurity concentration in the oxide semiconductor is reduced as much as possible.
  • impurities in the oxide semiconductor include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon and the like.
  • hydrogen as an impurity contained in the oxide semiconductor may form an oxygen deficiency in the oxide semiconductor.
  • defects containing hydrogen to an oxygen vacancy (hereinafter may be referred to as V O H.) May generate electrons serving as carriers.
  • a part of hydrogen may react with oxygen bonded to a metal atom to generate an electron as a carrier.
  • a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normal-on characteristics. Further, since hydrogen in the oxide semiconductor easily moves due to stress such as heat and electric field, if the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may deteriorate.
  • the oxide semiconductor used for the transistor 200T it is preferable to use a high-purity intrinsic oxide semiconductor in which impurities such as hydrogen and oxygen deficiency are reduced.
  • the metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, it is preferable that one or a plurality of types selected from aluminum, gallium, yttrium, and tin are contained. Further, one or more kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt and the like may be contained. For example, a metal oxide having indium, zinc, and gallium (In-Ga-Zn-based oxide), and a metal oxide having indium, zinc, and tin (In-Sn-Zn-based oxide). ), Or a metal oxide (In-Ga-Zn-Sn-based oxide) having indium, zinc, gallium, and tin can be preferably used.
  • FIG. 15A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (metal oxides containing In, Ga, and Zn).
  • IGZO metal oxides containing In, Ga, and Zn
  • oxide semiconductors are roughly classified into “Amorphous (amorphous)”, “Crystalline (crystallinity)", and “Crystal (crystal)”.
  • Amorphous includes “completable amorphous”.
  • the "Crystalline” includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned crystal) (extracting single crystal crystal).
  • single crystal, poly crystal, and single crystal amorphous are excluded from the classification of "Crystalline”.
  • “Crystal” includes single crystal and poly crystal.
  • the structure in the thick frame shown in FIG. 15A is an intermediate state between "Amorphous” and “Crystal", and belongs to a new boundary region (New crystal line phase). .. That is, the structure can be rephrased as a structure completely different from the energetically unstable "Amorphous” and "Crystal".
  • the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Evaluation) spectrum.
  • XRD X-ray diffraction
  • FIG. 15B the XRD spectrum obtained by GIXD (Glazing-Incidence XRD) measurement of the CAAC-IGZO film classified as "Crystalline" is shown in FIG. 15B (the vertical axis represents the intensity (Intensity) as an arbitrary unit (a.u.)). (Represented by).
  • the GIXD method is also referred to as a thin film method or a Seemann-Bohlin method.
  • the XRD spectrum obtained by the GIXD measurement shown in FIG. 15B will be simply referred to as an XRD spectrum.
  • a peak showing clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film.
  • the crystal structure of the film or the substrate can be evaluated by a diffraction pattern (also referred to as a microelectron diffraction pattern) observed by a micro electron diffraction method (NBED: Nano Beam Electron Diffraction).
  • the diffraction pattern of the CAAC-IGZO film is shown in FIG. 15C.
  • FIG. 15C is a diffraction pattern observed by the NBED in which the electron beam is incident parallel to the substrate.
  • electron beam diffraction is performed with the probe diameter set to 1 nm.
  • oxide semiconductors may be classified differently from FIG. 15A.
  • oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors.
  • the non-single crystal oxide semiconductor include the above-mentioned CAAC-OS and nc-OS.
  • the non-single crystal oxide semiconductor includes a polycrystalline oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.
  • CAAC-OS CAAC-OS
  • nc-OS nc-OS
  • a-like OS the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.
  • CAAC-OS is an oxide semiconductor having a plurality of crystal regions, the plurality of crystal regions having the c-axis oriented in a specific direction.
  • the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface to be formed of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film.
  • the crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region in which the lattice arrangement is aligned. Further, the CAAC-OS has a region in which a plurality of crystal regions are connected in the ab plane direction, and the region may have distortion.
  • the strain refers to a region in which a plurality of crystal regions are connected in which the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another grid arrangement is aligned.
  • CAAC-OS is an oxide semiconductor that is c-axis oriented and not clearly oriented in the ab plane direction.
  • Each of the plurality of crystal regions is composed of one or a plurality of minute crystals (crystals having a maximum diameter of less than 10 nm).
  • the maximum diameter of the crystal region is less than 10 nm.
  • the size of the crystal region may be about several tens of nm.
  • CAAC-OS has indium (In) and oxygen. It tends to have a layered crystal structure (also referred to as a layered structure) in which a layer (hereinafter, In layer) and a layer having elements M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are laminated. There is. Indium and element M can be replaced with each other. Therefore, the (M, Zn) layer may contain indium. In addition, the In layer may contain the element M. In addition, Zn may be contained in the In layer.
  • the layered structure is observed as a lattice image in, for example, a high-resolution TEM image.
  • the position of the peak indicating the c-axis orientation may vary depending on the type and composition of the metal elements constituting CAAC-OS.
  • a plurality of bright spots are observed in the electron diffraction pattern of the CAAC-OS film. Note that a certain spot and another spot are observed at point-symmetrical positions with the spot of the incident electron beam passing through the sample (also referred to as a direct spot) as the center of symmetry.
  • the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit lattice is not limited to a regular hexagon and may be a non-regular hexagon. Further, in the above strain, it may have a lattice arrangement such as a pentagon or a heptagon.
  • a clear grain boundary cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion because the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal atoms. It is thought that this is the reason.
  • CAAC-OS for which no clear crystal grain boundary is confirmed, is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of the transistor.
  • a configuration having Zn is preferable.
  • In-Zn oxide and In-Ga-Zn oxide are more suitable than In oxide because they can suppress the generation of grain boundaries.
  • CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries can be confirmed. Therefore, it can be said that CAAC-OS is unlikely to cause a decrease in electron mobility due to grain boundaries. Further, since the crystallinity of the oxide semiconductor may be lowered due to the mixing of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor having few impurities and defects (oxygen deficiency, etc.). Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, the oxide semiconductor having CAAC-OS is resistant to heat and has high reliability. CAAC-OS is also stable against high temperatures in the manufacturing process (so-called thermal budget). Therefore, if CAAC-OS is used for the OS transistor, the degree of freedom in the manufacturing process can be expanded.
  • nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less).
  • nc-OS has tiny crystals. Since the size of the minute crystal is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystal is also referred to as a nanocrystal.
  • nc-OS does not show regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film.
  • the nc-OS may be indistinguishable from the a-like OS and the amorphous oxide semiconductor depending on the analysis method.
  • a peak indicating crystallinity is not detected in the Out-of-plane XRD measurement using a ⁇ / 2 ⁇ scan.
  • electron beam diffraction also referred to as limited field electron diffraction
  • a diffraction pattern such as a halo pattern is performed. Is observed.
  • electron diffraction also referred to as nanobeam electron diffraction
  • an electron beam having a probe diameter for example, 1 nm or more and 30 nm or less
  • An electron diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be acquired.
  • the a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor.
  • the a-like OS has a void or low density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.
  • a-like OS has a higher hydrogen concentration in the membrane than nc-OS and CAAC-OS.
  • CAC-OS relates to the material composition.
  • CAC-OS is, for example, a composition of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size close thereto.
  • the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size close thereto.
  • the mixed state is also called a mosaic shape or a patch shape.
  • CAC-OS has a structure in which the material is separated into a first region and a second region to form a mosaic shape, and the first region is distributed in the membrane (hereinafter, also referred to as a cloud shape). It says.). That is, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.
  • the atomic number ratios of In, Ga, and Zn with respect to the metal elements constituting CAC-OS in the In-Ga-Zn oxide are expressed as [In], [Ga], and [Zn], respectively.
  • the first region is a region in which [In] is larger than [In] in the composition of the CAC-OS film.
  • the second region is a region in which [Ga] is larger than [Ga] in the composition of the CAC-OS film.
  • the first region is a region in which [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region.
  • the second region is a region in which [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.
  • the first region is a region in which indium oxide, indium zinc oxide, or the like is the main component.
  • the second region is a region in which gallium oxide, gallium zinc oxide, or the like is the main component. That is, the first region can be rephrased as a region containing In as a main component. Further, the second region can be rephrased as a region containing Ga as a main component.
  • a region containing In as a main component (No. 1) by EDX mapping acquired by using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy). It can be confirmed that the region (1 region) and the region containing Ga as a main component (second region) have a structure in which they are unevenly distributed and mixed.
  • EDX Energy Dispersive X-ray spectroscopy
  • CAC-OS When CAC-OS is used for a transistor, the conductivity caused by the first region and the insulating property caused by the second region act in a complementary manner to switch the switching function (On / Off function). Can be added to CAC-OS. That is, the CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS for the transistor, high on-current ( Ion ), high field effect mobility ( ⁇ ), and good switching operation can be realized.
  • Ion on-current
  • ⁇ high field effect mobility
  • Oxide semiconductors have various structures, and each has different characteristics.
  • the oxide semiconductor according to one aspect of the present invention has two or more of amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS. You may.
  • the oxide semiconductor as a transistor, a transistor with high field effect mobility can be realized. Moreover, a highly reliable transistor can be realized.
  • the carrier concentration of the oxide semiconductor is 1 ⁇ 10 17 cm -3 or less, preferably 1 ⁇ 10 15 cm -3 or less, more preferably 1 ⁇ 10 13 cm -3 or less, and more preferably 1 ⁇ 10 11 cm ⁇ . It is 3 or less, more preferably less than 1 ⁇ 10 10 cm -3 , and more than 1 ⁇ 10 -9 cm -3 .
  • the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density.
  • a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • An oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • the trap level density may also be low.
  • the charge captured at the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel forming region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.
  • Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
  • the concentration of silicon and carbon in the oxide semiconductor and the concentration of silicon and carbon near the interface with the oxide semiconductor are set to 2. ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the oxide semiconductor contains an alkali metal or an alkaline earth metal
  • a defect level may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • the nitrogen concentration in the oxide semiconductor obtained by SIMS is less than 5 ⁇ 10 19 atoms / cm 3 , preferably 5 ⁇ 10 18 atoms / cm 3 or less, and more preferably 1 ⁇ 10 18 atoms / cm 3 or less. , More preferably 5 ⁇ 10 17 atoms / cm 3 or less.
  • hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency.
  • oxygen deficiency When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated.
  • a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have a normally-on characteristic. Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , more preferably 5 ⁇ 10 18 atoms / cm. Less than 3 , more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • FIG. 16 is a block diagram showing a configuration example of a semiconductor device that functions as a memory device.
  • the semiconductor device 10s has a peripheral circuit 20 and a memory cell array 90.
  • the peripheral circuit 20 includes a row decoder 71, a word line driver circuit 72, a column driver 75, an output circuit 73, and a control logic circuit 74.
  • the column driver 75 includes a column decoder 81, a precharge circuit 82, an amplifier circuit 83, and a write circuit 84.
  • the precharge circuit 82 has a function of precharging the wiring LBL, the wiring GBL, and the like.
  • the amplifier circuit 83 has a function of amplifying the data signal read from the wiring GBL. The amplified data signal is output to the outside of the semiconductor device 10s as a digital data signal RDATA via the output circuit 73.
  • the semiconductor device 10s is supplied with a low power supply voltage (VSS), a high power supply voltage for the peripheral circuit 20 (VDD), and a high power supply voltage (VIL) for the memory cell array 90 from the outside.
  • VSS low power supply voltage
  • VDD high power supply voltage
  • VIL high power supply voltage
  • control signal (CE, WE, RE), the address signal ADDR, and the data signal WDATA are input to the semiconductor device 10s from the outside.
  • the address signal ADDR is input to the row decoder 71 and the column decoder 81, and WDATA is input to the write circuit 84.
  • the control logic circuit 74 processes input signals (CE, WE, RE) from the outside to generate control signals for the low decoder 71 and the column decoder 81.
  • CE is a chip enable signal
  • WE is a write enable signal
  • RE is a read enable signal.
  • the signal processed by the control logic circuit 74 is not limited to this, and other control signals may be input as needed. For example, a control signal for determining a defective bit may be input, and a data signal read from an address of a specific memory cell may be specified as a defective bit.
  • FIG. 17 shows various storage devices for each layer.
  • a storage device located in the upper layer is required to have a faster access speed, and a storage device located in the lower layer is required to have a large storage capacity and a high recording density.
  • FIG. 17 shows, in order from the top layer, a memory, a SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), and a 3D NAND memory, which are mixedly loaded as registers in an arithmetic processing unit such as a CPU.
  • SRAM Static Random Access Memory
  • DRAM Dynamic Random Access Memory
  • 3D NAND memory which are mixedly loaded as registers in an arithmetic processing unit such as a CPU.
  • the memory that is mixedly loaded as a register in an arithmetic processing unit such as a CPU is used for temporary storage of arithmetic results, and therefore is frequently accessed from the arithmetic processing unit. Therefore, an operation speed faster than the storage capacity is required.
  • the register also has a function of holding setting information of the arithmetic processing unit.
  • SRAM is used for cache, for example.
  • the cache has a function of duplicating and holding a part of the information held in the main memory. By replicating frequently used data to the cache, the access speed to the data can be increased.
  • DRAM is used, for example, in main memory.
  • the main memory has a function of holding programs and data read from the storage.
  • the recording density of the DRAM is approximately 0.1 to 0.3 Gbit / mm 2 .
  • the 3D NAND memory is used, for example, for storage.
  • the storage has a function of holding data that needs to be stored for a long period of time and various programs used in the arithmetic processing unit. Therefore, the storage is required to have a storage capacity larger than the operating speed and a high recording density.
  • the recording density of the storage device used for storage is approximately 0.6 to 6.0 Gbit / mm 2 .
  • the semiconductor device that functions as the storage device of one aspect of the present invention has a high operating speed and can hold data for a long period of time.
  • the semiconductor device of one aspect of the present invention can be suitably used as a semiconductor device located in the boundary region 901 including both the layer in which the cache is located and the layer in which the main memory is located.
  • the semiconductor device of one aspect of the present invention can be suitably used as a semiconductor device located in the boundary region 902 including both the layer in which the main memory is located and the layer in which the storage is located.
  • FIG. 18A shows a perspective view of the electronic component 700 and the substrate on which the electronic component 700 is mounted (mounting substrate 704).
  • the electronic component 700 shown in FIG. 18A has a semiconductor device 10 in which a laminated block 30 is laminated on a silicon substrate 11 in a mold 711.
  • FIG. 18A does not partially reflect the inside of the electronic component 700 in order to show the inside of the electronic component 700.
  • the electronic component 700 has a land 712 on the outside of the mold 711.
  • the land 712 is electrically connected to the electrode pad 713, and the electrode pad 713 is electrically connected to the semiconductor device 10 by a wire 714.
  • the electronic component 700 is mounted on, for example, the printed circuit board 702. A plurality of such electronic components are combined and each is electrically connected on the printed circuit board 702 to complete the mounting board 704.
  • FIG. 18B shows a perspective view of the electronic component 730.
  • the electronic component 730 is an example of SiP (System in package) or MCM (Multi-chip module).
  • the electronic component 730 is provided with an interposer 731 on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 10 are provided on the interposer 731.
  • the electronic component 730 shows an example in which the semiconductor device 10 is used as a wideband memory (HBM: High Bandwidth Memory). Further, as the semiconductor device 735, an integrated circuit (semiconductor device) such as a CPU, GPU, or FPGA can be used.
  • HBM High Bandwidth Memory
  • the package substrate 732 a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used.
  • the interposer 731 a silicon interposer, a resin interposer, or the like can be used.
  • the interposer 731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches.
  • the plurality of wirings are provided in a single layer or multiple layers.
  • the interposer 731 has a function of electrically connecting the integrated circuit provided on the interposer 731 to the electrode provided on the package substrate 732.
  • the interposer may be referred to as a "rewiring board” or an "intermediate board”.
  • a through electrode may be provided on the interposer 731, and the integrated circuit and the package substrate 732 may be electrically connected using the through electrode.
  • TSV Three Silicon Via
  • interposer 731 It is preferable to use a silicon interposer as the interposer 731. Since it is not necessary to provide an active element in the silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult with a resin interposer.
  • the interposer on which the HBM is mounted is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer as the interposer on which the HBM is mounted.
  • the reliability is unlikely to decrease due to the difference in the expansion coefficient between the integrated circuit and the interposer. Further, since the surface of the silicon interposer is high, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is unlikely to occur. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on an interposer, it is preferable to use a silicon interposer.
  • a heat sink may be provided so as to be overlapped with the electronic component 730.
  • the heat sink it is preferable that the heights of the integrated circuits provided on the interposer 731 are the same.
  • the heights of the semiconductor device 10 and the semiconductor device 735 are the same.
  • an electrode 733 may be provided on the bottom of the package substrate 732.
  • FIG. 18B shows an example in which the electrode 733 is formed of a solder ball.
  • BGA Ball Grid Array
  • the electrode 733 may be formed of a conductive pin.
  • PGA Peripheral Component Interconnect
  • the electronic component 730 can be mounted on another substrate by using various mounting methods, not limited to BGA and PGA.
  • BGA Band-GPU
  • PGA Stimble Pin Grid Array
  • LGA Land Grid Array
  • QFP Quad Flat Package
  • QFJ Quad Flat J-leaded package
  • QFN QuadNeged
  • the robot 7100 includes an illuminance sensor, a microphone, a camera, a speaker, a display, various sensors (infrared sensor, ultrasonic sensor, acceleration sensor, piezo sensor, optical sensor, gyro sensor, etc.), a moving mechanism, and the like.
  • the electronic component 730 has a processor and the like, and has a function of controlling these peripheral devices.
  • the electronic component 700 has a function of storing the data acquired by the sensor.
  • the microphone has a function of detecting acoustic signals such as user's voice and environmental sound.
  • the speaker has a function of emitting audio signals such as voice and warning sound.
  • the robot 7100 can analyze the audio signal input via the microphone and emit the necessary audio signal from the speaker. In the robot 7100, it is possible to communicate with the user by using a microphone and a speaker.
  • the camera has a function of photographing the surroundings of the robot 7100. Further, the robot 7100 has a function of moving by using a moving mechanism. The robot 7100 can capture an image of the surroundings using a camera, analyze the image, and detect the presence or absence of an obstacle when moving.
  • the flying object 7120 has a propeller, a camera, a battery, and the like, and has a function of autonomously flying.
  • the electronic component 730 has a function of controlling these peripheral devices.
  • the image data taken by the camera is stored in the electronic component 700.
  • the electronic component 730 can analyze the image data and detect the presence or absence of an obstacle when moving.
  • the remaining battery level can be estimated from the change in the storage capacity of the battery by the electronic component 730.
  • the cleaning robot 7140 has a display arranged on the upper surface, a plurality of cameras arranged on the side surface, brushes, operation buttons, various sensors, and the like. Although not shown, the cleaning robot 7140 is provided with tires, suction ports, and the like. The cleaning robot 7140 is self-propelled, can detect dust, and can suck dust from a suction port provided on the lower surface.
  • the electronic component 730 can analyze an image taken by a camera and determine the presence or absence of an obstacle such as a wall, furniture, or a step. Further, when an object that is likely to be entangled with the brush such as wiring is detected by image analysis, the rotation of the brush can be stopped.
  • the automobile 7160 has an engine, tires, brakes, a steering device, a camera, and the like.
  • the electronic component 730 controls to optimize the running state of the automobile 7160 based on data such as navigation information, speed, engine state, gear selection state, and brake usage frequency.
  • the image data taken by the camera is stored in the electronic component 700.
  • the electronic component 700 and / or the electronic component 730 can be incorporated into a TV device 7200 (television receiver), a smartphone 7210, a PC (personal computer) 7220, 7230, a game machine 7240, a game machine 7260, and the like.
  • the electronic component 730 built into the TV device 7200 can function as an image engine.
  • the electronic component 730 performs image processing such as noise removal and resolution up-conversion.
  • the smartphone 7210 is an example of a mobile information terminal.
  • the smartphone 7210 includes a microphone, a camera, a speaker, various sensors, and a display unit. These peripherals are controlled by electronic components 730.
  • PC7220 and PC7230 are examples of notebook PCs and stationary PCs, respectively.
  • a keyboard 7232 and a monitoring device 7233 can be connected to the PC 7230 wirelessly or by wire.
  • the game machine 7240 is an example of a portable game machine.
  • the game machine 7260 is an example of a stationary game machine.
  • a controller 7262 is connected to the game machine 7260 wirelessly or by wire. Electronic components 700 and / or electronic components 730 can also be incorporated into the controller 7262.
  • each embodiment can be made into one aspect of the present invention by appropriately combining with the configurations shown in other embodiments or examples. Further, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined.
  • the content described in one embodiment is another content (may be a part of the content) described in the embodiment, and / or one or more. It is possible to apply, combine, or replace the contents described in another embodiment (some contents may be used).
  • figure (which may be a part) described in one embodiment is another part of the figure, another figure (which may be a part) described in the embodiment, and / or one or more.
  • figures (which may be a part) described in another embodiment of the above more figures can be constructed.
  • the components are classified by function and shown as blocks independent of each other.
  • it is difficult to separate the components for each function and there may be a case where a plurality of functions are involved in one circuit or a case where one function is involved in a plurality of circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification, and can be appropriately paraphrased according to the situation.
  • the size, the thickness of the layer, or the area is shown in an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to that scale. It should be noted that the drawings are schematically shown for the sake of clarity, and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing lag.
  • electrode and “wiring” in the present specification and the like do not functionally limit these components.
  • an “electrode” may be used as part of a “wiring” and vice versa.
  • the terms “electrode” and “wiring” include the case where a plurality of “electrodes” and “wiring” are integrally formed.
  • the voltage and the potential can be paraphrased as appropriate.
  • the voltage is a potential difference from a reference potential.
  • the reference potential is a ground voltage (ground voltage)
  • the voltage can be paraphrased as a potential.
  • the ground potential does not necessarily mean 0V.
  • the electric potential is relative, and the electric potential given to the wiring or the like may be changed depending on the reference electric potential.
  • a node can be paraphrased as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc., depending on a circuit configuration, a device structure, and the like.
  • terminals, wiring, etc. can be paraphrased as nodes.
  • a and B are connected means that A and B are electrically connected.
  • the term “A and B are electrically connected” refers to an object (an element such as a switch, a transistor element, or a diode, or a circuit including the element and wiring) between A and B. ) Is present, it means a connection capable of transmitting an electric signal between A and B.
  • the case where A and B are electrically connected includes the case where A and B are directly connected.
  • the fact that A and B are directly connected means that the electric signal between A and B is transmitted through the wiring (or electrode) between A and B without going through the object.
  • a possible connection is a connection that can be regarded as the same circuit diagram when represented by an equivalent circuit.
  • the switch means a switch that is in a conductive state (on state) or a non-conducting state (off state) and has a function of controlling whether or not a current flows.
  • the switch means a switch having a function of selecting and switching a path through which a current flows.
  • the channel length is defined as, for example, in the top view of the transistor, a region or channel where the semiconductor (or the portion where the current flows in the semiconductor when the transistor is on) and the gate overlap is formed. The distance between the source and drain in the region.
  • the channel width is a source in, for example, a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap, or a region where a channel is formed.
  • membrane and layer can be interchanged with each other in some cases or depending on the situation.
  • conductive layer to the term “conductive layer”.
  • insulating film to the term “insulating layer”.
  • PCL1 Precharge line
  • PCL2 Precharge line
  • T11 Period
  • T12 Period
  • T13 Period
  • T14 Period
  • T15 Period
  • Period Period
  • 10 Semiconductor device
  • 10A Semiconductor device
  • 10s Semiconductor device
  • 11 Silicon substrate
  • 20 Peripheral circuit
  • 21 Low driver
  • 22 Peripheral circuit
  • 22_A Precharge circuit
  • 22_B Precharge circuit
  • 22_C Sense amplifier
  • 22_D Switch circuit
  • 22_E Switch circuit
  • 23_A Switch
  • 23_C Switch
  • 23_D Switch
  • 24_1 Transistor
  • 24_3 Transistor
  • 24_4 Transistor
  • 24_6 Transistor
  • 25 Circuit
  • 25_2 Transistor
  • 25_3 Transistor
  • 25_4 Transistor
  • 29 Circuit
  • 30 Laminated block
  • 30_N Laminated block
  • 30_1 Laminated block
  • 31_N La

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  • Non-Volatile Memory (AREA)
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US17/613,605 US12015012B2 (en) 2019-06-07 2020-05-25 Semiconductor device
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US18/740,603 US12381187B2 (en) 2019-06-07 2024-06-12 Semiconductor device
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4220711A3 (en) * 2022-01-27 2023-12-27 Invention And Collaboration Laboratory Pte. Ltd. Ic package including a substrate and three monolithic dies
WO2026009118A1 (ja) * 2024-07-05 2026-01-08 株式会社半導体エネルギー研究所 記憶装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11974422B2 (en) * 2021-11-04 2024-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015039006A (ja) * 2010-07-02 2015-02-26 株式会社半導体エネルギー研究所 半導体装置
WO2017158465A1 (ja) * 2016-03-18 2017-09-21 株式会社半導体エネルギー研究所 記憶装置
JP2018201003A (ja) * 2017-05-26 2018-12-20 株式会社半導体エネルギー研究所 半導体装置及び電子機器

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012256821A (ja) 2010-09-13 2012-12-27 Semiconductor Energy Lab Co Ltd 記憶装置
TWI574259B (zh) 2010-09-29 2017-03-11 半導體能源研究所股份有限公司 半導體記憶體裝置和其驅動方法
JP6607681B2 (ja) * 2014-03-07 2019-11-20 株式会社半導体エネルギー研究所 半導体装置
JP6635670B2 (ja) 2014-04-11 2020-01-29 株式会社半導体エネルギー研究所 半導体装置
US9728243B2 (en) 2015-05-11 2017-08-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device or electronic component including the same
JP2018206456A (ja) 2017-06-07 2018-12-27 株式会社半導体エネルギー研究所 記憶装置
US11205461B2 (en) 2017-06-27 2021-12-21 Semiconductor Energy Laboratory Co., Ltd. Memory device comprising first through fourth transistors
US11004477B2 (en) * 2018-07-31 2021-05-11 Micron Technology, Inc. Bank and channel structure of stacked semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015039006A (ja) * 2010-07-02 2015-02-26 株式会社半導体エネルギー研究所 半導体装置
WO2017158465A1 (ja) * 2016-03-18 2017-09-21 株式会社半導体エネルギー研究所 記憶装置
JP2018201003A (ja) * 2017-05-26 2018-12-20 株式会社半導体エネルギー研究所 半導体装置及び電子機器

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4220711A3 (en) * 2022-01-27 2023-12-27 Invention And Collaboration Laboratory Pte. Ltd. Ic package including a substrate and three monolithic dies
WO2026009118A1 (ja) * 2024-07-05 2026-01-08 株式会社半導体エネルギー研究所 記憶装置

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