WO2020244412A1 - 一种以太网数据传输的方法和通信设备 - Google Patents

一种以太网数据传输的方法和通信设备 Download PDF

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Publication number
WO2020244412A1
WO2020244412A1 PCT/CN2020/092211 CN2020092211W WO2020244412A1 WO 2020244412 A1 WO2020244412 A1 WO 2020244412A1 CN 2020092211 W CN2020092211 W CN 2020092211W WO 2020244412 A1 WO2020244412 A1 WO 2020244412A1
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Prior art keywords
bit stream
trigger
code block
group
fec
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PCT/CN2020/092211
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English (en)
French (fr)
Inventor
孙德胜
刘永志
丁力
朱志刚
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP20819247.6A priority Critical patent/EP3972221B1/en
Publication of WO2020244412A1 publication Critical patent/WO2020244412A1/zh
Priority to US17/457,584 priority patent/US11606167B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0002—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission rate
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0006—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0033—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the transmitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0036—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/324—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0015—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the adaptation strategy
    • H04L1/0017—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the adaptation strategy where the mode-switching is based on Quality of Service requirement
    • H04L1/0018—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the adaptation strategy where the mode-switching is based on Quality of Service requirement based on latency requirement
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L2001/0092—Error control systems characterised by the topology of the transmission link
    • H04L2001/0096—Channel splitting in point-to-point links

Definitions

  • This application relates to the field of communications, and in particular to a method and communication equipment for Ethernet data transmission.
  • the high-speed Ethernet interface has a larger bandwidth and can provide services for more users. It is precisely because there are many users connected, there is rarely a situation where there is no user data transmission at a high speed Ethernet interface. Therefore, for high-speed Ethernet, it is difficult to achieve the effect of reducing power through this solution.
  • the Ethernet interface usually uses a strong forward error correction (FEC) scheme to encode and decode the bit stream, such as the Reed-Solomon (RS) encoding and decoding scheme, which introduces a large delay , Wasting system resources.
  • FEC forward error correction
  • RS Reed-Solomon
  • the present application provides a method for Ethernet data transmission, which can perform error-free switching of the working mode of the physical layer, so that the power of the Ethernet interface and the delay of data transmission can be adjusted while ensuring data transmission.
  • a method for Ethernet data transmission including: a first device sends a first bit stream to a second device, where the first bit stream is N logical data passing through the physical layer of the first device Channel sent; the first device sends a first trigger flag group to the second device, the first trigger flag group is used to indicate the end of the first bit stream transmission; in response to the first trigger flag group The first device sends a second bit stream to the second device, the second bit stream is sent through P logical channels of the physical layer of the first device, and both N and P are positive Integer.
  • the trigger flag By sending the trigger flag, it indicates the time when the processing mode of the bit stream is changed, so as to realize the error-free switching of the physical layer working modes of the first device and the second device during the bit stream transmission. While ensuring the data transmission, the Ethernet Adjust the power of the network interface and the delay of data transmission.
  • the time when the processing method of the bit stream changes can also be understood as the position of the processing method change in the bit stream.
  • the change of the number of logical channels can adjust the bit stream transmission rate, which can reduce the power consumption of the system.
  • the first trigger tag group includes P trigger tags; the first device sends the first trigger tag group to the second device, including: the first trigger tag group The device sends the i-th trigger flag of the P trigger flags through the i-th logical channel of the P logical channels, and i is a positive integer.
  • the switching time can be made accurate and compatible with the existing Ethernet data transmission process.
  • the first trigger tag group includes N trigger tags; the first device sends the first trigger tag group to the second device, including: the first trigger tag group The device sends the i-th trigger flag among the N trigger flags through the i-th logical channel among the N logical channels, where i is a positive integer.
  • the switching time can be made accurate and compatible with the existing Ethernet data transmission process.
  • the i-th trigger flag includes information for identifying the i-th logical channel.
  • the first bitstream is obtained by encoding using a first forward error correction FEC encoding method; the second bitstream is obtained by encoding using a second FEC encoding method, so The error correction capability of the second FEC encoding method is different from that of the first FEC encoding method.
  • the transmission delay can be adjusted and the transmission efficiency can be improved.
  • one of the first bit stream and the second bit stream is obtained through forward error correction FEC encoding.
  • the transmission delay can be adjusted and the transmission efficiency can be improved.
  • the first bit stream includes an anchor point code block
  • the anchor point code block is used to indicate a time when the first bit stream ends sending.
  • the first device and the second device can agree on the time when the handover occurs. Make the switching of the physical layer working mode more flexible.
  • the first trigger mark group is an alignment mark AM group.
  • the alignment mark AM as a trigger mark, the impact on data transmission can be reduced, and the process of switching the physical layer working mode can be simplified.
  • the method further includes: receiving a response code block corresponding to the anchor code block sent by the second device;
  • the device sending the first trigger tag group includes: according to the response code block, the first device sends the first trigger tag group to the second device.
  • a method for Ethernet data transmission including: a second device receiving a first bit stream sent by a first device, the first bit stream passing through the N physical layer of the second device Received by the logical channel; the second device receives the first trigger flag group sent by the first device, the first trigger flag group is used to indicate the end of the first bit stream; in response to the first trigger flag Group reception, the second device receives a second bit stream sent by the first device, the second bit stream is received through P logical channels of the physical layer of the second device, N and P both Is a positive integer.
  • the time for the processing mode of the bit stream to be changed is determined, so as to realize the error-free switching of the physical layer working mode of the first device and the second device during the bit stream transmission.
  • the Ethernet Adjust the power of the network interface and the delay of data transmission.
  • the time when the processing method of the bit stream changes can also be understood as the position of the processing method change in the bit stream.
  • the change of the number of logical channels can adjust the bit stream transmission rate, which can reduce the power consumption of the system.
  • the first trigger tag group includes P trigger tags; the second device receives the first trigger tag group sent by the first device, and includes: The second device receives the i-th trigger flag among the P trigger flags through the i-th logical channel among the P logical channels, where i is a positive integer.
  • the first trigger tag group includes N trigger tags; the second device receives the first trigger tag group sent by the first device, and includes: The second device receives the i-th trigger flag among the N trigger flags through the i-th logical channel among the N logical channels, where i is a positive integer.
  • the i-th trigger flag includes information for identifying the i-th logical channel.
  • the first bitstream is obtained by encoding using a first forward error correction FEC encoding method; the second bitstream is obtained by encoding using a second FEC encoding method, so The error correction capability of the second FEC encoding method is different from that of the first FEC encoding method; the method includes: the second device performs the first FEC decoding method corresponding to the first FEC encoding method to the first FEC encoding method. A bit stream is decoded; the second device decodes the second bit stream in a second FEC decoding mode corresponding to the second FEC encoding mode.
  • one of the first bitstream and the second bitstream is obtained through forward error correction FEC encoding, and the method includes: the second device pairing FEC decoding is performed on the bit stream obtained by FEC encoding.
  • the first bit stream includes an anchor point code block
  • the anchor point code block is used to indicate a time when the first bit stream ends.
  • the first trigger mark group is an alignment mark AM group.
  • the method further includes: the second device sends a response code block corresponding to the anchor code block to the first device, the anchor code block Used to indicate the sending of the first trigger flag group.
  • a communication device including: a communication interface; the communication interface is used to send a first bit stream to a second device, and the first bit stream is a physical layer of N logic through the communication interface Channel; the communication interface is also used to send a first trigger flag group to the second device, the first trigger flag group is used to indicate the end of the first bit stream transmission; in response to the first To trigger the sending of the flag group, the communication interface is further configured to send a second bit stream to the second device, the second bit stream is sent through P logical channels of the physical layer of the communication interface, N , P are both positive integers.
  • the first trigger tag group includes P trigger tags
  • the communication interface is configured to send the P through the i-th logical channel among the P logical channels.
  • the i-th trigger flag among the trigger flags, i is a positive integer.
  • the first trigger mark group includes N trigger marks
  • the communication interface is configured to send the N trigger marks through the i-th logical channel among the N logical channels.
  • the i-th trigger flag among the trigger flags, i is a positive integer.
  • the i-th trigger flag includes information for identifying the i-th logical channel.
  • the first bit stream is obtained by encoding using a first forward error correction FEC encoding method; the second bit stream is obtained by encoding using a second FEC encoding method, so The error correction capability of the second FEC encoding method is different from that of the first FEC encoding method.
  • one of the first bit stream and the second bit stream is obtained through forward error correction FEC encoding.
  • the first bit stream includes an anchor point code block
  • the anchor point code block is used to indicate the time when the first bit stream ends sending.
  • the first bit stream includes an anchor point code block
  • the anchor point code block is used to indicate the time when the first bit stream ends sending.
  • the first trigger mark group is an alignment mark AM group.
  • the communication interface is further configured to: receive a response code block corresponding to the anchor code block sent by the second device; The second device sends the first trigger flag group.
  • a communication device which is characterized by comprising: a communication interface; the communication interface is configured to receive a first bit stream sent by a first device, and the first bit stream is transmitted through the communication interface Received by N logical channels of the physical layer; the communication interface is further configured to receive a first trigger flag group sent by the first device, where the first trigger flag group is used to indicate the end of the first bit stream; In response to receiving the first trigger flag group, the communication interface is further configured to receive a second bit stream sent by the first device, where the second bit stream is prepared through the physical layer of the communication interface For P logical channels, N and P are both positive integers.
  • the first trigger mark group includes P trigger marks
  • the communication interface is configured to receive the P through the i-th logical channel among the P logical channels.
  • the i-th trigger flag among the trigger flags, i is a positive integer.
  • the first trigger mark group includes N trigger marks
  • the communication interface is configured to receive the N trigger marks through the i-th logical channel among the N logical channels.
  • the i-th trigger flag among the trigger flags, i is a positive integer.
  • the i-th trigger flag includes information for identifying the i-th logical channel.
  • the first bitstream is obtained by encoding using a first forward error correction FEC encoding method
  • the second bitstream is obtained by encoding using a second FEC encoding method, so The error correction capability of the second FEC encoding method is different from that of the first FEC encoding method
  • the communication device includes a processor, and the processor is configured to: use a first FEC decoding method corresponding to the first FEC encoding method, Decoding the first bitstream; and decoding the second bitstream through a second FEC decoding manner corresponding to the second FEC encoding manner.
  • one of the first bit stream and the second bit stream is obtained through forward error correction FEC encoding
  • the communication device includes: a processor, and The processor is used to perform FEC decoding on the bit stream obtained through forward error correction FEC encoding.
  • the first bit stream includes an anchor point code block
  • the anchor point code block is used to indicate a time when the first bit stream ends.
  • the first trigger mark group is an alignment mark AM group.
  • the communication interface is further configured to send a response code block corresponding to the anchor code block to the first device, where the anchor code block is used to indicate The sending of the first trigger flag group.
  • a communication device which includes a generating module and a transceiver module; the transceiver module is used to send a first bit stream to a second device, where the first bit stream is N logical components that pass through the physical layer of the communication device. Channel sent.
  • the generating module is used to generate the first trigger mark group.
  • the transceiver module is further configured to send a first trigger flag group to the second device, where the first trigger flag group is used to indicate the end of sending the first bit stream.
  • the transceiver module is further configured to send a second bit stream to the second device, where the second bit stream is P logical channels passing through the physical layer of the communication device When sent, N and P are both positive integers.
  • the first trigger mark group includes P trigger marks; the transceiver module is configured to send the P trigger marks through the i-th logical channel among the P logical channels.
  • the i-th trigger mark in the trigger mark, i is a positive integer.
  • the i-th trigger flag includes information for identifying the i-th logical channel.
  • the first bit stream is obtained by encoding using a first forward error correction FEC encoding method
  • the second bit stream is obtained by encoding using a second FEC encoding method
  • the second FEC encoding method is the same as the The error correction capability of the first FEC encoding method is different.
  • one of the first bit stream and the second bit stream is obtained through forward error correction FEC encoding.
  • the first bit stream includes an anchor point code block
  • the anchor point code block is used to indicate a time when the first bit stream ends sending.
  • the first trigger mark group is an alignment mark AM group.
  • the transceiver module is further configured to receive a response code block corresponding to the anchor code block sent by the second device; according to the response code block, the transceiver module is configured to Sending the first trigger flag group to the second device.
  • a communication device including a transceiver module and a processing module.
  • the transceiver module is configured to receive a first bit stream sent by a first device, where the first bit stream is received through N logical channels of the physical layer of the communication device.
  • the transceiver module is further configured to receive a first trigger flag group sent by the first device, where the first trigger flag group is used to indicate the end of the first bit stream.
  • the transceiver module is further configured to receive a second bit stream sent by the first device, where the second bit stream is the P logic through the physical layer of the communication device N and P are all positive integers received by the channel.
  • the processing module is used for processing the first bit stream and the second bit stream.
  • the first trigger mark group includes P trigger marks.
  • the transceiver module is configured to receive the i-th trigger flag of the P trigger flags through the i-th logical channel of the P logical channels, where i is a positive integer.
  • the first trigger mark group includes N trigger marks.
  • the transceiver module is configured to receive the i-th trigger flag among the N trigger flags through the i-th logical channel among the N logical channels, where i is a positive integer.
  • the i-th trigger flag includes information for identifying the i-th logical channel.
  • the first bit stream is obtained by encoding using a first forward error correction FEC encoding method; the second bit stream is obtained by encoding using a second FEC encoding method, so The error correction capability of the second FEC encoding method is different from that of the first FEC encoding method.
  • the processing module is configured to: decode the first bit stream through a first FEC decoding method corresponding to the first FEC encoding method; and decode the first bit stream through a second FEC decoding method corresponding to the second FEC encoding method. The second bit stream is decoded.
  • one of the first bit stream and the second bit stream is obtained through forward error correction FEC encoding.
  • the processing module is used to perform FEC decoding on the bit stream obtained through forward error correction FEC encoding.
  • the first bit stream includes an anchor point code block
  • the anchor point code block is used to indicate a time when the first bit stream ends.
  • the first trigger mark group is an alignment mark AM group.
  • the transceiver module 1510 is further configured to send a response code block corresponding to the anchor code block to the first device, where the anchor code block is used to indicate all The sending of the first trigger flag group.
  • a computer program storage medium characterized in that the computer program storage medium has program instructions, and when the program instructions are executed, the above method is executed.
  • a chip is provided.
  • the chip system includes at least one processor.
  • a program instruction is executed in the at least one processor, the above method is executed.
  • Figure 1 is a schematic diagram of a network connected based on Ethernet technology.
  • Fig. 2 is a schematic structural diagram of a communication device.
  • Fig. 3 is a schematic flowchart of an Ethernet data transmission method.
  • Fig. 4 is a schematic flow chart of another Ethernet data transmission method.
  • FIG. 5 is a schematic flowchart of a method for transmitting data over an Ethernet network according to an embodiment of the present application.
  • Fig. 6 is a schematic diagram of the types of 64B/66B code blocks in the IEEE802.3 specification.
  • Figure 7 is a schematic diagram of a control code block of type 0x4B.
  • FIG. 8 is a schematic flowchart of a method for transmitting data over an Ethernet network according to another embodiment of the present application.
  • FIG. 9 is a schematic flowchart of a method for transmitting data over an Ethernet network according to another embodiment of the present application.
  • 10a to 10d are schematic diagrams of data transmission over an Ethernet provided by another embodiment of the present application.
  • FIG. 11 is a schematic flowchart of a method for transmitting data through Ethernet according to another embodiment of the present application.
  • Figures 12a to 12c are schematic diagrams of data transmission over an Ethernet provided by another embodiment of the present application.
  • FIG. 13 is a schematic flowchart of a method for transmitting data over Ethernet according to another embodiment of the present application.
  • FIG. 14a to 14d are schematic diagrams of data transmission through an Ethernet provided by another embodiment of the present application.
  • FIG. 15 is a schematic flowchart of a method for transmitting data through Ethernet according to another embodiment of the present application.
  • FIGS 16a to 16c are schematic diagrams of data transmission over an Ethernet provided by another embodiment of the present application.
  • Fig. 17 is a schematic flowchart of yet another Ethernet data transmission method.
  • FIG. 18 is a schematic flowchart of a method for transmitting data over Ethernet according to another embodiment of the present application.
  • FIG. 19 is a schematic flowchart of a method for transmitting data over Ethernet according to another embodiment of the present application.
  • FIGS 20a to 20c are schematic diagrams of data transmission over an Ethernet provided by another embodiment of the present application.
  • FIG. 21 is a schematic flowchart of a communication method provided by an embodiment of the present application.
  • FIG. 22 is a schematic diagram of an anchor point package provided by an embodiment of the present application.
  • FIG. 23 is a schematic structural diagram of a communication device provided by an embodiment of the present application.
  • FIG. 24 is a schematic structural diagram of a communication device according to another embodiment of the present application.
  • FIG. 25 is a schematic structural diagram of a communication device according to another embodiment of the present application.
  • FIG. 26 is a schematic structural diagram of a communication device according to another embodiment of the present application.
  • Ethernet-related standards issued by the Institute of Electrical and Electronics Engineers (IEEE) 802.3 working group have been greatly welcomed by network vendors for their concise, best-effort transmission methods and standardized interconnection mechanisms.
  • IEEE 802.3 working group Ethernet-based transmission technology has been widely used in telecommunication networks.
  • Figure 1 is a schematic diagram of a network connected based on Ethernet technology.
  • the communication device 110 and the communication device 120 and the communication device 130 perform user data transmission based on Ethernet
  • the communication device 140 and the communication device 120 and the communication device 130 perform user data transmission based on Ethernet.
  • Two communication devices based on Ethernet for user data transmission can be connected by cable or optical fiber.
  • Fig. 2 is a schematic structural diagram of a communication device.
  • the communication device 110 is used for data transmission based on Ethernet.
  • the communication device 110 includes a main control switching unit, an interface unit, and the like.
  • the main control switching unit includes a network processor (NP) or a switching chip.
  • the interface unit is used for information interaction between the device 110 and other devices.
  • the interface unit includes an Ethernet interface, and the data transmission process of the Ethernet interface can refer to Figure 3 and Figure 4.
  • the Ethernet interface can be used to perform all or part of the functions of the medium access control (MAC) layer, the reconciliation sublayer (RS), and the physical (PHY) layer.
  • the method of data transmission by the Ethernet interface can be implemented by a chip or FPGA.
  • Fig. 3 is a schematic flow chart of a method for Ethernet data transmission, which mainly describes related processing procedures of the physical layer.
  • the packet is verified and follows a certain medium independent interface (medium independent interface, MII) requires coding, which is sent to the physical coding sublayer (PCS) through xMII.
  • the PCS sublayer receives xMII information sent by various MII (some kind of MII, xMII) interfaces, and performs bit code block coding and rate matching.
  • xMII is generally used between the MAC layer and the physical layer of Ethernet equipment. In some embodiments, the xMII interface exists within the integrated circuit.
  • the PCS sublayer is coded according to the 64-bit (bit, B)/66B rule to form a serial stream.
  • the PCS sublayer further encodes the 64B/66B code block into a 257B code block stream according to the 256B/257B coding rule.
  • an alignment marker (AM) group is inserted.
  • AM alignment marker
  • the 257B code block stream is distributed to two forward error correction (FEC) codes according to 10-bit symbols, and check bits are added.
  • FEC forward error correction
  • the FEC encoding and decoding methods adopted by the 2-channel FEC are the same, and the encoding-decoding rate and the ability to resist burst errors can be improved through the 2-channel FEC.
  • PCSL physical coding sublayer lanes
  • the inserted AM will be distributed on each PCSL.
  • the symbols on the PCSL may be sent to the second device through the physical medium attachment (PMA) and physical medium dependent (PMD).
  • PMA physical medium attachment
  • PMD physical medium dependent
  • the second device receives the symbols sent by the first device through PMD and PMA, uses the AM on each PCSL to lock the channel, and reorders each PCS channel to obtain a symbol stream, and then RS-decodes the symbol stream to form a serial code Block stream and remove the AM group in the serial code block stream, and then descramble and reverse transcode the serial code block stream after removing the AM group to obtain a 64B/66B serial code block stream.
  • 64B The serial code block stream of /66B is decoded and rate-matched and sent to the RS sublayer and MAC layer, and the data is transmitted to the data link layer through the MAC layer.
  • a bit is a bit in a binary number, a unit of measurement of the amount of information, and the smallest unit of the amount of information.
  • the code block stream of 257B, the code block stream of 66B, and the symbol stream distributed to the logical channel can all be understood as bit streams.
  • FIG. 3 only briefly describes the processing flow of the Ethernet interface, and other processing procedures can be added in the application, or some of the processing procedures described above can be reduced.
  • the above method is applicable to 200G and 400G Ethernet interfaces.
  • the process of FEC encoding, FEC decoding and 257B transcoding may not be included.
  • Fig. 4 is a schematic flowchart of a method for transmitting data on an Ethernet, which mainly describes related processing procedures of the physical layer. The method shown in Figure 4 is applicable to 40G and 100G Ethernet interfaces.
  • the packet is checked, encoded according to xMII requirements, and sent to the PCS sublayer through xMII.
  • the PCS sublayer encodes the received information through the xMII interface in accordance with the 64B/66B encoding rules to form a serial 66B code block stream.
  • the code block stream of the 66B code block is scrambled, distributed to 20 PCSLs, and inserted into the AM of each PCSL.
  • a 100G Ethernet interface includes 20 PCSLs, 20 PCSLs correspond to 20 AMs, and each AM is sent via a PCSL.
  • the data in PCSL is sent to the second device via PMA and PMD.
  • the PCS sublayer of the second device receives the bit stream sent by the first device through the PCSL.
  • the second device locks the PCSL according to the AM in each PCSL, eliminates jitter, and reorders each PCSL to form a serial stream. After that, AM is removed and descrambling is performed.
  • the 66B code block stream is decoded and sent to the MII interface, and the MAC/RS sublayer receives information from the MII interface.
  • the FEC sublayer of the first device receives the bit stream sent by the PCSL.
  • the FEC sublayer may be a sublayer in the physical layer.
  • the PCS sublayer includes the FEC sublayer.
  • the AM of each FECL has a corresponding relationship with the AM of multiple PCSLs.
  • the corresponding relationship is also called the mapping relationship.
  • the AM of each FECL can be determined.
  • FEC encoding is performed and distributed to multiple FECLs according to the symbols. For example, 100G is 4 FECLs.
  • PMA and PMD the data in FECL is sent to the second device.
  • the second device receives the transmitted bit stream from the FECL.
  • the second device locks each channel according to the AM information of each FECL to eliminate jitter.
  • the locked FECLs are reordered, and after FEC decoding, a 257B serial stream is formed and the AM group is removed.
  • the 257B code block stream is transcoded into a 66B code block stream, inserted into the AM of each PCSL, and distributed to the PCSL.
  • the AM of PCSL has a corresponding relationship with the AM of FECL.
  • the AM corresponding to each PCSL inserted by the second device is the same as the AM corresponding to the PCSL inserted by the first device.
  • the PCS sublayer of the second device receives the bit stream sent by the FEC sublayer through the PCSL.
  • the second device locks the FECL according to the AM in each FECL, eliminates jitter, and reorders each FECL to form a serial stream.
  • the AM of each PCSL is removed and descrambling is performed.
  • the 66B code block stream is decoded and sent to the xMII interface.
  • the MAC/RS sublayer receives the information from the xMII interface and completes the verification and related processing, and then restores the Ethernet packet.
  • AM group can be several code blocks.
  • the logical channel in this application can refer to the physical coding sublayer lane (PCSL), or the forward error correction coding lane (FECL), or 200G, 400G and higher speed Ethernet
  • PCSL physical coding sublayer lane
  • FECL forward error correction coding lane
  • 200G, 400G and higher speed Ethernet The channel deployed in the interface for independent FEC encoding, decoding and symbol distribution. That is, the serial bit stream is distributed to at least one FEC code according to the symbol, and distributed to a group of FEC channels according to the symbol, and the at least one FEC can be considered as a logical channel. The same is true for the receiving direction.
  • the 2-channel FEC encoding in the first device may be a logical channel.
  • the 2-channel FEC decoding in the second device can be a logical channel.
  • PCSL can also be referred to as FEC lane (FECL).
  • Logic channels are generally visible in the chip, that is, they start or end inside the integrated circuit.
  • the attachment unit interface may be called a physical channel.
  • the physical channel is deployed between the chips, or between the chip and the optical module.
  • the logical channel and the bus channel are different paths in the transmission process, and can also be understood as different levels in the transmission process (for example, the physical channel can be regarded as the service layer of the logical channel).
  • multiple channels for independent FEC encoding (at least one encoder) and symbol distribution can also be used.
  • c physical channels correspond to one logical channel.
  • c logical channels correspond to one physical channel, and the code block stream is distributed to each logical channel according to the symbol in the first device. If one or more logical channels correspond to one physical channel, the data on the logical channel can correspond to The second device receives the data sent by the b physical channels of the first device through b physical channels, and then distributes the data of one physical channel to c logical channels.
  • PCSL for a 200G Ethernet interface, there can be 8 parallel logical channels PCSL, which can be that the bits on two logical channels are distributed to one physical channel, and each logical channel transmits 25G of payload data.
  • Two logical channels correspond to one physical channel, and one physical channel transmits 50G payload data.
  • the FEC encoding and decoding that is, the use of encoding and decoding technology to correct bit errors in the transmission process.
  • the FEC encoding may be, for example, Reed-Solomon (RS) encoding.
  • RS Reed-Solomon
  • the purpose of RS encoding is to further improve the correct rate of the bit stream during transmission.
  • the bits with errors can be corrected according to the inserted check bits.
  • RS coding it can be considered that without changing the original code block stream, some check bits are inserted every certain bit interval.
  • RS decoding it can be considered that without changing the original code block stream, the error bits in the transmission process are calculated and restored based on the check bits inserted every certain bit interval during RS encoding. After the check is completed, these check bits are removed.
  • IEEE802.3 standard 200G, 400G Ethernet interface adopts RS (544,514) scheme
  • 100G Ethernet interface can adopt RS (544,514) or RS (528,514) scheme.
  • Some manufacturers also use the RS (272,257) program. These RS schemes have strong error correction capability RS (544,514), but the time delay introduced is also longer.
  • the RS (272,257) has weak error correction capability, but introduces less delay.
  • IEEE 802.3 standardizes a low-power management technology energy-efficient Ethernet (EEE).
  • EEE low-power management technology energy-efficient Ethernet
  • the MAC/RS layer sends a low-power idle (low-power idle) to the PCS layer.
  • Power idle (LPI) code block some elements in the PCS sublayer, PMA sublayer, and PMD sublayer are turned off and enter a deep sleep state.
  • Some of the closed components may be components with higher energy consumption, such as logical channels and physical channels.
  • the MAC layer receives the data and sends idle code blocks to the PCS layer. When the PCS layer monitors the idle code block, it immediately wakes up the closed working elements, that is, the closed working elements are powered on.
  • the high-speed Ethernet interface has a larger bandwidth and can provide services for more users. It is precisely because of the large number of connected users that high-speed Ethernet interfaces rarely have scenarios where there is no traffic at all. Therefore, for high-speed Ethernet, it is difficult to achieve the effect of reducing power through this solution.
  • Layer 2 includes the MAC layer
  • Layer 3 includes the Internet protocol (IP) layer, multi-protocol label switching (multi-protocol label switching, MPLS) layer, etc.
  • IP Internet protocol
  • MPLS multi-protocol label switching
  • This technology requires deployment of a network management or controller for configuration, which is a network-level behavior and has a greater impact on the system.
  • the packet transmission rates on the two paths may be different, in order to ensure that no packets are lost and packets are not out of order, during the switching process, the receiving end device needs to set up functional modules for buffering and packet reordering, which is costly Big.
  • Ethernet link adopts a strong FEC at the physical layer.
  • the IEEE 802.3 standard 200G and 400G Ethernet interfaces use RS (544,514), which has a large delay.
  • FEC schemes with weaker error correction capabilities or no FEC can meet the requirements. Regardless of the business scenarios, they are all processed by FEC with stronger capabilities, which introduces a larger transmission delay and wastes system resources.
  • this application provides a method for data transmission via Ethernet.
  • FIG. 5 is a schematic flowchart of a method for transmitting data over an Ethernet provided by an embodiment of the present application.
  • step S501 the first device sends the first bit stream to the second device.
  • the first bit stream is sent through N logical channels of the physical layer of the first device.
  • the first device distributes the serial bit stream to multiple logical channels according to bit code blocks or symbols
  • the second device locks and reorders the multiple logical channels and receives the bit code blocks Or symbol to form a serial bit stream.
  • the sequential pairs of bit code blocks or symbols in multiple logical channels are fixed. Therefore, it can be considered that the first device sends a bit stream to the second device through multiple logical channels.
  • the first bit stream may include logical channel indication information, and the logical channel indication information is used to indicate P logical channels for sending the second bit stream.
  • the network manager may send logical channel indication information to the first device and the second device, indicating P logical channels for sending the second bit stream.
  • the first bit stream may include anchor point information, and the anchor point information is used to indicate the time when the first bit stream ends sending. It can also be understood that the anchor point information is used to indicate the position of the first trigger mark group in the bit stream.
  • the anchor point information may be, for example, an anchor point code block.
  • the anchor point information can also correspond to multiple code blocks.
  • the anchor point information can also be represented by an anchor point packet, see the description of Figs. 21-22.
  • the second device receives the anchor code block. After receiving the anchor code block, the second device may remove the anchor code block. The second device may remove the anchor code block from the serial bit stream after reordering the logical channels to form a serial bit stream.
  • the second device can detect the trigger mark according to the anchor code block.
  • the second device can monitor logic channels and detect trigger marks in multiple logic channels.
  • the second device may reorder the logical channels to form a serial bit stream, and then detect the trigger mark in the serial bit stream.
  • the second device can remove the trigger mark from the serial bit stream.
  • the removal of the trigger mark can also be called the extraction of the trigger mark. Removing the trigger mark can reduce the interference to data transmission.
  • the first device and the second device can configure the switching of working modes, reducing system overhead.
  • the anchor code block may include physical layer switching information, and the physical layer switching information is used to identify that the code block is used for switching the physical layer working mode.
  • the anchor code block may include an anchor code block identifier, and the anchor code block identifier is used to indicate that the code block is an anchor code block.
  • the anchor code block may include trigger indication information, and the trigger indication information is used to indicate the position of the trigger tag group in the bit stream.
  • the anchor code block may include first handover mode indication information, and the first handover mode indication information is used to indicate a handover mode.
  • the switching mode includes the switching of the transmission rate and/or the switching of the transmission delay. To switch the transmission rate, before and after the switch, the bit stream is sent through different numbers of logical channels. The transmission delay is switched. Before and after the switching, different FEC coding methods (including no FEC coding) are used to obtain the bit stream.
  • the second device may send a response code block to the first device.
  • the response code block is used to indicate the sending of the first trigger flag group. That is, according to the response code block, the first device sends the first trigger flag group to the second device.
  • the physical layer of the first device may include a sending logical channel and a receiving logical channel.
  • the sending logical channel can be used to send a bit stream to the second device.
  • the receiving logical channel can be used to receive the bit stream sent by the second device.
  • the sending logic channel and the receiving logic channel of the first device can run simultaneously.
  • the first device may receive the response information sent by the second device through the receiving logical channel, and the response information may be, for example, an anchor code block or adopt the same type as the anchor code block.
  • the response message can be a response code block.
  • the response code block may include the identification of the response information, for example, the corresponding field in the response code block and the anchor code block identification identifies that the code block is a "response" code block.
  • the response code block may include second switching mode indication information.
  • the first device may determine the switching mode according to the second switching mode indication information in the response code block.
  • the anchor code block includes the first switching mode indication information, and the first switching mode indication information indicates that the switching mode is speed reduction and delay reduction.
  • the response code block includes the second switching mode indication information, and the second switching mode indication information indicates that the transmission rate is unchanged and the delay is reduced.
  • the first device determines that the switching mode is constant transmission rate to reduce delay.
  • the second device may determine the second handover mode indication information according to the handover mode that can be supported.
  • the response code block may include physical layer switching information, and the physical layer switching information is used to identify that the code block is used for switching the physical layer working mode.
  • the first device does not stop sending the first bit stream, and does not perform steps S502-S503. If the first device receives the response code block, steps S502-S503 are performed.
  • the reliability of the switching process can be improved. If the second device does not support the switching of the physical layer working mode, only the first device performs the switching, which may cause data reception errors. When the second device supports the switching of the physical layer working mode, sending the response code block to the first device can improve the reliability of the switching process and avoid data loss.
  • the response code block may also include second switching mode indication information, and the second switching mode indication information may indicate the type of switching mode supported by the second device. Thereby further improving the reliability of the handover process.
  • the first device may also determine that the second device supports the switching of the physical layer working mode through the information sent by the gateway.
  • the first bitstream does not include anchor code blocks.
  • the first device and the second device can determine the switching mode through network management configuration.
  • step S502 the first device sends a first trigger flag group to the second device, where the first trigger flag group is used to indicate the end of sending the first bit stream.
  • the first trigger mark group may be a mark for switching between two different working modes.
  • the first trigger flag group can be sent in the same manner as the first bit stream or the second bit stream.
  • the first trigger mark group includes trigger marks corresponding to the aforementioned N logical channels or P logical channels.
  • the first trigger flag group includes AMs corresponding to the aforementioned N or P logical channels.
  • the embodiment of the present application does not limit the form of the trigger flag group, which may be one or more 257B code blocks, or one or more 66B code blocks, or other forms.
  • the first trigger mark group can reuse the AM group, that is, the first trigger mark group can be an AM group.
  • the first trigger tag group may include one or more 66B code blocks, and the one or more 66B code blocks correspond to N or P PCSL AMs.
  • the first device may insert the trigger flag group in the serial first bit stream before the first bit stream is distributed to the N logical channels.
  • the first device may insert the trigger mark in the logical channel corresponding to each trigger mark in the first trigger mark group during the process of distributing the first bit stream.
  • the second device receives the first trigger flag group.
  • the second device can detect the trigger mark corresponding to each logical channel. After detecting the trigger mark, the second device may remove the trigger mark from the bit stream.
  • the trigger mark is the AM of the logic channel
  • the process of removing the AM is the removal of the trigger mark.
  • step S503 in response to the sending of the first trigger flag group, the first device sends the second bit stream to the second device.
  • the second bit stream is sent through P logical channels of the physical layer of the first device, and N and P are both positive integers.
  • the first trigger mark group may include N trigger marks, and the first device may send the i-th trigger mark of the N trigger marks through the i-th logical channel of the N logical channels.
  • the first trigger mark group may include P trigger marks, and the first device may send the i-th trigger mark of the P trigger marks through the i-th logical channel of the P logical channels.
  • the P logical channels for sending the P trigger flags are the same as the P logical channels for sending the second bit stream by the first device.
  • the second device In response to receiving the first trigger flag group, the second device receives a second bit stream sent by the first device.
  • the trigger marks sent through each logical channel may be the same or different.
  • the i-th trigger mark may include information for identifying the i-th logical channel.
  • N and P can be the same or different.
  • the first bit stream and the second bit stream can be sent through the same or different numbers of logical channels.
  • the first bit stream and the second bit stream may be sent through the same logical channel.
  • the transmission rate of the bit stream can be changed, that is, the transmission rate can be switched. If N is greater than P, before and after the first trigger flag group is sent, the number of physical layer logical channels used to send the bit stream is reduced, the power consumption of the system is reduced, and the transmission rate of the bit stream is reduced. If N is less than P, before and after the first trigger flag group is sent, the number of physical layer logical channels used to send the bit stream increases, the power consumption of the system increases, and the transmission rate of the bit stream increases.
  • the physical layer logical channel that does not perform bit stream transmission can be taken out of operation.
  • the logical channel exiting operation means that the logical channel stops sending the bit stream, that is, the physical device corresponding to the logical channel exits operation.
  • One physical channel corresponds to one or more logical channels. Some logical channels stop sending bit streams, which may cause some physical channels to stop sending bit streams, further reducing system power consumption. Therefore, when the control logic channel exits operation, the logical channel corresponding to the minimum number of physical channels can be controlled to exit operation. In other words, more physical channels can be taken out of operation and system power consumption can be reduced.
  • FEC encoding methods correspond to different error correction capabilities. Using FEC coding will introduce delay. If the FEC encoding method with stronger error correction capability is adopted for encoding, the longer the delay will be introduced.
  • the first bit stream may be obtained by encoding in a first FEC encoding manner
  • the second bit stream may be obtained by encoding in a second FEC encoding manner
  • the first FEC encoding manner may be different from the second FEC encoding manner.
  • Different FEC encoding methods correspond to different error correction capabilities, that is, the second FEC encoding method has different error correction capabilities from the first FEC encoding method.
  • the second device receives the first bit stream.
  • the second device decodes the first bit stream by using the first FEC decoding mode corresponding to the first FEC encoding mode.
  • the second device receives the second bit stream.
  • the second device decodes the second bit stream in a second FEC decoding manner corresponding to the second FEC encoding manner.
  • one of the first bit stream and the second bit stream is obtained through FEC encoding.
  • one of the first bitstream and the second bitstream has undergone FEC encoding, and the other has not undergone FEC encoding.
  • the second device performs FEC decoding on the bit stream obtained by FEC encoding.
  • the data processing process is almost unchanged before and after the switch.
  • the switch of transmission delay at any time before and after the switch, even if the bit stream does not undergo FEC encoding and decoding, the bit stream still needs to be transmitted through FECL.
  • the first device may agree with the second device to switch the working mode and the time point of the switch through the anchor code block.
  • the time point of the switch can be understood as the position in the bitstream.
  • the first device can instruct the second device to switch by triggering the transmission of the tag group, thereby ensuring error-free codes.
  • the first device triggers the sending of the mark group, which can be used as the starting point of the new working mode or the end point of the original working mode.
  • the second device triggers the reception of the mark group, which can be used as the starting point of the new working mode or the end point of the original working mode.
  • the trigger mark group can be used as the starting point of a new working mode, or the end of the original working mode.
  • the switching of the working mode can be the exit or resumption of operation of some logical channels, the change of the FEC scheme, the combination of these two methods, or the switching of other physical layer working modes.
  • Changing the FEC scheme may include whether to switch FEC and switch the FEC codec mode.
  • Fig. 6 is a schematic diagram of the types of 64B/66B code blocks in the IEEE802.3 specification.
  • 64B/66B encoding encodes 64bit data or control information into 66bit blocks for transmission.
  • the first two bits of the 66bit block represent the synchronization header, and the last 64bit can be called the data payload.
  • the sync header is "01”
  • the 64 bits after the sync header are all data.
  • the sync header is "10”
  • the 64 bits after the sync header include data and/or control information.
  • the first 8 bits in the data load that is, the 8 bits adjacent to the sync header, are the type domain, which can indicate the type of the control code block.
  • the last 56 bits in the data payload that is, the 56 bits after the type field are control information and/or data.
  • D represents data bytes, each data byte is 8 bits; C represents control bytes, each control byte is 7 bits; S represents the beginning of the data packet, and T represents the end of the data packet; O Represents the ordered set control code block (for example, the type is 0x4B, the value of O is different, and the usage scenarios are different). S can only appear in the 0th and 4th bytes of the 8 bytes, and T can appear in any byte.
  • a code block containing S can be called an S code block, and a code block containing T can be called a T code block.
  • Idle (IDLE) code blocks is C 0 ⁇ C 7 0, low power consumption (LPI) block code C 0 ⁇ C 7 to 6.
  • the anchor code block may be a 64B/66B control code block.
  • the control code block may be of type 0x4B, 0x2D, 0x55, 0x00, etc.
  • the response code block can be a 64B/66B control code block.
  • the type can be 0x4B, 0x2D, 0x55, 0x00, etc.
  • the trigger flag sent to each logical channel can be a 64B/66B control code block.
  • the control code block as a trigger flag can be of type 0x4B, 0x2D, 0x55, 0x00, etc.
  • the trigger mark group can also be multiplexed with AM.
  • control code block of type 0x4B The information in the 0x4B control code block can be used to indicate that the code block is an anchor code block, a response code block, or a trigger mark.
  • Figure 7 is a schematic diagram of a control code block of type 0x4B.
  • A, B, C, and D are respectively several bits in the control code block.
  • the type of code block can be indicated by the 2-bit A field. For example, "01" in the A field indicates that the code block is an anchor code block, and "11" in the A field indicates that the code block is a response code block. If the trigger mark is a code block of 66B, the A field being "10" indicates that the code block is a trigger mark.
  • the position of the trigger mark in the code block stream can be identified by the B field, for example, the trigger mark group and the anchor can be identified by B The number of code blocks in the code block interval, or the number of AM groups between the trigger flag group and the anchor code block.
  • the C field can reuse the O0 field.
  • O0 is a reserved field, which can be called a sequence ordered set.
  • the 4 bits of C can be used to identify failures.
  • the C field is "0000" for normal
  • the C field is "0001" for local failure
  • the C field is "0010" for remote failure.
  • the C field can be other values, such as "0100” or "1010", etc., indicating that the code block is a code block used to indicate the physical layer operating mode switch.
  • the prefix "0x” means hexadecimal code.
  • "1010" can be marked as "0xa”.
  • the D field can include 4 bits, which can be used to indicate the switching type.
  • the code block is an anchor code block
  • the 2 bits in the D field can be used to indicate the switching of the transmission rate, and the other 2 bits can indicate the switching of the transmission delay. That is, the D field may be the first switching mode indication information.
  • "0001" in the D field can mean acceleration
  • "0010” means deceleration
  • "0100” means extra time delay
  • "1000” means minus time delay
  • the D field can identify the simultaneous switching of the transmission rate and the transmission delay.
  • the C field can be used to indicate that the code block is a code block used to indicate physical layer operating mode switching.
  • the D field may be used to indicate the switching type, that is, the D field may be the second switching mode indication information.
  • the A field is "10", that is, the trigger flag, and the B field can be used to indicate the logic channel corresponding to the trigger flag group.
  • the first device periodically sends AM in each PCSL or FECL
  • the second device periodically receives AM in each PCSL or FECL.
  • AM will send and receive periodically on each channel, and the AMs of different logical channels carry information identifying the corresponding logical channels. Therefore, the trigger mark group can reuse AM.
  • B in the anchor code block may indicate that after the first device inserts the anchor code block, the AM of the Mth cycle sent is the trigger flag group.
  • B in the anchor code block may indicate that in the serial bit stream, the AM in the M-th period after the anchor code block is the trigger flag group.
  • FIG. 8 is a schematic flowchart of a method for transmitting data over an Ethernet provided in an embodiment of the present application.
  • the 100G Ethernet interface can be electrically interconnected using 10 ⁇ 10Gbps physical channels without FEC. According to IEEE802.3, 100G Ethernet interface corresponds to 20 PCS channels.
  • PCSL is a logical channel.
  • 1-2# logical channel corresponds to 1# physical channel
  • 3-4# logical channel corresponds to 2# physical channel, and the corresponding relationship between other logical channels and physical channels can be deduced by analogy.
  • 1#Logical channel means that the number of the logical channel is 1.
  • the bit stream sent in each PCS channel is in 66B code blocks.
  • the network manager can issue logical channel indication information to instruct the link to bypass the 11-20#PCS channel, that is, the 11-20#PCS channel no longer transmits data and can enter the dormant state, for example
  • These logical channels and the corresponding physical channels can be closed.
  • the logical channel numbers of the 20 PCS channels corresponding to the Ethernet interface are 1 ⁇ 20#, this time it is required to bypass 11 ⁇ 20#, that is, the 11 ⁇ 20# logical channel exits operation, and the corresponding physical channel is 6 ⁇ 10#.
  • Each trigger mark in the trigger mark group may be a control code block as shown in FIG. 7. Refer to Figure 9 for the specific switching process.
  • FIG. 9 is a schematic flowchart of a method for transmitting data over an Ethernet provided in an embodiment of the present application.
  • the logical channel is PCSL.
  • Step S901 The first device inserts the anchor point code block.
  • the MAC layer of the first device receives the data packet.
  • the PCS sublayer of the first device inserts anchor code blocks in the serial bit stream.
  • the code blocks shown in shade in the figure are anchor code blocks.
  • the anchor point code block may be inserted at the position of an integer multiple after the first code block corresponding to AM in the bit stream.
  • the first device detects an AM code block of the PCS channel and maintains an integer multiple of N with the AM.
  • N is the number of working channels in the current mode. For example, if N is 20, the anchor code block is inserted at a position where the distance from the AM code block is 50 ⁇ 20 code block, that is, the 50 ⁇ 20th code block after the AM is the anchor code block.
  • the B field can be set to M in the anchor code block. M is used to indicate the position of the trigger mark group.
  • M may indicate that in the bitstream, the M-th code block after the anchor code block is the first code block of the trigger tag group, for example, the M-th code block after the anchor code block starts as the trigger tag group .
  • the first device starts M counting and counts the number of code blocks sent after the anchor code block is inserted.
  • the anchor code block may contain switching type information.
  • the switching type information is "0x2", which can indicate that the mode switching type is reduced speed.
  • the first device sends the anchor code block to the second device.
  • the anchor code block is distributed to the logical channel.
  • the first device sends the bitstream to the second device.
  • the anchor code block inserted in the serial bit stream is sent to the second device along with the bit stream.
  • step S902 the second device receives the anchor code block.
  • the second device removes the anchor code block from the serial bit stream.
  • the code blocks shown in shade in the figure are anchor code blocks.
  • the second device may send response information to the first device, and the response information may be, for example, a response code block.
  • the second device may send the response code block to the first device through the sending logic channel of the second device.
  • the sending logical channel of the second device is used to send the bit stream to the first device.
  • the first device receives the response code block before counting to M, and then proceeds to step S903.
  • step S903 the first device inserts a trigger mark.
  • the first device counts to M and inserts the trigger mark group.
  • the number of trigger marks in the trigger mark group is 10 or 20, which corresponds to 10 logical channels used for bit stream transmission after switching. Or corresponding to the 20 logical channels used for bit stream transmission before switching.
  • the first device distributes the trigger mark group.
  • the first device has finished distributing the trigger mark group, and each trigger mark has been distributed to the corresponding logical channel.
  • the shaded part in the figure is the trigger mark.
  • the 100G Ethernet interface distributes the serial bit stream to the logical channel according to 66B code blocks, and the number of trigger marks is the number of 66B code blocks occupied by the trigger marks.
  • the first device may agree with the second device that when the transmission rate is switched, whether the inserted trigger mark group is sent through the logical channel before the switching or the logical channel after the switching. That is, the first device and the second device may agree to distribute the trigger mark group through the logical channel 1-10#, or distribute the trigger mark group through the logical channel 1-20#.
  • the distributor of the first device distributes the trigger through the 1 ⁇ 10# logical channels Mark group, 11 ⁇ 20# logic channel exits operation.
  • the distributor can be considered as a device in the first device that distributes the serial bit stream to each logical channel.
  • the distributor will distribute the trigger mark group through the logical channels 1-20#, and then , 11 ⁇ 20# logic channel exits operation.
  • the trigger mark group is the demarcation point for the distributor of the first device to work according to the old and new modes, and is the starting point of the new mode.
  • the distance between the anchor code block and the first AM code block is 50 ⁇ 20
  • the distance between the first code block and the anchor code block corresponding to the trigger flag group is 10240.
  • 10240+1000 is an integer multiple of 20 (452 times).
  • the bit stream sent in each PCS channel has a symbol of 66 bits, so each trigger mark in the trigger mark group will be sent to the desired logical channel.
  • the trigger tag is distributed to the logical channel.
  • the first device sends the bitstream to the second device.
  • the trigger mark is sent to the second device.
  • step S904 when the count of the second device is about to reach M, a trigger flag is received.
  • the second device detects the trigger mark corresponding to each channel on the corresponding 1 ⁇ 10# logic channel, or, see Figure 10d, the second device is in 1 ⁇ 10#
  • the logic channel locks and reorders to form a serial stream and then detects the trigger mark group.
  • the symbol corresponding to the trigger mark in the logic channel and the code block corresponding to the trigger mark in the serial bit stream are indicated by shading.
  • the second device removes the trigger mark and completes the extraction of the trigger mark.
  • the second device detects the trigger mark corresponding to each channel on the 1 ⁇ 20# logic channel, or after the logic channel is locked and reordered to form a serial stream Trigger the mark group. After that, the receiver of the second device no longer receives any symbols from the 11-20# logical channels.
  • the receiver can be considered as a device in the second device that receives and sorts the bit code blocks or symbols of each logical channel.
  • the second device After the second device receives the trigger mark from the logical channel, there is no useful information on the 11-20# logical channel, but it may be a pseudo-random binary sequence (PRBS) or other interference inserted by the first device .
  • PRBS pseudo-random binary sequence
  • the second device switches to the new working mode. In other words, after receiving the trigger mark, the second device only receives symbols from the logical channels 1# ⁇ 10#.
  • the trigger mark is the demarcation point where the receiver of the second device works according to the old and new modes, and is the starting point of the new mode.
  • the second device may receive PCS sublayer trigger flag.
  • the logical channel has been locked, and the PCS sublayer of the second device can detect and remove the trigger flag group in the serial bit stream.
  • the PCS sublayer of the second device may receive and detect the trigger mark corresponding to the logical channel in multiple logical channels.
  • the detection of the trigger mark can be understood as the recognition of the trigger mark.
  • the serial bit stream includes the trigger mark, and the trigger mark is removed.
  • the first device sends the anchor code block to notify the second device that after the 10240 code block, the 11-20# logical channel immediately exits the data transmission between the first device and the second device.
  • the first device counts to 10240, the first device inserts the trigger mark group corresponding to 1-10# logic channel, and stops sending data on 11-20# logic channel.
  • the trigger mark in the trigger mark group is used to guide the second device to complete the speed reduction switch.
  • the first device and the second device can be switched synchronously based on the code block of the PCS sublayer, switching from the high-speed mode to the low-speed mode, the second device has no code blocks or bit errors, and no buffering or packet reordering is required Module, simple and efficient.
  • the first device sends the anchor code block and the trigger mark, and the second device receives the anchor code block and the trigger mark to complete the physical layer switching.
  • Table 1 is the AM specification of 100G Ethernet PCSL in IEEE802.3.
  • the 100G Ethernet interface includes 20 PCSLs.
  • bit interleaved parity (BIP) bytes are used for error checking, and M bytes (M 1 -M 6 ) are used to identify logical channels and logical channel alignment.
  • BIP bit interleaved parity
  • Table 2 is the AM specification of 100G Ethernet FECL in IEEE802.3.
  • the 100G Ethernet interface includes 4 FECLs.
  • amp_tx_i represents the AM corresponding to the PCSL numbered i.
  • one FECL corresponds to multiple PCSLs.
  • the symbols transmitted through the multiple PCSLs are transmitted through the FECL.
  • the numbers of the multiple PCSLs corresponding to the FECL numbered 1 are 0, 4, 8, 12, and 16, respectively.
  • PCSL and FECL have a corresponding relationship, that is, each FECL corresponds to multiple PCSLs.
  • Logical channel exit or start operation refers to FECL and multiple PCSL corresponding to the FECL exit or start operation.
  • 100G Ethernet interface 0#, 4#, 8#, 16#PCSL corresponds to 0#FECL.
  • 0#, 4#, 8#, 16# PCSL AM corresponds to 0#FECL AM.
  • 0#, 4#, 8#, 16#PCSL corresponds to 0#FECL.
  • the trigger flags of 0#, 4#, 8#, 16#PCSL correspond to the trigger flags of 0#FECL.
  • FIG. 11 is a schematic flowchart of a method for transmitting data over an Ethernet provided by an embodiment of the present application.
  • the logical channel is PCSL.
  • the 400G Ethernet interface specifies 16 PCSL/FECL logical channels, which are electrically interconnected by 8 ⁇ 50Gbps physical channels. Each physical channel corresponds to 2 logical channels.
  • the FEC scheme uses RS (544,514).
  • the network manager issues an instruction to request the link to bypass the 9-16# logical channel.
  • 1-2# logical channels correspond to 1# physical channels
  • 3-4# logical channels correspond to 2# physical channels
  • the corresponding relationships between other logical channels and physical channels can be deduced by analogy .
  • the logical channel number is 1 ⁇ 16#, this time it is required to bypass 9 ⁇ 16#, that is, the 9 ⁇ 16# logical channel exits operation, and the corresponding physical channel is 5 ⁇ 8#.
  • the AM group can be reused as the trigger mark group.
  • step S1001 the first device inserts the anchor code block.
  • the first device sends a bit stream through 16 logical channels.
  • the AM group corresponding to 16 logical channels is inserted.
  • the second device inserts 8 257B code blocks corresponding to 16 AMs, that is, the second device inserts an AM group with a size of 8 257B code blocks, and the AM group includes 16 AMs.
  • the AM group is shown in the shaded part of the serial bit stream in Figure 12a. Each AM in the AM group can be sent to a corresponding logical channel.
  • the shaded parts of the PCS/FEC channels in Figure 12a indicate the symbols corresponding to the AM sent to the 16 logical channels.
  • the first device sends the anchor code block.
  • the first device inserts the anchor code block into the serial bit stream of the PCS layer.
  • the anchor code block guides the first device and the second device to switch the physical layer working mode, which is compatible with the existing bit stream transmission mode in Ethernet, and does not need to increase the hardware structure for switching, which can reduce the impact on the system .
  • the first device can insert an anchor code block into the 66B code block stream, and the anchor code block is a 66B code block.
  • the first device may insert an anchor code block into the 257B code block stream, and the anchor code block is a 257B code block. Inserting a smaller 66B anchor code block, transmission of the anchor code block occupies less resources, which can reduce system overhead.
  • the handover type is reduced speed, and the handover type information carried by the anchor code block may be "0x2".
  • the D field of the anchor code block may be "0x2".
  • the A field of the anchor code block can be "01”
  • the C field can be "0x6”
  • the anchor code block can be set without B, that is, the number of code blocks between the trigger flag group and the anchor code block is not set
  • Identification that is, the position of the trigger mark group in the bit stream is not identified. At this time, the position of the trigger flag group in the bit stream can be configured by the network manager.
  • the AM group inserted 10 times is included between the trigger mark group and the anchor code block, that is, the 11th AM inserted after the anchor code block is sent is the trigger mark group.
  • the anchor code block is distributed to multiple logical channels.
  • step S1002 the second device receives the anchor code block.
  • the second device monitors the bit stream, receives and removes the anchor code block.
  • the second device may receive and detect the anchor code block from the logical channel, or may detect the anchor code block after the bit stream received after the channel is locked and reordered forms a serial bit stream. After detecting the anchor code block, the second device may remove the anchor code block.
  • the second device After detecting the anchor code block, the second device starts counting. According to the count of the second device, the second device can determine the position of the trigger mark sent by the first device.
  • the second device may send a response code block to the first device.
  • the second device may send the response code block to the first device through the sending logic channel of the second device.
  • the sending logical channel of the second device is used to send the bit stream to the first device.
  • the first device does not receive the response code block before the 11th AM insertion, and cancels the switching of the physical layer working mode, that is, steps S1003-S1004 are not performed.
  • the first device receives the response code block before the 11th AM insertion, and then proceeds to step S1003.
  • step S1003 the first device inserts a trigger mark.
  • the trigger mark can be AM.
  • the first device counts to the 10th AM insertion, that is, 10 AM has been sent since the anchor point code block is sent, and is ready for the 11th AM insertion.
  • the first device when the AM insertion period is reached, the first device immediately inserts 8 AMs corresponding to logical channels 1 to 8 # according to the new mode.
  • 8 AMs correspond to 4 257B code blocks.
  • the inserted AM is distributed.
  • Distribute AM according to the new mode that is, the switched mode.
  • each AM of the PCS/FEC channel is distributed to the corresponding logical channel 1-8#. Starting from the 11th AM distribution, the distributor no longer sends bit streams through the 9-16# logical channels.
  • the sending of the trigger mark group is the demarcation point for the distributor of the first device to work in the old and new modes, and is also the starting point of the new mode.
  • step S1004 the second device receives the trigger flag.
  • the second device counts to the 10th AM receiving cycle, that is, it has received 10 AMs since receiving the anchor code block, and prepares for the 11th AM reception.
  • the receiver of the second device receives the 11th round of AM from logical channels 1-8#. Since receiving the 11th AM, that is, when the trigger mark is received, the receiver only receives code blocks from logical channels 1 to 8 #, and no longer receives code blocks from 9 to 16 #, and switches to a new working mode.
  • the reception of the trigger mark group is the demarcation point for the receiver of the second device to work according to the old and new modes, and is the starting point of the new working mode.
  • the second device can remove the trigger mark.
  • the network manager configures the relative position of the trigger tag group and the anchor code block in the bit stream, and the logical channel exits operation by sending and receiving the anchor code block and the trigger tag group at the corresponding position. Guided by the anchor code block and the trigger mark group, the speed reduction switch is completed to avoid bit errors.
  • the sending of the trigger tag group can also be through the same logical channel as the anchor code block. In other words, immediately after the trigger flag group is sent, the switch to reduce the number of channels is performed.
  • step S1003 when the first device counts the AM insertion period, the first device still inserts 16 AMs corresponding to logical channels 1-16# according to the previous mode.
  • the distributor distributes the 16 AMs to the corresponding logical channels 1-16#. After the distributor completes the 11th AM distribution of logical channels 9-16#, it will no longer send bit streams through logical channels 9-16#, and logical channels 9-16# exit operation.
  • step S1004 when the second device counts the 11th AM receiving cycle, the second device still receives 16 AMs in the previous mode, that is, the 16 AMs corresponding to logical channels 1 to 16 #, the 16 AMs AM is used as the trigger mark group. After the receiver receives the trigger mark group, it will no longer receive bit streams from the 9-16# logic channel, and the 9-16# logic channel will exit operation.
  • the position of the trigger mark in the bit stream is determined.
  • the trigger mark guides the exit of part of the logic channels of the first device and the second device, which can realize slow switching and avoid bit errors.
  • the switching of the working modes of the first device and the second device is completed, and the switching from the high-speed mode to the low-speed mode is completed.
  • the second device performs corresponding processing on the first device, and there is no code block or bit error. There is no need to set up a cache or packet reordering module, and the impact on the system is small.
  • Trigger markers are multiplexed with AM, which reduces the number of bits occupied by sending trigger marker groups, achieving a lower cost, simplicity and efficiency.
  • the trigger mark sent to each logic channel can be an AM sent through the logic channel at a certain time.
  • the AM sent in each PCSL uniquely identifies the PCSL, that is, each AM uniquely identifies the corresponding PCSL, and is sent through the corresponding PCSL.
  • Table 3 is the AM specification of 400G Ethernet in IEEE802.3. Among them, CM 0 , CM 1 , CM 2 , CM 3 , CM 4 , and CM 5 are common identifiers of logical channels, and UM 0 , UM 1 , UM 2 , UM 3 , UM 4 , and UM 5 uniquely identify a logical channel.
  • FIG. 13 is a schematic flowchart of an Ethernet data transmission method provided by an embodiment of the present application.
  • the logical channel is PCSL.
  • the 400G Ethernet interface uses 8 ⁇ 50Gbps physical channels for electrical interconnection. Each physical channel corresponds to 2 logical channels, that is, a total of 16 logical channels are used.
  • the FEC scheme uses the RS (544,514) method.
  • the network management issues instructions to switch to logic channel 1 ⁇ 8# to run from logic channel 1 ⁇ 8#, that is, logic channel 9 ⁇ 16# that exited operation will resume operation.
  • 1-2# logical channels correspond to 1# physical channels
  • 3-4# logical channels correspond to 2# physical channels, and the corresponding relationships between other logical channels and physical channels can be deduced by analogy .
  • step S1101 the first device inserts the anchor code block.
  • the first device sends a bit stream through 8 logical channels.
  • 8 AM corresponding to the 8 channels are inserted.
  • Each of the 8 AMs can be sent to a corresponding logical channel.
  • the first device sends the anchor code block.
  • the first device inserts the anchor code block into the serial bit stream of the PCS layer. That is, the first device carries the information in the anchor code block in the bit stream sent.
  • the anchor code block can be set to B bytes.
  • Each AM inserted in the 9th round after the block serves as a trigger mark.
  • the handover type is accelerated, the anchor code block can be set to D, and the handover type information carried by the anchor code block can be "0x1", that is, the handover is accelerated.
  • step S1102 the second device receives the anchor code block.
  • the second device monitors the bit stream and detects the anchor code block in the received bit stream.
  • the second device can lock and reorder each logical channel, and then detect the anchor code block after the received symbols form a serial bit stream.
  • the second device After detecting the anchor code block, the second device starts counting. According to the statistics of the second device, the second device can determine the position of the trigger mark group sent by the first device.
  • the second device may remove the anchor code block.
  • step S1103 the first device inserts a trigger mark.
  • the first device counts to M and waits for the next cycle of inserting the AM group, that is, 8 rounds of AM have been sent since the anchor point code block is sent, and it is ready for the 9th round of AM insertion.
  • the first device when the 9th round of AM group insertion cycle is reached, the first device immediately inserts 16 AM groups corresponding to AM according to the new mode, 16 is the number of logical channels working in the new mode, that is, the AM group corresponds 1 ⁇ 16#Logical channel.
  • 16 AMs are distributed.
  • the second device uses the new mode to distribute symbols, and distributes the bit stream to 16 logical channels.
  • each AM is distributed to the corresponding logical channel 1-16#.
  • the distributor performs the 9th round of AM distribution, the 9-16# logical channel resumes operation, and the bit stream is sent through the 1-16# logical channel.
  • the sending of the trigger mark group is the demarcation point for the first device distributor to work in the old and new modes, that is, the starting point of the new mode.
  • step S1104 the second device receives the trigger flag.
  • the second device counts to M and waits for the next cycle of AM reception, that is, it has received 8 rounds of AM since receiving the anchor code block, and is ready for the 9th round of AM reception.
  • 16 AMs are respectively transmitted through 16 logical channels.
  • the receiver monitors and receives the 9th round of AM from the 1-16# logic channels. Since receiving the 9th AM, that is, when the trigger flag group is received, the receiver receives the bit stream from the logic channel 1 to 16 # and switches to the new working mode.
  • the reception of the trigger mark group is the demarcation point for the receiver of the second device to work in the old and new modes, that is, the starting point of the new mode.
  • the anchor code block By sending the anchor code block on the first device of the 400G link, it is agreed with the second device that after 8 rounds of AM codewords are sent, when the 9th round of AM is sent, the 9 ⁇ 16# logical channels will resume operation and pass 1 ⁇ 16 #Logical channel sends bit stream.
  • the 16 AMs inserted in the 9th round guide the first device and the second device to complete the accelerated switching.
  • the second device can remove the trigger mark.
  • the position of the trigger flag group in the bit stream can be determined.
  • the second device By triggering the transmission of the flag group, for the same symbol in the bit stream, the second device performs the corresponding processing on the first device, and there is no code block or bit error.
  • Switching from low-speed mode to high-speed mode and other physical layer working modes does not need to set up a buffer or packet reordering module, which has little impact on the system.
  • the trigger mark corresponding to each logical channel in the trigger mark group can be multiplexed with the AM corresponding to the logical channel, reducing the number of bits occupied by the sending trigger mark group, and realizing the switching of the working mode occupies less system resources, which is simple and efficient. There is no need to set up a cache or packet reordering module, and the impact on the system is small.
  • FIG. 15 is a schematic flowchart of an Ethernet data transmission method provided by an embodiment of the present application.
  • the first device Before switching, the first device sends the first bit stream to the second device.
  • the first bit stream is obtained through the first FEC encoding method. Then the second device receives the first bit stream and performs the first FEC decoding on the first bit stream.
  • the first bit stream is not FEC encoded. Then the second device receives the first bit stream and does not need to perform FEC decoding on the first bit stream.
  • the second device After the handover, the second device sends the second bitstream to the second device.
  • the second bit stream is obtained through the second FEC encoding method. Then the second device receives the second bit stream and performs the first FEC decoding on the second bit stream.
  • the second bit stream is not FEC encoded. Then the second device receives the second bit stream and does not need to perform FEC decoding on the second bit stream.
  • At least one of them is FEC encoded.
  • the logical channel is FECL.
  • the first device performs first FEC encoding to obtain a bit stream. After the handover, the first device does not perform FEC encoding.
  • the first FEC encoding method may be RS (544,514), for example.
  • the FEC encoding mode is switched from RS (544,514) to no FEC encoding.
  • the first device performs the first FEC encoding and sends the bit stream through 4 FECLs.
  • the first device is inserted into the AM group for FECL alignment.
  • Each AM in the AM group can be sent to a corresponding FECL.
  • the corresponding trigger mark can be AM.
  • step S1301 the first device inserts the anchor code block.
  • the first device inserts anchor code blocks into the serial bit stream before performing FEC encoding on the bit stream.
  • the anchor code block is the code block shaded in Figure 16a.
  • the first device inserts the anchor code block in the bit stream.
  • the anchor code block can be set to B bytes.
  • the multiple AMs inserted in the 9th round are the trigger mark groups.
  • the handover type is accelerated, the anchor code block can be set to D, and the handover type information carried by the anchor code block can be "0x8", that is, to reduce the delay handover.
  • step S1302 the second device receives the anchor code block.
  • the second device receives the bit stream and performs the first FEC decoding on the bit stream.
  • the first FEC decoding is a decoding method corresponding to the first FEC encoding.
  • the second device monitors the bit stream and detects anchor code blocks.
  • the second device can detect the anchor code block in the serial bit stream after reordering the multi-channel locking and reordering, and the received bit stream forms a serial bit stream, and can also obtain the anchor code block in the FECL.
  • the second device After receiving the anchor code block, or after detecting the anchor code block, the second device starts counting. According to the statistics of the second device, the second device can determine the position of the trigger flag group sent by the first device.
  • the second device can remove the anchor code block.
  • step S1303 the first device inserts a trigger mark.
  • the first device counts to M and waits for the next cycle of inserting the AM group, that is, the AM group has been sent 8 times since the anchor code block is sent, and it is ready to insert the AM in the 9th round.
  • the multiple AMs inserted in the 9th round are the trigger mark groups.
  • the trigger mark corresponds to the code block shaded in Figure 16b.
  • the first device When the period of trigger mark group insertion is reached, the first device inserts the trigger mark group. Starting from the trigger flag group in the bitstream, the first device no longer performs the first FEC encoding. In other words, for the AM group inserted this time and subsequent bit streams, the first FEC encoding is not performed. That is, after the 66B code block corresponding to the AM group is transcoded into a 257B code block, the corresponding first symbol is directly distributed to the 4 FEC channels.
  • the sending of the trigger mark group is the demarcation point for the first device distributor to work in the old and new modes, that is, the starting point of the new mode.
  • the bit stream sent before the trigger mark may be called the first bit stream, and the bit stream sent after the trigger mark may be called the second bit stream.
  • step S1304 the second device receives the trigger flag.
  • the second device counts to M and waits for AM group reception in the next cycle, that is, it has received 8 rounds of AM groups since receiving the anchor code block, and is ready for the 9th round of AM reception.
  • the multiple AMs inserted in the 9th round are the trigger mark groups.
  • the trigger mark corresponds to the code block shaded in Figure 16b.
  • the transcoding After receiving the 9th round of AM, switch to a new working mode. That is to say, for the symbols corresponding to this round of AM and the symbols received later, after forming a 257B code block, the transcoding is sent to a 66B code block. That is, the first FEC decoding is no longer performed.
  • the reception of the trigger mark group is the demarcation point for the receiver of the second device to work in the old and new modes, that is, the starting point of the new mode.
  • the anchor code block By sending the anchor code block to the first device on the 100G link, it is agreed with the second device that after 8 rounds of AM codewords are sent, when the 9th round of AM is sent, a switch to reduce the delay is performed.
  • the first device When the first device is inserted into the 9th round of AM, the inserted AM guides the first device and the second device to complete the switch to reduce the delay.
  • the second device can remove the trigger mark.
  • the position of the trigger flag group in the bit stream can be determined.
  • the second device By triggering the transmission of the flag group, for the same symbol in the bit stream, the second device performs corresponding processing on the first device, and there is no code block or bit error.
  • Switching from high-latency mode to low-latency mode and other physical layer working modes does not need to set up a buffer or packet reordering module, which has little impact on the system.
  • the trigger mark multiplexes AM which reduces the number of bits occupied by sending the trigger mark group, and realizes the switching and spreading of working modes with few system resources, which is simple and efficient. There is no need to set up a cache or packet reordering module, and the impact on the system is small.
  • the transmission delay switching that is, before and after the physical layer working mode switching, the transmission delay caused by different FEC codec or no FEC codec is different. It can also be understood that the error correction ability is different before and after the switch, that is, the error correction capability is different. Wrong ability to switch.
  • the switching of working modes with different delays can be completed after the flag group is triggered. That is, for the first device, the trigger flag group is still encoded using the first FEC encoding method. After the first FEC encoding is performed on the first trigger marker group, the first FEC encoding is not performed on the bit stream after the trigger marker group. Correspondingly, after receiving and detecting the trigger flag group, the second device performs the first FEC decoding on the trigger flag group. For the bit stream after the trigger flag group, no FEC decoding is performed.
  • the working modes of the first device and the second device can also be switched from low delay to high delay.
  • the first device does not perform FEC encoding.
  • the first device sends the trigger flag group, and performs the first FEC encoding on the trigger flag group and the subsequent bit stream.
  • the second device detects the trigger flag corresponding to the trigger flag group, and performs the first FEC decoding on the trigger flag group and the subsequent bit stream.
  • Fig. 17 is a schematic flowchart of a method for Ethernet data transmission, mainly describing related processing procedures of the physical layer.
  • the 257B code block stream is distributed to multiple channels according to 10-bit symbols for FEC encoding and symbol distribution.
  • a channel that independently performs FEC encoding (one or more encoders) and symbol distribution can also be called a logical channel.
  • each logical channel After the first device distributes the code block stream to multiple logical channels, each logical channel independently performs FEC encoding on the bit stream, and performs independent distribution and interleaving. Each logical channel can correspond to multiple FEC encoding and decoding, and the multiple FEC encoding and decoding methods are the same. For the first device, each logical channel independently distributes symbols after multiple FEC encoding. For the second device, each logical channel independently receives symbols and then performs multi-channel FEC decoding.
  • Each channel that independently performs FEC encoding and decoding, symbol distribution, and reception can be understood as a logical channel. That is, the first device distributes the code block stream to multiple logical channels.
  • the FEC mode of each logical channel can be the same or different.
  • each logical channel that is, each channel for independently performing FEC encoding and symbol distribution, corresponds to multiple PCSLs. That is, the symbols in each FEC-encoded channel are distributed to multiple PCSLs corresponding to the channel.
  • the symbols on the PCSL are sent to the second device through the PMA sublayer and the PMD sublayer.
  • the second device serves as the receiving end to receive the symbols sent by the first device through PMD and PMA.
  • Each logical channel independently performs FEC encoding and symbol reception.
  • the receiving end uses the AM on multiple PCSLs corresponding to the channel to lock the channel to eliminate jitter. Locking and eliminating jitter can be implemented based on AM on all PCSLs corresponding to all logic channels. It should be understood that all PCSLs may be aligned, or all PCSLs corresponding to one or more logical channels may be aligned. Perform reordering and FEC decoding on multiple PCSL channels corresponding to the channel. After FEC decoding, the PCS sublayer of the second device de-interleaves the symbols on the multiple logical channels (re-order each logical channel as needed before interleaving) to form a serial code block stream, and perform subsequent processing procedures .
  • each logical channel adopts 1 FEC codec of IEEE802.3 specification 100G
  • each logical channel corresponds to a 100G FEC independent codec and distribution symbol path
  • the 200G interface includes 2 Such a logical channel.
  • the 400G Ethernet interface includes two such logical channels.
  • other processing procedures can be added in the application, or some of the above-mentioned processing procedures can be reduced.
  • FIG. 18 is a schematic flowchart of a method for transmitting data over an Ethernet provided by an embodiment of the present application.
  • the Ethernet interface corresponds to 4 channels for FEC encoding and symbol distribution independently. After the symbols in each channel for FEC encoding are distributed to multiple PCSL/FECLs, they are distributed to one or more physical channels through PMA. That is, one channel for FEC encoding and symbol distribution corresponds to one or more physical channels.
  • the first device and the second device can only increase or decrease the number of PCSL/FECL running.
  • the first device and the second device can also increase or decrease the running channels that independently perform FEC encoding and symbol distribution, further reducing system power consumption.
  • Logical channels are used to represent channels for independent FEC encoding and distribution. 1# logical channel corresponds to and 1-2# physical channel, 2# logical channel corresponds to 3-4# physical channel, and the corresponding relationship between other logical channels and physical channels can be deduced by analogy.
  • the PCSL/FECL corresponding to each logical channel can be numbered separately.
  • 1-4#PCSL/FECL corresponding to 1# logical channel corresponds to 1-2# physical channel; 2# logical channel 1-4#PCSL/FECL corresponds to 3-4# physical channel.
  • the PCSL/FECL corresponding to the logical channel that transmits the 257B serial code block stream can also be encoded simultaneously.
  • the distributor in the first device is used to perform the FEC symbol distribution in FIG. 17.
  • the receiver in the second device is used to perform the de-interleaving in FIG. 17.
  • the network manager can issue logical channel indication information to instruct some logical channels to exit operation. For example, the network manager instructs 3-4# logical channel to exit operation.
  • FIG. 19 is a schematic flowchart of a method for transmitting data over an Ethernet according to an embodiment of the present application.
  • the logical channel refers to a channel that independently performs FEC encoding and symbol distribution.
  • step S1801 the first device inserts the anchor code block.
  • the first device sends the bit stream through the two logical channels 1# and 2#.
  • PCSL/FECL unified coding The symbols in the 2 logic channels are distributed to 16 PCSLs.
  • the AM group corresponding to 16 PCSLs is inserted.
  • Each AM in the AM group can be sent to a corresponding PCSL through its corresponding logical channel.
  • step S1802 the second device receives the anchor code block.
  • the second device may also start counting after detecting or removing the anchor code block. According to the count of the second device, the second device can determine the position of the trigger mark group sent by the first device.
  • the first device inserts a trigger mark.
  • the trigger mark can correspond to 1# logic channel. Taking the trigger mark can be multiplexed AM as an example, the trigger mark of 1# logical channel corresponds to the AM of 1-8#PCSL, and the trigger mark of the 2# logical channel corresponds to the AM of 9-16#PCSL.
  • the first device when the AM insertion period is reached, the first device immediately inserts 8 AMs corresponding to 1 ⁇ 8#PCSL according to the new mode.
  • the inserted AM is distributed.
  • AM distributed to 1# logical channel.
  • each AM is distributed to the corresponding 1-8#PCSL.
  • step S1803 the first device no longer sends the bit stream through 2# logical channel and 9-16#PCSL.
  • step S1804 the second device receives the trigger flag.
  • the second device counts to the AM reception period as the trigger mark, and receives the trigger mark through 1 to 8#PCSL and the corresponding 1# logical channel.
  • the second device can remove the trigger mark.
  • the second device receives the bit stream through 1 ⁇ 8#PCSL and the corresponding 1# logical channel, and no longer sends the bit stream through 2# logical channel and 9 ⁇ 16#PCSL.
  • FIG. 21 is a schematic flowchart of a communication method provided by an embodiment of the present application.
  • the anchor information can be an anchor packet.
  • step S2101 the first device inserts the anchor packet.
  • the MAC layer of the first device receives the data packet.
  • the MAC layer of the first device inserts the anchor packet in the serial bit stream.
  • the format of the anchor packet can be seen in the description of Figure 22.
  • the anchor packet can be used to indicate the position of the trigger tag group in the bitstream.
  • the anchor packet may include switching mode indication information.
  • the switching mode indication information is used to indicate the switching mode of the working mode.
  • the switching mode of the working mode includes the switching of the transmission rate and/or the switching of the transmission delay.
  • step S2102 the first device sends an anchor packet to the second device.
  • the anchor packet is distributed to the logical channel.
  • the first device sends the bitstream to the second device.
  • the bitstream includes anchor packets.
  • the anchor packet is used to indicate the position of the trigger tag group in the bit stream.
  • step S2103 the first device inserts the trigger mark group into the bit stream according to the position of the trigger mark group indicated by the anchor packet.
  • step S2104 the first device sends a trigger flag group. It should be understood that the trigger flag group is sent after the anchor packet.
  • the first device switches the working mode when it starts sending the trigger mark group or when it finishes sending the trigger mark group.
  • the second device receives the bitstream.
  • the bit stream includes anchor packets and trigger tag groups.
  • the MAC of the second device switches the working mode according to the position of the trigger flag group indicated by the anchor packet in the bit stream when it starts to receive the trigger flag group or when the reception of the trigger flag group is completed.
  • the switching time of the working mode of the second device corresponds to the switching time of the working mode of the first device.
  • the second device may remove the anchor packet from the bit stream.
  • the second device may remove the trigger mark group from the bit stream.
  • step S2101 to step S2104 it is possible to complete the synchronous switching of the working mode of the first device and the second device based on the anchor packet of the MAC layer, without setting a buffer or packet reordering module, which is simple and efficient.
  • the anchor packet may include one or more of switching mode indication information, anchor packet identifier, and trigger indication information.
  • the switching mode indication information is used to indicate the switching mode.
  • the switching mode includes the switching of the transmission rate and/or the switching of the transmission delay.
  • the anchor package identifier is used to indicate that the package is an anchor package.
  • the trigger indication information is used to indicate the position of the trigger mark group in the bit stream.
  • the trigger mark group can be an AM group or other mark groups.
  • FIG. 22 is a schematic diagram of an anchor point package provided by an embodiment of the present application.
  • the anchor packet can include a 7-byte preamble, a 1-byte start frame delimiter (SFD), an 8-byte message field (MSG_filed), and 52-byte padding. Field (padding), 4-byte frame check sequence (FCS), etc.
  • the value of the preamble can be 0x55.
  • SFD can be used as an anchor packet identifier to indicate that the packet is an anchor packet.
  • the value of SFD can be 0xD4.
  • the message field may include switching mode indication information. For example, 0x0000000000000001 can indicate acceleration, and 0x0000000000000002 can indicate deceleration.
  • FIG. 23 is a schematic structural diagram of a communication device provided by an embodiment of itself.
  • the communication device 1400 is used for transmission of Ethernet data.
  • the communication device 1400 includes a generating module 1410 and a transceiver module 1420.
  • the transceiver module 1420 is configured to send a first bit stream to a second device, where the first bit stream is sent through N logical channels of the physical layer of the communication device.
  • the generating module 1410 is used to generate the first trigger mark group.
  • the transceiver module 1420 is further configured to send a first trigger flag group to the second device, where the first trigger flag group is used to indicate the end of sending the first bit stream.
  • the transceiver module 1420 is further configured to send a second bit stream to the second device, where the second bit stream is the P logic through the physical layer of the communication device For the channel sent, N and P are both positive integers.
  • the first trigger mark group includes P trigger marks
  • the transceiver module 1420 is configured to send the i-th trigger flag among the P trigger flags through the i-th logical channel among the P logical channels, where i is a positive integer.
  • the i-th trigger flag includes information for identifying the i-th logical channel.
  • the first bit stream is obtained by encoding using a first forward error correction FEC encoding method
  • the second bit stream is obtained by encoding using a second FEC encoding method
  • the second FEC encoding method is the same as the The error correction capability of the first FEC encoding method is different.
  • one of the first bit stream and the second bit stream is obtained through forward error correction FEC encoding.
  • the first bit stream includes an anchor point code block, and the anchor point code block is used to indicate a time when the first bit stream ends sending.
  • the first trigger mark group is an alignment mark AM group.
  • the transceiver module 1420 is further configured to receive a response code block corresponding to the anchor point code block sent by the second device; according to the response code block, the transceiver module 1420 is configured to send to the second device The first trigger mark group.
  • FIG. 24 is a schematic structural diagram of a communication device provided by the embodiment itself.
  • the communication device 1500 is used for transmission of Ethernet data.
  • the communication device 1500 includes a transceiver module 1510 and a processing module 1520.
  • the transceiver module 1510 is configured to receive a first bit stream sent by a first device, where the first bit stream is received through N logical channels of the physical layer of the communication device.
  • the transceiver module 1510 is further configured to receive a first trigger flag group sent by the first device, where the first trigger flag group is used to indicate the end of the first bit stream.
  • the transceiver module 1510 is further configured to receive a second bit stream sent by the first device, where the second bit stream passes through P of the physical layer of the communication device. N and P are all positive integers received by the logical channel.
  • the processing module 1520 is configured to process the first bit stream and the second bit stream.
  • the first trigger mark group includes P trigger marks.
  • the transceiver module 1510 is configured to receive the i-th trigger flag of the P trigger flags through the i-th logical channel of the P logical channels, where i is a positive integer.
  • the i-th trigger flag includes information for identifying the i-th logical channel.
  • the first bit stream is obtained by encoding using a first forward error correction FEC encoding method
  • the second bit stream is obtained by encoding using a second FEC encoding method
  • the second FEC encoding method is the same as the The error correction capability of the first FEC encoding method is different.
  • the processing module 1520 is configured to: decode the first bitstream through a first FEC decoding mode corresponding to the first FEC encoding mode; and perform a second FEC decoding mode corresponding to the second FEC encoding mode to decode the first bitstream.
  • the second bit stream is decoded.
  • one of the first bit stream and the second bit stream is obtained through forward error correction FEC encoding.
  • the processing module 1520 is configured to perform FEC decoding on the bit stream obtained by FEC encoding.
  • the first bit stream includes an anchor point code block, and the anchor point code block is used to indicate the time when the first bit stream ends.
  • the first trigger mark group is an alignment mark AM group.
  • the transceiver module 1510 is further configured to send a response code block corresponding to the anchor code block to the first device, where the anchor code block is used to indicate the sending of the first trigger flag group.
  • FIG. 25 is a schematic structural diagram of a communication device provided by an embodiment of the present application.
  • the communication device 1600 includes a communication interface 1610.
  • the communication interface 1610 is configured to send a first bit stream to a second device, where the first bit stream is sent through N logical channels of the physical layer of the communication interface 1610;
  • the communication interface 1610 is further configured to send a first trigger flag group to the second device, where the first trigger flag group is used to indicate the end of sending the first bit stream;
  • the communication interface 1610 is further configured to send a second bit stream to the second device, where the second bit stream is P logical channels through the physical layer of the communication interface 1610 When sent, N and P are both positive integers.
  • the communication device 1600 includes a processor for generating the first trigger flag group.
  • the first trigger mark group includes P trigger marks
  • the communication interface 1610 is configured to send the i-th trigger flag among the P trigger flags through the i-th logical channel among the P logical channels, where i is a positive integer.
  • the i-th trigger flag includes information for identifying the i-th logical channel.
  • the first bit stream is obtained by encoding using a first forward error correction FEC encoding method
  • the second bit stream is obtained by encoding using a second FEC encoding method
  • the second FEC encoding method is the same as the The error correction capability of the first FEC encoding method is different.
  • one of the first bit stream and the second bit stream is obtained through forward error correction FEC encoding.
  • the first bit stream includes an anchor point code block, and the anchor point code block is used to indicate a time when the first bit stream ends sending.
  • the first trigger mark group is an alignment mark AM group.
  • the communication interface 1610 is further configured to receive a response code block corresponding to the anchor code block sent by the second device; according to the response code block, the communication interface 1610 is configured to send to the second device The first trigger mark group.
  • FIG. 26 is a schematic structural diagram of a communication device provided by an embodiment of the present application.
  • the communication device 1700 includes a communication interface 1710.
  • the communication interface 1710 is configured to receive a first bit stream sent by a first device, where the first bit stream is received through N logical channels of the physical layer of the communication interface 1710.
  • the communication interface 1710 is further configured to receive a first trigger flag group sent by the first device, where the first trigger flag group is used to indicate the end of the first bit stream.
  • the communication interface 1710 is further configured to receive a second bit stream sent by the first device, where the second bit stream is the P logic through the physical layer of the communication interface 1710 N and P are all positive integers received by the channel.
  • the communication device 1700 includes a processor configured to process the first bit stream and the second bit stream.
  • the first trigger mark group includes P trigger marks.
  • the communication interface 1710 is configured to receive the i-th trigger flag of the P trigger flags through the i-th logical channel of the P logical channels, where i is a positive integer.
  • the i-th trigger flag includes information for identifying the i-th logical channel.
  • the first bit stream is obtained by encoding using a first forward error correction FEC encoding method
  • the second bit stream is obtained by encoding using a second FEC encoding method
  • the second FEC encoding method is the same as the The error correction capability of the first FEC encoding method is different.
  • the communication device 1700 also includes a processor, configured to: decode the first bit stream in a first FEC decoding manner corresponding to the first FEC encoding manner; and decode the first bit stream in a second FEC encoding manner corresponding to the second FEC encoding manner
  • the FEC decoding mode decodes the second bit stream.
  • one of the first bit stream and the second bit stream is obtained through forward error correction FEC encoding.
  • the communication device 1700 also includes a processor, which is configured to perform FEC decoding on the bit stream obtained through forward error correction FEC encoding.
  • the first bit stream includes an anchor point code block, and the anchor point code block is used to indicate the time when the first bit stream ends.
  • the first trigger mark group is an alignment mark AM group.
  • the communication interface 1710 is further configured to send a response code block corresponding to the anchor code block to the first device, where the anchor code block is used to indicate the sending of the first trigger flag group.
  • An embodiment of the present application also provides a communication system, which includes one or more of the aforementioned communication devices.
  • An embodiment of the present application further provides a computer program storage medium, which is characterized in that the computer program storage medium has program instructions, and when the program instructions are executed, the foregoing method is executed.
  • An embodiment of the present application further provides a chip system, characterized in that the chip system includes at least one processor, and when the program instructions are executed in the at least one processor, the foregoing method is executed.
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • each unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of this application essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program code .

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Abstract

本申请提供了一种以太网数据传输的方法，包括：第一设备向第二设备发送第一比特流，第一比特流是通过第一设备的物理层的N个逻辑通道发送的；第一设备向第二设备发送第一触发标记组，第一触发标记组用于指示第一比特流结束发送；响应于第一触发标记组的发送，第一设备向第二设备发送第二比特流，第二比特流是通过第一设备的物理层的P个逻辑通道发送的，N、P均为正整数。通过触发标记的发送，指示对比特流的处理方式变化的时间，从而实现比特流传输的过程中第一设备和第二设备物理层工作模式的无误码切换，在保证数据传输的同时，对以太网接口的功率、数据传输的延时等进行调整。

Description

一种以太网数据传输的方法和通信设备
本申请要求于2019年6月4日提交中国专利局、申请号为201910483078.6、申请名称为“一种以太网数据传输的方法和通信设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，具体涉及一种以太网数据传输的方法和通信设备。
背景技术
当整个以太网接口没有用户数据传输时，以太网接口物理层的部分元件可以进入休眠状态。高速以太网接口具有较大的带宽，能够为更多的用户提供服务。也正是因为连接的用户较多，高速以太网接口很少存在完全没有用户数据传输的情况。因此，对于高速以太网，通过此方案很难达到减小功率的效果。
以太网接口通常采用较强的前向纠错(forwarding error correction，FEC)方案对比特流进行编解码，比如里德-所罗门(Reed-Solomon，RS)编码和解码方案，引入较大的延时，浪费系统资源。
发明内容
本申请提供一种以太网数据传输的方法，能够对物理层的工作模式进行无误码切换，从而能够在保证数据传输的同时，对以太网接口的功率、数据传输的延时等进行调整。
第一方面，提供了一种以太网数据传输的方法，包括：第一设备向第二设备发送第一比特流，所述第一比特流是通过所述第一设备的物理层的N个逻辑通道发送的；所述第一设备向所述第二设备发送第一触发标记组，所述第一触发标记组用于指示所述第一比特流结束发送；响应于所述第一触发标记组的发送，所述第一设备向所述第二设备发送第二比特流，所述第二比特流是通过所述第一设备的物理层的P个逻辑通道发送的，N、P均为正整数。
通过触发标记的发送，指示对比特流的处理方式变化的时间，从而实现比特流传输的过程中第一设备和第二设备物理层工作模式的无误码切换，在保证数据传输的同时，对以太网接口的功率、数据传输的延时等进行调整。对比特流的处理方式变化的时间，也可以理解为比特流中处理方式改变的位置。
逻辑通道数量的改变，可以调整比特流传输速率，从而可以减小系统的功耗。
结合第一方面，在一些可能的实现方式中，所述第一触发标记组包括P个触发标记；所述第一设备向所述第二设备发送第一触发标记组，包括：所述第一设备通过所述P个逻辑通道中的第i个逻辑通道发送所述P个触发标记中的第i个触发标记，i为正整数。
通过将第一触发标记组中的每一个触发标记发送至对应的逻辑通道，可以使得切换时 间准确，可以兼容现有的以太网数据传输流程。
结合第一方面，在一些可能的实现方式中，所述第一触发标记组包括N个触发标记；所述第一设备向所述第二设备发送第一触发标记组，包括：所述第一设备通过所述N个逻辑通道中的第i个逻辑通道发送所述N个触发标记中的第i个触发标记，i为正整数。
通过将第一触发标记组中的每一个触发标记发送至对应的逻辑通道，可以使得切换时间准确，可以兼容现有的以太网数据传输流程。
结合第一方面，在一些可能的实现方式中，所述第i个触发标记包括用于标识所述第i个逻辑通道的信息。
结合第一方面，在一些可能的实现方式中，所述第一比特流通过第一前向纠错FEC编码方式进行编码得到；所述第二比特流通过第二FEC编码方式进行编码得到，所述第二FEC编码方式与所述第一FEC编码方式的纠错能力不同。
通过FEC编码方式的变化，可以调整传输延时，提高传输效率。
结合第一方面，在一些可能的实现方式中，所述第一比特流、所述第二比特流中一个通过前向纠错FEC编码得到。
通过FEC编码方式的变化，可以调整传输延时，提高传输效率。
结合第一方面，在一些可能的实现方式中，所述第一比特流包括锚点码块，所述锚点码块用于指示所述第一比特流结束发送的时间。
通过锚点码块，第一设备和第二设备可以约定切换发生的时间。使得物理层工作模式的切换更加灵活。
结合第一方面，在一些可能的实现方式中，所述第一触发标记组是对齐标记AM组。
通过将对齐标记AM作为触发标记，可以减小对数据传输的影响，简化物理层工作模式切换的流程。
结合第一方面，在一些可能的实现方式中，所述方法还包括：接收所述第二设备发送的对应于所述锚点码块的回应码块；所述第一设备向所述第二设备发送第一触发标记组，包括：根据所述回应码块，所述第一设备向所述第二设备发送所述第一触发标记组。
通过接收回应码块确定工作模式的切换，可以提高切换流程的可靠性。
第二方面，提供了一种以太网数据传输的方法，包括：第二设备接收第一设备发送的第一比特流，所述第一比特流是通过所述第二设备的物理层的N个逻辑通道接收的；所述第二设备接收所述第一设备发送的第一触发标记组，所述第一触发标记组用于指示所述第一比特流结束；响应于所述第一触发标记组的接收，所述第二设备接收所述第一设备发送的第二比特流，所述第二比特流是通过所述第二设备的物理层的P个逻辑通道接收的，N、P均为正整数。
通过触发标记的接收，确定对比特流的处理方式变化的时间，从而实现比特流传输的过程中第一设备和第二设备物理层工作模式的无误码切换，在保证数据传输的同时，对以太网接口的功率、数据传输的延时等进行调整。对比特流的处理方式变化的时间，也可以理解为比特流中处理方式改变的位置。
逻辑通道数量的改变，可以调整比特流传输速率，从而可以减小系统的功耗。
结合第二方面，在一些可能的实现方式中，所述第一触发标记组包括P个触发标记；所述第二设备接收所述第一设备发送的第一触发标记组，包括：所述第二设备通过所述P个逻辑通道中的第i个逻辑通道接收所述P个触发标记中的第i个触发标记，i为正整数。
结合第二方面，在一些可能的实现方式中，所述第一触发标记组包括N个触发标记；所述第二设备接收所述第一设备发送的第一触发标记组，包括：所述第二设备通过所述N个逻辑通道中的第i个逻辑通道接收所述N个触发标记中的第i个触发标记，i为正整数。
结合第二方面，在一些可能的实现方式中，所述第i个触发标记包括用于标识所述第i个逻辑通道的信息。
结合第二方面，在一些可能的实现方式中，所述第一比特流通过第一前向纠错FEC编码方式进行编码得到；所述第二比特流通过第二FEC编码方式进行编码得到，所述第二FEC编码方式与所述第一FEC编码方式的纠错能力不同；所述方法包括：所述第二设备通过所述第一FEC编码方式对应的第一FEC解码方式，对所述第一比特流进行解码；所述第二设备通过所述第二FEC编码方式对应的第二FEC解码方式，对所述第二比特流进行解码。
结合第二方面，在一些可能的实现方式中，所述第一比特流、所述第二比特流中一个是通过前向纠错FEC编码得到的，所述方法包括：所述第二设备对通过前向纠错FEC编码得到的比特流进行FEC解码。
结合第二方面，在一些可能的实现方式中，所述第一比特流包括锚点码块，所述锚点码块用于指示所述第一比特流结束的时间。
结合第二方面，在一些可能的实现方式中，所述第一触发标记组是对齐标记AM组。
结合第二方面，在一些可能的实现方式中，所述方法还包括：所述第二设备向所述第一设备发送对应于所述锚点码块的回应码块，所述锚点码块用于指示所述第一触发标记组的发送。
第三方面，提供一种通信设备，包括：通信接口；所述通信接口用于向第二设备发送第一比特流，所述第一比特流是通过所述通信接口的物理层的N个逻辑通道发送的；所述通信接口还用于，向所述第二设备发送第一触发标记组，所述第一触发标记组用于指示所述第一比特流结束发送；响应于所述第一触发标记组的发送，所述通信接口还用于，向所述第二设备发送第二比特流，所述第二比特流是通过所述通信接口的物理层的P个逻辑通道发送的，N、P均为正整数。
结合第三方面，在一些可能的实现方式中，
结合第三方面，在一些可能的实现方式中，所述第一触发标记组包括P个触发标记，所述通信接口用于通过所述P个逻辑通道中的第i个逻辑通道发送所述P个触发标记中的第i个触发标记，i为正整数。
结合第三方面，在一些可能的实现方式中，所述第一触发标记组包括N个触发标记，所述通信接口用于通过所述N个逻辑通道中的第i个逻辑通道发送所述N个触发标记中的第i个触发标记，i为正整数。
结合第三方面，在一些可能的实现方式中，所述第i个触发标记包括用于标识所述第i个逻辑通道的信息。
结合第三方面，在一些可能的实现方式中，所述第一比特流通过第一前向纠错FEC编码方式进行编码得到；所述第二比特流通过第二FEC编码方式进行编码得到，所述第二FEC编码方式与所述第一FEC编码方式的纠错能力不同。
结合第三方面，在一些可能的实现方式中，所述第一比特流、所述第二比特流中一个通过前向纠错FEC编码得到。
结合第三方面，在一些可能的实现方式中，所述第一比特流包括锚点码块，所述锚点码块用于指示所述第一比特流结束发送的时间。
结合第三方面，在一些可能的实现方式中，所述第一比特流包括锚点码块，所述锚点码块用于指示所述第一比特流结束发送的时间。
结合第三方面，在一些可能的实现方式中，所述第一触发标记组是对齐标记AM组。
结合第三方面，在一些可能的实现方式中，所述通信接口还用于：接收所述第二设备发送的对应于所述锚点码块的回应码块；根据所述回应码块，向所述第二设备发送所述第一触发标记组。
第四方面，提供一种通信设备，其特征在于，包括：通信接口；所述通信接口用于，接收第一设备发送的第一比特流，所述第一比特流是通过所述通信接口的物理层的N个逻辑通道接收的；所述通信接口还用于，接收所述第一设备发送的第一触发标记组，所述第一触发标记组用于指示所述第一比特流结束；响应于所述第一触发标记组的接收，所述通信接口还用于，接收所述第一设备发送的第二比特流，所述第二比特流是通过所述通信接口备的物理层的P个逻辑通道接收的，N、P均为正整数。
结合第四方面，在一些可能的实现方式中，所述第一触发标记组包括P个触发标记，所述通信接口用于通过所述P个逻辑通道中的第i个逻辑通道接收所述P个触发标记中的第i个触发标记，i为正整数。
结合第四方面，在一些可能的实现方式中，所述第一触发标记组包括N个触发标记，所述通信接口用于通过所述N个逻辑通道中的第i个逻辑通道接收所述N个触发标记中的第i个触发标记，i为正整数。
结合第四方面，在一些可能的实现方式中，所述第i个触发标记包括用于标识所述第i个逻辑通道的信息。
结合第四方面，在一些可能的实现方式中，所述第一比特流通过第一前向纠错FEC编码方式进行编码得到；所述第二比特流通过第二FEC编码方式进行编码得到，所述第二FEC编码方式与所述第一FEC编码方式的纠错能力不同；所述通信设备包括处理器，所述处理器用于：通过所述第一FEC编码方式对应的第一FEC解码方式，对所述第一比特流进行解码；通过所述第二FEC编码方式对应的第二FEC解码方式，对所述第二比特流进行解码。
结合第四方面，在一些可能的实现方式中，所述第一比特流、所述第二比特流中一个是通过前向纠错FEC编码得到的，所述通信设备包括：处理器，所述处理器用于对通过前向纠错FEC编码得到的比特流进行FEC解码。
结合第四方面，在一些可能的实现方式中，所述第一比特流包括锚点码块，所述锚点码块用于指示所述第一比特流结束的时间。
结合第四方面，在一些可能的实现方式中，所述第一触发标记组是对齐标记AM组。
结合第四方面，在一些可能的实现方式中，所述通信接口还用于，向所述第一设备发送对应于所述锚点码块的回应码块，所述锚点码块用于指示所述第一触发标记组的发送。
第五方面，提供一种通信装置，包括生成模块、收发模块；收发模块用于向第二设备发送第一比特流，所述第一比特流是通过所述通信设备的物理层的N个逻辑通道发送的。生成模块用于生成第一触发标记组。收发模块还用于，向所述第二设备发送第一触发标记组，所述第一触发标记组用于指示所述第一比特流结束发送。响应于所述第一触发标记组 的发送，收发模块还用于，向所述第二设备发送第二比特流，所述第二比特流是通过所述通信设备的物理层的P个逻辑通道发送的，N、P均为正整数。
结合第五方面，在一些可能的实现方式中，所述第一触发标记组包括P个触发标记；，收发模块用于通过所述P个逻辑通道中的第i个逻辑通道发送所述P个触发标记中的第i个触发标记，i为正整数。
结合第五方面，在一些可能的实现方式中，所述第i个触发标记包括用于标识所述第i个逻辑通道的信息。
可选地，所述第一比特流通过第一前向纠错FEC编码方式进行编码得到；所述第二比特流通过第二FEC编码方式进行编码得到，所述第二FEC编码方式与所述第一FEC编码方式的纠错能力不同。
结合第五方面，在一些可能的实现方式中，所述第一比特流、所述第二比特流中一个通过前向纠错FEC编码得到。
结合第五方面，在一些可能的实现方式中，所述第一比特流包括锚点码块，所述锚点码块用于指示所述第一比特流结束发送的时间。
结合第五方面，在一些可能的实现方式中，所述第一触发标记组是对齐标记AM组。
结合第五方面，在一些可能的实现方式中，收发模块还用于接收所述第二设备发送的对应于所述锚点码块的回应码块；根据所述回应码块，收发模块用于向所述第二设备发送所述第一触发标记组。
第六方面，提供的一种通信设备，包括收发模块，处理模块。收发模块用于接收第一设备发送的第一比特流，所述第一比特流是通过所述通信设备的物理层的N个逻辑通道接收的。收发模块还用于，接收所述第一设备发送的第一触发标记组，所述第一触发标记组用于指示所述第一比特流结束。响应于所述第一触发标记组的接收，收发模块还用于，接收所述第一设备发送的第二比特流，所述第二比特流是通过所述通信设备的物理层的P个逻辑通道接收的，N、P均为正整数。处理模块用于对所述第一比特流、所述第二比特流进行处理。
结合第六方面，在一些可能的实现方式中，所述第一触发标记组包括P个触发标记。收发模块用于，通过所述P个逻辑通道中的第i个逻辑通道接收所述P个触发标记中的第i个触发标记，i为正整数。
结合第六方面，在一些可能的实现方式中，所述第一触发标记组包括N个触发标记。收发模块用于，通过所述N个逻辑通道中的第i个逻辑通道接收所述N个触发标记中的第i个触发标记，i为正整数。
结合第六方面，在一些可能的实现方式中，所述第i个触发标记包括用于标识所述第i个逻辑通道的信息。
结合第六方面，在一些可能的实现方式中，所述第一比特流通过第一前向纠错FEC编码方式进行编码得到；所述第二比特流通过第二FEC编码方式进行编码得到，所述第二FEC编码方式与所述第一FEC编码方式的纠错能力不同。处理模块用于：通过所述第一FEC编码方式对应的第一FEC解码方式，对所述第一比特流进行解码；通过所述第二FEC编码方式对应的第二FEC解码方式，对所述第二比特流进行解码。
结合第六方面，在一些可能的实现方式中，所述第一比特流、所述第二比特流中一个是通过前向纠错FEC编码得到的。处理模块用于对通过前向纠错FEC编码得到的比特流 进行FEC解码。
结合第六方面，在一些可能的实现方式中，所述第一比特流包括锚点码块，所述锚点码块用于指示所述第一比特流结束的时间。
结合第六方面，在一些可能的实现方式中，所述第一触发标记组是对齐标记AM组。
结合第六方面，在一些可能的实现方式中，收发模块1510还用于，向所述第一设备发送对应于所述锚点码块的回应码块，所述锚点码块用于指示所述第一触发标记组的发送。
第七方面，提供一种计算机程序存储介质，其特征在于，所述计算机程序存储介质具有程序指令，当所述程序指令被执行时，使得上文中的方法被执行。
第八方面，提供一种芯片，所述芯片系统包括至少一个处理器，当程序指令在所述至少一个处理器中执行时，使得上文中的方法被执行。
附图说明
图1是一种基于以太网技术连接的网络的示意图。
图2是一种通信设备的示意性结构图。
图3是一种以太网数据传输方法的示意性流程图。
图4是另一种以太网数据传输方法的示意性流程图。
图5是本申请一个实施例提供的一种以太网传输数据方法的示意性流程图。
图6是IEEE802.3规范的64B/66B码块的类型的示意图。
图7是类型为0x4B的控制码块的示意图。
图8是本申请另一个实施例提供的一种以太网传输数据方法的示意性流程图。
图9是本申请又一个实施例提供的一种以太网传输数据方法的示意性流程图。
图10a至图10d是本申请另一个实施例提供的一种以太网传输数据的示意图。
图11是本申请又一个实施例提供的一种以太网传输数据方法的示意性流程图。
图12a至图12c是本申请另一个实施例提供的一种以太网传输数据的示意图。
图13是本申请又一个实施例提供的一种以太网传输数据方法的示意性流程图。
图14a至图14d是本申请另一个实施例提供的一种以太网传输数据的示意图。
图15是本申请又一个实施例提供的一种以太网传输数据方法的示意性流程图。
图16a至图16c是本申请又一个实施例提供的一种以太网传输数据的示意图。
图17又一种以太网数据传输方法的示意性流程图。
图18是本申请又一个实施例提供的一种以太网传输数据方法的示意性流程图。
图19是本申请又一个实施例提供的一种以太网传输数据方法的示意性流程图。
图20a至图20c是本申请又一个实施例提供的一种以太网传输数据的示意图。
图21是本申请实施例提供的一种通信方法的示意性流程图。
图22是本申请实施例提供的一种锚点包的示意图。
图23是本申请一个实施例提供的一种通信设备的示意性结构图。
图24是本申请另一个实施例提供的一种通信设备的示意性结构图。
图25是本申请又一个实施例提供的一种通信设备的示意性结构图。
图26是本申请又一个实施例提供的一种通信设备的示意性结构图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
电气和电子工程师协会(institute of electrical and electronics engineers，IEEE)802.3工作组发布的以太网相关标准，以其简洁、尽力而为的传输方式和标准化互通互联的机制受到网络厂商的极大欢迎。目前基于以太网的传输技术已经在电信网络得到广泛应用。
图1是一种基于以太网技术连接的网络的示意图。
通信设备110与通信设备120、通信设备130基于以太网进行用户数据传输，通信设备140与通信设备120、通信设备130基于以太网进行用户数据传输。基于以太网进行用户数据传输的两个通信设备可以通过电缆或光纤的方式连接。
图2是一种通信设备的示意性结构图。通信设备110用于基于以太网的数据传输。
通信设备110包括主控交换单元、接口单元等。主控交换单元包括网络处理器(network processor，NP)或交换芯片。接口单元用于设备110与其他设备进行信息交互。接口单元包括以太网接口，以太网接口对数据传输的流程可以参考图3和图4。以太网接口可以用于执行媒体访问控制(medium access control，MAC)层、协调子层(reconciliation sublayer，RS)、物理(physical，PHY)层的全部或部分功能。以太网接口进行的数据传输的方法可以通过芯片或FPGA实现。
图3是一种以太网数据传输的方法的示意性流程图，主要描述物理层的相关处理过程。
对于第一设备，一个以太网包进入媒体访问控制(medium access control，MAC)层/协调子层(reconciliation sublayer，RS)后，对包进行校验并按照某种介质独立接口(medium independent interface，MII)要求实施编码，通过xMII发送至物理编码子层(physical coding sublayer，PCS)。PCS子层接收各种MII(some kind of MII，xMII)接口发送的xMII信息，进行比特码块编码和速率匹配。xMII一般应用于以太网设备的MAC层和物理层之间。在一些实施例中，xMII接口存在于集成电路内。PCS子层按照64比特(bit，B)/66B规则编码，形成一条串行流。之后，PCS子层将64B/66B码块按照256B/257B编码规则进一步编码为257B的码块流。257B码块经过扰码处理后，插入对齐标记(alignment marker，AM)组。AM组的也是若干个257B。插入AM组之后，257B码块流按照10比特的符号分发到2路前向纠错(forwarding error correction，FEC)编码，加入校验比特，FEC编码后再按照每个符号10bit分发至8条PCSL。应当理解，2路FEC采用的FEC编解码方式相同，通过2路FEC可以提高编解码速率和抗突发误码能力。然后通过分布和交织，按照符号(一个符号为10比特)分发至8条物理编码子层通道(physical coding sublayer lane，PCSL)。插入的AM会分布在每一条PCSL上。PCSL上的符号可以通过物理媒介接入子层(physical medium attachment，PMA)和物理媒介相关子层(physical medium dependent，PMD)发送至第二设备。
第二设备通过PMD和PMA接收第一设备发送的符号，利用每个PCSL上的AM进行通道锁定，并对各个PCS通道重排序得到符号流，然后对符号流进行RS解码之后，形成串行码块流并移除串行码块流中的AM组，然后对移除AM组之后的串行码块流进行解扰和反向转码之后得到64B/66B的串行码块流，对64B/66B的串行码块流进行解码和速率匹配发送到RS子层和MAC层，通过MAC层将数据传送到数据链路层。
比特是二进制数字中的位，信息量的度量单位，为信息量的最小单位。257B的码块 流、66B的码块流、以及分发至逻辑通道的符号流，均可以理解为比特流。
需要说明的是，为了方便理解，图3只是简述了以太网接口的处理流程，具体在应用中可以增加其他的处理过程，或者减少上述部分处理过程。上述方法适用于200G和400G以太网接口。对于40G和100G的以太网接口，可以不包括FEC编码、FEC解码和257B转码的过程。
图4是一种以太网传输数据方法的示意性流程图，主要描述物理层的相关处理过程。图4所示的方法适用于40G和100G以太网接口。
对于第一设备，即发送端，一个以太网包进入MAC层/RS子层后，对包进行校验，按照xMII要求编码并通过xMII发送至PCS子层。PCS子层通过xMII接口对接收的信息按照64B/66B编码规则进行编码，形成一条串行的66B码块流。对66B码块的码块流进行扰码处理，分发至20条PCSL，并插入各PCSL的AM。根据IEEE 802.3，100G以太网接口包括20条PCSL，20条PCSL对应于20个AM，每一个AM分别通过一条PCSL发送。
不进行FEC编码的情况，PCSL中的数据经PMA和PMD，发送至第二设备。第二设备PCS子层接收第一设备通过PCSL发送的比特流。
第二设备根据每条PCSL中的AM，对PCSL进行锁定，消除抖动，对各PCSL重排序形成串行流。之后，去除AM，进行解扰。对66B码块流进行解码并发送至MII接口，MAC/RS子层从MII接口接收信息。
进行FEC编码的情况，在第一设备将码块流分发至PCSL之后，第一设备的FEC子层接收PCSL发送的比特流。FEC子层可以是物理层中的一个子层。为了方便理解，可以认为PCS子层包括FEC子层。利用每个PCSL上的AM进行PCSL的锁定，并对各个通道重排序得到串行的66B码块流，之后移除PCSL的AM。66B码块流按照256B/257B编码规则进一步编码为257B的码块流。之后，插入AM组，AM组包括对应于各前向纠错编码通道(forwarding error correction lane，FECL)的AM。每条FECL的AM与多条PCSL的AM具有对应关系。对应关系也称为映射关系。根据各PCSL的AM，可以确定每条FECL的AM。插入AM组后，进行FEC编码，并按照符号分发至多条FECL，比如100G是4条FECL。经PMA和PMD，FECL中的数据发送至第二设备。
第二设备即接收端从FECL接收传输的比特流。第二设备根据每个FECL的AM信息锁定各个通道，消除抖动。锁定后的各FECL经过重排序，FEC解码后，形成257B串行流并移除AM组，将257B的码块流转码为66B的码块流，插入各PCSL的AM，并分发至PCSL。PCSL的AM与FECL的AM具有对应关系。第二设备插入的对应每条PCSL的AM与第一设备插入的对应该PCSL的AM相同。
第二设备PCS子层接收FEC子层通过PCSL发送的比特流。
第二设备根据每条FECL中的AM，对FECL进行锁定，消除抖动，对各FECL重排序形成串行流。之后，去除各PCSL的AM，并进行解扰。对66B码块流进行解码并发送至xMII接口，MAC/RS子层从xMII接口接收信息完成校验及相关处理后恢复出以太网包。
应当理解，图4只是简述了以太网接口的一种处理流程。
AM组，AM组可以是若干个码块。例如，对于200G的以太网接口，AM组是4个257B，4个257B由8个120比特以及65比特的填充域和3比特的状态域组成(4*257＝120*8+65+3)；又例如，对于400G的以太网接口，AM组是8个257B，8个257B 由16个120比特以及133比特的填充域和3比特的状态域组成(8*257＝120*16+133+3)。再例如，对于100G以太网接口，AM组是5个257B，5个257B由20个64比特以及5比特的填充域组成(5*257＝20*64+5)。
逻辑通道，本申请中的逻辑通道可以指物理编码子层通道(physical coding sublayer lane，PCSL)，或者前向纠错编码通道(forwarding error correction lane，FECL)，或者200G、400G以及更高速以太网接口中部署的独立进行FEC编解码和符号分发的通道。也就是说，串行比特流按照符号分发到至少一路FEC编码，并按照符号分发至一组FEC通道，所述至少一路FEC可以认为是一个逻辑通道。接收方向也是如此。参照图3的处理流程，第一设备中2路FEC编码，可以是一个逻辑通道。第二设备中2路FEC解码，可以是一个逻辑通道。对于200G/400G以太网接口，PCSL也可以称为FEC通道(FEC lane，FECL)。逻辑通道一般在芯片内可见，即在于集成电路内部开始或终结。
连接单元接口(attachment unit interface，AUI)可以称为物理通道。物理通道部署于芯片之间，或者芯片与光模块之间。
应当理解，实际上逻辑通道和总线通道是传输过程中的不同路径，也可以理解为传输过程中的不同层次(比如物理通道可以认为是逻辑通道的服务层)。物理通道与逻辑通道的对应关系可以是a个逻辑通道与b个物理通道对应，a＝b*c，或者，b＝a*c，a，b，c是正整数。对于200G、400G以及更高速以太网接口，也可以采用多路独立进行FEC编码(至少一个编码器)和符号分发的通道，此时，c个物理通道对应一个逻辑通道。对于PCSL或FECL，c个逻辑通道对应一个物理通道，在第一设备将码块流按照符号分发到各个逻辑通道，若一个或多个逻辑通道对应一个物理通道，逻辑通道上的数据可以向对应的物理通道发送，第二设备通过b个物理通道接收第一设备的b个物理通道发送的数据，然后将一个物理通道的数据分发到c个逻辑通道。例如，如图2所示，对于200G的以太网接口，可以有8个并行的逻辑通道PCSL，可以是两个逻辑通道上的比特分发到一条物理通道，每个逻辑通道传输25G的净荷数据，两个逻辑通道对应一个物理通道，一个物理通道传输50G的净荷数据。
FEC编解码，即采用编解码技术纠正传输过程中的比特错误。FEC编码例如可以是里德-所罗门(Reed-Solomon，RS)编码等。进行RS编码，目的是为了进一步提高比特流在传输过程中的正确率，RS解码时可以根据插入的校验比特纠正发生错误的比特。对于RS编码，可以认为在不改变原码块流的情况下，每间隔一定比特插入一些校验比特。对于RS解码，可以认为在不改变原码块流的情况下，根据RS编码时每间隔一定比特插入的校验比特计算并恢复传送过程中出错的比特。校验完成之后，这些校验比特被移除。
FEC编解码的方式，IEEE802.3规范200G、400G以太网接口采用RS(544,514)方案，100G以太网接口可以采用RS(544,514)或RS(528,514)方案。一些厂家还采用RS(272,257)的方案。这些RS方案，纠错能力RS(544,514)较强，但引入的时延也较长。而RS(272,257)纠错能力较弱，但引入时延较小。
IEEE 802.3规范了一种低功耗管理技术高能效以太网(energy-efficient Ethernet，EEE)，当整个以太网端口没有包发送或接收时，MAC/RS层向PCS层发送低功耗空闲(low power idle，LPI)码块，PCS子层、PMA子层、PMD子层中的部分元件关闭，进入休眠状态(deep sleep)。关闭的部分元件可以是耗能较高的元件，例如逻辑通道、物理通道等。MAC层接收到数据，向PCS层发送空闲(idle)码块。当PCS层监测空闲(idle)码块时，立即 唤醒已经关闭的工作元件，即已经关闭的工作元件上电开启。
只有当整个以太网接口没有流量时才能进入休眠模式。高速以太网接口具有较大的带宽，能够为更多的用户提供服务。也正是因为连接的用户较多，高速以太网接口很少存在完全没有流量的场景。因此，对于高速以太网，通过此方案很难达到减小功率的效果。
另一种降低功耗的方式，在2层(layer 2，L2)或3层(layer 3，L3)可以将业务流量从某些节点和链路调整到其他的节点和链路。2层包括MAC层，3层包括互联网协议(internet protocol，IP)层、多协议标签交换(multi-protocol label switching，MPLS)层等。例如，对于图1中的场景，数据一从设备110经设备120发送至设备140，数据二从设备110经设备130发送至设备140。场景中传输的数据较少。在数据传输过程中，对数据一进行传输路径的切换。切换后，数据一和数据二均从设备110经设备130发送至设备140。设备110-设备120-设备140路径上的设备可以进入休眠状态，降低系统功耗。
该技术需要部署网管或控制器进行配置，是一种网络级的行为，对系统的影响较大。同时，由于两条路径上包传输的速率可能不同，为了保证不丢包，包不乱序，在进行切换的过程中，接收端设备需要设置用于缓存、包重排序的功能模块，成本较大。
另外，以太网链路在物理层采用能力较强的FEC。IEEE 802.3规范的200G、400G以太网接口采用RS(544,514)，延时较大。在一些情况下，采用纠错能力较弱的FEC方案，或者不进行FEC，就可以满足要求。不区分业务场景，均通过能力较强的FEC进行处理，引入较大的传输时延，浪费系统资源。
为了解决上述传输延时较大或功耗较高的问题，可以对物理层的工作模式进行切换。为了保证数据无误码传输，本申请提供了一种以太网传输数据的方法。
图5是本申请实施例提供的一种以太网传输数据方法的示意性流程图。
在步骤S501，第一设备向第二设备发送第一比特流。第一比特流是通过所述第一设备的物理层的N个逻辑通道发送的。
应当理解，根据分发和重排序的规则，第一设备将串行的比特流按照比特码块或符号分发至多个逻辑通道，第二设备锁定和重排序多个逻辑通道并接收比特码块或符号，以形成串行的比特流。多个逻辑通道中的比特码块或符号进行排序的顺序性对固定，因此，可以认为第一设备通过多个逻辑通道向第二设备发送一条比特流。
可选地，第一比特流可以包括逻辑通道指示信息，所述逻辑通道指示信息用于指示用于发送第二比特流的P个逻辑通道。或者，网管可以向第一设备和第二设备发送逻辑通道指示信息，指示用于发送第二比特流的P个逻辑通道。
第一比特流可以包括锚点信息，所述锚点信息用于指示所述第一比特流结束发送的时间。也可以理解为，锚点信息用于指示第一触发标记组在比特流中的位置。锚点信息例如可以是锚点码块。锚点信息也可以对应多个码块。锚点信息也可以通过锚点包表示，参见图21至图22的说明。
第二设备接收锚点码块。第二设备在接收锚点码块后，可以将锚点码块去除。第二设备可以在逻辑通道重排序形成串行的比特流后，在串行的比特流中去除锚点码块。
第二设备可以根据锚点码块，以检测触发标记。第二设备可以监测逻辑通道，在多个逻辑通道中检测触发标记。或者，第二设备可以在逻辑通道重排序，形成串行的比特流后，在串行的比特流中检测触发标记。
第二设备可以在串行的比特流中去除触发标记。去除触发标记，也可以称为触发标记 的提取。去除触发标记，可以减小对数据传输的干扰。
仅通过一个锚点码块，第一设备与第二设备就可以对工作模式的切换进行配置，减小了系统开销。
可选地，锚点码块可以包括物理层切换信息，物理层切换信息用于标识该码块用于物理层工作模式的切换。
可选地，锚点码块可以包括锚点码块标识，锚点码块标识用于表示该码块为锚点码块。
可选地，锚点码块可以包括触发指示信息，触发指示信息用于指示触发标记组的在比特流中的位置。
可选地，锚点码块可以包括第一切换方式指示信息，第一切换方式指示信息用于指示切换的方式。切换的方式包括传输速率的切换和/或传输延时的切换。进行传输速率的切换，切换前后，通过不同的逻辑通道的数量进行比特流的发送。进行传输延时的切换，切换前后，采用不同的FEC编码方式(包括不进行FEC编码)得到比特流。
在一些实施例中，第二设备接收锚点码块后，可以向第一设备发送回应码块。回应码块用于指示第一触发标记组的发送。也就是说，根据所述回应码块，第一设备向第二设备发送第一触发标记组。
第一设备的物理层可以包括发送逻辑通道和接收逻辑通道。发送逻辑通道可以用于向第二设备发送比特流。接收逻辑通道可以用于接收第二设备发送的比特流。第一设备的发送逻辑通道和接收逻辑通道可以同时运行。
第一设备可以通过接收逻辑通道接收第二设备发送的回应信息，回应信息例如可以是锚点码块，或者采用与锚点码块相同的类型。也就是说，回应信息可以是回应码块。回应码块可以包括回应信息的标识，例如在回应码块中与锚点码块标识的相应域标识该码块是“回应”码块。
可选地，回应码块可以包括第二切换方式指示信息。第一设备可以根据回应码块中的第二切换方式指示信息，确定切换的方式。
例如，锚点码块包括第一切换方式指示信息，第一切换方式指示信息指示切换的方式为降速和降低延时。回应码块包括第二切换方式指示信息，第二切换方式指示信息指示切换的方式为传输速率不变，降低延时。第一设备根据回应码块中的第二切换方式指示信息，确定切换的方式为传输速率不变，降低延时。第二设备可以根据能够支持的切换方式，确定第二切换方式指示信息。
可选地，回应码块可以包括物理层切换信息，物理层切换信息用于标识该码块用于物理层工作模式的切换。
如果第一设备未接收回应码块，第一设备不停止第一比特流的发送，不再进行步骤S502-S503。如果第一设备接收回应码块，进行步骤S502-S503。
通过接收回应码块确定工作模式的切换，可以提高切换流程的可靠性。如果第二设备不支持物理层工作模式的切换，仅第一设备进行切换，可能导致数据接收错误。第二设备在支持物理层工作模式的切换时，向第一设备发送回应码块，可以提高切换流程的可靠性，避免数据的丢失。回应码块还可以包括第二切换方式指示信息，第二切换方式指示信息可以表示第二设备支持的切换方式的类型。从而进一步提高切换流程的可靠性。
当然，第一设备也可以通过网关发送的信息，确定第二设备支持物理层工作模式的切换。
在另一些实施例中，第一比特流不包括锚点码块。这种情况，第一设备和第二设备可以通过网管配置的方式，确定切换的方式。
在步骤S502，第一设备向第二设备发送第一触发标记组，所述第一触发标记组用于指示所述第一比特流结束发送。
第一触发标记组可以是两种不同工作模式切换的标志。
第一触发标记组可以与第一比特流发送的方式相同，或者与第二比特流发送的方式相同。
第一触发标记组包括对应于上述N个逻辑通道或P个逻辑通道的触发标记。
第一比特流包括锚点码块时，对应于某一轮AM的发送，每个逻辑通道对应的AM可以作为该逻辑通道对应的触发标记。第一触发标记组包括对应于上述N个或P个逻辑通道的AM。
本申请实施例对触发标记组的形式不作限定，可以是一个或多个257B码块，或者一个或多个66B码块，或者还可以是其他形式。第一触发标记组可以复用AM组，即第一触发标记组可以是AM组。或者，在100G以太网接口中，不进行FEC的情况，第一触发标记组可以是包括一个或多个66B码块，该一个或多个66B码块对应于N个或P个PCSL的AM。
第一设备可以在第一比特流分发至N个逻辑通道之前，在串行的第一比特流中插入触发标记组。或者，第一设备可以在第一比特流分发的过程中，在第一触发标记组中的每个触发标记对应的逻辑通道中插入该触发标记。
第二设备接收第一触发标记组。第二设备可以检测对应于各逻辑通道的触发标记。在检测触发标记后，第二设备可以将触发标记从比特流中去除。触发标记为逻辑通道的AM时，去除AM的过程即为触发标记的去除。
在步骤S503，响应于第一触发标记组的发送，第一设备向第二设备发送第二比特流。第二比特流是通过第一设备的物理层的P个逻辑通道发送的，N、P均为正整数。
第一触发标记组可以包括N个触发标记，第一设备可以通过所述该N个逻辑通道中的第i个逻辑通道发送该N个触发标记中的第i个触发标记。
或者，第一触发标记组可以包括P个触发标记，第一设备可以通过P个逻辑通道中的第i个逻辑通道发送该P个触发标记中的第i个触发标记。发送这P个触发标记的P个逻辑通道与第一设备发送第二比特流的P个逻辑通道相同。
响应于所述第一触发标记组的接收，所述第二设备接收所述第一设备发送的第二比特流。
通过每个逻辑通道发送的触发标记可以相同或不同，例如，第i个触发标记可以包括用于标识所述第i个逻辑通道的信息。
N与P可以相同或不同。也就是说，第一比特流与第二比特流可以通过相同或不同数量的逻辑通道发送。在一些实施例中，第一比特流与第二比特流可以通过相同的逻辑通道发送。
通过不同数量的逻辑通道发送第一比特流和第二比特流，可以改变比特流的传输速率，即进行传输速率的切换。如果N大于P，第一触发标记组发送前后，用于发送比特流的物理层逻辑通道数量减小，系统的功耗减小，比特流的传输速率降低。如果N小于P，第一触发标记组发送前后，用于发送比特流的物理层逻辑通道数量增加，系统的功耗增大， 比特流的传输速率增加。
不进行比特流传输的物理层逻辑通道可以退出运行。逻辑通道退出运行即该逻辑通道停止比特流的发送，也就是说，逻辑通道对应的物理器件退出运行。一条物理通道对应于一条或多个逻辑通道。部分逻辑通道停止发送比特流，可能使得部分物理通道停止发送比特流，进一步减小系统的功耗。因此，控制逻辑通道退出运行时，可以控制数量尽量少的物理通道对应的逻辑通道退出运行。也就是说，可以使得更多的物理通道退出运行，减小系统功耗。
通过步骤S501-S503，也可以进行传输延时的切换。
不同的FEC编码方式对应于不同的纠错能力。采用FEC编码，会引入延时。采用纠错能力越强的FEC编码方式进行编码，引入的延时越长。
可选地，第一比特流可以通过第一FEC编码方式进行编码得到，第二比特流可以通过第二FEC编码方式进行编码得到，第一FEC编码方式可以与第二FEC编码方式不同。不同的FEC编码方式对应于不同的纠错能力，也就是说，第二FEC编码方式与第一FEC编码方式的纠错能力不同。
第二设备接收第一比特流。第二设备通过所述第一FEC编码方式对应的第一FEC解码方式，对所述第一比特流进行解码。
第二设备接收第二比特流。第二设备通过所述第二FEC编码方式对应的第二FEC解码方式，对所述第二比特流进行解码。
可选地，所述第一比特流、所述第二比特流中的一个通过FEC编码得到。也就是说，所述第一比特流、所述第二比特流中，其中一个经过了FEC编码，另一个未经过FEC编码。第二设备对通过前向纠错FEC编码得到的比特流进行FEC解码。
应当理解，在切换前后，数据的处理过程几乎不变。例如，对于图4所示的以太网传输数据方法，对于传输延时的切换，在切换前后的任一时刻，即使比特流不经过FEC编解码，仍需要通过FECL进行比特流的传输。也就是说，仅仅是FEC编解码过程中的编解码码方式的改变，其他的处理过程不变。
通过步骤S501-S503，可以实现物理层工作模式切换时数据的无误码传输。
第一设备可以通过锚点码块与第二设备约定工作模式的切换，以及切换的时间点。切换的时间点可以理解为比特流中的位置。
第一设备可以通过触发标记组的发送，指示第二设备进行切换，从而保证无误码。第一设备触发标记组的发送，可以作为新的工作模式的起点，或者原工作模式的终点。第二设备触发标记组的接收，可以作为新的工作模式的起点，或者原工作模式的终点。也就是说，触发标记组可以作为新的工作模式的起点，或者原工作模式的终点。
工作模式的切换，可以是部分逻辑通道退出运行或恢复运行，可以是改变FEC方案，也可以是这两种方式的组合，或其他物理层工作模式的切换。改变FEC方案可以包括是否进行FEC的切换，以及FEC编解码方式的切换。
通过上述方式，实现了物理层无误码切换，不影响业务传输。并且，不需要设置较大的缓存以及包重排序模块，减小系统成本，能够兼容现有的IEEE82.3架构，操作简便，容易实施。
图6是IEEE802.3规范的64B/66B码块的类型的示意图。
64B/66B编码将64bit数据或控制信息编码成66bit块传输，66bit块的前两位表示同 步头，后64bit可以称为数据净荷。同步头有“01”和“10”两种。数据码块中，同步头为“01”，同步头后的64bit都是数据。控制码块中，同步头为“10”，同步头后的64bit包括数据和/或控制信息。控制码块中，数据负荷中的前8bit，即与同步头相邻的8bit是类型域，可以表示控制码块的类型。数据负载中的后56bit，即类型域之后的56bit是控制信息和/或数据。64B/66B码块中，D表示数据字节，每个数据字节为8bit；C表示控制字节，每个控制字节为7bit；S表示数据包的开始，T表示数据包的结束；O表示ordered set控制码块(例如，类型为0x4B，O的取值不同，使用场景不同)。S只会出现在8字节中的第0和第4字节，T能够出现在任意的字节。包含S的码块可以称为S码块，包含T的码块可以称为T码块。空闲(idle)码块中的C 0～C 7为0，低功耗(LPI)码块中的C 0～C 7为6。
锚点码块可以是64B/66B控制码块，例如，作为锚点码块的控制码块，类型可以是0x4B、0x2D、0x55、0x00等。
回应码块可以是64B/66B控制码块，例如，作为回应码块的控制码块，类型可以是0x4B、0x2D、0x55、0x00等。
对于按照66B符号分发的情况，发送至每个逻辑通道的触发标记可以是64B/66B控制码块，例如，作为触发标记的控制码块，类型可以是0x4B、0x2D、0x55、0x00等。触发标记组也可以复用AM。
下面以类型为0x4B的控制码块进行说明。可以通过类型为0x4B的控制码块中的信息表示该码块为锚点码块、回应码块或触发标记。
图7是类型为0x4B的控制码块的示意图。
在类型为0x4B的控制码块中，A、B、C、D分别是该控制码块中的几个比特。可以通过2比特的A字段表示码块的类型。例如，A字段为“01”表示该码块为锚点码块，A字段为“11”表示该码块为回应码块。若触发标记为66B的码块，A字段为“10”表示该码块为触发标记。
当A字段的标识是“01”，即该码块为锚点码块时，可以通过B字段标识触发标记的在码块流中的位置，例如，可以通过B标识触发标记组与该锚点码块间隔的码块的个数，或触发标记组与锚点码块之间的AM组的数量。
C字段可以复用O0字段。根据IEEE802.3，O0是预留的字段，可以称为顺序排序设置(sequence ordered set)。C的4bit可以用于标识故障，例如C字段为“0000”表示正常，C字段为“0001”表示本地故障，C字段为“0010”表示远端故障。可以通过C字段为其他值，例如“0100”或“1010”等，表示该码块是用于指示物理层工作模式切换的码块。前缀“0x”表示是十六进制码。例如，“1010”可以标示为“0xa”。
D字段可以包括4比特，可以用于表示切换类型。该码块为锚点码块时，可以通过D字段中的2bit表示传输速率的切换，另2bit表示传输延时的切换。即D字段可以是第一切换方式指示信息。例如，D字段为“0001”可以表示加速、“0010”表示减速、“0100”表示加时延，“1000”表示减时延等。也就是说，通过D字段可以标识传输速率和传输延时同时切换的情况。
当A字段是“11”，即该码块为回应码块时，可以通过C字段表示该码块是用于指示物理层工作模式切换的码块。可以通过D字段表示切换类型，即D字段可以是第二切换方式指示信息。
A字段是“10”，即触发标记，可以通过B字段表示该触发标记组对应的逻辑通道。
根据IEEE802.3，第一设备在各PCSL或FECL周期性发送AM，第二设备在各PCSL或FECL周期性接收AM。AM在每个通道上都会周期性的收发，且不同逻辑通道的AM携带标识对应逻辑通道的信息。因此，触发标记组可以复用AM。此时，锚点码块中的B可以表示第一设备插入锚点码块后，发送的第M个周期的AM为触发标记组。也就是说，对于第二设备，锚点码块中的B可以表示在串行比特流中，位于锚点码块后的第M个周期的AM为触发标记组。
图8是本申请实施例提供的一种以太网传输数据方法的示意性流程图。
100G以太网接口，可以采用10×10Gbps物理通道电互联，可以不进行FEC。根据IEEE802.3，100G以太网接口对应20条PCS通道。PCSL为逻辑通道。1-2#逻辑通道对应于1#物理通道，3-4#逻辑通道对应于2#物理通道，其他逻辑通道与物理通道的对应关系以此类推。1#逻辑通道表示该逻辑通道的编号为1。每条PCS通道中发送的比特流，单位为66B码块。当链路流量远小于50G时，网管可以下发逻辑通道指示信息，指示链路旁路11～20#PCS通道，即11～20#PCS通道不再进行数据的传输，可以进入休眠状态，例如可以关闭该这些逻辑通道以及对应的物理通道。以太网接口对应的20条PCS通道的逻辑通道编号1～20#，此次要求旁路11～20#，即11～20#逻辑通道退出运行，对应的物理通道是6～10#。
第一设备发起切换，第二设备配合。触发标记组中的每个触发标记可以是图7所示的控制码块。具体的切换过程参见图9。
图9是本申请实施例提供的一种以太网传输数据方法的示意性流程图。逻辑通道为PCSL。
步骤S901，第一设备插入锚点码块。
参见图10a，第一设备MAC层接收数据包。第一设备PCS子层在串行的比特流中插入锚点码块。图中阴影所示的码块为锚点码块。
为了便于确定触发码块的位置，可以在比特流中AM对应的第一个码块之后的整数倍的位置，插入锚点码块。第一设备检测PCS通道的一个AM码块，与该AM保持N的整数倍。N为当前模式的工作通道数。例如，N为20，在与该AM码块距离为50×20码块的位置插入锚点码块，即该AM之后的第50×20个码块为锚点码块。参考图7所示的锚点码块的格式，锚点码块中可以将B字段设置为M。M用于表示触发标记组的位置。例如，M可以表示在比特流中，锚点码块之后的第M个码块为触发标记组的第一个码块，例如，锚点码块之后的第M个码块开始为触发标记组。M的值可以由第一设备确定，或者由网管配置。例如，M＝10240。插入锚点码块时，第一设备启动M计数，统计插入锚点码块后发送的码块数。锚点码块可以包含切换类型信息。切换类型信息为“0x2”，可以表示模式切换类型为降速。
在步骤S901之后，第一设备向第二设备发送锚点码块。根据以太网接口的分发规则，锚点码块被分发至逻辑通道。第一设备向第二设备发送比特流。在串行的比特流中插入的锚点码块，随比特流发送至第二设备。
在步骤S902，第二设备接收锚点码块。
参见图10b，第二设备在串行的比特流中去除锚点码块。图中阴影所示的码块为锚点码块。
根据锚点码块，第二设备获取M＝10240的信息，并启动M计数，统计锚点码块的接 收开始接收的码块的数量。
第二设备可以向第一设备发送回应信息，回应信息例如可以是回应码块。第二设备可以通过第二设备的发送逻辑通道向第一设备发送回应码块。第二设备的发送逻辑通道用于向第一设备发送比特流。
第一设备在计数至M时，仍未接收到回应码块，则取消物理层工作模式的切换，即不再进行步骤S903-S904。
第一设备在在计数至M之前，接收回应码块，则进行步骤S903。
在步骤S903，第一设备插入触发标记。
参见图10c，T 2a时，第一设备计数至M，插入触发标记组，触发标记组中触发标记的个数为10或20，即对应于切换后用于比特流传输的10个逻辑通道，或对应于切换前用于比特流传输的20个逻辑通道。第一设备分发触发标记组。T 2b时，第一设备已经完成分发触发标记组，每个触发标记已经分发至对应的逻辑通道。图中阴影所示的部分为触发标记。100G以太网接口按照66B码块将串行的比特流分发至逻辑通道，触发标记的数量即为触发标记占用的66B码块的数量。
第一设备可以与第二设备约定，在传输速率切换时，插入的触发标记组通过切换前的逻辑通道发送，还是通过切换后的逻辑通道发送。即，第一设备可以与第二设备约定通过1～10#逻辑通道分发触发标记组，或通过1～20#逻辑通道分发触发标记组。
若第一设备插入对应于1～10#这10个逻辑通道的触发标记组，10为新模式下的逻辑通道(PCS通道)数，第一设备的分发器通过1～10#逻辑通道分发触发标记组，11～20#逻辑通道退出运行。分发器可以认为是第一设备中将串行的比特流分发至各逻辑通道的装置。
若第一设备插入对应于1～20#这20个逻辑通道的触发标记组，20为原模式下的逻辑通道(PCS通道)数，分发器通过1～20#逻辑通道分发触发标记组，之后，11～20#逻辑通道退出运行。触发标记组是第一设备的分发器按照新老模式工作的分界点，是新模式的开始点。
由于锚点码块与第一个AM码块距离为50×20，触发标记组对应的第一个码块与锚点码块距离是10240。10240+1000是20的整数倍(452倍)。每条PCS通道中发送的比特流，符号为66bit，所以触发标记组中的每个触发标记都会发送至期望的逻辑通道上。
根据以太网接口的分发规则，触发标记被分发至逻辑通道。第一设备向第二设备发送比特流。触发标记发送至第二设备。
在步骤S904，第二设备的计数即将到M时，接收触发标记。
若第一设备插入对应于1～10#逻辑通道的触发标记组，第二设备在对应的1～10#逻辑通道检测每个通道对应的触发标记，或者，参见如图10d，第二设备在1～10#逻辑通道锁定重排序形成串行流之后检测触发标记组。图10d中，用阴影表示触发标记在逻辑通道中对应的符号，以及触发标记在串行的比特流中对应的码块。在串行的比特流中，第二设备去除触发标记，完成触发标记的提取。
若第一设备插入对应于1～20#逻辑通道的触发标记组，第二设备在1～20#逻辑通道检测每个通道对应的触发标记，或在逻辑通道锁定重排序形成串行流之后检测触发标记组。之后，第二设备的接收器不再从11～20#逻辑通道接收任何符号。接收器可以认为是第二设备中接收各逻辑通道的比特码块或符号并对其进行排序的装置。
可以认为，第二设备从逻辑通道接收触发标记之后，11～20#逻辑通道上已经没有有用信息，而可能是第一设备插入的伪随机二进制序列(pseudo-random binary sequence，PRBS)或其他干扰。第二设备切换到新的工作模式。也就是说，接收触发标记之后，第二设备只从1#～10#逻辑通道接收符号。触发标记是第二设备的接收器按照新老模式工作的分界点，是新模式的起点。
参见图10d，在T 3a时，第二设备PCS子层可以接收触发标记。在T 3a时，逻辑通道已完成锁定，第二设备PCS子层可以在串行的比特流中检测并去除触发标记组。
或者，在T 3a时，第二设备PCS子层可以在多个逻辑通道接收并检测对应于该逻辑通道的触发标记。检测触发标记可以理解为对触发标记的识别。T 3b时，逻辑通道进行重排序形成串行的比特流时，串行的比特流中包括触发标记，去除触发标记。
在100G以太网链路，第一设备发送锚点码块，通知第二设备在10240码块之后，11～20#逻辑通道立即退出第一设备与第二设备之间的数据传输。当第一设备计数至10240，第一设备插入对应于1-10#逻辑通道的触发标记组，并停止在11-20#逻辑通道上发送数据。触发标记组中的触发标记用于引导第二设备完成降速切换。
通过上述方案，可以基于PCS子层的码块，完成第一设备和第二设备的同步切换，从高速模式切换至低速模式，第二设备无码块或比特错误，不需要设置缓存或包重排序模块，简洁高效。
也可以通过将某一次通过每条FECL发送的AM作为一个触发标记。通过第一设备发送锚点码块、触发标记，第二设备接收锚点码块、触发标记，完成物理层的切换。
表1是IEEE802.3中100G以太网PCSL的AM规范。100G以太网接口包括20条PCSL。AM中，比特交织奇偶校验(bit interleaved parity，BIP)字节用于误码校验，M字节(M 1-M 6)用于标识逻辑通道和逻辑通道对齐。
表1
Figure PCTCN2020092211-appb-000001
表2是IEEE802.3中100G以太网FECL的AM规范。100G以太网接口包括4条FECL。其中，amp_tx_i表示编号为i的PCSL对应的AM。也就是说，一条FECL对应于多个PCSL。 经过该多个PCSL传输的符号，通过该FECL传输。编号为1的FECL对应的多条PCSL的编号分别为0，4，8，12，16。
表2
Figure PCTCN2020092211-appb-000002
对于40G和100G以太网接口进行FEC的情况，PCSL与FECL具有对应关系，即每条FECL对应于多个PCSL。逻辑通道退出或开始运行，是指FECL以及该FECL对应的多个PCSL退出或开始运行。
例如，100G以太网接口，0#、4#、8#、16#PCSL对应于0#FECL。0#、4#、8#、16#PCSL的AM对应于0#FECL的AM。0#、4#、8#、16#PCSL对应于0#FECL。0#、4#、8#、16#PCSL的触发标记对应于0#FECL的触发标记。
图11是本申请实施例提供的一种以太网传输数据方法的示意性流程图。逻辑通道为PCSL。
400G以太网接口规范16条PCSL/FECL逻辑通道，采用8×50Gbps物理通道电互联。每条物理通道对应于2个逻辑通道。FEC方案采用RS(544,514)。当链路流量远小于200G时，网管下发指令，要求链路旁路9～16#逻辑通道。逻辑通道与物理通道的对应关系参考图8。1-2#逻辑通道对应于1#物理通道，3-4#逻辑通道对应于2#物理通道，其他逻辑通道与物理通道的对应关系以此类推。逻辑通道编号1～16#，此次要求旁路9～16#，即9～16#逻辑通道退出运行，对应的物理通道是5～8#。
可以复用AM组作为触发标记组。
在步骤S1001，第一设备插入锚点码块。
参见如图12a，第一设备通过16个逻辑通道发送比特流。第一设备插入用于通道对齐的AM组时，插入对应于16条逻辑通道的AM组。根据IEEE 802.3，第二设备插入16个AM对应的8个257B码块，即第二设备插入大小为8个257B码块的AM组，该AM组包括16个AM。AM组如图12a中串行比特流的阴影部分所示。AM组中的每个AM能够发送至对应的一个逻辑通道。图12a中PCS/FEC通道的阴影部分，表示发送到16条逻辑通道的AM对应的符号。
第一设备发送锚点码块。第一设备在PCS层串行的比特流中插入锚点码块。通过锚点码块引导第一设备和第二设备进行物理层工作模式的切换，与以太网中现有的比特流传输方式兼容，不需要为实现切换增加硬件结构，能够减小对系统的影响。
第一设备可以在66B码块流中插入锚点码块，锚点码块为66B码块。或者，第一设备可以在257B码块流中插入锚点码块，锚点码块为257B码块。插入较小的66B锚点码块，传输锚点码块占用的资源较少，可以减小系统开销。
66B锚点码块的格式可以参考图8。切换类型为降速，锚点码块携带的切换类型信息可以是“0x2”。锚点码块的D字段可以是“0x2”。另外，锚点码块的A字段可以是“01”，C字段可以是“0x6”，锚点码块可以不设置B，即触发标记组与该锚点码块间隔的码块 的数量不进行标识，也就是说不标识触发标记组在比特流中的位置。此时，触发标记组在比特流中的位置可以由网管配置。例如，根据网管配置，触发标记组与该锚点码块之间包括10次插入的AM组，也就是说，在发送锚点码块之后的第11次插入的AM作为触发标记组。根据以太网接口的分发规则，锚点码块被分发至多个逻辑通道。
在步骤S1002，第二设备接收锚点码块。
第二设备对比特流进行监测，接收并去除锚点码块。第二设备可以在从逻辑通道接收并检测锚点码块，也可以在对通道锁定和重排序之后接收的比特流形成串行的比特流之后检测锚点码块。检测到锚点码块之后，第二设备可以去除锚点码块。
检测到锚点码块之后，第二设备启动计数。根据第二设备的计数，第二设备能够确定第一设备发送的触发标记的位置。
第二设备可以向第一设备发送回应码块。第二设备可以通过第二设备的发送逻辑通道向第一设备发送回应码块。第二设备的发送逻辑通道用于向第一设备发送比特流。
第一设备在第11次AM插入之前，仍未接收到回应码块，则取消物理层工作模式的切换，即不再进行步骤S1003-S1004。
第一设备在第11次AM插入之前，接收回应码块，则进行步骤S1003。
在步骤S1003，第一设备插入触发标记。触发标记可以是AM。
第一设备计数至第10次AM插入，即自发送锚点码块后已经发送了10次AM，准备第11次插入AM。
参见图12b，在T 2a时，当到达AM插入的周期，第一设备立即按照新模式插入对应1～8#逻辑通道的8个AM。如图12b串行比特流中的阴影所示，根据IEEE 802.3，8个AM对应于4个257B码块。在T 2b时，对插入的AM进行分发。按照新模式，即切换后的模式即对AM进行分发。在T 2c时，如图中阴影所示，PCS/FEC通道的每个AM分发至对应的1～8#逻辑通道。分发器从进行第11次AM分发开始，不再通过9～16#逻辑通道发送比特流。触发标记组的发送是第一设备的分发器按照新老模式工作的分界点，也是新模式的起点。
在步骤S1004，第二设备接收触发标记。
第二设备计数至第10个接收AM的周期，即自接收锚点码块后已经接收了10次AM，准备第11次的AM接收。参见图12c，第二设备的接收器从1～8#逻辑通道接收第11轮AM。自接收第11次的AM，即接收触发标记开始，接收器只从1～8#逻辑通道接收码块，不再从9～16#接收码块，切换到新的工作模式。触发标记组的接收是第二设备的接收器按照新老模式工作的分界点，是新的工作模式的起点。
之后，第二设备可以去除触发标记。
在400G以太网链路，网管配置触发标记组与锚点码块在比特流中的相对位置，通过锚点码块以及对应位置的触发标记组的发送和接收，逻辑通道退出运行。通过锚点码块和触发标记组的引导，完成降速的切换，避免误码。
在另一种可能的方式中，触发标记组的发送也可以通过与锚点码块相同的逻辑通道。也就是说，在触发标记组发送之后，立即进行减少通道数量的切换。
在步骤S1003，当第一设备计数到AM插入的周期，第一设备依然按照之前模式，插入对应1～16#逻辑通道的16个AM。分发器将该16个AM分发至对应的1～16#逻辑通道。分发器在完成第11次9～16#逻辑通道的AM分发后，即不再通过9～16#逻辑通道发送比特 流，9～16#逻辑通道退出运行。
对应的，在步骤S1004，当第二设备计数到第11个接收AM的周期，第二设备依然按照之前模式，接收16个AM，即对应1～16#逻辑通道的16个AM，该16个AM作为触发标记组。接收器接收触发标记组之后，不再从9～16#逻辑通道接收比特流，9～16#逻辑通道退出运行。
通过锚点码块的发送和接收，确定触发标记在比特流中的位置。通过触发标记引导第一设备和第二设备的部分逻辑通道退出，能够实现降速切换，避免误码。
通过上述步骤，基于物理层的触发标记，完成第一设备和第二设备工作模式的切换，从高速模式切换至低速模式。对于比特流中的同一符号，第二设备于第一设备进行了相对应的处理，无码块或比特错误。不需要设置缓存或包重排序模块，对系统的影响小。触发标记复用AM，减少发送触发标记组占用的比特数量，实现代价更小，简洁高效。
发送至每个逻辑通道的触发标记可以为某一次通过该逻辑通道发送的AM。每个PCSL中发送的AM唯一标识该PCSL，即每个AM唯一标识对应的PCSL，通过对应的PCSL发送。表3是IEEE802.3中400G以太网的AM规范。其中，CM 0,CM 1,CM 2,CM 3,CM 4,CM 5是逻辑通道的共同标识，而UM 0,UM 1,UM 2,UM 3,UM 4,UM 5唯一标识一个逻辑通道。
表3
Figure PCTCN2020092211-appb-000003
图13是本申请实施例提供的一种以太网数据传输方法的示意性流程图。逻辑通道为PCSL。
400G以太网接口，采用8×50Gbps物理通道电互联。每条物理通道对应于2个逻辑通道，即共采用16个逻辑通道。FEC方案采用RS(544,514)方式。网管下发指令，要求由1～8#逻辑通道运行，切换到1～16#逻辑通道运行，即退出运行的9～16#逻辑通道恢复运行。逻辑通道与物理通道的对应关系参考图8。1-2#逻辑通道对应于1#物理通道，3-4#逻辑通 道对应于2#物理通道，其他逻辑通道与物理通道的对应关系以此类推。
在步骤S1101，第一设备插入锚点码块。
参见图14a，第一设备通过8个逻辑通道发送比特流。第一设备插入用于逻辑通道对齐的AM时，插入对应于该8条通道的8个AM。8个AM中的每个AM能够发送至对应的一个逻辑通道。
第一设备发送锚点码块。第一设备在PCS层串行的比特流中插入锚点码块。也就是说，第一设备在发送的比特流中携带有锚点码块中的信息。锚点码块的格式可以参考图6。锚点码块可以设置B字节，例如，B字节的信息表示M＝8，即该锚点码块与触发标记组之间发送了8轮AM组，也就是说，在发送锚点码块之后的第9轮插入的每个AM作为一个触发标记。切换类型为加速，锚点码块可以设置D，锚点码块携带的切换类型信息可以是“0x1”，即加速切换。
在步骤S1102，第二设备接收锚点码块。
第二设备对比特流进行监测，在接收的比特流中检测锚点码块。第二设备可以对各个逻辑通道锁定和重排序，接收的符号形成串行的比特流之后检测锚点码块。
检测到锚点码块之后，第二设备启动计数。根据第二设备的统计，第二设备能够确定第一设备发送的触发标记组的位置。
之后，第二设备可以去除锚点码块。
在步骤S1103，第一设备插入触发标记。
第一设备计数到M，等待下一轮插入AM组的周期，即自发送锚点码块后已经发送了8轮AM，准备第9轮插入AM。
参见图14b，在T 2a时，到达第9轮AM组插入的周期，第一设备立即按照新模式插入16个AM对应的AM组，16为新模式下工作的逻辑通道数，即AM组对应1～16#逻辑通道。在T 2b时，对16个AM进行分发。此时，第二设备采用新模式分发符号，将比特流分发至16条逻辑通道。在T 2c时，每个AM分发至对应的1～16#逻辑通道。分发器在进行第9轮AM的分发时，9-16#逻辑通道恢复运行，比特流通过1～16#逻辑通道发送。触发标记组的发送是第一设备分发器按照新老模式工作的分界点，也就是新模式的起点。
在步骤S1104，第二设备接收触发标记。
第二设备计数到M，等待下一周期的AM接收，即自接收锚点码块后已经接收了8轮AM，准备第9轮的AM接收。参见图14c，T 3a时，16个AM分别通过16个逻辑通道传输。参见图14d，T 3b时，接收器监测并从1～16#逻辑通道分别接收第9轮的AM。自接收第9次的AM，即接收触发标记组开始，接收器从1～16#逻辑通道接收比特流，切换到新的工作模式。触发标记组的接收是第二设备的接收器按照新老模式工作的分界点，即新模式的起点。
通过在400G链路第一设备发送锚点码块，与第二设备约定在发送完8轮AM码字之后，在发送第9轮AM时，9～16#逻辑通道恢复运行，通过1～16#逻辑通道发送比特流。当第一设备插入第9轮AM组，通过第9轮插入的16个AM引导第一设备和第二设备完成加速切换。
之后，第二设备可以去除触发标记。
通过锚点码块的传输，能够确定触发标记组在比特流中的位置。通过触发标记组的传输，对于比特流中的同一符号，第二设备于第一设备进行了相对应的处理，无码块或比特 错误。从低速模式切换至高速模式等物理层工作模式的切换，不需要设置缓存或包重排序模块，对系统的影响小。触发标记组中对应于每个逻辑通道触发标记可以复用对应于该逻辑通道中的AM，减少发送触发标记组占用的比特数量，实现工作模式的切换占用的系统资源少，简洁高效。不需要设置缓存或包重排序模块，对系统的影响小。
图15是本申请实施例提供的一种以太网数据传输方法的示意性流程图。
为了方便说明切换的过程，本申请实施例通过不同的方框或线条表示不同的FEC编解码方式，或不进行FEC编码的情况。应当理解，不同的FEC编码方式可以由相同或不同的物理器件实现。
在切换之前，第一设备向第二设备发送第一比特流。
第一比特流是通过第一FEC编码方式得到的。则第二设备接收第一比特流，对第一比特流进行第一FEC解码。
或者，第一比特流未经过FEC编码。则第二设备接收第一比特流，对第一比特流无需进行FEC解码。
在切换之后，第二设备向第二设备发送第二比特流。
第二比特流是通过第二FEC编码方式得到的。则第二设备接收第二比特流，对第二比特流进行第一FEC解码。
或者，第二比特流未通过FEC编码。则第二设备接收第二比特流，对第二比特流无需进行FEC解码。
对于第一比特流和第二比特流，至少一个经过FEC编码。
以100G以太网接口，对降低延时切换的处理流程进行说明。逻辑通道为FECL。示例性地，切换前，第一设备进行第一FEC编码以得到比特流。切换后，第一设备不进行FEC编码。第一FEC编码方式例如可以是RS(544,514)等。
100G以太网接口，FEC编码方式由RS(544,514)切换至不进行FEC编码。
第一设备进行第一FEC编码，通过4条FECL发送比特流。第一设备插入用于FECL对齐的AM组。AM组中的每个AM能够发送至对应的一条FECL。触发标记组中，对应于触发标记可以是AM。
在步骤S1301，第一设备插入锚点码块。
参见图16a，第一设备在对比特流进行FEC编码之前，在串行的比特流中插入锚点码块。锚点码块即图16a中阴影所示的码块。第一设备在比特流中插入锚点码块。锚点码块的格式可以参考图8。锚点码块可以设置B字节，例如，B字节的信息表示M＝8，即触发标记组与该锚点码块的间隔为8轮AM组，也就是说，在发送锚点码块之后第9轮插入的多个AM为触发标记组。切换类型为加速，锚点码块可以设置D，锚点码块携带的切换类型信息可以是“0x8”，即降低延时切换。
在步骤S1302，第二设备接收锚点码块。
第二设备接收比特流，对比特流进行第一FEC解码。第一FEC解码是对应于第一FEC编码的解码方式。
第二设备对比特流进行监测，检测锚点码块。第二设备可以在对多通道锁定重排序，接收的比特流形成串行的比特流之后，在串行的比特流中检测锚点码块，也可以在FECL中获取锚点码块。
接收锚点码块后，或者检测到锚点码块之后，第二设备启动计数。根据第二设备的统 计，第二设备能够确定第一设备发送的触发标记组的位置。
第二设备可以去除锚点码块。
在步骤S1303，第一设备插入触发标记。
参见图16b，第一设备计数到M，等待下一轮插入AM组的周期，即自发送锚点码块后已经发送了8次AM组，准备第9轮插入AM。第9轮插入的多个AM即为触发标记组。触发标记对应于图16b中阴影所示的码块。
到达触发标记组插入的周期，第一设备插入触发标记组。从比特流中的触发标记组开始，第一设备不再进行第一FEC编码。也就是说，对于此次插入的AM组以及后续的比特流，不再进行第一FEC编码。即，将该AM组对应的66B码块，转码为257B码块后，对应的第一个符号直接分发至4条FEC通道。触发标记组的发送是第一设备分发器按照新老模式工作的分界点，也就是新模式的起点。在触发标记之前发送的比特流可以称为第一比特流，在触发标记之后发送的比特流可以称为第二比特流。
在步骤S1304，第二设备接收触发标记。
参见图16c，第二设备计数到M，等待下一周期的AM组接收，即自接收锚点码块后已经接收了8轮AM组，准备第9轮的AM接收。第9轮插入的多个AM即为触发标记组。触发标记对应于图16b中阴影所示的码块。
自接收第9轮的AM起，切换到新的工作模式。也就是说，对于该轮AM对应的符号以及之后接收的符号，形成257B码块后，转码为66B码块发送。即不再进行第一FEC解码。触发标记组的接收是第二设备的接收器按照新老模式工作的分界点，即新模式的起点。
通过在100G链路第一设备发送锚点码块，与第二设备约定在发送完8轮AM码字之后，在发送第9轮AM时，进行降低延时的切换。当第一设备插入第9轮AM，通过插入的AM引导第一设备和第二设备完成降低延时的切换。
之后，第二设备可以去除触发标记。
通过锚点码块的传输，能够确定触发标记组在比特流中的位置。通过触发标记组的传输，对于比特流中的同一符号，第二设备于第一设备进行了相对应的处理，无码块或比特错误。从高延时模式切换至低延时模式等物理层工作模式的切换，不需要设置缓存或包重排序模块，对系统的影响小。触发标记复用AM，减少发送触发标记组占用的比特数量，实现工作模式的切换展通的系统资源少，简洁高效。不需要设置缓存或包重排序模块，对系统的影响小。
应当理解，传输延时的切换，即物理层工作模式切换前后，由于进行不同的FEC编解码或不进行FEC编解码导致的传输延时不同，也可以理解为切换前后纠错能力不同，即纠错能力的切换。
在另一些实施例中，可以在触发标记组之后，完成不同延时的工作模式的切换。也就是说，对于第一设备，触发标记组仍采用第一FEC编码方式进行编码。第一触发标记组进行第一FEC编码后，不再对触发标记组之后的比特流进行第一FEC编码。对应地，第二设备在接收并检测触发标记组后，对触发标记组进行第一FEC解码。对于触发标记组之后的比特流，不再进行FEC解码。
通过类似的方式，第一设备和第二设备的工作模式也可以由低延时切换为高延时。例如，在步骤S1303之前，第一设备不进行FEC编码。在步骤S1303，第一设备发送触发标记组，对触发标记组以及之后的比特流进行第一FEC编码。在步骤S1304，第二设备检测 触发标记组对应的触发标记，对触发标记组以及之后的比特流进行第一FEC解码。
图17是一种以太网数据传输的方法的示意性流程图，主要描述物理层的相关处理过程。
参照图3，在插入AM后，257B码块流按照10比特的符号分发到多路通道进行FEC编码以及符号分发。一路独立进行FEC编码(一个或多个编码器)和符号分发的通道也可以称为一条逻辑通道。
第一设备将码块流分发至多个逻辑通道后，每个逻辑通道独立对比特流进行FEC编码，并独立进行分发和交织。每个逻辑通道可以对应于多路FEC编解码，该多路FEC编解码的方式相同。对于第一设备，每个逻辑通道在多路FEC编码后，独立进行符号的分发。对于第二设备，每个逻辑通道独立进行符号的接收后，进行多路FEC解码。
每个独立进行FEC编解码和符号分发、接收的通道可以理解为一个逻辑通道。也就是说，第一设备将码块流分发至多个逻辑通道。每个逻辑通道的FEC方式可以相同或不同。
第一设备中，每个逻辑通道，即每路独立进行FEC编码和符号分发的通道，对应于多个PCSL。也就是说，每路进行FEC编码的通道中的符号分发至与该通道对应的多个PCSL。PCSL上的符号通过PMA子层和PMD子层发送至第二设备。
第二设备作为接收端通过PMD和PMA接收第一设备发送的符号。每路独立进行FEC编码和符号接收的逻辑通道，接收端利用该通道对应的多个PCSL上的AM进行通道锁定，消除抖动。可以基于所有逻辑通道对应的所有PCSL上的AM实施锁定和消除抖动。应当理解，可以将所有PCSL进行对齐，或者，可以将一个或多个逻辑通道对应的所有PCSL对齐。对通过该通道对应的多个PCSL通道进行重排序和FEC解码。在FEC解码后，第二设备PCS子层对多个逻辑通道上的符号进行解交织(交织之前根据需要对各逻辑通道进行重排序)，形成串行的码块流，并进行后续的处理流程。
上述方法适用于200G和400G等高速以太网接口。当每个逻辑通道采用IEEE802.3规范100G的1个FEC编解码器，可以理解，对于200G以太网，每个逻辑通道对应于一个100G的FEC独立编解码和分发符号路径，200G接口包括2个这样的逻辑通道。可以理解，当每个逻辑通道采用IEEE802.3规范的200G的2路FEC编解码和分发路径，对于400G以太网接口包含2个这样的逻辑通道。具体在应用中可以增加其他的处理过程，或者减少上述部分处理过程。
图18是本申请实施例提供的一种以太网传输数据方法的示意性流程图。
以太网接口对应4条分别独立进行FEC编码和符号分发的通道。每条进行FEC编码的通道中的符号分发至多条PCSL/FECL后，通过PMA分发至一条或多条物理通道。也就是说，一条进行FEC编码和符号分发的通道对应于一条或多条物理通道。
第一设备和第二设备可以仅仅增加或减少运行的PCSL/FECL数量。第一设备和第二设备也可以对运行的独立进行FEC编码和符号分发的通道增加或减少，进一步降低系统功耗。
用逻辑通道表示独立进行FEC编码和分发的通道。1#逻辑通道对应于和1-2#物理通道，2#逻辑通道对应于3-4#物理通道，其他逻辑通道与物理通道的对应关系以此类推。
由于每个逻辑通道独立进行FEC编码和分发，可以对每个逻辑通道对应的PCSL/FECL分别编号。也就是说1#逻辑通道对应的1-4#PCSL/FECL，对应于1-2#物理通 道；2#逻辑通道对应的1-4#PCSL/FECL，对应于3-4#物理通道。或者，也可以对传输257B串行码块流的逻辑通道对应的PCSL/FECL同一进行编码。
第一设备中的分发器用于执行图17中的FEC符号分发。第二设备中的接收器用于执行图17中的解交织。
网管可以下发逻辑通道指示信息，指示部分逻辑通道退出运行。例如，网管指示3-4#逻辑通道退出运行。
图19是本申请实施例提供的一种以太网传输数据方法的示意性流程图。本实施例中，逻辑通道是指独立进行FEC编码和符号分发的通道。
在步骤S1801，第一设备插入锚点码块。
参见图20a，第一设备通过1#和2#这2个逻辑通道发送比特流。PCSL/FECL统一编码。2个逻辑通道中的符号分发至16条PCSL。第一设备插入用于通道对齐的AM组时，插入对应于16条PCSL的AM组。AM组中的每个AM通过与其对应的逻辑通道，能够发送至对应的一个PCSL。
在步骤S1802，第二设备接收锚点码块。
接收锚点码块之后，也可以在检测或去除锚点码块之后，第二设备启动计数。根据第二设备的计数，第二设备能够确定第一设备发送的触发标记组的位置。
在步骤S1803，第一设备插入触发标记。触发标记可以对应于1#逻辑通道。以触发标记可以是复用AM为例，1#逻辑通道的触发标记对应于1-8#PCSL的AM，2#逻辑通道的触发标记对应于9-16#PCSL的AM。
参见图20b，在T 2a时，当到达AM插入的周期，第一设备立即按照新模式插入对应1～8#PCSL的8个AM。在T 2b时，对插入的AM进行分发。AM分发至1#逻辑通道。在T 2c时，每个AM分发至对应的1～8#PCSL。
在步骤S1803之后，第一设备不再通过2#逻辑通道以及9～16#PCSL发送比特流。
在步骤S1804，第二设备接收触发标记。
参见图20c，第二设备计数至作为触发标记的AM接收的周期，通过1～8#PCSL以及对应的1#逻辑通道接收触发标记。
第二设备可以去除触发标记。
之后，第二设备通过1～8#PCSL以及对应的1#逻辑通道接收比特流，不再通过2#逻辑通道以及9～16#PCSL发送比特流。
图21是本申请实施例提供的一种通信方法的示意性流程图。
锚点信息可以是锚点包。
在步骤S2101，第一设备插入锚点包。
第一设备MAC层接收数据包。
第一设备的MAC层在串行的比特流中插入锚点包。锚点包的格式可以参见图22的说明。锚点包可以用于指示触发标记组在比特流中的位置。
优选地，锚点包可以包括切换方式指示信息。切换方式指示信息用于指示工作模式的切换方式。工作模式的切换方式包括传输速率的切换和/或传输延时的切换。进行传输速率的切换，切换前后，通过不同的逻辑通道的数量进行比特流的发送。进行传输延时的切换，切换前后，采用不同的FEC编码方式(包括不进行FEC编码)得到比特流。
在步骤S2102，第一设备向第二设备发送锚点包。根据以太网接口的分发规则，锚点 包被分发至逻辑通道。
第一设备向第二设备发送比特流。比特流中包括锚点包。锚点包用于指示触发标记组在比特流中的位置。
在步骤S2103，第一设备按照锚点包指示的触发标记组的位置在比特流中插入触发标记组。
在步骤S2104，第一设备发送触发标记组。应当理解，触发标记组在锚点包之后发送。
第一设备在开始发送触发标记组时，或者完成触发标记组的发送时，进行工作模式的切换。
第二设备接收比特流。比特流包括锚点包和触发标记组。第二设备的MAC接收锚点包后，根据锚点包指示的触发标记组在比特流中的位置，在开始接收触发标记组时，或者完成触发标记组的接收时，进行工作模式的切换。
应当理解，第二设备工作模式的切换时间与第一设备工作模式的切换时间相对应。当第一设备工作模式的切换发生在开始发送触发标记组时，第二设备在开始接收触发标记组时进行工作模式的切换。
第二设备在接收锚点包之后，可以在比特流中去除锚点包。
第二设备在接收触发标记组之后，可以在比特流中去除触发标记组。
通过步骤S2101至步骤S2104，可以基于MAC层的锚点包，完成第一设备和第二设备工作模式的同步切换，不需要设置缓存或包重排序模块，简洁高效。
当锚点包可以包括切换方式指示信息、锚点包标识、触发指示信息等中的一种或多种。切换方式指示信息用于指示切换的方式。切换的方式包括传输速率的切换和/或传输延时的切换。锚点包标识用于表示该包为锚点包。触发指示信息用于指示触发标记组的在比特流中的位置。
触发标记组的在比特流中的位置等信息也可以根据协议确定。触发标记组可以是AM组，也可以是其他标记组。
图22是本申请实施例提供的一种锚点包的示意图。
锚点包可以包括7字节(byte)的前导符(preamble)、1字节的帧首定界符(start frame delimiter，SFD)、8字节的消息域(MSG_filed)、52字节的填充域(padding)、4字节的帧校验序列(frame check sequence，FCS)等。
前导符的取值可以是0x55。
SFD可以作为锚点包标识，用于指示该包为锚点包。SFD的取值可以是0xD4。
消息域可以包括切换方式指示信息。例如，0x0000000000000001可以表示加速，0x0000000000000002可以表示减速。
上文结合图1至图22的描述了本申请实施例的方法实施例，下面结合图23至图26，描述本申请实施例的装置实施例。应理解，方法实施例的描述与装置实施例的描述相互对应，因此，未详细描述的部分可以参见前面方法实施例。
图23是本身请实施例提供的一种通信设备的示意性结构图。通信设备1400用于以太网数据的传输。
通信设备1400包括生成模块1410、收发模块1420。
收发模块1420用于向第二设备发送第一比特流，所述第一比特流是通过所述通信设备的物理层的N个逻辑通道发送的。
生成模块1410用于生成第一触发标记组。
收发模块1420还用于，向所述第二设备发送第一触发标记组，所述第一触发标记组用于指示所述第一比特流结束发送。
响应于所述第一触发标记组的发送，收发模块1420还用于，向所述第二设备发送第二比特流，所述第二比特流是通过所述通信设备的物理层的P个逻辑通道发送的，N、P均为正整数。
可选地，所述第一触发标记组包括P个触发标记；
可选地，收发模块1420用于通过所述P个逻辑通道中的第i个逻辑通道发送所述P个触发标记中的第i个触发标记，i为正整数。
可选地，所述第i个触发标记包括用于标识所述第i个逻辑通道的信息。
可选地，所述第一比特流通过第一前向纠错FEC编码方式进行编码得到；所述第二比特流通过第二FEC编码方式进行编码得到，所述第二FEC编码方式与所述第一FEC编码方式的纠错能力不同。
可选地，所述第一比特流、所述第二比特流中一个通过前向纠错FEC编码得到。
可选地，所述第一比特流包括锚点码块，所述锚点码块用于指示所述第一比特流结束发送的时间。
可选地，所述第一触发标记组是对齐标记AM组。
可选地，收发模块1420还用于接收所述第二设备发送的对应于所述锚点码块的回应码块；根据所述回应码块，收发模块1420用于向所述第二设备发送所述第一触发标记组。
图24是本身请实施例提供的一种通信设备的示意性结构图。通信设备1500用于以太网数据的传输。
通信设备1500包括收发模块1510，处理模块1520。
收发模块1510用于，接收第一设备发送的第一比特流，所述第一比特流是通过所述通信设备的物理层的N个逻辑通道接收的。
收发模块1510还用于，接收所述第一设备发送的第一触发标记组，所述第一触发标记组用于指示所述第一比特流结束。
响应于所述第一触发标记组的接收，收发模块1510还用于，接收所述第一设备发送的第二比特流，所述第二比特流是通过所述通信设备的物理层的P个逻辑通道接收的，N、P均为正整数。
处理模块1520用于对所述第一比特流、所述第二比特流进行处理。
可选地，所述第一触发标记组包括P个触发标记。
收发模块1510用于，通过所述P个逻辑通道中的第i个逻辑通道接收所述P个触发标记中的第i个触发标记，i为正整数。
可选地，所述第i个触发标记包括用于标识所述第i个逻辑通道的信息。
可选地，所述第一比特流通过第一前向纠错FEC编码方式进行编码得到；所述第二比特流通过第二FEC编码方式进行编码得到，所述第二FEC编码方式与所述第一FEC编码方式的纠错能力不同。
处理模块1520用于：通过所述第一FEC编码方式对应的第一FEC解码方式，对所述第一比特流进行解码；通过所述第二FEC编码方式对应的第二FEC解码方式，对所述第二比特流进行解码。
可选地，所述第一比特流、所述第二比特流中一个是通过前向纠错FEC编码得到的。
处理模块1520用于对通过前向纠错FEC编码得到的比特流进行FEC解码。
可选地，所述第一比特流包括锚点码块，所述锚点码块用于指示所述第一比特流结束的时间。
可选地，所述第一触发标记组是对齐标记AM组。
可选地，收发模块1510还用于，向所述第一设备发送对应于所述锚点码块的回应码块，所述锚点码块用于指示所述第一触发标记组的发送。
图25是本申请实施例提供的一种通信设备的示意性结构图。通信设备1600包括通信接口1610。
通信接口1610用于向第二设备发送第一比特流，所述第一比特流是通过通信接口1610的物理层的N个逻辑通道发送的；
通信接口1610还用于，向所述第二设备发送第一触发标记组，所述第一触发标记组用于指示所述第一比特流结束发送；
响应于所述第一触发标记组的发送，通信接口1610还用于，向所述第二设备发送第二比特流，所述第二比特流是通过通信接口1610的物理层的P个逻辑通道发送的，N、P均为正整数。
可选地，通信设备1600包括处理器，用于生成第一触发标记组。
可选地，所述第一触发标记组包括P个触发标记；
可选地，通信接口1610用于通过所述P个逻辑通道中的第i个逻辑通道发送所述P个触发标记中的第i个触发标记，i为正整数。
可选地，所述第i个触发标记包括用于标识所述第i个逻辑通道的信息。
可选地，所述第一比特流通过第一前向纠错FEC编码方式进行编码得到；所述第二比特流通过第二FEC编码方式进行编码得到，所述第二FEC编码方式与所述第一FEC编码方式的纠错能力不同。
可选地，所述第一比特流、所述第二比特流中一个通过前向纠错FEC编码得到。
可选地，所述第一比特流包括锚点码块，所述锚点码块用于指示所述第一比特流结束发送的时间。
可选地，所述第一触发标记组是对齐标记AM组。
可选地，通信接口1610还用于接收所述第二设备发送的对应于所述锚点码块的回应码块；根据所述回应码块，通信接口1610用于向所述第二设备发送所述第一触发标记组。
图26是本申请实施例提供的一种通信设备的示意性结构图。通信设备1700包括通信接口1710。
通信接口1710用于，接收第一设备发送的第一比特流，所述第一比特流是通过通信接口1710的物理层的N个逻辑通道接收的。
通信接口1710还用于，接收所述第一设备发送的第一触发标记组，所述第一触发标记组用于指示所述第一比特流结束。
响应于所述第一触发标记组的接收，通信接口1710还用于，接收所述第一设备发送的第二比特流，所述第二比特流是通过通信接口1710的物理层的P个逻辑通道接收的，N、P均为正整数。
可选地，通信设备1700包括处理器，用于对所述第一比特流、所述第二比特流进行 处理。
可选地，所述第一触发标记组包括P个触发标记。
通信接口1710用于，通过所述P个逻辑通道中的第i个逻辑通道接收所述P个触发标记中的第i个触发标记，i为正整数。
可选地，所述第i个触发标记包括用于标识所述第i个逻辑通道的信息。
可选地，所述第一比特流通过第一前向纠错FEC编码方式进行编码得到；所述第二比特流通过第二FEC编码方式进行编码得到，所述第二FEC编码方式与所述第一FEC编码方式的纠错能力不同。
通信设备1700还包括处理器，处理器用于：通过所述第一FEC编码方式对应的第一FEC解码方式，对所述第一比特流进行解码；通过所述第二FEC编码方式对应的第二FEC解码方式，对所述第二比特流进行解码。
可选地，所述第一比特流、所述第二比特流中一个是通过前向纠错FEC编码得到的。
通信设备1700还包括处理器，处理器用于对通过前向纠错FEC编码得到的比特流进行FEC解码。
可选地，所述第一比特流包括锚点码块，所述锚点码块用于指示所述第一比特流结束的时间。
可选地，所述第一触发标记组是对齐标记AM组。
可选地，通信接口1710还用于，向所述第一设备发送对应于所述锚点码块的回应码块，所述锚点码块用于指示所述第一触发标记组的发送。
本申请实施例还提供一种通信系统，其包括一个或多个前述的通信设备。
本申请实施例还提供一种计算机程序存储介质，其特征在于，所述计算机程序存储介质具有程序指令，当所述程序指令被执行时，使得前文中的方法被执行。
本申请实施例还提供一种芯片系统，其特征在于，所述芯片系统包括至少一个处理器，当程序指令在所述至少一个处理器中执行时，使得前文中的方法被执行。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (34)

  1. 一种以太网数据传输的方法，其特征在于，包括：
    第一设备向第二设备发送第一比特流，所述第一比特流是通过所述第一设备的物理层的N个逻辑通道发送的；
    所述第一设备向所述第二设备发送第一触发标记组，所述第一触发标记组用于指示所述第一比特流结束发送；
    响应于所述第一触发标记组的发送，所述第一设备向所述第二设备发送第二比特流，所述第二比特流是通过所述第一设备的物理层的P个逻辑通道发送的，N、P均为正整数。
  2. 根据权利要求1所述的方法，其特征在于，所述第一触发标记组包括P个触发标记；
    所述第一设备向所述第二设备发送第一触发标记组，包括：所述第一设备通过所述P个逻辑通道中的第i个逻辑通道发送所述P个触发标记中的第i个触发标记，i为正整数。
  3. 根据权利要求2所述的方法，其特征在于，所述第i个触发标记包括用于标识所述第i个逻辑通道的信息。
  4. 根据权利要求1-3中任一项所述的方法，其特征在于，所述第一比特流通过第一前向纠错FEC编码方式进行编码得到；所述第二比特流通过第二FEC编码方式进行编码得到，所述第二FEC编码方式与所述第一FEC编码方式的纠错能力不同。
  5. 根据权利要求1-3中任一项所述的方法，其特征在于，所述第一比特流、所述第二比特流中一个通过前向纠错FEC编码得到。
  6. 根据权利要求1-5中任一项所述的方法，其特征在于，所述第一比特流包括锚点码块，所述锚点码块用于指示所述第一比特流结束发送的时间。
  7. 根据权利要求6所述的方法，其特征在于，所述第一触发标记组是对齐标记AM组。
  8. 根据权利要求6或7所述的方法，其特征在于，所述方法还包括：
    接收所述第二设备发送的对应于所述锚点码块的回应码块；
    所述第一设备向所述第二设备发送第一触发标记组，包括：根据所述回应码块，所述第一设备向所述第二设备发送所述第一触发标记组。
  9. 一种以太网数据传输的方法，其特征在于，包括：
    第二设备接收第一设备发送的第一比特流，所述第一比特流是通过所述第二设备的物理层的N个逻辑通道接收的；
    所述第二设备接收所述第一设备发送的第一触发标记组，所述第一触发标记组用于指示所述第一比特流结束；
    响应于所述第一触发标记组的接收，所述第二设备接收所述第一设备发送的第二比特流，所述第二比特流是通过所述第二设备的物理层的P个逻辑通道接收的，N、P均为正整数。
  10. 根据权利要求9所述的方法，其特征在于，所述第一触发标记组包括P个触发标记；
    所述第二设备接收所述第一设备发送的第一触发标记组，包括：所述第二设备通过所 述P个逻辑通道中的第i个逻辑通道接收所述P个触发标记中的第i个触发标记，i为正整数。
  11. 根据权利要求10所述的方法，其特征在于，所述第i个触发标记包括用于标识所述第i个逻辑通道的信息。
  12. 根据权利要求9-11中任一项所述的方法，其特征在于，所述第一比特流通过第一前向纠错FEC编码方式进行编码得到；所述第二比特流通过第二FEC编码方式进行编码得到，所述第二FEC编码方式与所述第一FEC编码方式的纠错能力不同；
    所述方法包括：
    所述第二设备通过所述第一FEC编码方式对应的第一FEC解码方式，对所述第一比特流进行解码；
    所述第二设备通过所述第二FEC编码方式对应的第二FEC解码方式，对所述第二比特流进行解码。
  13. 根据权利要求9-11中任一项所述的方法，其特征在于，所述第一比特流、所述第二比特流中一个是通过前向纠错FEC编码得到的，
    所述方法包括：所述第二设备对通过前向纠错FEC编码得到的比特流进行FEC解码。
  14. 根据权利要求9-13中任一项所述的方法，其特征在于，所述第一比特流包括锚点码块，所述锚点码块用于指示所述第一比特流结束的时间。
  15. 根据权利要求14所述的方法，其特征在于，所述第一触发标记组是对齐标记AM组。
  16. 根据权利要求14或15所述的方法，其特征在于，所述方法还包括：
    所述第二设备向所述第一设备发送对应于所述锚点码块的回应码块，所述锚点码块用于指示所述第一触发标记组的发送。
  17. 一种通信设备，其特征在于，包括：通信接口；所述通信接口用于向第二设备发送第一比特流，所述第一比特流是通过所述通信接口的物理层的N个逻辑通道发送的；
    所述通信接口还用于，向所述第二设备发送第一触发标记组，所述第一触发标记组用于指示所述第一比特流结束发送；
    响应于所述第一触发标记组的发送，所述通信接口还用于，向所述第二设备发送第二比特流，所述第二比特流是通过所述通信接口的物理层的P个逻辑通道发送的，N、P均为正整数。
  18. 根据权利要求17所述的通信设备，其特征在于，所述第一触发标记组包括P个触发标记；
    所述通信接口用于通过所述P个逻辑通道中的第i个逻辑通道发送所述P个触发标记中的第i个触发标记，i为正整数。
  19. 根据权利要求18所述的通信设备，其特征在于，所述第i个触发标记包括用于标识所述第i个逻辑通道的信息。
  20. 根据权利要求17-19中任一项所述的通信设备，其特征在于，所述第一比特流通过第一前向纠错FEC编码方式进行编码得到；所述第二比特流通过第二FEC编码方式进行编码得到，所述第二FEC编码方式与所述第一FEC编码方式的纠错能力不同。
  21. 根据权利要求17-19中任一项所述的通信设备，其特征在于，所述第一比特流、所述第二比特流中一个通过前向纠错FEC编码得到。
  22. 根据权利要求17-21中任一项所述的通信设备，其特征在于，所述第一比特流包括锚点码块，所述锚点码块用于指示所述第一比特流结束发送的时间。
  23. 根据权利要求22所述的通信设备，其特征在于，所述第一触发标记组是对齐标记AM组。
  24. 根据权利要求22或23所述的通信设备，其特征在于，所述通信接口还用于：
    接收所述第二设备发送的对应于所述锚点码块的回应码块；
    根据所述回应码块，向所述第二设备发送所述第一触发标记组。
  25. 一种通信设备，其特征在于，包括：通信接口；
    所述通信接口用于，接收第一设备发送的第一比特流，所述第一比特流是通过所述通信接口的物理层的N个逻辑通道接收的；
    所述通信接口还用于，接收所述第一设备发送的第一触发标记组，所述第一触发标记组用于指示所述第一比特流结束；
    响应于所述第一触发标记组的接收，所述通信接口还用于，接收所述第一设备发送的第二比特流，所述第二比特流是通过所述通信接口的物理层的P个逻辑通道接收的，N、P均为正整数。
  26. 根据权利要求25所述的通信设备，其特征在于，所述第一触发标记组包括P个触发标记；
    所述通信接口用于通过所述P个逻辑通道中的第i个逻辑通道接收所述P个触发标记中的第i个触发标记，i为正整数。
  27. 根据权利要求26所述的通信设备，其特征在于，所述第i个触发标记包括用于标识所述第i个逻辑通道的信息。
  28. 根据权利要求25-27中任一项所述的通信设备，其特征在于，所述第一比特流通过第一前向纠错FEC编码方式进行编码得到；所述第二比特流通过第二FEC编码方式进行编码得到，所述第二FEC编码方式与所述第一FEC编码方式的纠错能力不同；
    所述通信设备包括处理器，所述处理器用于：
    通过所述第一FEC编码方式对应的第一FEC解码方式，对所述第一比特流进行解码；
    通过所述第二FEC编码方式对应的第二FEC解码方式，对所述第二比特流进行解码。
  29. 根据权利要求9-11中任一项所述的通信设备，其特征在于，所述第一比特流、所述第二比特流中一个是通过前向纠错FEC编码得到的，
    所述通信设备包括：处理器，所述处理器用于对通过前向纠错FEC编码得到的比特流进行FEC解码。
  30. 根据权利要求25-29中任一项所述的通信设备，其特征在于，所述第一比特流包括锚点码块，所述锚点码块用于指示所述第一比特流结束的时间。
  31. 根据权利要求30所述的通信设备，其特征在于，所述第一触发标记组是对齐标记AM组。
  32. 根据权利要求30或31所述的通信设备，其特征在于，
    所述通信接口还用于，向所述第一设备发送对应于所述锚点码块的回应码块，所述锚点码块用于指示所述第一触发标记组的发送。
  33. 一种计算机程序存储介质，其特征在于，所述计算机程序存储介质具有程序指令，当所述程序指令被执行时，使得如权利要求1至16中任一项所述的方法被执行。
  34. 一种芯片，其特征在于，所述芯片包括至少一个处理器，当程序指令被所述至少一个处理器中执行时，使得如权利要求1至16中任一项所述的方法被执行。
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