WO2020244350A1 - Substrat matriciel, panneau d'affichage et dispositif d'affichage - Google Patents

Substrat matriciel, panneau d'affichage et dispositif d'affichage Download PDF

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Publication number
WO2020244350A1
WO2020244350A1 PCT/CN2020/088131 CN2020088131W WO2020244350A1 WO 2020244350 A1 WO2020244350 A1 WO 2020244350A1 CN 2020088131 W CN2020088131 W CN 2020088131W WO 2020244350 A1 WO2020244350 A1 WO 2020244350A1
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Prior art keywords
interlayer dielectric
base substrate
groove structure
layer
orthographic projection
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PCT/CN2020/088131
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English (en)
Chinese (zh)
Inventor
田雪雁
李小龙
李良坚
屈财玉
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京东方科技集团股份有限公司
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Publication of WO2020244350A1 publication Critical patent/WO2020244350A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements

Definitions

  • the embodiments of the present disclosure relate to an array substrate, a display panel, and a display device.
  • Flat panel displays (F1at Pane Disp1ay, FPD) have become mainstream products in the display market, and there are more and more types of flat panel displays, such as liquid crystal displays (Liquid Crystal Disp1ay, LCD), organic light emitting diodes (Organic Light Emitting Diode, OLED) Display, plasma display panel (P1asma Disp1ay Pane1, PDP) and field emission display (Field Emission Display, FED), etc.
  • liquid crystal displays Liquid Crystal Disp1ay, LCD
  • organic light emitting diodes Organic Light Emitting Diode, OLED
  • plasma display panel P1asma Disp1ay Pane1, PDP
  • Field emission display Field Emission Display
  • AMOLED Active Matrix OLED
  • matrix OLED display technology is accelerating its entry into the high-end smart phone market with its unique performance advantages in display performance, thinness, flexibility, and foldability.
  • an array substrate including a base substrate and a thin film transistor and an interlayer dielectric structure on the base substrate, the thin film transistor including a gate, an active layer, and a source and drain layer ,
  • the source and drain layer includes a source electrode and a drain electrode.
  • the interlayer dielectric structure is a laminated structure including an organic interlayer dielectric layer and an inorganic interlayer dielectric layer, and the organic interlayer dielectric layer is located on the side of the inorganic interlayer dielectric layer facing the base substrate.
  • the thickness of the organic interlayer dielectric layer is greater than the thickness of the inorganic interlayer dielectric layer.
  • the thickness of the organic interlayer dielectric layer is 2 to 4 times the thickness of the inorganic interlayer dielectric layer.
  • it further includes a gate insulating layer located between the active layer and the gate, the interlayer dielectric structure covers the gate insulating layer; the gate insulating layer has an opening facing the interlayer
  • the first groove structure of the dielectric structure, the organic interlayer dielectric layer fills the first groove structure, the orthographic projection of the first groove structure on the base substrate and the active layer, the The orthographic projection of each of the gate, the source and the drain on the base substrate does not overlap each other.
  • the first groove structure penetrates the gate insulating layer.
  • the array substrate includes a plurality of the first groove structures, wherein the plurality of first groove structures are periodically distributed.
  • the orthographic projection of the first groove structure on the base substrate is a square, a rectangle, or a circle.
  • the orthographic projection of the first groove structure on the base substrate is a ring, and the ring surrounds the orthographic projection of the thin film transistor on the base substrate.
  • the array substrate further includes a buffer layer located between the base substrate and the gate insulating layer, and the buffer layer has an opening facing the gate at a position corresponding to the first groove structure.
  • the second groove structure of the insulating layer, and the organic interlayer dielectric layer fills the second groove structure.
  • the second groove structure penetrates the buffer layer.
  • the base substrate has a third groove structure with an opening facing the gate insulating layer at a position corresponding to the first groove structure, and the organic interlayer dielectric layer fills the third groove structure .
  • the third groove structure does not penetrate the base substrate.
  • the orthographic projection of the second groove structure on the base substrate completely coincides with the orthographic projection of the first groove structure on the base substrate; and the third groove structure is on the base substrate.
  • the orthographic projection of the base substrate completely coincides with the orthographic projection of the first groove structure on the base substrate.
  • the orthographic projection of the third groove structure on the base substrate falls within the orthographic projection of the second groove structure on the base substrate, and the third groove structure is on the substrate.
  • the area of the orthographic projection of the substrate is smaller than the area of the orthographic projection of the second groove structure on the base substrate, and the orthographic projection of the second groove structure on the base substrate falls into the first groove.
  • the structure is within the orthographic projection of the base substrate and the area of the orthographic projection of the second groove structure on the base substrate is smaller than the area of the orthographic projection of the first groove structure on the base substrate .
  • the gate is located on the side of the gate insulating layer away from the base substrate, and the active layer is located on the side of the gate insulating layer facing the base substrate; and
  • the source electrode and the drain electrode are electrically connected to the active layer through via holes penetrating the interlayer dielectric structure and the gate insulating layer, respectively.
  • the active layer is located on the side of the gate insulating layer away from the base substrate, and the gate is located on the side of the gate insulating layer facing the base substrate; and
  • the source electrode and the drain electrode are respectively electrically connected to the active layer through through holes penetrating the interlayer dielectric structure.
  • the array substrate further includes a display electrode, wherein the interlayer dielectric structure covers the thin film transistor, the gate is located on a side of the gate insulating layer away from the base substrate, and the The source layer is located on the side of the gate insulating layer facing the base substrate; and the display electrode is electrically connected to the thin film transistor through a through hole penetrating the interlayer dielectric structure and the gate insulating layer The drain.
  • the array substrate further includes a display electrode, wherein the interlayer dielectric structure covers the thin film transistor, the active layer is located on a side of the gate insulating layer away from the base substrate, and the The gate is located on the side of the gate insulating layer facing the base substrate; and the display electrode is electrically connected to the drain of the thin film transistor through a through hole penetrating the interlayer dielectric structure.
  • a display panel including the above-mentioned array substrate.
  • a display device including the display panel as described above.
  • FIG. 1 is a schematic cross-sectional structure diagram of an array substrate provided by an embodiment of the present disclosure, in which the gate is located above the active layer;
  • FIG. 2 is a schematic structural diagram of an array substrate provided with a first groove structure in a gate insulating layer provided by an embodiment of the disclosure
  • FIG. 3 is a schematic top view of the structure of an array substrate provided by an embodiment of the disclosure.
  • FIG. 4 is a schematic structural diagram of an array substrate with a first groove structure penetrating the gate insulating layer provided by an embodiment of the disclosure
  • FIG. 5 is a schematic structural view of an array substrate provided with a second groove structure in the buffer layer provided by an embodiment of the disclosure
  • FIG. 6 is a schematic structural diagram of an array substrate with a second groove structure penetrating the buffer layer provided by an embodiment of the disclosure
  • FIG. 7 is a schematic diagram of a manufacturing process of an array substrate in an embodiment of the disclosure.
  • FIG. 8 is a schematic cross-sectional structure diagram of an array substrate provided by an embodiment of the disclosure, in which the active layer is located above the gate;
  • FIG. 9 is a schematic cross-sectional structure diagram of an array substrate provided by an embodiment of the disclosure, in which the interlayer dielectric structure covers the thin film transistor and the gate is located above the active layer;
  • FIG. 10 is a schematic cross-sectional structure diagram of an array substrate provided by an embodiment of the disclosure, in which the interlayer dielectric structure covers the thin film transistor and the active layer is located above the gate;
  • FIG. 11 is a schematic structural diagram of an array substrate provided with a third groove structure on a base substrate provided by an embodiment of the disclosure.
  • TFT-LCD Thin Film Transistor LCD
  • LTPS Low Temperature Poly-silicon
  • the peripheral driving circuit can be fabricated on the glass substrate at the same time to achieve the goal of system integration and save space And the cost of the driver IC.
  • AMOLED Active Matrix Organic Light Emitting Diode
  • polyimide PI
  • PI polyimide
  • the LTPS-AMOLED/LCD display usually includes an inorganic layer and a metal layer, which causes the LTPS-AMOLED/LCD display to have great difficulties in folding. After multiple bendings, the inorganic layer and the metal layer generate stress, which may cause cracks, which can easily cause the entire display to fail.
  • the electrical performance of the TFT in the LTPS AMOLED/LCD display may be degraded after multiple bending, resulting in problems such as unsatisfactory reliability test.
  • the inorganic ILD in the flexible AMOLED display is a stack of SiO2 and SiNx.
  • the thickness of the entire inorganic ILD is greater than 5000 angstroms, which is the thickest inorganic film layer in the array substrate, which is likely to cause stress and failure problems after bending.
  • an embodiment of the present disclosure provides an array substrate including a thin film transistor and an interlayer dielectric structure 4 on a base substrate 1.
  • the thin film transistor includes a gate 2, an active layer 6 and a source-drain layer 3.
  • the drain layer 3 includes a source electrode and a drain electrode.
  • the interlayer dielectric structure 4 is a laminated structure including an organic interlayer dielectric layer 41 and an inorganic interlayer dielectric layer 42.
  • the organic interlayer dielectric layer 41 is located on the inorganic interlayer dielectric layer 42 Face the side of the base substrate 1.
  • the interlayer dielectric structure 4 is a laminated structure including an organic interlayer dielectric layer 41 and an inorganic interlayer dielectric layer 42.
  • the organic interlayer dielectric layer 41 is located on the facing liner of the inorganic interlayer dielectric layer 42.
  • the interlayer dielectric structure 4 of the embodiment of the present disclosure is a laminated structure of an organic interlayer dielectric layer 41 and an inorganic interlayer dielectric layer 42, wherein the organic interlayer dielectric layer 41 has bending resistance Therefore, the display panel made of the array substrate can have strong bending resistance during the bending process, and the problem of the interlayer dielectric structure 4 is not likely to occur during the multiple bending process, and the organic interlayer dielectric layer 41
  • the inorganic interlayer dielectric layer 42 on the other side can play a good insulation role, avoiding other display problems when the interlayer dielectric structure 4 only includes the organic interlayer dielectric layer 41, and thus makes the interlayer dielectric structure 4 It has better insulation and can also improve the display panel including the array substrate.
  • the interlayer dielectric structure 4 After multiple bending, the interlayer dielectric structure 4 is easy to break, which will lead to the problem of display panel failure, which can avoid the interlayer dielectric structure only including When the inorganic interlayer dielectric layer is thicker, the problem that the thicker inorganic interlayer dielectric layer is very easy to break occurs.
  • the array substrate in the embodiment of the present disclosure may be an array substrate of an OLED display panel.
  • the base substrate 1 may be a flexible base substrate, and the material may be polyimide (PI).
  • the thin film transistor includes a gate 2, an active layer 6 and a source-drain layer 3.
  • the thin film transistor may also include a gate insulating layer 5 between the gate 2 and the active layer 6, and the gate 2 and the active layer 6 pass through
  • the gate insulating layers 5 are insulated from each other
  • the source drain layer 3 includes a source electrode and a drain electrode
  • the source electrode and the drain electrode are electrically connected to the active layer 6.
  • the thin film transistor is a top-gate thin film transistor, the active layer 6 is located under the gate 2, the gate insulating layer 5 is located between the gate 2 and the active layer 6, and the active layer 6 is located on the gate.
  • the gate 2 and the active layer 6 are insulated from each other by the gate insulating layer 5.
  • the source electrode and the drain electrode are electrically connected to the active layer 6 through through holes H1 penetrating the interlayer dielectric structure 4 and the gate insulating layer 5 respectively.
  • the thin film transistor is a bottom-gate thin film transistor
  • the gate 2 is located under the active layer 6
  • the gate insulating layer 5 is located between the gate 2 and the active layer 6, and the gate 2 is located at the gate.
  • the gate 2 and the active layer 6 are insulated from each other by the gate insulating layer 5.
  • the source and drain respectively pass through the through hole H2 that penetrates the interlayer dielectric structure 4 and the active layer 6 Electrical connection.
  • the interlayer dielectric structure 4 is located between the active layer 6 and the source drain layer 3.
  • the embodiments of the present disclosure are not limited to this.
  • the array substrate further includes a display electrode 8.
  • the interlayer dielectric structure 4 covers the thin film transistor and is located between the display electrode 8 and the source and drain layer 3. between.
  • the thin film transistor is a top-gate thin film transistor, and the display electrode 8 is electrically connected to the drain through a through hole H3 penetrating the interlayer dielectric structure 4 and the gate insulating layer 5.
  • the thin film transistor is a bottom-gate thin film transistor, and the display electrode 8 is electrically connected to the drain through a through hole H4 penetrating the interlayer dielectric structure 4.
  • the display electrode 8 is a pixel electrode.
  • the thickness of the organic interlayer dielectric layer 41 is greater than the thickness of the inorganic interlayer dielectric layer 42.
  • the thickness of the organic interlayer dielectric layer 41 is greater than the thickness of the inorganic interlayer dielectric layer 42, which can ensure that the interlayer dielectric structure 4 has strong bending resistance.
  • the thickness of the organic interlayer dielectric layer 41 is 2 to 4 times the thickness of the inorganic interlayer dielectric layer 42 to better ensure the bending resistance of the interlayer dielectric structure 4.
  • the organic interlayer dielectric layer 41 may include any suitable organic material, such as polyimide resin, epoxy resin, acrylic resin, combinations thereof, and so on.
  • the inorganic interlayer dielectric layer 42 may include any suitable inorganic materials, such as nitrides, oxides, oxynitrides, and combinations thereof, and further, such as silicon nitride, silicon oxide, silicon oxynitride, and combinations thereof. Wait.
  • the organic interlayer dielectric layer 41 and the inorganic interlayer dielectric layer 42 are in direct contact with each other; more specifically, the organic interlayer dielectric layer 41 and the inorganic interlayer dielectric layer 42 are in direct surface contact, so that they are perpendicular to the substrate. In the direction of the substrate 1, there is no other film layer between the organic interlayer dielectric layer 41 and the inorganic interlayer dielectric layer 42.
  • the array substrate further includes a gate insulating layer 5 between the gate 2 and the active layer 6.
  • the gate 2 and the active layer 6 are insulated from each other by the gate insulating layer 5, and the interlayer dielectric structure 4 covers the gate. Insulation layer 5.
  • the gate insulating layer 5 has a first groove structure 50 with an opening facing the interlayer dielectric structure 4.
  • the organic interlayer dielectric layer 41 fills the first groove structure 50, and the first groove structure 50 is in the substrate
  • the orthographic projection of the substrate 1 and the orthographic projection of each of the active layer 6, the gate 2, the source electrode and the drain electrode on the base substrate 1 do not overlap each other.
  • the gate insulating layer 5 also has a first groove structure 50, that is, the gate insulating layer 5 under the organic interlayer dielectric layer 41 is grooved, and the first groove structure 50 can be arranged The stress during bending of the organic interlayer dielectric layer 41 is dispersed, and the bending resistance of the organic interlayer dielectric layer 41 is further enhanced. Moreover, since the gate insulating layer 5 is generally an inorganic layer, digging holes for the inorganic gate insulating layer 5 in the area without thin film transistors can reduce the area of the inorganic gate insulating layer 5 in the entire array substrate, and further The gate insulating layer 5 can also have better bending performance when bending. In addition, the first groove structure 50 is filled and flattened by the organic interlayer dielectric layer 41, so that the surface of the array substrate can be very flat, and the source and drain layer 3 laid later can be prevented from breaking.
  • the orthographic projection of the first groove structure 50 on the base substrate 1 and the orthographic projection of the active layer 6 on the base substrate 1 do not overlap each other, that is, when trenching the gate insulating layer 5, it is necessary to avoid Dig into the active layer 6.
  • the orthographic projection of the first groove structure 50 on the base substrate 1 and the orthographic projections of the gate 2, the source, and the drain may not overlap each other, that is, the gate insulating layer 5 may be divided by and Dig holes in areas other than the corresponding area of the thin film transistor.
  • the first groove structure 50 may be formed in the display area (ie, the AA' area in FIG. 3) and the area where the GOA (Gate on Array) is located; in addition, the first groove structure 50 may also be formed in the peripheral packaging area (ie, FIG. 3 The area where the middle sealant is located), the binding area (that is, the area between the AA′ area and the FPC PAD in FIG. 3), or other areas other than the foregoing area form the first groove structure 50.
  • the FPC PAD is used for electrical connection with a flexible printed circuit (Flexible Printed Circuit, FPC) (not shown). The electrical signal from the FPC is transmitted to the IC circuit via the FPC PAD, and the IC circuit transmits the electrical signal to the AA area and GOA to realize image display in AA area.
  • FPC Flexible Printed Circuit
  • the first groove structure 50 penetrates the gate insulating layer 5.
  • the first groove structure 50 penetrates the gate insulating layer 5 to maximize the bending resistance of the gate insulating layer 5.
  • the array substrate further includes a buffer layer 7 located between the base substrate 1 and the gate insulating layer 5.
  • the buffer layer 7 has an opening at a position corresponding to the first groove structure 50 facing the gate insulating layer.
  • the second groove structure 70 of layer 5 and the organic interlayer dielectric layer 41 fill the second groove structure 70. That is, in the embodiment of the present disclosure, the buffer layer 7 is also grooved and filled with the organic interlayer dielectric layer 41, so that the buffer layer 7 has better bending resistance.
  • the second groove structure 70 is located at a position corresponding to the first groove 50 structure, and the second groove structure 70 can be directly formed when the first groove structure 50 is formed, that is, the gate can be formed by one patterning process.
  • the first groove structure 50 of the polar insulating layer 5 and the second groove structure 70 of the buffer layer 7 can simplify the manufacturing process of the first groove structure 50 and the second groove structure 70.
  • the second groove structure 70 penetrates the buffer layer 7.
  • the second groove structure 70 penetrates through the buffer layer 7 to maximize the bending resistance of the buffer layer 7.
  • the base substrate 1 can also be grooved at a position corresponding to the first groove structure 50 to form a third groove structure 90, but the third groove structure 90 is a structure that does not penetrate the base substrate 1, such as Shown in Figure 11.
  • the other film layer may also be grooved at a position corresponding to the first groove structure 50.
  • the orthographic projection of the first groove structure 50 on the base substrate 1 is a square, a rectangle, or a circle.
  • the orthographic projection of the first groove structure 50 on the base substrate is a square, a rectangle, or a circle, which can facilitate the production of the first groove structure 50.
  • the orthographic projection of the second groove structure 70 on the base substrate 1 can also be square, rectangular, or circular.
  • the orthographic projection of the third groove structure 90 on the base substrate 1 can also be square, rectangular, or circular.
  • the orthographic projection of the second groove structure 70 on the base substrate 1 completely coincides with the orthographic projection of the first groove structure 50 on the base substrate 1 to complete the first groove structure 50 and the second groove structure 50 through a one-time patterning process. ⁇ 70 ⁇ Groove structure 70.
  • the orthographic projection of the third groove structure 90 on the base substrate 1 and the orthographic projection of the first groove structure 50 on the base substrate 1 completely overlap, so as to facilitate the third groove structure 90 and the second groove
  • the structure 70 and the first groove structure 50 are completed by a one-time patterning process.
  • the size of the orthographic projection of the first groove structure 50 on the base substrate 1 is 2 to 10 microns; more specifically, for example, when the orthographic projection of the first groove structure 50 on the base substrate 1 is circular , The diameter of the circle is 2 microns to 10 microns.
  • the orthographic projection of the third groove structure 90 on the base substrate 1 falls within the orthographic projection of the second groove structure 70 on the base substrate 1 and the area of the orthographic projection of the third groove structure 90 on the base substrate 1 Smaller than the area of the orthographic projection of the second groove structure 70 on the base substrate 1, the orthographic projection of the second groove structure 70 on the base substrate 1 falls within the orthographic projection of the first groove structure 50 on the base substrate 1 and The area of the orthographic projection of the second groove structure 70 on the base substrate 1 is smaller than the area of the orthographic projection of the first groove structure 50 on the base substrate 1.
  • the third groove structure 90, the second groove structure 70 and the first groove structure 50 can also be completed by a one-time patterning process, and the etching difficulty can be reduced.
  • first groove structures 50 there are multiple first groove structures 50, and the multiple first groove structures 50 may be periodically distributed.
  • the plurality of first groove structures 50 are periodically distributed, which can make the bending resistance performance of each position of the array substrate basically consistent.
  • the plurality of first groove structures 50 may also be arranged non-periodically.
  • there are multiple second groove structures 70 there are multiple second groove structures 70, and the multiple second groove structures 70 may be periodically distributed.
  • the orthographic projection of the first groove structure 50 on the base substrate 1 is a ring that surrounds the orthographic projection of the thin film transistor on the base substrate 1.
  • the orthographic projection of the second groove structure 70 on the base substrate 1 is annular, and surrounds the orthographic projection of the thin film transistor on the base substrate 1.
  • the orthographic projection of the third groove structure 90 on the base substrate 1 is annular, and surrounds the orthographic projection of the thin film transistor on the base substrate 1.
  • the ring may or may not be closed.
  • the manufacturing process of the array substrate can be as shown in Figure 7, that is, the patterned active layer 6 (Active) is formed on the base substrate 1 through the first mask process; A patterned gate 2 is formed on the side of the source layer 6 facing away from the base substrate 1 (for example, two gates Gate1 and Gate2 can be formed by two second mask processes); The gate insulating layer 5 is dug (Gate Hole, of course, before the second masking process, the gate insulating layer 5 is formed between the gate and the active layer) to form the first groove structure 50; The mask process patterns the interlayer dielectric structure 4 to form through holes exposing the active layer, so that the subsequently formed source and drain electrodes are electrically connected to the active layer (for example, before the fourth mask process is performed) , The active layer can also be doped (Dopant Activation) and hydrogenation process (Hydrogenation) to form an interlayer dielectric structure 4); a patterned source and drain layer (SD) is formed through the fifth mask process; Six masking processes form a patterned active
  • embodiments of the present disclosure also provide a display panel, including the array substrate provided by the embodiments of the present disclosure.
  • the display panel further includes an opposite substrate disposed opposite to the array substrate. The sealant joins the array substrate and the counter substrate to each other.
  • embodiments of the present disclosure also provide a display device, including the display panel provided by the embodiments of the present disclosure.
  • the interlayer dielectric structure in the array substrate provided by the implementation of the present disclosure is a laminated structure including an organic interlayer dielectric layer and an inorganic interlayer dielectric layer.
  • the organic interlayer dielectric layer is located on the side of the inorganic interlayer dielectric layer facing the base substrate.
  • the interlayer dielectric structure of the embodiment of the present disclosure is a laminated structure of an organic interlayer dielectric layer and an inorganic interlayer dielectric layer, wherein the organic interlayer dielectric layer has bending resistance performance, and a display panel made of an array substrate It can have strong bending resistance during the bending process, and the problem of interlayer dielectric structure fracture is not easy to occur during multiple bending processes, while the inorganic interlayer dielectric layer on the other side of the organic interlayer dielectric layer can be Play a good insulation effect, and thus make the interlayer dielectric structure have a better insulation effect, and can also improve the problem that the interlayer dielectric structure of the display panel is easily broken after multiple bending, which will lead to the failure of the display panel. It can avoid the problem that the thicker inorganic interlayer dielectric layer is easily broken when the interlayer dielectric layer only includes a thicker inorganic interlayer dielectric layer.

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Abstract

La présente invention concerne un substrat matriciel, un panneau d'affichage et un dispositif d'affichage. Le substrat matriciel comprend un substrat de base, et un transistor à couches minces et une structure diélectrique intercouche sur le substrat de base, le transistor à couches minces comprenant une électrode de grille, une couche active et une couche de source/drain ; la couche de source/drain comprend une électrode de source et une électrode de drain ; la structure diélectrique intercouche est une structure stratifiée comprenant une couche diélectrique intercouche organique et une couche diélectrique intercouche inorganique ; et la couche diélectrique intercouche organique est située sur une face, faisant face au substrat de base, de la couche diélectrique intercouche inorganique.
PCT/CN2020/088131 2019-06-05 2020-04-30 Substrat matriciel, panneau d'affichage et dispositif d'affichage WO2020244350A1 (fr)

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CN109300964A (zh) * 2018-10-26 2019-02-01 武汉华星光电半导体显示技术有限公司 柔性oled面板及其制作方法
CN110112204A (zh) * 2019-06-05 2019-08-09 京东方科技集团股份有限公司 一种阵列基板、显示面板和显示装置

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Publication number Priority date Publication date Assignee Title
CN115117093A (zh) * 2022-06-14 2022-09-27 厦门天马微电子有限公司 显示面板及其制造方法、显示装置

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