WO2020237504A1 - 超声波感测电路及其驱动方法、探测基板和触控面板 - Google Patents

超声波感测电路及其驱动方法、探测基板和触控面板 Download PDF

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Publication number
WO2020237504A1
WO2020237504A1 PCT/CN2019/088828 CN2019088828W WO2020237504A1 WO 2020237504 A1 WO2020237504 A1 WO 2020237504A1 CN 2019088828 W CN2019088828 W CN 2019088828W WO 2020237504 A1 WO2020237504 A1 WO 2020237504A1
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Prior art keywords
transistor
node
coupled
terminal
voltage
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PCT/CN2019/088828
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English (en)
French (fr)
Inventor
杨盛际
董学
陈小川
王辉
卢鹏程
黄冠达
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京东方科技集团股份有限公司
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Priority to EP19931294.3A priority Critical patent/EP3979053B1/en
Priority to US16/765,295 priority patent/US11295105B2/en
Priority to CN201980000744.4A priority patent/CN112639703B/zh
Priority to PCT/CN2019/088828 priority patent/WO2020237504A1/zh
Publication of WO2020237504A1 publication Critical patent/WO2020237504A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/043—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using propagating acoustic waves
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1306—Sensors therefor non-optical, e.g. ultrasonic or capacitive sensing

Definitions

  • the present disclosure relates to the field of sensing technology, in particular, to an ultrasonic sensing circuit and a driving method thereof, a detection substrate, and a touch panel.
  • Ultrasonic sensing technology is a technology that uses ultrasonic signals to realize information sensing.
  • an ultrasonic sensor emits an ultrasonic signal, receives the reflected ultrasonic signal, and converts the received ultrasonic signal into an electrical signal. Then, the electric signal is read by the reading circuit, so as to realize the sensing of information.
  • the embodiments of the present disclosure provide an ultrasonic sensing circuit and a driving method thereof, a detection substrate, and a touch panel.
  • an ultrasonic sensing circuit including an ultrasonic sensing circuit, an input circuit, a reset circuit, a storage circuit, a selection circuit, a source follower, and a compensation circuit.
  • the ultrasonic sensing circuit is coupled to the first node and the first power supply voltage terminal, and is configured to transmit and receive ultrasonic signals, and generate a sensing voltage corresponding to the received ultrasonic signals to provide to the first node.
  • the input circuit is coupled to the first control signal terminal, the first node, and the second node, and is configured to provide the sensing voltage of the first node to the second node according to the first control signal from the first control signal terminal.
  • the reset circuit is coupled to the reset control signal terminal, the second node is coupled to the first power supply voltage terminal, and is configured to provide the first power supply voltage from the first power supply voltage terminal to the second power supply voltage terminal according to the reset control signal from the reset control signal terminal.
  • the node resets the voltage of the second node.
  • the storage circuit is coupled between the second node and the second power supply voltage terminal, and is configured to store the voltage difference between the second node and the second power supply voltage terminal.
  • the selection circuit is coupled to the selection signal terminal, the third power supply voltage terminal and the third node, and is configured to provide the third power supply voltage from the third power supply voltage terminal to the third node according to the selection signal from the selection signal terminal.
  • the source follower includes: a first pole coupled to the third node; a control pole coupled to the compensation circuit via the fourth node; and a second pole coupled to the output terminal, configured to output a corresponding The current of the voltage between the first pole and the control pole.
  • the compensation circuit is coupled to the second power supply voltage terminal, the second control signal terminal, the third control signal terminal, the second node, the third node, the fourth node and the output terminal, and is configured to receive the sensing voltage of the second node , And according to the sensing voltage and the third power supply voltage, provide a compensated sensing voltage to the control electrode of the source follower.
  • the first power supply voltage and the second power supply voltage are lower than the third power supply voltage respectively.
  • the compensation circuit includes a first transistor, a second transistor, a first capacitor, an inverter, a third transistor, and a fourth transistor.
  • the control electrode of the first transistor is coupled to the second control signal terminal, the first electrode of the first transistor is coupled to the second node, and the second electrode of the first transistor is coupled to the fourth node.
  • the control electrode of the second transistor is coupled to the second control signal terminal, the first electrode of the second transistor is coupled to the second power supply voltage terminal, and the second electrode of the second transistor is coupled to the fifth node.
  • the first terminal of the first capacitor is coupled to the third node, and the second terminal of the first capacitor is coupled to the fifth node.
  • the first pole of the inverter is coupled to the second control signal terminal, and the second pole of the inverter is coupled to the control pole of the third transistor.
  • the first electrode of the third transistor is coupled to the fifth node, and the second electrode of the third transistor is coupled to the fourth node.
  • the control electrode of the fourth transistor is coupled to the third control signal terminal, the first electrode of the fourth transistor is coupled to the second power supply voltage terminal, and the second electrode of the fourth transistor is coupled to the output terminal.
  • the first transistor, the second transistor, the third transistor and the fourth transistor are of the same type.
  • the compensation circuit includes a first transistor, a second transistor, a first capacitor, a third transistor, and a fourth transistor.
  • the control electrode of the first transistor is coupled to the second control signal terminal, the first electrode of the first transistor is coupled to the second node, and the second electrode of the first transistor is coupled to the fourth node.
  • the control electrode of the second transistor is coupled to the second control signal terminal, the first electrode of the second transistor is coupled to the second power supply voltage terminal, and the second electrode of the second transistor is coupled to the fifth node.
  • the first terminal of the first capacitor is coupled to the third node, and the second terminal of the first capacitor is coupled to the fifth node.
  • the control electrode of the third transistor is coupled to the second control signal terminal, the first electrode of the third transistor is coupled to the fifth node, and the second electrode of the third transistor is coupled to the fourth node.
  • the control electrode of the fourth transistor is coupled to the third control signal terminal, the first electrode of the fourth transistor is coupled to the second power supply voltage terminal, and the second electrode of the fourth transistor is coupled to the output terminal.
  • the third transistor is of a different type from the first transistor, the second transistor, and the fourth transistor.
  • the ultrasonic sensor circuit includes an ultrasonic sensor and a rectifier circuit.
  • the ultrasonic sensor is coupled to the first node, and the rectifier circuit is coupled between the first node and the first power voltage terminal.
  • the input circuit includes a fifth transistor.
  • the control electrode of the fifth transistor is coupled to the first control signal terminal, the first electrode of the fifth transistor is coupled to the first node, and the second electrode of the fifth transistor is coupled to the second node.
  • the reset circuit includes a sixth transistor.
  • the control electrode of the sixth transistor is coupled to the reset control signal terminal, the first electrode of the sixth transistor is coupled to the first power supply voltage terminal, and the second electrode of the sixth transistor is coupled to the second node.
  • the storage circuit includes a second capacitor.
  • the first terminal of the second capacitor is coupled to the second node, and the second terminal of the second capacitor is coupled to the second power voltage terminal.
  • the selection circuit includes a seventh transistor.
  • the control electrode of the seventh transistor is coupled to the selection signal terminal, the first electrode of the seventh transistor is coupled to the third power supply voltage terminal, and the second electrode of the seventh transistor is coupled to the third node.
  • the first power supply voltage terminal is provided with a common voltage.
  • the detection substrate includes a plurality of ultrasonic sensing circuits according to the first aspect of the present disclosure.
  • a touch panel includes the detection substrate according to the second aspect of the present disclosure.
  • a method for driving the ultrasonic sensing circuit includes: resetting the voltage at the second node through a reset circuit; generating a sensing voltage corresponding to the received ultrasonic signal in response to the ultrasonic signal received by the ultrasonic sensing circuit, and providing the sensing voltage through the input circuit To the second node and store it in the storage circuit; provide the sensing voltage to the fourth node, and charge both ends of the first capacitor in the compensation circuit, so that the voltage at the first end of the first capacitor is the third
  • the power supply voltage, the voltage of the second terminal of the first capacitor is the second power supply voltage; the voltage of the first terminal of the first capacitor is reduced to the sum of the sensing voltage and the threshold voltage of the source follower; and the voltage of the first capacitor
  • the voltage at the first terminal is increased to the third power supply voltage to provide a compensated sensing voltage to the control electrode of the source follower, which outputs current.
  • Figure 1 shows an exemplary circuit diagram of an existing ultrasonic sensing circuit
  • Figure 2 shows a schematic block diagram of an ultrasonic sensing circuit according to an embodiment of the present disclosure
  • FIG. 3 shows an exemplary circuit diagram of an ultrasonic sensing circuit according to an embodiment of the present disclosure
  • FIG. 4 shows an exemplary circuit diagram of an ultrasonic sensing circuit according to an embodiment of the present disclosure
  • FIG. 5 shows a timing diagram of various signals in the working process of the ultrasonic sensing circuit shown in FIG. 2;
  • FIG. 6 shows a schematic flowchart of a method for driving an ultrasonic sensing circuit according to an embodiment of the present disclosure
  • FIG. 7 shows a schematic block diagram of a detection substrate according to an embodiment of the present disclosure.
  • FIG. 8 shows a schematic block diagram of a touch panel according to an embodiment of the present disclosure.
  • Fig. 1 shows an exemplary schematic diagram of an existing ultrasonic sensing circuit.
  • the ultrasonic sensing circuit 100 may include an ultrasonic sensor UT, a filter diode D, a reset transistor TRST, a source follower SF, and a selection switch transistor TEM.
  • the ultrasonic sensor UT transmits and receives ultrasonic signals, and then converts the received ultrasonic signals into electrical signals.
  • the electric signal is supplied to the control electrode of the source follower SF.
  • the source follower SF can output a corresponding current I from the second pole according to the voltage difference V GS between the voltage of the electrical signal and the voltage VDD of the first pole. According to the current I, the corresponding information can be determined.
  • the current I output at the second pole of the source follower SF can be determined by formula (1):
  • K represents the coefficient
  • V th represents the threshold voltage of the source follower SF.
  • the embodiments of the present disclosure provide an ultrasonic sensing circuit, which can perform threshold voltage compensation on the voltage of the control electrode of the source follower, so that the current I output from the second electrode is independent of the threshold voltage. , Thus avoiding the accuracy problems caused by the difference in threshold voltage.
  • the embodiments of the present disclosure provide an ultrasonic sensing circuit and a driving method thereof, a detection substrate, and a touch panel.
  • the embodiments and examples of the present disclosure will be described in detail below with reference to the accompanying drawings.
  • FIG. 2 shows a schematic block diagram of an ultrasonic sensing circuit 200 according to an embodiment of the present disclosure.
  • the ultrasonic sensing circuit 200 may include an ultrasonic sensing circuit 210, an input circuit 220, a reset circuit 230, a storage circuit 240, a selection circuit 250, a source follower SF, and a compensation circuit 260. It will be described in detail below with reference to the drawings.
  • the ultrasonic sensing circuit 210 may be coupled with the first node J1 and the first power supply voltage terminal.
  • the ultrasonic sensor circuit 210 can transmit ultrasonic signals and receive reflected ultrasonic signals. Further, the ultrasonic sensing circuit 210 may generate a sensing voltage V Data corresponding to the received ultrasonic signal to provide to the first node J1.
  • the first power supply voltage terminal may be a common voltage terminal, for example, a common ground terminal.
  • the first power supply voltage V1 is the common voltage V com .
  • the first power supply voltage terminal can also be grounded. At this time, the first power supply voltage V1 is zero.
  • the input circuit 220 is coupled to the first control signal terminal, the first node J1 and the second node J2.
  • the input circuit 220 receives the first control signal CTR1 from the first control signal terminal, and provides the sensing voltage of the first node J1 to the second node J2 according to the first control signal CTR1.
  • the reset circuit 230 is coupled to the reset control signal terminal, the second node J2 and the first power voltage terminal.
  • the reset circuit 230 receives the reset control signal RESET from the reset control signal terminal, and receives the first power supply voltage V1 from the first power supply voltage terminal.
  • the reset circuit 230 provides the first power supply voltage V1 to the second node J2 according to the reset control signal RESET to reset the voltage of the second node J2.
  • the storage circuit 240 is coupled between the second node J2 and the second power supply voltage terminal, and stores the voltage difference between the second node J2 and the second power supply voltage terminal.
  • the second power supply voltage terminal may be a ground terminal, and at this time, the second power supply voltage V2 is zero.
  • the selection circuit 250 is coupled to the selection signal terminal, the third power voltage terminal, and the third node J3.
  • the selection circuit 250 receives the selection signal EM from the selection signal terminal, receives the third power supply voltage V3 from the third power supply voltage terminal, and provides the third power supply voltage V3 to the third node J3 according to the selection signal EM.
  • the third power supply voltage terminal is used to provide the working voltage to the ultrasonic sensing circuit 200, therefore, the third power supply voltage V3 is a high level higher than the first power supply voltage V1 and the second power supply voltage V2 Voltage.
  • the control pole of the source follower SF is coupled to the fourth node J4, the first pole is coupled to the third node J3, and the second pole is coupled to the output terminal OUTPUT.
  • the compensation circuit 260 is also coupled to the fourth node J4. Therefore, the control electrode of the source follower SF is coupled to the compensation circuit 260 via the fourth node J4.
  • the source follower SF outputs a current signal corresponding to the voltage between the first pole and the control pole through the output terminal OUTPUT.
  • the compensation circuit 260 is coupled to the second power supply voltage terminal, the second control signal terminal, the third control signal terminal, the second node J2, the third node J3, the fourth node J4, and the output terminal OUTPUT.
  • the compensation circuit 260 receives the second control signal CTR2 from the second control signal terminal, receives the third control signal CTR3 from the third control signal terminal, and provides compensation to the fourth node J4 according to the second control signal CTR2 and the third control signal CTR3 , Thereby providing a compensated sensing voltage to the control electrode of the source follower SF.
  • FIG. 3 shows an exemplary circuit diagram of the ultrasonic sensing circuit 300 according to an embodiment of the present disclosure.
  • the ultrasonic sensing circuit 300 may include a first transistor T1 to a seventh transistor T7, a first capacitor C1, a second capacitor C2, an inverter M, and a source follower SF.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • a thin film transistor is taken as an example for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable.
  • the gate of the transistor is referred to as a control electrode, and the two poles other than the gate are referred to as a first pole and a second pole, respectively.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the transistor Regardless of the threshold voltage, if the transistor is a P-type transistor, the on-voltage is a low-level voltage, and the off-voltage is a high-level voltage. If the transistor is an N-type transistor, the turn-on voltage is a high-level voltage, and the turn-off voltage is a low-level voltage. In the case of considering the threshold voltage, if the transistor is a P-type transistor, when the voltage difference between the control electrode of the transistor and the first electrode is less than or equal to the threshold voltage, the transistor is turned on. If the transistor is an N-type transistor, when the voltage difference between the control electrode and the first electrode of the transistor is greater than or equal to the threshold voltage, the transistor is turned on.
  • the compensation circuit 260 includes a first transistor T1, a second transistor T2, a first capacitor C1, an inverter M, a third transistor T3, and a fourth transistor T4.
  • the compensation circuit 260 will be described in detail with reference to the drawings.
  • the control electrode of the first transistor T1 is coupled to the second control signal terminal to receive the second control signal CTR2.
  • the first pole of the first transistor T1 is coupled to the second node J2, and the second pole is coupled to the fourth node J4.
  • the second control signal CTR2 when the second control signal CTR2 is at a low level, the first transistor T1 is turned on, and the voltage of the second node J2 is provided to the fourth node J4.
  • the control electrode of the second transistor T2 is coupled to the second control signal terminal to receive the second control signal CTR2.
  • the first electrode of the second transistor T2 is coupled to the second power voltage terminal to receive the second power voltage V2.
  • the second electrode of the second transistor T2 is coupled to the fifth node J5. In this embodiment, when the second control signal CTR2 is at a low level, the second transistor T2 is turned on, and the received second power supply voltage V2 is provided to the fifth node J5.
  • the first terminal of the first capacitor C1 is coupled to the third node J3, and the second terminal is coupled to the fifth node J5 to store the voltage difference between the voltage of the third node J3 and the voltage of the fifth node J5.
  • the first The voltage of the fifth node J5 becomes the difference between the changed voltage of the third node J3 and the stored voltage difference of the first capacitor C1.
  • the first pole of the inverter M is coupled to the second control signal terminal to receive the second control signal CTR2.
  • the second pole of the inverter M is coupled to the control pole of the third transistor T3.
  • the voltage of the control electrode of the third transistor T3 is at a low level.
  • the voltage of the control electrode of the third transistor T3 is at a high level under the action of the inverter M.
  • the first pole of the third transistor T3 is coupled to the fifth node J5, and the second pole is coupled to the fourth node J4.
  • the third transistor T3 When the voltage of the control electrode of the third transistor T3 is at a low level, the third transistor T3 is turned on, and the voltage of the fifth node J5 is provided to the fourth node J4.
  • the control electrode of the fourth transistor T4 is coupled to the third control signal terminal to receive the third control signal CTR3.
  • the first pole of the fourth transistor T4 is coupled to the second power supply voltage terminal, and the second pole is coupled to the output terminal OUTPUT.
  • the fourth transistor T4 is turned on, so that the voltage of the second electrode of the source follower SF becomes the second power supply voltage V2.
  • the ultrasonic sensor circuit 210 includes an ultrasonic sensor UT and a rectifier circuit.
  • the ultrasonic sensor circuit UT is coupled to the first node J1.
  • the rectifier circuit is coupled between the first node J1 and the first power voltage terminal.
  • the rectifier circuit is a diode D.
  • the reverse voltage at the first node J1 (the part less than the first power supply voltage V1) is supplied to the first power supply voltage terminal via the diode D.
  • the input circuit 220 includes a fifth transistor T5.
  • the control electrode of the fifth transistor T5 is coupled to the first control signal terminal to receive the first control signal CTR1.
  • the first pole of the fifth transistor T5 is coupled to the first node J1, and the second pole is coupled to the second node J2.
  • the fifth transistor T5 when the first control signal CTR1 is at a low level, the fifth transistor T5 is turned on, and the sensing voltage at the first node J1 is provided to the second node J2.
  • the reset circuit 230 includes a sixth transistor T6.
  • the control electrode of the sixth transistor T6 is coupled to the reset control signal terminal to receive the reset control signal RESET.
  • the first pole of the sixth transistor T6 is coupled to the first power voltage terminal to receive the first power voltage V1.
  • the second electrode of the sixth transistor T6 is coupled to the second node J2.
  • the sixth transistor T6 when the reset control signal RESET is at a low level, the sixth transistor T6 is turned on, so as to provide the first power supply voltage V1 to the second node J2 to reset the voltage of the second node J2.
  • the storage circuit 240 includes a second capacitor C2.
  • the first terminal of the second capacitor C2 is coupled to the second node J2, and the second terminal is coupled to the second power voltage terminal.
  • the second capacitor C2 when the voltage of the second node J2 is at a high level, stores and maintains the voltage difference between the second node J2 and the second power supply voltage terminal.
  • the selection circuit 250 includes a seventh transistor T7.
  • the control electrode of the seventh transistor T7 is coupled to the selection signal terminal to receive the selection signal EM.
  • the first electrode of the seventh transistor T7 is coupled to the third power voltage terminal to receive the third power voltage V3.
  • the second electrode of the seventh transistor T7 is coupled to the third node J3. In an embodiment, when the selection signal EM is at a low level, the seventh transistor T7 is turned on to provide the third power supply voltage V3 to the third node J3.
  • the first transistor T1 to the seventh transistor T7 and the source follower SF are of the same type, and both are P-type transistors.
  • the first transistor T1 to the seventh transistor T7 and the source follower SF may also be N-type transistors.
  • the ultrasonic sensing circuit 210 may only include the ultrasonic sensor UT, which is coupled to the first node J1.
  • the ultrasonic sensing circuit 300 may also include a rectifier circuit, such as a diode. The rectifier circuit is coupled between the second node J2 and the first power voltage terminal.
  • Fig. 4 shows an exemplary circuit diagram of an ultrasonic sensing circuit 400 according to another embodiment of the present disclosure.
  • the ultrasonic sensing circuit 400 may include a first transistor T1 to a seventh transistor T7, a first capacitor C1 and a second capacitor C2, and a source follower SF.
  • a single third transistor T3' is used instead of the inverter M and the third transistor T3 in FIG.
  • the control electrode of the third transistor T3' is coupled to the second control signal terminal to receive the second control signal CTR2.
  • the first pole of the third transistor T3' is coupled to the fifth node J5, and the second pole is coupled to the fourth node J4.
  • the third transistor T3' when the second control signal CTR2 is at a high level, the third transistor T3' is turned on to provide the voltage of the fifth node J5 to the fourth node J4.
  • the first transistor T1, the second transistor T2, the fourth transistor T4 to the seventh transistor T7, and the source follower SF are all P-type transistors.
  • the third transistor T3' is different from the other transistors in that it is an N-type transistor.
  • the first transistor T1, the second transistor T2, the fourth transistor T4 to the seventh transistor T7, and the source follower SF may also be N-type transistors, and the third transistor T3' is a P-type transistor.
  • FIG. 5 shows a timing diagram of various signals in the working process of the ultrasonic sensing circuit 300 shown in FIG. 3. It is understandable that the signal voltage in the signal timing diagram shown in FIG. 5 is only schematic, and does not represent a true voltage value.
  • a low-level reset control signal RESET is provided at the reset control signal terminal, and the sixth transistor T6 is turned on.
  • the received first power supply voltage V1 is provided to the second node J2 to reset the voltage of the second node J2.
  • the ultrasonic sensor circuit 300 transmits and receives ultrasonic signals to generate a sensing voltage V Data corresponding to the received ultrasonic signals.
  • the sensing voltage corresponding to the received ultrasonic signal may be an AC voltage
  • the diode D removes the reverse voltage (the part less than the first power supply voltage V1) in the AC voltage through rectification, so that the first A sensing voltage V Data including only a forward voltage (a portion greater than the first power supply voltage V1) is generated at the node J1.
  • the ultrasonic sensing circuit 300 receives the low-level first control signal CTR1, the fifth transistor T5 is turned on, and the sensing voltage V Data at the first node J1 is provided to the second node J2.
  • the difference between the sensing voltage V Data and the third power supply voltage V 3 is smaller than the threshold voltage V th , that is, V Data -V3 ⁇ -
  • a low-level second control signal CTR2 is provided at the second control signal terminal, the second transistor T2 is turned on, the second power supply voltage V2 is provided to the fifth node J5, the first transistor T1 is turned on, and the ultrasonic
  • the sensing circuit 300 receives the low-level selection signal EM, the seventh transistor T7 is turned on, and the third power supply voltage V3 is provided to the third node J3.
  • the first capacitor C1 stores the voltage difference between the third node J3 and the fifth node J5 as V3-V2.
  • the second power supply voltage terminal is the ground terminal, so the voltage difference between the third node J3 and the fifth node J5 is equal to V3.
  • the sensing voltage V Data is provided to the fourth node J 4 . Since V Data -V3 ⁇ -
  • a low-level second control signal CTR2 is provided at the second control signal terminal, the second transistor T2 is turned on, and the second power supply voltage V2 is continuously provided to the fifth node J5.
  • the source follower SF remains conductive.
  • the ultrasonic sensing circuit 300 receives the low-level third control signal CTR3, and the fourth transistor T4 is turned on. Therefore, the voltage of the third node J3 is discharged (that is, the first capacitor C1 is discharged) until the source follower SF is turned off.
  • the voltage of the third node J3 is V Data +
  • the voltage difference stored by the first capacitor C1 is V Data +
  • a low-level selection signal EM is provided at the selection signal terminal, the seventh transistor T7 is turned on, and the third power supply voltage V3 is provided to the third node J3, so the voltage of the third node J3 is V3. Due to the equipotential jump of the first capacitor C1, the voltage of the fifth node J5 is V3-(V Data +
  • the ultrasonic sensing circuit 300 receives the high-level second control signal CTR2. Under the action of the inverter M, the third transistor T3 is turned on, and the voltage of the fifth node J5 is supplied to the fourth node J4, so the fourth node The voltage of J4 is V3-(V Data +
  • ) is provided to the control electrode of the source follower SF.
  • the current I output from the second pole of the source follower can be calculated, as shown in formula (2):
  • K represents the coefficient
  • FIG. 6 shows a schematic flowchart of a method for driving an ultrasonic sensing circuit according to an embodiment of the present disclosure.
  • the ultrasonic sensing circuit may be any applicable ultrasonic sensing circuit based on the embodiments of the present disclosure.
  • step 610 the voltage of the second node J2 is reset by the reset circuit 230.
  • the reset circuit 230 provides the received low-level first power supply voltage V1 to the second node J2 according to the reset control signal RESET, so as to reset the second node J2.
  • step 620 in response to the ultrasonic sensing circuit 210 receiving the ultrasonic signal and generating a sensing voltage V Data corresponding to the received ultrasonic signal, the sensing voltage V Data is provided to the second node J2 through the input circuit 220 and stored in In the storage circuit 240.
  • the ultrasonic sensor UT sends an ultrasonic signal and receives the reflected ultrasonic signal to obtain the corresponding AC voltage.
  • the rectifier circuit rectifies the AC voltage to generate the sensing voltage V Data including only the forward voltage at the first node J1.
  • the input circuit 220 provides the sensing voltage V Data at the first node J1 to the second node J2 according to the first control signal CTR1.
  • the storage circuit 240 stores the voltage difference between the sensing voltage V Data and the second power supply voltage V2.
  • the sensing voltage V Data is provided to the fourth node J4, and the two ends of the first capacitor C1 in the compensation circuit 260 are charged, so that the voltage of the first end of the first capacitor C1 is the third power supply voltage V3, the voltage of the second terminal of the first capacitor C1 is the second power supply voltage V2.
  • the third power voltage V3 is provided to the third node J3 according to the selection signal EM, so the voltage of the first terminal of the first capacitor C1 is V3.
  • the second control signal CTR2 the second power supply voltage V2 is provided to the fifth node J5. Therefore, the voltage of the second terminal of the first capacitor C1 is V2.
  • the second power supply voltage terminal is the ground terminal, so the voltage difference stored by the first capacitor C1 is V3-V2, that is, V3.
  • step 640 the voltage of the first terminal of the first capacitor C1 is reduced to the sum of the sensing voltage V Data and the threshold voltage V th of the source follower SF.
  • the fifth transistor T5 is turned on.
  • the source follower SF is turned on, so the third node J3 is discharged (that is, the first capacitor C1 is discharged) until the voltage between the control electrode and the first electrode of the source follower SF is less than its threshold voltage, namely
  • the voltage of the control electrode of the source follower SF is V Data
  • the voltage of the first electrode (or the third node J3) of the source follower SF is V Data +
  • the voltage difference stored by the first capacitor C1 is V Data +
  • step 650 the voltage of the first terminal of the first capacitor C1 is increased to the third power supply voltage V3 to provide a compensated sensing voltage to the control electrode of the source follower SF, and the source follower SF outputs a current.
  • the third power supply voltage V3 is again provided to the third node J3, so the voltage of the third node J3 is V3. Due to the equipotential jump of the first capacitor C1, the voltage of the fifth node J5 is V3-(V Data +
  • the third transistor T3 is turned on, and the voltage of the fifth node J5 is provided to the fourth node J4, so the voltage of the fourth node J4 is V3-(V Data +
  • ) is provided to the control electrode of the source follower SF.
  • the source follower SF outputs a current signal through the output terminal OUTPUT according to the compensated voltage.
  • the current I output at the second pole of the source follower SF has nothing to do with its threshold voltage V th . That is, the accuracy of the collected information is not affected by the threshold voltage V th of the source follower SF.
  • FIG. 7 shows a schematic block diagram of a detection substrate 700 according to an embodiment of the present disclosure.
  • the detection substrate 700 may include a plurality of ultrasonic sensing circuits 200 according to embodiments of the present disclosure.
  • FIG. 8 shows a schematic block diagram of a touch panel 800 according to an embodiment of the present disclosure.
  • the touch panel 800 is the detection substrate 700 shown in FIG. 7.
  • the touch panel may be a liquid crystal panel, a liquid crystal TV, a display, an OLED panel, an OLED TV, an electronic paper display device, a mobile phone, a tablet computer with information collection function (for example, fingerprint recognition function or touch control function, etc.) , Laptops, digital photo frames, navigators, etc.

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Abstract

一种超声波感测电路（200），其包括超声波传感电路（210）、输入电路（220）、复位电路（230）、存储电路（240）、选择电路（250）、源极跟随器（SF）和补偿电路（260）。超声波传感电路（210）产生与所接收的超声波信号对应的感测电压以提供给第一节点（J1）。输入电路（220）根据第一控制信号（CTR1），将第一节点（J1）的电压提供给第二节点（J2）。复位电路（230）根据复位控制信号（RESET），对第二节点（J2）的电压进行复位。存储电路（240）存储第二节点（J2）与第二电源电压端之间的电压差。选择电路（250）根据选择信号（EM），将第三电源电压（V3）提供给第三节点（J3）。源极跟随器（SF）通过输出端（OUTPUT）输出对应于在其第一极与控制极之间的电压的电流。补偿电路（260）根据感测电压和第三电源电压（V3），向源极跟随器（SF）控制极提供补偿的感测电压。

Description

超声波感测电路及其驱动方法、探测基板和触控面板 技术领域
本公开涉及传感技术领域，具体地，涉及超声波感测电路及其驱动方法、探测基板以及触控面板。
背景技术
当前，随着技术的高速发展，信息感测技术在例如触摸控制、指纹识别的技术领域中得到广泛应用。超声波感测技术是一种使用超声波信号来实现信息感测的技术。通常，在超声波感测电路中，超声波传感器发射超声波信号，接收所反射的超声波信号，并将所接收的超声波信号转换成电信号。然后，通过读取电路读取该电信号，从而实现信息的感测。
发明内容
本公开的实施例提供了超声波感测电路及其驱动方法、探测基板以及触控面板。
根据本公开的第一方面，提供了一种超声波感测电路，其包括超声波传感电路、输入电路、复位电路、存储电路、选择电路、源极跟随器以及补偿电路。超声波传感电路耦接第一节点和第一电源电压端，并被配置为发射并接收超声波信号，并产生与所接收的超声波信号对应的感测电压以提供给所述第一节点。输入电路耦接第一控制信号端、第一节点和第二节点，并被配置为根据来自第一控制信号端的第一控制信号，将第一节点的所述感测电压提供给第二节点。复位电路耦接复位控制信号端、第二节点和第一电源电压端耦接，并被配置为根据来自复位控制信号端的复位控制信号，将来自第一电源电压端的第一电源电压提供给第二节点以对第二节点的电压进行复位。存储电路耦接在第二节点和第二电源电压端之间，并被配置为存储第二节点与第二电源电压端之间的电压差。选择电路耦接选择信号端、第三电源电压端和第三节点，并被配置为根据来自选择信号端 的选择信号，将来自第三电源电压端的第三电源电压提供给第三节点。源极跟随器包括：与第三节点耦接的第一极；经由第四节点与补偿电路耦接的控制极；以及与输出端耦接的第二极，被配置为通过输出端输出对应于在第一极与控制极之间的电压的电流。补偿电路耦接第二电源电压端、第二控制信号端、第三控制信号端、第二节点、第三节点、第四节点和输出端，并被配置为接收该第二节点的感测电压，并根据该感测电压和第三电源电压，向源极跟随器的控制极提供补偿的感测电压。其中，第一电源电压和第二电源电压分别低于第三电源电压。
在本公开的实施例中，补偿电路包括第一晶体管、第二晶体管、第一电容、反相器、第三晶体管和第四晶体管。第一晶体管的控制极耦接第二控制信号端，第一晶体管的第一极耦接第二节点，第一晶体管的第二极耦接第四节点。第二晶体管的控制极耦接第二控制信号端，第二晶体管的第一极耦接第二电源电压端，第二晶体管的第二极耦接第五节点。第一电容的第一端耦接第三节点，第一电容的第二端耦接第五节点。反相器的第一极耦接第二控制信号端，反相器的第二极耦接第三晶体管的控制极。第三晶体管的第一极耦接第五节点，第三晶体管的第二极耦接第四节点。以及第四晶体管的控制极耦接第三控制信号端，第四晶体管的第一极耦接第二电源电压端，第四晶体管的第二极耦接输出端。进一步地第一晶体管、第二晶体管、第三晶体管和第四晶体管的类型相同。
在本公开的实施例中，补偿电路包括第一晶体管、第二晶体管、第一电容、第三晶体管和第四晶体管。第一晶体管的控制极耦接第二控制信号端，第一晶体管的第一极耦接第二节点，第一晶体管的第二极耦接第四节点。第二晶体管的控制极耦接第二控制信号端，第二晶体管的第一极耦接第二电源电压端，第二晶体管的第二极耦接第五节点。第一电容的第一端耦接第三节点，第一电容的第二端耦接第五节点。第三晶体管的控制极耦接第二控制信号端，第三晶体管的第一极耦接第五节点，第三晶体管的第二极耦接第四节点。第四晶体管的控制极耦接第三控制信号端，第四晶体管的第一极耦接第二电源电压端，第四晶体管的第二极耦接输出端。进一 步地，第三晶体管与第一晶体管、第二晶体管和第四晶体管的类型不同。
在本公开的实施例中，超声波传感电路包括超声波传感器和整流电路。超声波传感器耦接第一节点，整流电路耦接在第一节点与第一电源电压端之间。
在本公开的实施例中，输入电路包括第五晶体管。第五晶体管的控制极耦接第一控制信号端，第五晶体管的第一极耦接第一节点，第五晶体管的第二极耦接第二节点。
在本公开的实施例中，复位电路包括第六晶体管。第六晶体管的控制极耦接复位控制信号端，第六晶体管的第一极耦接第一电源电压端，第六晶体管的第二极耦接第二节点。
在本公开的实施例中，存储电路包括第二电容。第二电容的第一端耦接第二节点，第二电容的第二端耦接第二电源电压端。
在本公开的实施例中，选择电路包括第七晶体管。第七晶体管的控制极耦接选择信号端，第七晶体管的第一极耦接第三电源电压端，第七晶体管的第二极耦接第三节点。
在本公开的实施例中，第一电源电压端被提供公共电压。
根据本公开的第二方面，提供了一种探测基板。该探测基板包括多个根据本公开的第一方面的超声波感测电路。
根据本公开的第三方面，提供了一种触控面板。该触控面板包括根据本公开的第二方面所述的探测基板。
根据本公开的第四方面，提供一种用于驱动根据本公开的第一方面的超声波感测电路的方法。该方法包括：通过复位电路对第二节点处的电压进行复位；响应于超声波传感电路接收的超声波信号并产生与所接收的超声波信号对应的感测电压，通过输入电路将该感测电压提供给第二节点并存储在存储电路中；将感测电压提供给第四节点，并对补偿电路中的第一电容的两端充电，以使该第一电容的第一端的电压为第三电源电压，该第一电容的第二端的电压为第二电源电压；使第一电容的第一端的电压降低至感测电压与源极跟随器的阈值电压之和；以及使第一电容的第一端的电 压提高至第三电源电压，以向源极跟随器的控制极提供补偿的感测电压，该源极跟随器输出电流。
附图说明
为了更清楚地说明本公开的技术方案，下面将对实施例的附图进行简单说明。应当知道，以下描述的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。在附图中：
图1示出了已有的超声波感测电路的示例性电路图；
图2示出了根据本公开的实施例的超声波感测电路的示意性框图；
图3示出了根据本公开的实施例的超声波感测电路的示例性电路图；
图4示出了根据本公开的实施例的超声波感测电路的示例性电路图；
图5示出了如图2所示的超声波感测电路的工作过程中各信号的时序图；
图6示出了根据本公开的实施例的用于驱动超声波感测电路的方法的示意性流程图；
图7示出了根据本公开的实施例的探测基板的示意性框图；以及
图8示出了根据本公开的实施例的触控面板的示意性框图。
具体实施方式
为了使本公开的实施例的技术方案和优点更加清楚，下面将结合附图，对本公开的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例仅仅是本公开的一部分实施例，而并非全部的实施例。基于所描述的实施例，本领域的普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，也都属于本公开的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内技术人员所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制， 而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“耦接”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，并且可以是直接连接也可以通过中间介质间接连接。
图1示出了已有的超声波感测电路的示例性示意图。如图1所示，超声波感测电路100可包括超声波传感器UT、滤波二极管D、复位晶体管TRST、源极跟随器SF和选择开关晶体管TEM。超声波传感器UT发射并接收超声波信号，然后将所接收的超声波信号转化为电信号。该电信号被提供到源极跟随器SF的控制极。源极跟随器SF可根据该电信号的电压与第一极的电压VDD之间的电压差V GS，从第二极输出对应的电流I。根据该电流I，可确定相应的信息。在源极跟随器SF的第二极输出的电流I可通过公式(1)确定：
I＝K(V GS-V th) 2  公式(1)
其中，K表示系数，V th表示源极跟随器SF的阈值电压。
因此，通过公式(1)可以看出，在第二极输出的电流I与源极跟随器SF的阈值电压V th有关。因此，在已有的超声波感测电路中，源极跟随器的阈值电压的差异会直接影响所采集的信息的准确性。
针对上述准确性问题，本公开的实施例提供了一种超声波感测电路，其能够对源极跟随器的控制极的电压进行阈值电压补偿，使从第二极输出的电流I与阈值电压无关，从而避免了由阈值电压的差异造成的准确性问题。
本公开的实施例提供了超声波感测电路及其驱动方法、探测基板以及触控面板。下面结合附图对本公开的实施例及其示例进行详细说明。
图2示出了根据本公开的实施例的超声波感测电路200的示意性框图。如图2所示，超声波感测电路200可包括超声波传感电路210、输入电路220、复位电路230、存储电路240、选择电路250、源极跟随器SF以及补偿电路260。下面参照附图，对其进行详细描述。
超声波传感电路210可与第一节点J1和第一电源电压端耦接。超声波传感电路210可发射超声波信号，并接收反射的超声波信号。进一步地，超声波传感电路210可产生与所接收的超声波信号对应的感测电压V Data以提供给第一节点J1。在本公开的实施例中，第一电源电压端可以是公共电压端，例如，公共接地端。在这种情况下，第一电源电压V1是公共电压V com。可替换地，第一电源电压端也可接地，此时，第一电源电压V1为零。
输入电路220与第一控制信号端、第一节点J1和第二节点J2耦接。输入电路220从第一控制信号端接收第一控制信号CTR1，并根据第一控制信号CTR1，将第一节点J1的感测电压提供给第二节点J2。
复位电路230与复位控制信号端、第二节点J2和第一电源电压端耦接。复位电路230从复位控制信号端接收复位控制信号RESET，从第一电源电压端接收第一电源电压V1。复位电路230根据复位控制信号RESET，将第一电源电压V1提供给第二节点J2，以对该第二节点J2的电压进行复位。
存储电路240耦接在第二节点J2与第二电源电压端之间，并存储第二节点J2与第二电源电压端之间的电压差。在本公开的实施例中，第二电源电压端可以是接地端，此时，第二电源电压V2为零。
选择电路250与选择信号端、第三电源电压端和第三节点J3耦接。选择电路250从选择信号端接收选择信号EM，从第三电源电压端接收第三电源电压V3，并根据选择信号EM，将第三电源电压V3提供给第三节点J3。在本公开的实施例中，第三电源电压端用于向超声波感测电路200提供工作电压，因此，第三电源电压V3是高于第一电源电压V1和第二电源电压V2的高电平电压。
源极跟随器SF的控制极与第四节点J4耦接，第一极与第三节点J3耦接，第二极与输出端OUTPUT耦接。补偿电路260也与第四节点J4耦接，因此，源极跟随器SF的控制极经由第四节点J4与补偿电路260耦接。源极跟随器SF通过输出端OUTPUT输出对应于在第一极与控制极之间的电压的电流信号。
补偿电路260与第二电源电压端、第二控制信号端、第三控制信号端 第二节点J2、第三节点J3、第四节点J4和输出端OUTPUT耦接。补偿电路260从第二控制信号端接收第二控制信号CTR2，从第三控制信号端接收第三控制信号CTR3，并根据第二控制信号CTR2和第三控制信号CTR3，向第四节点J4提供补偿的感测电压，从而向源极跟随器SF的控制极提供补偿的感测电压。
以下通过示例性电路结构来对本公开的实施例提供的超声波感测电路进行描述。图3示出了根据本公开的实施例的超声波感测电路300的示例性电路图。如图3所示，超声波感测电路300可以包括第一晶体管T1至第七晶体管T7、第一电容C1、第二电容C2、反相器M以及源极跟随器SF。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其它特性相同的开关器件。本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，晶体管的栅极被称为控制极，除了栅极之外的两极被分别称为第一极和第二极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。在不考虑阈值电压的情况下，如果晶体管是P型晶体管，则导通电压为低电平电压，关断电压为高电平电压。如果晶体管是N型晶体管，则导通电压为高电平电压，关断电压为低电平电压。在考虑阈值电压的情况下，如果晶体管是P型晶体管，则当晶体管的控制极与第一极之间的电压差小于或等于阈值电压时，晶体管导通。如果晶体管是N型晶体管，则当晶体管的控制极与第一极之间的电压差大于或等于阈值电压时，晶体管导通。
如图3所示，补偿电路260包括第一晶体管T1、第二晶体管T2、第一电容C1、反相器M、第三晶体管T3和第四晶体管T4。下面，参照附图对补偿电路260进行具体描述。
第一晶体管T1的控制极耦接第二控制信号端，以接收第二控制信号CTR2。第一晶体管T1的第一极耦接第二节点J2，第二极耦接第四节点J4。在本实施例中，在第二控制信号CTR2为低电平时，第一晶体管T1导通， 第二节点J2的电压被提供给第四节点J4。
第二晶体管T2的控制极耦接第二控制信号端，以接收第二控制信号CTR2。第二晶体管T2的第一极耦接第二电源电压端，以接收第二电源电压V2。第二晶体管T2的第二极耦接第五节点J5。在本实施例中，当第二控制信号CTR2为低电平时，第二晶体管T2导通，所接收的第二电源电压V2被提供给第五节点J5。
第一电容C1的第一端耦接第三节点J3，第二端耦接第五节点J5，以存储第三节点J3的电压与第五节点J5的电压之间的电压差。在实施例中，当第三节点J3的电压改变，第五节点J5处于悬空状态时，由于第一电容C1所存储的电压差不变(即，电容的等势跳变作用)，因此，第五节点J5的电压变为第三节点J3的改变后的电压与第一电容C1的所存储的电压差的差。
反相器M的第一极耦接第二控制信号端，以接收第二控制信号CTR2。反相器M的第二极耦接第三晶体管T3的控制极。在实施例中，当第二控制信号CTR2的电压为高电平时，在反相器M的作用下，第三晶体管T3的控制极的电压为低电平。当第二控制信号CTR2的电压为低电平时，在反相器M的作用下，第三晶体管T3的控制极的电压为高电平。
第三晶体管T3的第一极耦接第五节点J5，第二极耦接第四节点J4。当第三晶体管T3的控制极的电压为低电平时，第三晶体管T3导通，第五节点J5的电压被提供给第四节点J4。
第四晶体管T4的控制极耦接第三控制信号端，以接收第三控制信号CTR3。第四晶体管T4的第一极耦接第二电源电压端，第二极耦接输出端OUTPUT。当第三控制信号CTR3为低电平时，第四晶体管T4导通，以使源极跟随器SF的第二极的电压变为第二电源电压V2。
超声波传感电路210包括超声波传感器UT和整流电路。超声波传感电路UT耦接第一节点J1。整流电路耦接在第一节点J1与第一电源电压端之间。在实施例中，整流电路是二极管D。第一节点J1处的反向电压(小于第一电源电压V1的部分)经由二极管D被提供给第一电源电压端。
输入电路220包括第五晶体管T5。第五晶体管T5的控制极耦接第一控制信号端，以接收第一控制信号CTR1。第五晶体管T5的第一极耦接第一节点J1，第二极耦接第二节点J2。在实施例中，当第一控制信号CTR1为低电平时，第五晶体管T5导通，第一节点J1处的感测电压被提供给第二节点J2。
复位电路230包括第六晶体管T6。第六晶体管T6的控制极耦接所述复位控制信号端，以接收复位控制信号RESET。第六晶体管T6的第一极耦接第一电源电压端，以接收第一电源电压V1。第六晶体管T6的第二极耦接第二节点J2。在实施例中，当复位控制信号RESET为低电平时，第六晶体管T6导通，从而将第一电源电压V1提供给第二节点J2，以对第二节点J2的电压进行复位。
存储电路240包括第二电容C2。第二电容C2的第一端耦接第二节点J2，第二端耦接第二电源电压端。在实施例中，当第二节点J2的电压为高电平时，第二电容C2存储并保持第二节点J2与第二电源电压端之间的电压差。
选择电路250包括第七晶体管T7。第七晶体管T7的控制极耦接选择信号端，以接收选择信号EM。第七晶体管T7的第一极耦接第三电源电压端，以接收第三电源电压V3。第七晶体管T7的第二极耦接第三节点J3。在实施例中，当选择信号EM为低电平时，第七晶体管T7导通，将第三电源电压V3提供给第三节点J3。
在图3所示的实施例中，第一晶体管T1至第七晶体管T7以及源极跟随器SF的类型相同，均是P型晶体管。本领域的技术人员知道，第一晶体管T1至第七晶体管T7以及源极跟随器SF也可以是N型晶体管。
此外，在本公开的其它实施例中，超声波传感电路210可以仅包括超声波传感器UT，其耦接到第一节点J1。此时，超声波感测电路300还可包括整流电路，例如二极管。该整流电路耦接在第二节点J2与第一电源电压端之间。
图4示出了根据本公开的另一实施例的超声波感测电路400的示例性 电路图。如图4所示，超声波感测电路400可以包括第一晶体管T1至第七晶体管T7、第一电容C1和第二电容C2以及源极跟随器SF。与图3所示的超声波感测电路300不同，在图4所示的补偿电路260中，使用单个第三晶体管T3′代替图3中的反相器M和第三晶体管T3。
第三晶体管T3′的控制极耦接第二控制信号端，以接收第二控制信号CTR2。第三晶体管T3′的第一极耦接第五节点J5，第二极耦接第四节点J4。在实施例中，当第二控制信号CTR2为高电平时，第三晶体管T3′导通，将第五节点J5的电压提供给第四节点J4。图4所示的超声波感测电路400的其余的电路组成部分的结构和功能与图3所示的超声波感测电路300的电路组成部分相同，在此不再赘述。
在图4所示的实施例中，第一晶体管T1、第二晶体管T2、第四晶体管T4至第七晶体管T7以及源极跟随器SF均是P型晶体管。第三晶体管T3′与其余晶体管的类型不同，是N型晶体管。本领域的技术人员知道，第一晶体管T1、第二晶体管T2、第四晶体管T4至第七晶体管T7以及源极跟随器SF也可以是N型晶体管，而第三晶体管T3′是P型晶体管。
下面结合图5中的信号时序图，对图3中所示的超声波感测电路300的工作过程进行说明。
图5示出了如图3所示的超声波感测电路300的工作过程中各信号的时序图。可以理解的是，图5所示的信号时序图中的信号电压只是示意性的，不代表真实电压值。
如图5所示，在第1时段，在复位控制信号端提供低电平的复位控制信号RESET，第六晶体管T6导通。所接收的第一电源电压V1被提供给第二节点J2，以对第二节点J2的电压进行复位。
在第2时段，超声波传感电路300通过发射并接收超声波信号，产生与所接收的超声波信号对应的感测电压V Data。在实施例中，与所接收的超声波信号对应的感测电压可能是交流电压，二极管D通过整流将该交流电压中的反向电压(小于第一电源电压V1的部分)去除，从而在第一节点J1处产生仅包括正向电压(大于第一电源电压V1的部分)的感测电压V Data。 另外，超声波感测电路300接收低电平的第一控制信号CTR1，第五晶体管T5导通，第一节点J1处的感测电压V Data被提供给第二节点J2。在实施例中，感测电压V Data与第三电源电压V 3之间的差小于阈值电压V th，即V Data-V3<-|V th|。
在第3时段，在第二控制信号端提供低电平的第二控制信号CTR2，第二晶体管T2导通，第二电源电压V2被提供给第五节点J5，第一晶体管T1导通，超声波感测电路300接收低电平的选择信号EM，第七晶体管T7导通，第三电源电压V3被提供给第三节点J3。第一电容C1存储第三节点J3与第五节点J5之间的电压差为V3-V2。如前所述，在本实施例中，第二电源电压端为接地端，因此第三节点J3与第五节点J5之间的电压差等于V3。另外，当第一晶体管T1导通时，感测电压V Data被提供给第四节点J 4。由于V Data-V3<-|V th|，因此，源极跟随器SF导通。
在第4时段，在第二控制信号端提供低电平的第二控制信号CTR2，第二晶体管T2导通，第二电源电压V2被继续提供给第五节点J5。源极跟随器SF保持导通。超声波感测电路300接收低电平的第三控制信号CTR3，第四晶体管T4导通。因此，第三节点J3的电压被放电(即，第一电容C1被放电)，直至源极跟随器SF关断。在源极跟随器SF关断时，第三节点J3的电压为V Data+|V th|。此时，第一电容C1存储的电压差为V Data+|V th|-V2，即V Data+|V th|。
在第5时段，在选择信号端提供低电平的选择信号EM，第七晶体管T7导通，第三电源电压V3被提供给第三节点J3，因此第三节点J3的电压为V3。由于第一电容C1的等势跳变的作用，第五节点J5的电压为V3-(V Data+|V th|)。超声波感测电路300接收高电平的第二控制信号CTR2，在反向器M的作用下，第三晶体管T3导通，第五节点J5的电压被提供给第四节点J4，因此第四节点J4的电压为V3-(V Data+|V th|)。从而，向源极跟随器SF的控制极提供补偿的感测电压V3-(V Data+|V th|)。此时根据公式(1)可以计算从源极跟随器的第二极输出的电流I，如公式(2)所示：
I＝K(V GS-V th) 2
＝K[(V3-V Data-|V th|)-V3+|V th|] 2
＝K·V Data 2         公式(2)
其中，K表示系数。
根据公式(2)可以得出，在源极跟随器SF的第二极输出的电流I与其阈值电压V th无关。因此，所采集的信息的准确性不受源极跟随器的阈值电压V th的影响。
此外，本公开的实施例还提供了用于驱动超声波感测电路的方法。图6示出了根据本公开的实施例的用于驱动超声波感测电路的方法的示意性流程图。超声波感测电路可以是基于本公开的实施例的任何可适用的超声波感测电路。
在步骤610，通过复位电路230对第二节点J2的电压进行复位。在实施例中，复位电路230根据复位控制信号RESET，将所接收的低电平的第一电源电压V1提供给第二节点J2，以对第二节点J2进行复位。
在步骤620，响应于超声波传感电路210接收超声波信号并产生与所接收的超声波信号对应的感测电压V Data，通过输入电路220将该感测电压V Data提供给第二节点J2并存储在存储电路240中。在实施例中，超声波传感器UT发送超声波信号，并接收反射回的超声波信号，获得对应的交流电压。然后，整流电路对该交流电压进行整流，以在第一节点J1处产生仅包括正向电压的感测电压V Data。输入电路220根据第一控制信号CTR1，将第一节点J1处的感测电压V Data提供给第二节点J2。存储电路240存储感测电压V Data与第二电源电压V2之间的电压差。
在步骤630，将感测电压V Data提供给第四节点J4，并对补偿电路260中的第一电容C1的两端充电，以使第一电容C1的第一端的电压为第三电源电压V3，第一电容C1的第二端的电压为第二电源电压V2。在实施例中，根据选择信号EM，将第三电源电压V3提供给第三节点J3，因此第一电容C1的第一端的电压为V3。根据第二控制信号CTR2，将第二电源电压V2提供给第五节点J5，因此，第一电容C1的第二端的电压为V2。如前所述， 第二电源电压端是为接地端，因此第一电容C1存储的电压差为V3-V2，即V3。
在步骤640，使第一电容C1的第一端的电压降低至感测电压V Data与源极跟随器SF的阈值电压V th之和。在实施例中，根据第三控制信号CTR3，第五晶体管T5导通。并且源极跟随器SF导通，因此第三节点J3被放电(即，第一电容C1被放电)，直至源极跟随器SF的控制极与第一极之间的电压小于其阈值电压，即|V GS|<|V th|，源极跟随器SF关断。如前所述，源极跟随器SF的控制极的电压为V Data，因此源极跟随器SF的第一极(或第三节点J3)的电压为V Data+|V th|。此时，第一电容C1存储的电压差为V Data+|V th|。
在步骤650，使第一电容C1的第一端的电压提高至第三电源电压V3，以向源极跟随器SF的控制极提供补偿的感测电压，源极跟随器SF输出电流。在实施例中，根据选择信号EM，重新将第三电源电压V3提供给第三节点J3，因此第三节点J3的电压为V3。由于第一电容C1的等势跳变的作用，第五节点J5的电压为V3-(V Data+|V th|)。根据第二控制信号CTR2，第三晶体管T3导通，第五节点J5的电压被提供给第四节点J4，因此第四节点J4的电压为V3-(V Data+|V th|)。从而，向源极跟随器SF的控制极提供补偿的感测电压V3-(V Data+|V th|)。然后，源极跟随器SF根据该补偿后的电压，通过输出端OUTPUT输出电流信号。在实施例中，根据上述公式(2)可以得出，在源极跟随器SF的第二极输出的电流I与其阈值电压V th无关。即，所采集的信息的准确性不受源极跟随器SF的阈值电压V th的影响。
本领域技术人员可以理解，以上各步骤虽然按顺序描述，但并不构成对方法顺序的限定，本公开的实施例也可以以任何其它合适顺序实施。
另一方面，本公开的实施例还提供了探测基板。图7示出了根据本公开的实施例的探测基板700的示意性框图。在图7中，探测基板700可包括多个根据本公开的实施例所述的超声波感测电路200。
此外，本公开的实施例还提供了包括上述探测基板的触控面板。图8 示出了根据本公开的实施例的触控面板800的示意性框图。在图8中，触控面板800如图7所示的探测基板700。在实施例中，触控面板可以是具有信息采集功能(例如，指纹识别功能或触摸控制功能等)的液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等。以上对本公开的若干实施方式进行了详细描述，但本公开的保护范围并不限于此。显然，对于本领域的普通技术人员来说，在不脱离本公开的精神和范围的情况下，可以对本公开的实施例进行各种修改、替换或变形。本公开的保护范围由所附权利要求限定。

Claims (12)

  1. 一种超声波感测电路，包括：超声波传感电路、输入电路、复位电路、存储电路、选择电路、源极跟随器以及补偿电路，其中，
    所述超声波传感电路耦接第一节点和第一电源电压端，并被配置为发射并接收超声波信号，并产生与所接收的超声波信号对应的感测电压以提供给所述第一节点；
    所述输入电路耦接第一控制信号端、所述第一节点和第二节点，并被配置为根据来自所述第一控制信号端的第一控制信号，将所述第一节点的所述感测电压提供给所述第二节点；
    所述复位电路耦接复位控制信号端、所述第二节点和所述第一电源电压端，并被配置为根据来自所述复位控制信号端的复位控制信号，将来自所述第一电源电压端的第一电源电压提供给所述第二节点以对所述第二节点的电压进行复位；
    所述存储电路耦接在所述第二节点与第二电源电压端之间，并被配置为存储所述第二节点与所述第二电源电压端之间的电压差；
    所述选择电路耦接选择信号端、第三电源电压端和第三节点，并被配置为根据来自所述选择信号端的选择信号，将来自所述第三电源电压端的第三电源电压提供给所述第三节点；
    所述源极跟随器包括：与所述第三节点耦接的第一极；经由第四节点与所述补偿电路耦接的控制极；以及与输出端耦接的第二极，被配置为通过所述输出端输出对应于在所述第一极与所述控制极之间的电压的电流；
    所述补偿电路耦接所述第二电源电压端、第二控制信号端、第三控制信号端、所述第二节点、所述第三节点、所述第四节点和所述输出端，并被配置为接收所述第二节点的所述感测电压，并根据所述感测电压和所述第三电源电压，向所述源极跟随器的所述控制极提供补偿的感测电压；
    其中，所述第一电源电压和所述第二电源电压分别低于所述第三电源电压。
  2. 根据权利要求1所述的超声波感测电路，其中，所述补偿电路包括 第一晶体管、第二晶体管、第一电容、反相器、第三晶体管和第四晶体管，
    其中，所述第一晶体管的控制极耦接所述第二控制信号端，所述第一晶体管的第一极耦接所述第二节点，所述第一晶体管的第二极耦接所述第四节点；
    其中，所述第二晶体管的控制极耦接所述第二控制信号端，所述第二晶体管的第一极耦接所述第二电源电压端，所述第二晶体管的第二极耦接第五节点；
    其中，所述第一电容的第一端耦接所述第三节点，所述第一电容的第二端耦接所述第五节点；
    其中，所述反相器的第一极耦接所述第二控制信号端，所述反相器的第二极耦接所述第三晶体管的控制极；以及
    其中，所述第三晶体管的第一极耦接所述第五节点，所述第三晶体管的第二极耦接所述第四节点；以及
    其中，所述第四晶体管的控制极耦接所述第三控制信号端，所述第四晶体管的第一极耦接所述第二电源电压端，所述第四晶体管的第二极耦接所述输出端；
    其中，所述第一晶体管、所述第二晶体管、所述第三晶体管和所述第四晶体管的类型相同。
  3. 根据权利要求1所述的超声波感测电路，其中，所述补偿电路包括第一晶体管、第二晶体管、第一电容、第三晶体管和第四晶体管，
    其中，所述第一晶体管的控制极耦接所述第二控制信号端，所述第一晶体管的第一极耦接所述第二节点，所述第一晶体管的第二极耦接所述第四节点；
    其中，所述第二晶体管的控制极耦接所述第二控制信号端，所述第二晶体管的第一极耦接所述第二电源电压端，所述第二晶体管的第二极耦接所述第五节点；
    其中，所述第一电容的第一端耦接所述第三节点，所述第一电容的第二端耦接所述第五节点；以及
    其中，所述第三晶体管的控制极耦接所述第二控制信号端，所述第三晶体管的第一极耦接所述第五节点，所述第三晶体管的第二极耦接所述第四节点；以及
    其中，所述第四晶体管的控制极耦接所述第三控制信号端，所述第四晶体管的第一极耦接所述第二电源电压端，所述第四晶体管的第二极耦接所述输出端；
    其中，所述第三晶体管与所述第一晶体管、所述第二晶体管和所述第四晶体管的类型不同。
  4. 根据权利要求1至3中任一项所述的超声波感测电路，其中，所述超声波传感电路包括超声波传感器和整流电路，其中，所述超声波传感器耦接所述第一节点，所述整流电路耦接在所述第一节点与所述第一电源电压端之间。
  5. 根据权利要求1至3中任一项所述的超声波感测电路，其中，所述输入电路包括第五晶体管，所述第五晶体管的控制极耦接所述第一控制信号端，所述第五晶体管的第一极耦接所述第一节点，所述第五晶体管的第二极耦接所述第二节点。
  6. 根据权利要求1至3中任一项所述的超声波感测电路，其中，所述复位电路包括第六晶体管，所述第六晶体管的控制极耦接所述复位控制信号端，所述第六晶体管的第一极耦接所述第一电源电压端，所述第六晶体管的第二极耦接所述第二节点。
  7. 根据权利要求1至3中任一项所述的超声波感测电路，其中，所述存储电路包括第二电容，所述第二电容的第一端耦接所述第二节点，所述第二电容的第二端耦接所述第二电源电压端。
  8. 根据权利要求1至3中任一项所述的超声波感测电路，其中，所述选择电路包括第七晶体管，所述第七晶体管的控制极耦接所述选择信号端，所述第七晶体管的第一极耦接所述第三电源电压端，所述第七晶体管的第二极耦接所述第三节点。
  9. 根据权利要求1所述的超声波感测电路，其中，所述第一电源电压 端被提供公共电压。
  10. 一种探测基板，包括多个如权利要求1至9中任一项所述的超声波感测电路。
  11. 一种触控面板，包括如权利要求10所述的探测基板。
  12. 一种用于驱动如权利要求1至9中任一项所述的超声波感测电路的方法，包括：
    通过复位电路对第二节点的电压进行复位；
    响应于超声波传感电路接收的超声波信号并产生与所接收的超声波信号对应的感测电压，通过输入电路将所述感测电压提供给所述第二节点并存储在存储电路中；
    将所述感测电压提供给第四节点，并对补偿电路中的第一电容的两端充电，以使所述第一电容的第一端的电压为第三电源电压，所述第一电容的第二端的电压为第二电源电压；
    使所述第一电容的所述第一端的电压降低至所述感测电压与源极跟随器的阈值电压之和；以及
    使所述第一电容的所述第一端的电压提高至所述第三电源电压，以向所述源极跟随器的控制极提供补偿的感测电压，所述源极跟随器输出电流。
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