WO2020228425A1

WO2020228425A1 - Array substrate, manufacturing method therefor, display panel, and display device

Info

Publication number: WO2020228425A1
Application number: PCT/CN2020/081583
Authority: WO
Inventors: 黎文秀; 陈强; 方业周; 王旭; 陈志刚; 彭艳召; 任伟; 夏高飞; 刘耀祖; 高云; 彭利满
Original assignee: 京东方科技集团股份有限公司; 鄂尔多斯市源盛光电有限责任公司
Priority date: 2019-05-15
Filing date: 2020-03-27
Publication date: 2020-11-19
Also published as: CN110133928A; CN110133928B

Abstract

An array substrate, a manufacturing method therefor, and a display panel, wherein a black matrix layer (102) of the array substrate is located on one side of a base substrate (101), and a transistor device layer (103) and a color filter layer (104) are located on the other side of the base substrate (101). The black matrix layer (102), and the transistor device layer (103) and the color filter layer (104) are located on different sides of the base substrate (101), such that alignment marks (1021) are not blocked by the black matrix layer (102) when the transistor device layer (103) and the color filter layer (104) in the array substrate are formed, thereby ensuring that a mask can be accurately aligned with the alignment marks (1021), and ensuring high alignment accuracy for each layer in the finished array substrate.

Description

Array substrate and manufacturing method thereof, display panel and display device

This disclosure claims the priority of a Chinese patent application filed on May 15, 2019 with the application number 201910407090.9 and the invention title "Array substrate and its manufacturing method, display panel", the entire content of which is incorporated into this disclosure by reference.

Technical field

The present disclosure relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, a display panel, and a display device.

Background technique

The color filter (CF) is fabricated on the array substrate (array), that is, COA (CF on array) technology, which can solve the string in thin film transistor liquid crystal display (TFT-LCD) Color and color mixing issues.

In the related art, when manufacturing an array substrate using COA technology, after forming a transistor device layer and a passivation layer on the base substrate, a black matrix (BM) can be sequentially formed on the side of the passivation layer away from the transistor device layer. ) Layer and color filter (also called color film layer).

Summary of the invention

The present disclosure provides an array substrate, a manufacturing method thereof, a display panel, and a display device. The technical solution is as follows:

In one aspect, an array substrate is provided, and the array substrate includes:

A base substrate, a black matrix layer on one side of the base substrate, and a transistor device layer and a color film layer on the other side of the base substrate and stacked in sequence;

Wherein, the orthographic projection of the black matrix layer on the base substrate covers the orthographic projection of the transistors in the transistor device layer on the base substrate.

Optionally, the base substrate has a display area and a peripheral area surrounding the display area; a portion of the black matrix layer located in the peripheral area is provided with at least two alignment mark holes.

Optionally, the base substrate is a rectangular substrate; a portion of the black matrix layer located in the peripheral area is provided with four alignment mark holes;

The orthographic projections of the four alignment mark holes on the base substrate are respectively located at four corners of the base substrate.

Optionally, the base substrate is a rectangular substrate; a portion of the black matrix layer located in the peripheral area is provided with two alignment mark holes;

The orthographic projections of the two alignment mark holes on the base substrate are respectively located at two opposite corners of the base substrate.

Optionally, the orthographic projection of each of the alignment mark holes on the base substrate is in a cross shape.

Optionally, the array substrate further includes:

A protective layer located on the side of the black matrix layer away from the base substrate.

Optionally, the material of the protective layer includes indium tin oxide, silicon nitride or silicon oxide.

Optionally, the array substrate further includes: a light-shielding layer located between the transistor device layer and the base substrate;

A first passivation layer located between the transistor device layer and the color film layer;

And a flat layer, a common electrode layer, a second passivation layer, a pixel electrode layer, a spacer and an alignment layer which are located on the side of the color filter layer away from the base substrate and are sequentially stacked.

In another aspect, a manufacturing method of an array substrate is provided, and the method includes:

Forming a black matrix layer on one side of the base substrate;

Forming a transistor device layer and a color film layer in sequence on the other side of the base substrate;

Optionally, the base substrate has a display area and a peripheral area surrounding the display area; the forming a black matrix layer on one side of the base substrate includes:

Forming a black matrix material film layer covering the display area and the peripheral area on one side of the base substrate;

The black matrix material film layer is patterned to obtain a black matrix layer, and at least two alignment mark holes are formed in the portion of the black matrix layer located in the peripheral area.

Optionally, forming a transistor device layer and a color filter layer in sequence on the other side of the base substrate includes:

Aligning the mask plate based on the at least two alignment mark holes;

The mask is used to sequentially form a transistor device layer and a color film layer on the other side of the base substrate.

Optionally, the alignment of the mask plate based on the at least two alignment mark holes includes:

Recognizing each of the alignment mark holes through an optical camera;

Adjust the position of the mask plate according to the identified position of each of the alignment mark holes, so that the alignment mark points on the mask plate are aligned with the alignment mark holes.

Optionally, the base substrate is a rectangular substrate; the part of the black matrix layer located in the peripheral area is formed with four alignment mark holes; the four alignment mark holes are in the base substrate The orthographic projections are respectively located at the four corners of the base substrate.

Optionally, after the black matrix layer is formed on one side of the base substrate, the method further includes:

A protective layer is formed on the side of the black matrix layer away from the base substrate.

Optionally, the forming a protective layer on the side of the black matrix layer away from the base substrate includes:

Depositing an indium tin oxide film, a silicon nitride film or a silicon oxide film on the side of the black matrix layer away from the base substrate to obtain a protective layer.

Optionally, before sequentially forming the transistor device layer and the color filter layer on the other side of the base substrate, the method further includes: forming a light shielding layer on the other side of the base substrate;

After forming the transistor device layer on the other side of the base substrate and before forming the color filter layer, the method further includes:

Forming a first passivation layer on the side of the transistor device layer away from the base substrate;

After forming the color filter layer, the method further includes:

A flat layer, a common electrode layer, a second passivation layer, a pixel electrode layer, a spacer, and an alignment layer are sequentially formed on the side of the color filter layer away from the base substrate.

In yet another aspect, a display panel is provided. The display panel includes the array substrate as described in the above aspect, the cell-aligned substrate, and liquid crystals located between the array substrate and the cell-aligned substrate.

Optionally, the box-matching substrate includes: a glass substrate, and a protective film and an alignment layer that are located on a side of the glass substrate close to the liquid crystal and stacked in sequence.

In yet another aspect, a display device is provided, the display device comprising: the display panel as described in the above aspect, and a driving circuit connected to the display panel, the driving circuit being used for The transistor provides the drive signal.

Description of the drawings

In order to more clearly describe the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained from these drawings without creative work.

FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure;

2 is a schematic diagram of a partial structure of an array substrate provided by an embodiment of the present disclosure;

FIG. 3 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure;

4 is a flowchart of a manufacturing method of an array substrate provided by an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of the alignment of the mask plate when forming a color filter layer according to an embodiment of the present disclosure;

FIG. 6 is a flowchart of another method for manufacturing an array substrate provided by an embodiment of the present disclosure;

FIG. 7 is another schematic diagram of the alignment of the mask when forming the color film layer according to the embodiment of the present disclosure;

FIG. 8 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

FIG. 9 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

FIG. 10 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the following further describes the embodiments of the present disclosure in detail with reference to the accompanying drawings.

In the related art, since the material forming the black matrix layer does not transmit light, when the mask is used to form the black matrix layer and the color film layer, the mark on the mask cannot be aligned with the transistor device layer. The alignment mark points are aligned, resulting in low alignment accuracy of each film layer in the formed array substrate.

In order to ensure that the alignment marks on the mask plate can be accurately aligned with the alignment marks on the transistor device layer, a new black matrix material can be developed, which can transmit light at a specific wavelength, thereby It can be ensured that when the mask is used to expose the new black matrix material, the alignment mark on the mask can be aligned with the alignment mark on the transistor device layer. However, the development of new black matrix materials is difficult, expensive, and requires a lot of manpower.

The embodiments of the present disclosure provide an array substrate. Referring to FIG. 1, the array substrate may include:

A base substrate 101, a black matrix layer 102 on one side of the base substrate 101, and a transistor device layer 103 and a color film layer 104 on the other side of the base substrate 101 and stacked in sequence.

Wherein, the orthographic projection of the black matrix layer 102 on the base substrate 101 can cover the orthographic projection of the transistors in the transistor device layer 103 on the base substrate 101.

In the embodiment of the present disclosure, when manufacturing the array substrate, the black matrix layer 102 may be formed on one side of the base substrate 101 first, and then the black matrix layer 102 may be sequentially formed on the other side of the base substrate 101. Aligned transistor device layer 103 and color filter layer 104. Since the black matrix layer 102 is located on a different side of the base substrate 101 from the transistor device layer 103 and the color film layer 104, when a mask is used to form the transistor device layer 103 and the color film layer 104, the black matrix layer 102 will not block the Position marking points (for example, the alignment marking points on the light-shielding layer located on one side of the base substrate 101), so the mask can be accurately aligned with the positioning marking points, so that the manufactured array substrate includes The alignment accuracy of each film layer is high.

In summary, the embodiments of the present disclosure provide an array substrate. Since the black matrix layer in the array substrate is located on one side of the base substrate, the transistor device layer and the color film layer are located on the other side of the base substrate, namely The black matrix layer is located on a different side of the base substrate from the transistor device layer and the color film layer. Therefore, when forming the transistor device layer and the color film layer in the array substrate, the black matrix layer will not block the alignment mark points, which can ensure that the mask can be accurately aligned with the alignment mark points, thereby ensuring the final manufactured array The alignment accuracy of each film layer in the substrate is relatively high.

In the embodiment of the present disclosure, the base substrate 101 has a display area and a peripheral area surrounding the display area. FIG. 2 is a schematic diagram of a partial structure of an array substrate provided by an embodiment of the present disclosure. As shown in FIG. 2, the portion of the black matrix layer 102 located in the peripheral area may be provided with at least two alignment mark holes 1021. Each alignment mark hole 1021 penetrates the black matrix layer 102. That is, the alignment mark hole 1021 can transmit light.

In the process of manufacturing the array substrate, after the black matrix layer 102 is formed on one side of the base substrate 101, when subsequent layers such as the transistor device layer 103 and the color film layer 104 are formed on the other side of the base substrate 101, you can directly The at least two alignment mark holes 1021 are used as alignment mark points to align the mask plate. Therefore, there is no need to form new alignment mark points on each film layer, and the manufacturing process of the array substrate is simplified.

In the embodiment of the present disclosure, as shown in FIG. 2, the base substrate 101 may be a rectangular substrate. The portion of the black matrix layer 102 in the peripheral area may be provided with four alignment mark holes 1021, and the orthographic projections of the four alignment mark holes 1021 on the base substrate 101 may be respectively located at four corners of the base substrate 101.

Alternatively, the part of the black matrix layer 102 located in the peripheral area may also be provided with two alignment mark holes 1021, and the orthographic projection of the two alignment mark holes 1021 on the base substrate 101 may be located on the base substrate 101 The two opposite corners, that is, the connection line of the orthographic projection of the two alignment mark holes 1021, may be collinear with a diagonal line of the base substrate 101.

Or, the part of the black matrix layer 102 located in the peripheral area may be provided with three alignment mark holes 1021, and the orthographic projection of the three alignment mark holes 1021 on the base substrate 101 may be located on the triangle of the base substrate 101. .

Optionally, in the embodiment of the present disclosure, the orthographic projection of each alignment mark hole 1021 in the black matrix layer 102 on the base substrate 201 may be a cross, that is, each alignment mark hole 1021 may be a cross. hole. Alternatively, the orthographic projection of the alignment mark hole 1021 on the base substrate 201 may also be other shapes such as a circle or a rectangle. The embodiment of the present disclosure does not limit the shape of the alignment mark hole 1021.

FIG. 3 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure. Referring to FIG. 3, the array substrate 10 may further include: a protective layer 105 on the side of the black matrix layer 102 away from the base substrate 101. The protective layer 105 can be used to protect the black matrix layer 102 and prevent the black matrix layer 102 from being scratched, thereby effectively improving the service life of the array substrate.

Optionally, the material of the protective layer 105 may include indium tin oxide (ITO), silicon nitride (SiN), or silicon oxide (SiO ₂ ). For example, the material of the protective layer 105 may be ITO.

3, the array substrate 10 may further include: a light shield (LS) 106 disposed between the transistor device layer 103 and the base substrate 101, and a light shield (LS) 106 disposed between the transistor device layer 103 and the color film layer 104 A first passivation layer (PVX) 107, a planarization layer (PL) 108, a common electrode layer 109, a second passivation layer 110, a planarization layer (PL) 108, a common electrode layer 109, a second passivation layer 110, The pixel electrode layer 111, the spacer (PS) 112, and the alignment layer 113. Wherein, both the common electrode layer 109 and the pixel electrode layer 111 can be made of ITO. The alignment layer 113 may be made of polyimide (PI).

As can be seen from FIG. 3, the transistor device layer 103 may include: an active layer 1031, a gate insulator (GI) 1032, a gate electrode (gate ) 1033, an inter-layer dielectric (ILD) 1034, and source and drain electrodes 1035. Wherein, the source and drain electrodes 1035 may include a source (source) and a drain (drain). Wherein, the active layer 1031 may be made of polycrystalline silicon (P-Si) material.

Optionally, referring to FIG. 3, each transistor in the transistor device layer 103 may include two gate electrodes 1033, that is, the transistor may be a double gate transistor.

In summary, the embodiments of the present disclosure provide an array substrate. Since the black matrix layer in the array substrate is located on one side of the base substrate, the transistor device layer and the color film layer are located on the other side of the base substrate, namely The black matrix layer is located on a different side of the base substrate from the transistor device layer and the color film layer. Therefore, when forming the transistor device layer and the color film layer in the array substrate, the black matrix layer will not block the alignment mark points, which can ensure that the mask can be accurately aligned with the contrast mark points, thereby ensuring the final manufactured array substrate The alignment accuracy of each layer in the film is higher.

The embodiments of the present disclosure provide a method for manufacturing an array substrate. The method can be used to manufacture the array substrate provided in the above embodiments, for example, it can be used to manufacture the array substrate shown in any one of FIGS. 1 to 3. Referring to Figure 4, the method may include:

Step 201, forming a black matrix layer on one side of the base substrate.

A black matrix material can be coated on one side of the base substrate to form a black matrix material film layer. Then, the black matrix material film layer can be patterned to form a black matrix layer. Among them, the process of patterning treatment may include: exposure and development processes.

Step 202: sequentially forming a transistor device layer and a color film layer on the other side of the base substrate.

Wherein, the orthographic projection of the black matrix layer on the base substrate can cover the orthographic projection of the transistors in the transistor device layer on the base substrate.

In the embodiment of the present disclosure, when manufacturing the array substrate, a black matrix layer may be formed on one side of the base substrate, and then transistors aligned with the black matrix layer may be sequentially formed on the other side of the base substrate. Device layer and color film layer. Since the black matrix layer is located on a different side of the base substrate from the transistor device layer and the color film layer, when a mask is used to form the transistor device layer and the color film layer, the black matrix layer will not block the alignment marking points (such as the light shielding layer). In this way, it can be ensured that the alignment accuracy of each film layer included in the manufactured array substrate is high. Wherein, the alignment mark points in the light shielding layer may be formed after the mask plate and the black matrix layer are aligned.

For example, as shown in FIG. 5, when forming the red film layer in the color film layer 104, a layer of red filter material film 1041 can be formed first, and then based on at least two alignment mark holes 1021 in the black matrix layer 102 The mask 20 is aligned, and finally a red film layer is formed through processes such as exposure, development, and etching.

In summary, the embodiments of the present disclosure provide a method for manufacturing an array substrate, which can form a black matrix layer on one side of a base substrate, and then sequentially form a transistor device layer and a color on the other side of the base substrate. The film layer, the black matrix layer, is located on a different side of the base substrate from the transistor device layer and the color film layer. When forming the transistor device layer and the color film layer, the black matrix layer will not block the alignment mark points, and can ensure the alignment of the mask plate with the alignment mark points, so the manufacturing method of the array substrate provided by the embodiment of the present disclosure is used The alignment accuracy of each film layer in the array substrate is relatively high.

In the embodiment of the present disclosure, in the process of manufacturing the array substrate, after the black matrix layer is formed on one side of the base substrate, when the subsequent film layers such as the transistor device layer and the color film layer are formed on the other side of the base substrate, At least two alignment mark holes in the black matrix layer can be directly used as alignment mark points to align the mask plate, that is, the subsequent film layer can be formed with the black matrix layer as the base layer.

Taking the array substrate shown in FIG. 3 as an example, the manufacturing method of the array substrate provided by the embodiment of the present disclosure is introduced. Referring to FIG. 6, the method may include:

Step 301, forming a black matrix material film layer covering the display area and the peripheral area on one side of the base substrate.

For example, a process such as vapor deposition, inkjet printing, spray coating, doctor blade coating, or dip coating may be used to deposit a black matrix material on one side of the base substrate to form a black matrix material film layer.

Step 302: Perform a patterning process on the black matrix material film layer to obtain a black matrix layer, and at least two alignment mark holes are formed in a portion of the black matrix layer located in the peripheral area.

Wherein, the process of the patterning treatment may include processes such as exposure and development.

For example, as shown in FIG. 2, the black matrix layer 102 may include four alignment mark holes 1021, and the orthographic projections of the four alignment mark holes 1021 on the base substrate 101 may be respectively located on the base substrate. The four corners of 101.

FIG. 7 is another schematic diagram of the alignment of the mask plate when forming the color filter layer according to the embodiment of the present disclosure. Referring to FIG. 7, since at least two alignment mark holes 1021 are formed in the portion of the black matrix layer 102 located in the peripheral area, the subsequent film layer (such as the color film layer shown in FIG. 7) included in the array substrate is formed. At this time, each alignment mark hole 1021 in the black matrix layer 102 can be identified by the optical camera 30 to adjust the position of the mask plate 20 so that the alignment mark points 201 on the mask plate 20 are aligned with the alignment mark points 201 in the black matrix layer 102. The alignment of the bit mark holes 1021 can ensure the alignment accuracy of the respective film layers included in the manufactured array substrate. Optionally, the optical camera 30 may be a high-power optical camera.

Step 303, forming a protective layer on the side of the black matrix layer away from the base substrate.

In the embodiments of the present disclosure, a plasma enhanced chemical vapor deposition (PECVD) process can be used to deposit an ITO film, a SiN film, or a SiO2 film on the side of the black matrix layer away from the base substrate for protection Floor.

Step 304, forming a light shielding layer on the other side of the base substrate on which the protective layer is formed.

Further, the base substrate on which the black matrix layer and the protective layer are formed can be turned over, and a light shielding layer can be formed on the other side of the base substrate.

For example, a metal material can be deposited on the other side of the base substrate to obtain a light shielding layer. Optionally, the metal material may be molybdenum.

Step 305: sequentially forming a transistor device layer and a color film layer on the side of the light shielding layer away from the base substrate.

In the embodiments of the present disclosure, when forming each film layer and color filter layer in the transistor device layer, for the target film layer (such as the active layer, the gate electrode, or the source and drain electrode) that needs to be formed using a mask, the For the target film layer, the mask plate can be aligned based on at least two alignment mark holes in the black matrix layer, that is, the alignment mark points provided on the mask plate can be aligned with at least two of the black matrix layer. The alignment mark holes are aligned one by one to ensure the alignment accuracy of the formed target film layer and the black matrix layer. Wherein, the process of forming the target film layer by using the mask may include: coating a target material film, and patterning the target material film to obtain the target film layer. The patterning process may include: photoresist coating, exposure, development, etching, and photoresist stripping.

In the embodiment of the present disclosure, a plurality of masks with different patterns need to be used in the process of forming the transistor device layer, for example, 4 to 5 masks with different patterns are usually used. When forming the color film layer, it is also necessary to use multiple masks with different patterns, for example, usually 3 masks with different patterns are used.

Taking the array substrate shown in FIG. 3 as an example, the process of sequentially forming the transistor device layer and the color film layer on the side of the light shielding layer away from the base substrate is introduced. The process may include:

Step 3051, forming an active layer on the base substrate where the light shielding layer is formed.

Optionally, a process such as sputtering, thermal evaporation, or PECVD may be used to deposit an active material film layer on the base substrate on which the light shielding layer is formed, and pattern the active material film layer to obtain the active layer.

Step 3052, forming a gate insulating layer on the base substrate on which the active layer is formed.

For example, a PECVD process can be used to deposit a SiO2 film or a composite film of SiO2 and SiN on the active layer to obtain a gate insulating layer.

Step 3053, forming a gate electrode on the base substrate on which the gate insulating layer is formed.

In the embodiments of the present disclosure, one or more low-resistance metal material films can be deposited on the gate insulating layer by a physical vapor deposition method such as magnetron sputtering, and then the metal material film can be patterned to form a gate. electrode.

Step 3054, forming an interlayer insulating layer on the base substrate on which the gate metal pattern is formed.

Further, a PECVD process may be used to sequentially deposit an SiO2 film and a SiN film on the base substrate on which the gate electrode is formed to form an interlayer insulating layer, and the interlayer insulating layer may be etched through a mask and etching process to form a first contact Hole and second contact hole.

Step 3055, forming source and drain electrodes on the base substrate on which the interlayer insulating layer is formed.

A magnetron sputtering process can be used to deposit one or more low-resistance source and drain metal films on the interlayer insulating layer, and pattern the source and drain metal material films to form source and drain electrodes. Wherein, the source and drain electrodes may include a source electrode and a drain electrode. One of the source and drain electrodes may contact the active layer through the first contact hole, and the other electrode may contact the active layer through the second contact hole.

Optionally, the material for forming the source and drain metal film may include any one of molybdenum, molybdenum-niobium alloy, aluminum, aluminum neodymium alloy, titanium, and copper.

Step 3056, forming a first passivation layer on the base substrate where the active and drain electrodes are formed.

A PECVD process can be used to deposit a layer of SiN or SiO ₂ film on the base substrate forming the active drain electrode to obtain the first passivation layer.

Step 3057, forming a color film layer on the base substrate on which the first passivation layer is formed.

The color film layer may include a plurality of film layers of different colors, for example, may include a red film layer, a green film layer, and a blue film layer.

In the process of forming the color film layer, different color filter material films can be deposited on the surface of the first passivation layer in sequence (for example, a red filter material film, a green filter material film and a blue filter material can be deposited sequentially film). After each deposition is completed, the filter material film is patterned to form a color film.

For example, assuming that the color film layer includes a red film layer, a green film layer, and a blue film layer, the process of forming the color film layer may include: depositing a layer of red filter material on the first passivation layer using a PECVD process Then, the red filter material film is patterned to form a red film layer. The green film layer and the blue film layer are sequentially formed subsequently to obtain the color film layer.

Step 306: sequentially forming a flat layer, a common electrode layer, a second passivation layer, a pixel electrode layer, a spacer, and an alignment layer on the base substrate on which the color filter layer is formed.

In the embodiment of the present disclosure, a thin film of hot-melt material may be deposited on the color filter layer to form a flat layer. After that, a physical vapor deposition process may be used to deposit a thin film of transparent electrode material on the flat layer, and the transparent electrode material thin film may be patterned to form a common electrode layer. Subsequently, a PECVD process can be used to deposit a layer of SiN or SiO ₂ film on the base substrate on which the common electrode layer is formed to form a second passivation layer. After that, a magnetron sputtering process can be used to deposit one or more low-resistance semiconductor films on the second passivation layer, and the semiconductor films can be patterned to form a pixel electrode layer. Further, a spacer material film may be deposited on the base substrate on which the pixel electrode layer is formed, and the spacer material film may be patterned to form the spacer. Finally, a thin film of organic material is deposited between the spacer and the pixel electrode layer to form an alignment layer.

Optionally, the transparent electrode material forming the common electrode layer may be ITO. The organic material forming the alignment layer may be PI.

It should be noted that in the manufacturing process of the array substrate, after each film layer is formed, an alignment mark can also be set on the film layer, so that when the next film layer is formed, the alignment mark can be Point-to-point alignment of the mask plate can further improve the alignment accuracy between each film layer.

Optionally, the material forming the alignment mark points on each film layer may be the same as the material forming the film layer. Moreover, the orthographic projection of the alignment mark on each film layer on the base substrate may all be a cross.

In summary, the embodiments of the present disclosure provide a method for manufacturing an array substrate, which can form a black matrix layer on one side of a base substrate, and then sequentially form a transistor device layer and a color on the other side of the base substrate. The film layer, the black matrix layer, is located on a different side of the base substrate from the transistor device layer and the color film layer. When forming the transistor device layer and the color film layer, the black matrix layer will not block the alignment mark points, and can ensure the alignment of the mask plate with the alignment mark points, so the manufacturing method of the array substrate provided by the embodiment of the present disclosure is used The alignment accuracy of each film layer in the array substrate is relatively high. In addition, by adopting the manufacturing method of the array substrate provided by the embodiments of the present disclosure, there is no need to develop new black matrix materials, and only the film layer structure needs to be adjusted to solve the problem of low alignment accuracy of the black matrix layer and the transistor device layer in the prior art. The problem of saving R&D costs and manpower.

The embodiment of the present disclosure also provides a display panel. Referring to FIG. 8, the display panel may include: the array substrate 10 provided in the above-mentioned embodiment, the box substrate 40, and the array substrate 10 and the box substrate. LCD 50.

Wherein, the pair of box substrates 40 may include: a glass substrate 401, an overcoating (OC) 402 and an alignment layer 403 which are sequentially disposed on the glass substrate 401. The protective film 402 can be made of a transparent material.

FIG. 9 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure. Referring to FIG. 9, the display panel may include: an array substrate 60, an aligner substrate 70, and a liquid crystal 80 located between the array substrate 60 and the aligner substrate 70.

The array substrate 60 may include a base substrate 601, a light shielding layer 602, a transistor device layer 603, a first passivation layer 604, a color film layer 605, a flat layer 606, and a common electrode layer 607 which are sequentially disposed on the base substrate 601. , The second passivation layer 608, the pixel electrode layer 609 and the alignment layer 610. Wherein, the transistor device layer 603 may include: an active layer 6031, a gate insulating layer 6032, a gate electrode 6033, an interlayer insulating layer 6034, and source and drain electrodes 6035.

Optionally, each film layer included in the array substrate 60 may be provided with an alignment mark point.

As shown in FIG. 9, the pair of cell substrates 70 may include a glass substrate 701, and a black matrix layer 702, a protective film 703, a spacer 704 and an alignment layer 705 located on the side of the glass substrate 701 close to the liquid crystal 80 and stacked in sequence.

Since the black matrix layer 702 is disposed in the matching substrate 70, during the process of manufacturing the array substrate 60, the black matrix layer 702 will not block the alignment mark points (for example, the alignment mark points in the light shielding layer 602), and the array substrate The peripheral regions of each film layer included in 40 are all light-transmissive, so that accurate alignment between the mask plate and the alignment mark can be ensured, thereby ensuring high alignment accuracy of each film layer included in the array substrate 60.

Optionally, the black matrix layer 702 may be provided with alignment mark holes.

It should be noted that the spacer 704 may also be disposed on the array substrate 60, and the embodiment of the present disclosure does not limit the position of the spacer 704.

Taking the array substrate 60 shown in FIG. 9 as an example, the manufacturing process of the array substrate 60 is introduced. The process may include:

First, the light shielding layer 602 is formed on the base substrate 601, and then the active layer 6031, the gate insulating layer 6032, the gate electrode 6033, the interlayer insulating layer 6034, and the source and drain electrodes 6035 are sequentially formed on the light shielding layer 602, and then the active leakage is formed. A first passivation layer 604 is formed on the base substrate of the electrode 6035, a color film layer 605 is formed on the first passivation layer 604, and finally a flat layer 606, a common electrode layer 607, and a second passivation layer 605 are sequentially formed on the color film layer 605. The passivation layer 608, the pixel electrode layer 609, and the alignment layer 610.

Taking the box substrate 70 shown in FIG. 9 as an example, the manufacturing process of the box substrate 70 is introduced. The process may include:

First, a black matrix layer 702 is formed on the glass substrate 701, and then a protective film 703 is formed on the black matrix layer 702, and then a spacer 704 is formed on the protective film 703, and finally between the protective film 703 and the spacer 704 An alignment layer 705 is formed.

After the array substrate 60 and the box substrate 70 are manufactured, the array substrate 60 and the box substrate 70 can be aligned and pressed to form a display panel as shown in FIG. 9. In the process of aligning and pressing the box, the alignment mark holes on the black matrix layer 701 can be aligned with the alignment mark points on the source and drain electrodes 6035 included in the array substrate 60, thereby realizing the array substrate 60 and the box alignment substrate. 70 accurate alignment.

An embodiment of the present application also provides a display device. As shown in FIG. 10, the display device may include: the display panel 100 provided in the foregoing embodiment, and a driving circuit 200 connected to the display panel 100. Wherein, the driving circuit 200 can be used to provide driving signals for transistors in the display panel 100.

Optionally, the driving circuit 200 may include a gate driving circuit and a source driving circuit. The gate driving circuit may be used to provide a gate driving signal for the transistor, and the source driving circuit may be used to provide a data signal for the transistor.

The above are only exemplary embodiments of the present disclosure, and are not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection of the present disclosure. Within range.

Claims

An array substrate, the array substrate comprising:

A base substrate, a black matrix layer on one side of the base substrate, and a transistor device layer and a color film layer on the other side of the base substrate and stacked in sequence;

Wherein, the orthographic projection of the black matrix layer on the base substrate covers the orthographic projection of the transistors in the transistor device layer on the base substrate.
The array substrate according to claim 1, wherein the base substrate has a display area and a peripheral area surrounding the display area;

The part of the black matrix layer located in the peripheral area is provided with at least two alignment mark holes.
4. The array substrate according to claim 2, wherein the base substrate is a rectangular substrate; a portion of the black matrix layer located in the peripheral area is provided with four alignment mark holes;

The orthographic projections of the four alignment mark holes on the base substrate are respectively located at four corners of the base substrate.
3. The array substrate according to claim 2, wherein the base substrate is a rectangular substrate; a portion of the black matrix layer located in the peripheral area is provided with two alignment mark holes;

The orthographic projections of the two alignment mark holes on the base substrate are respectively located at two opposite corners of the base substrate.
4. The array substrate according to any one of claims 2 to 4, wherein the orthographic projection of each of the alignment mark holes on the base substrate is in a cross shape.
5. The array substrate according to any one of claims 1 to 5, the array substrate further comprising:

A protective layer located on the side of the black matrix layer away from the base substrate.
8. The array substrate according to claim 6, wherein the protective layer is made of indium tin oxide, silicon nitride, or silicon oxide.
8. The array substrate according to any one of claims 1 to 7, further comprising: a light-shielding layer located between the transistor device layer and the base substrate;

A first passivation layer located between the transistor device layer and the color film layer;

And a flat layer, a common electrode layer, a second passivation layer, a pixel electrode layer, a spacer and an alignment layer which are located on the side of the color filter layer away from the base substrate and are sequentially stacked.
A manufacturing method of an array substrate, the method comprising:

Forming a black matrix layer on one side of the base substrate;

Forming a transistor device layer and a color film layer in sequence on the other side of the base substrate;

Wherein, the orthographic projection of the black matrix layer on the base substrate covers the orthographic projection of the transistors in the transistor device layer on the base substrate.
The method according to claim 9, wherein the base substrate has a display area and a peripheral area surrounding the display area; the forming a black matrix layer on one side of the base substrate includes:

Forming a black matrix material film layer covering the display area and the peripheral area on one side of the base substrate;

The black matrix material film layer is patterned to obtain a black matrix layer, and at least two alignment mark holes are formed in the portion of the black matrix layer located in the peripheral area.
The method according to claim 10, forming a transistor device layer and a color film layer in sequence on the other side of the base substrate, comprising:

Aligning the mask plate based on the at least two alignment mark holes;

The mask plate is used to sequentially form a transistor device layer and a color film layer on the other side of the base substrate.
The method according to claim 11, wherein the alignment of the mask plate based on the at least two alignment mark holes comprises:

Recognizing each of the alignment mark holes through an optical camera;

Adjust the position of the mask plate according to the identified position of each of the alignment mark holes, so that the alignment mark points on the mask are aligned with the alignment mark holes.
The method according to any one of claims 10 to 12, wherein the base substrate is a rectangular substrate; the part of the black matrix layer located in the peripheral area is formed with four alignment mark holes;

The orthographic projections of the four alignment mark holes on the base substrate are respectively located at four corners of the base substrate.
The method according to any one of claims 10 to 13, wherein the orthographic projection of each of the alignment mark holes on the base substrate is in a cross shape.
The method according to any one of claims 9 to 14, after forming the black matrix layer on one side of the base substrate, the method further comprises:

A protective layer is formed on the side of the black matrix layer away from the base substrate.
The method according to claim 15, wherein the forming a protective layer on a side of the black matrix layer away from the base substrate comprises:

Depositing an indium tin oxide film, a silicon nitride film or a silicon oxide film on the side of the black matrix layer away from the base substrate to obtain a protective layer.
The method according to any one of claims 9 to 16, before sequentially forming a transistor device layer and a color filter layer on the other side of the base substrate, the method further comprises:

Forming a light shielding layer on the other side of the base substrate;

After forming the transistor device layer on the other side of the base substrate and before forming the color filter layer, the method further includes:

Forming a first passivation layer on the side of the transistor device layer away from the base substrate;

After forming the color filter layer, the method further includes:

A flat layer, a common electrode layer, a second passivation layer, a pixel electrode layer, a spacer, and an alignment layer are sequentially formed on the side of the color filter layer away from the base substrate.
A display panel comprising: the array substrate according to any one of claims 1 to 8, a cell-aligned substrate, and liquid crystals located between the array substrate and the cell-aligned substrate.
18. The display panel according to claim 18, the cell-matching substrate comprises: a glass substrate, and a protective film and an alignment layer that are located on a side of the glass substrate close to the liquid crystal and stacked in sequence.
A display device, the display device comprising: the display panel according to claim 18 or 19, and a drive circuit connected to the display panel;

The driving circuit is used to provide driving signals for the transistors in the display panel.