WO2020228316A1 - 薄膜晶体管、显示面板和显示装置 - Google Patents

薄膜晶体管、显示面板和显示装置 Download PDF

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Publication number
WO2020228316A1
WO2020228316A1 PCT/CN2019/124999 CN2019124999W WO2020228316A1 WO 2020228316 A1 WO2020228316 A1 WO 2020228316A1 CN 2019124999 W CN2019124999 W CN 2019124999W WO 2020228316 A1 WO2020228316 A1 WO 2020228316A1
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Prior art keywords
thin film
film transistor
carrier injection
injection structure
channel region
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PCT/CN2019/124999
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English (en)
French (fr)
Inventor
周晓梁
邵阳
徐琳
刘如胜
袁波
朱晖
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Yungu Guan Technology Co Ltd
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Yungu Guan Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6708—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • This application relates to the field of display technology, such as a thin film transistor, a display panel, and a display device.
  • TFT Thin Film Transistor
  • the present application provides a thin film transistor, a display panel, and a display device, which effectively reduces the concentration of residual carriers in the channel region of the active layer of the thin film transistor, and improves the effect of residual carriers in the channel region on the hysteresis characteristics of the thin film transistor.
  • the reliability issue optimizes the display effect of the display panel.
  • the embodiment of the present application provides a thin film transistor, including:
  • An active layer located on the substrate including a channel region, a source region located on a first side of the channel region, and a drain region located on a second side of the channel region;
  • the carrier injection structure forms Schottky contact with the channel region of the active layer, and the carrier injection structure is configured to inject into the channel region of the active layer and the source region or the drain region.
  • the region is doped with carriers of the opposite carrier type.
  • the embodiment of the present application also provides a display panel, including:
  • a plurality of pixel units each of the pixel units includes a pixel drive circuit and an organic light emitting structure, and the pixel drive circuit includes a thin film transistor provided by any embodiment of the present application;
  • At least the driving transistor in the pixel driving circuit is the thin film transistor, the driving transistor is configured to provide a driving current to the organic light emitting structure, and the organic light emitting structure is configured to emit light in response to the driving current.
  • the embodiment of the present application also provides a display device, including the display panel provided by any embodiment of the present application.
  • FIG. 1 is a schematic diagram of a top view structure of a thin film transistor provided by an embodiment of the application
  • FIG. 2 is a schematic diagram of a cross-sectional structure along the AA' direction in FIG. 1 provided by an embodiment of the application;
  • FIG. 3 is a schematic top view of another thin film transistor according to an embodiment of the application.
  • FIG. 4 is a schematic diagram of a cross-sectional structure along the BB' direction in FIG. 3 provided by an embodiment of the application;
  • FIG. 5 is a schematic top view of another thin film transistor according to an embodiment of the application.
  • FIG. 6 is a schematic diagram of a cross-sectional structure along the CC' direction in FIG. 5 provided by an embodiment of the application;
  • FIG. 7 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • FIG. 8 is a schematic structural diagram of a pixel unit provided by an embodiment of the application.
  • FIG. 9 is a schematic structural diagram of a display device provided by an embodiment of the application.
  • the embodiment of the application provides a thin film transistor.
  • the thin film transistor includes a substrate, an active layer and a gate located on the substrate, and a carrier injection structure located on the side of the active layer away from the gate.
  • the active layer includes The material of the channel region, the source region on the first side of the channel region, and the drain region on the second side of the channel region is a conductive material.
  • the carrier injection structure forms a Schottky contact with the channel region of the active layer, and the carrier injection structure is configured to inject into the channel region of the active layer the opposite type of doped carriers to the source region or the drain region Carrier.
  • the thin film transistor provided by the embodiments of the present application includes a substrate, an active layer and a gate located on the substrate, and a carrier injection structure located on the side of the active layer away from the gate.
  • the active layer includes a channel region, The source region on the first side of the channel region and the drain region on the second side of the channel region.
  • the material constituting the carrier injection structure is a conductive material.
  • the carrier injection structure and the channel region of the active layer form a Schottky Contact
  • the carrier injection structure is arranged to inject carriers of the opposite type to the doped carriers of the source or drain regions into the channel region of the active layer, so that it is beneficial to realize that when the thin film transistor is not working, the carrier
  • the carriers injected into the channel region by the carrier injection structure can recombine with the residual carriers in the channel region, effectively reducing the concentration of residual carriers in the channel region of the active layer of the thin film transistor, and improving the channel region
  • the residual carriers affect the hysteresis characteristics and reliability of the thin film transistor, thereby improving the display afterimage or brightness degradation of the display panel, and optimizing the display effect of the display panel.
  • the Schottky barrier formed between the carrier injection structure and the channel region is used to prevent the carrier injection structure from injecting carriers into the channel region and affecting the normal operation of the thin film transistor. process.
  • FIG. 1 is a schematic top view of the structure of a thin film transistor provided by an embodiment of the application
  • FIG. 2 is a schematic view of the cross-sectional structure along the AA' direction in FIG. 1 provided by an embodiment of the application.
  • a thin film transistor includes a substrate 1, an active layer P and a gate G on the substrate 1, and a carrier injection structure 2 on the side of the active layer P away from the gate G.
  • the source layer P includes a channel region a1, a source region a2 on the first side of the channel region a1, and a drain region a3 on the second side of the channel region a1.
  • the channel region a1 is the gate of the active layer P corresponding to the thin film transistor.
  • the thin film transistor also includes a source electrode S and a drain electrode D.
  • the source area a2 is the part of the active layer P corresponding to the source electrode S.
  • the source electrode S is arranged above the source area a2, and the drain area a3 is The active layer P corresponds to the portion where the drain D is disposed, and the drain D is disposed above the drain region a3.
  • the material that constitutes the carrier injection structure 2 is a conductive material, the carrier injection structure 2 forms a Schottky contact with the channel region a1 of the active layer P, and the carrier injection structure 2 is arranged to face the active layer P
  • the channel region a1 is implanted with carriers of the opposite type to the doped carriers of the source region a2 or the drain region a3.
  • the thin film transistor in conjunction with FIG. 1 and FIG. 2, after the thin film transistor operates for a period of time, there will be residual carriers in the channel region a1 of the active layer P of the thin film transistor, and the residual carriers in the channel region a1 It will affect the hysteresis characteristics and reliability of the thin film transistor, that is, the residual carriers in the channel region a1 will cause the gate G potential of the thin film transistor to change from a positive potential to a negative potential and the time from a negative potential to a positive potential is different , Cause the thin film transistor to have a hysteresis problem, and the hysteresis problem will cause the working state of the thin film transistor to be unstable, affect the reliability of the thin film transistor, and cause display sticking or brightness degradation of the display panel, and affect the display effect of the display panel.
  • the residual carriers in the channel region a1 of the active layer P of the thin film transistor are of the same type as the doped carriers of the source region a2 or the drain region a3, and the carrier injection structure 2 and
  • the channel region a1 of the active layer P forms a Schottky contact
  • the carrier injection structure 2 is configured to inject the channel region a1 of the active layer P into the channel region a1 of the active layer P.
  • the type of doped carriers is opposite to that of the source region a2 or the drain region a3.
  • the carrier injection structure 2 is used to inject doped carriers into the channel region a1 of the active layer P of the thin film transistor and the source region a2 or the drain region a3.
  • the residual carriers in the channel region a1 of the active layer P of the thin film transistor are of the same type as the doped carriers in the source region a2 or the drain region a3, that is, the carrier injection structure 2
  • the carriers injected into the channel region a1 can recombine with the residual carriers in the channel region a1, effectively reducing the concentration of the residual carriers in the P channel region a1 of the active layer of the thin film transistor, and improving the channel region a1.
  • the residual carriers affect the hysteresis characteristics and reliability of the thin film transistor, thereby improving the display afterimage or brightness degradation of the display panel, and optimizing the display effect of the display panel.
  • the Schottky barrier formed between the carrier injection structure 2 and the channel region a1 is used to prevent the carrier injection structure 2 from injecting carriers into the channel region a1 and affecting the film. The normal working process of the transistor.
  • the material constituting the carrier injection structure 2 can be set to be a metal material or a conductive oxide material.
  • the material constituting the carrier injection structure 2 can be set to be a metal material such as gold (Au) and platinum (Pt),
  • the material provided to form the carrier injection structure 2 is conductive oxide materials such as indium tin oxide (ITO) and aluminum zinc oxide (Aluminium Zinc Oxide, AZO).
  • ITO indium tin oxide
  • AZO aluminum zinc oxide
  • the material constituting the active layer P includes at least one of a silicon-based semiconductor material, an oxide semiconductor material, or an organic semiconductor material.
  • the carrier injection structure 2 composed of a metal material or a conductive oxide material can form Schottky contact with the channel region a1 of the active layer P, which is beneficial to realize the use of the carrier injection structure 2 when the thin film transistor is not working.
  • the carriers injected into the channel region a1 recombine with the residual carriers in the channel region a1 to reduce the concentration of residual carriers in the channel region a1 of the active layer P of the thin film transistor and improve the residual carriers in the channel region a1 Carriers affect the hysteresis characteristics and reliability of thin film transistors, thereby improving display afterimages or brightness degradation of the display panel, and optimizing the display effect of the display panel.
  • the carrier injection structure 2 forms a Schottky contact with the channel region a1 of the active layer P, which is also conducive to using the Schottky formed between the carrier structure and the channel region a1 when the thin film transistor is working.
  • the base barrier prevents the carrier injection structure 2 from injecting carriers into the channel region a1, which affects the normal working process of the thin film transistor.
  • the work function of the carrier injection structure 2 can be set to be greater than the work function of the channel region a1, or when the source region a2 or the drain region a3 When the doped carrier is holes, the work function of the carrier injection structure 2 is smaller than the work function of the channel region a1.
  • the carrier injection structure 2 can be set as a hole injection structure, that is, a carrier injection structure 2 Holes can be injected into the channel region a1 of the active layer P to recombine the residual carriers in the channel region a1, that is, residual electrons, and the work function of the carrier injection structure 2 is set to be greater than the work function of the channel region a1, So that the carrier injection structure 2 and the channel region a1 of the active layer P form a Schottky contact.
  • the carrier injection structure 2 can be set as an electron injection structure, that is, current carrying
  • the sub-injection structure 2 can inject electrons into the channel region a1 of the active layer P to recombine the residual carriers in the channel region a1, that is, the residual holes, and the work function of the carrier injection structure 2 is smaller than that of the channel region a1. Work function so that the carrier injection structure 2 and the channel region a1 of the active layer P form a Schottky contact.
  • the thin film transistor can be exemplarily set as a thin film transistor with a top gate structure.
  • the carrier injection structure 2 is located on the side of the active layer P away from the gate G, that is, the carrier injection structure 2 is located where there is Under the source layer P and covered by the active layer P, it is beneficial to prevent the arrangement of the carrier injection structure 2 from affecting the normal operation of the thin film transistor when the thin film transistor is working normally.
  • disposing the carrier injection structure 2 not in contact with the source region a2 or the drain region a3 is also beneficial to prevent the carrier injection structure 2 from affecting the normal operation of the thin film transistor when the thin film transistor is working normally.
  • the cross section of the carrier injection structure 2 when the thin film transistor is a thin film transistor with a top gate structure, along the direction perpendicular to the substrate 1, the cross section of the carrier injection structure 2 can be set as a trapezoidal cross section, that is, along the direction perpendicular to the substrate 1.
  • the angle formed between the upper edge of the cross-section of the carrier injection structure 2 and the edges on both sides is greater than 90°. If due to the problem of the etching process, the cross section of the carrier injection structure 2 is rectangular in the direction perpendicular to the substrate 1, that is, the angle formed between the upper edge of the cross section and the edges on both sides is approximately 90°.
  • the angle between adjacent edges of the carrier injection structure 2 along the cross section perpendicular to the substrate 1 can be adjusted by controlling the etching process of the carrier injection structure 2, so that the thin film of the top gate structure For the transistor, along the direction perpendicular to the substrate 1, the cross-section of the carrier injection structure 2 is a trapezoidal cross-section, which effectively reduces the probability that the active layer P of the thin film transistor will be cut off.
  • the carrier injection structure 2 can be set as a patterned structure, which is exemplarily arranged in a direction perpendicular to the substrate 1, and the cross section of the carrier injection structure 2 is a trapezoidal cross section. Reduce the probability of a cutoff problem in the active layer P of the thin film transistor.
  • FIG. 3 is a schematic top view of another thin film transistor provided by an embodiment of the application
  • FIG. 4 is a schematic cross-sectional structure view along the BB' direction in FIG. 3 provided by an embodiment of the application, which is similar to the structure shown in FIGS. 1 and 2
  • the difference between the thin film transistors is that the thin film transistors shown in FIGS. 3 and 4 can also be provided with the carrier injection structure 2 as a planar structure, and can also be provided along the direction perpendicular to the substrate 1.
  • the cross section of the carrier injection structure 2 It has a trapezoidal cross-section to reduce the probability of a cutoff problem in the active layer P of the thin film transistor.
  • the carrier injection structure 2 is not in contact with the source region a2 or the drain region a3, which is beneficial to prevent the arrangement of the carrier injection structure 2 from affecting the normal operation of the thin film transistor when the thin film transistor is working normally.
  • the array substrate provided with the thin film transistor is arranged on the organic light emitting display panel.
  • the top-gate thin film transistor in the organic light-emitting display panel does not need to add a new light-shielding structure.
  • the gate G of the thin-film transistor can be used as the light-shielding structure of the channel region a1 to improve the activeness of the thin film transistor.
  • FIG. 5 is a schematic top view of another thin film transistor provided by an embodiment of the application
  • FIG. 6 is a schematic cross-sectional structure view along the CC' direction in FIG. 5 provided by an embodiment of the application. 5 and 6, it can also be a thin film transistor with a bottom gate structure.
  • the carrier injection structure 2 is located on the side of the active layer P away from the gate G, that is, the carrier injection structure 2 is located in the active layer.
  • the upper part of the layer P is beneficial to prevent the arrangement of the carrier injection structure 2 from affecting the normal operation of the thin film transistor when the thin film transistor is working normally.
  • the carrier injection structure 2 can be set not to be in contact with the source region a2 or the drain region a3, which helps prevent the carrier injection structure 2 from affecting the normal operation of the thin film transistor when the thin film transistor is working normally.
  • the carrier injection structure 2 can also be set as a patterned structure.
  • the carrier injection structure 2 is exemplarily arranged in a direction perpendicular to the substrate 1, and the interface of the carrier injection structure 2 is two trapezoids. section. It is also possible to set the carrier injection structure 2 as a planar structure, which can be arranged in a direction perpendicular to the substrate 1.
  • the cross section of the carrier injection structure 2 is a trapezoidal cross section.
  • the carrier injection The shape of the cross section of the structure 2 in the direction perpendicular to the substrate 1 is not limited.
  • the backlight is located where The array substrate of the thin film transistor is on the side away from the light emitting side, and the light emitted by the backlight irradiates the channel region a1 of the active layer P of the thin film transistor to generate photo-generated carriers.
  • the thin film transistor with bottom gate structure does not need to add a new light-shielding structure.
  • the gate G of the thin film transistor can be used as the light-shielding structure of the channel region a1, which improves the light emitted from the backlight to the active layer P of the thin film transistor. There is a problem that photo-generated carriers are generated in the channel area a1, which affects the switching characteristics of the thin film transistor.
  • the embodiment of the present application does not limit the number of carrier injection structures 2 in the thin film transistor, and ensures that the carrier injection structures 2 are located on the side of the active layer P away from the gate G and do not contact the source region a2 or the drain region a3 OK.
  • the thickness of the carrier injection structure 2 is greater than or equal to 5 nm along a direction perpendicular to the substrate 1.
  • the carrier injection structure 2 will have a poor carrier injection effect, which will affect the residual carriers in the channel region a1.
  • the improvement effect of the problems affecting the hysteresis characteristics and reliability of the thin film transistor is poor.
  • the thickness of the carrier injection structure 2 may be less than or equal to 500 nm along a direction perpendicular to the substrate 1.
  • the carrier injection structure 2 is too thick in the direction perpendicular to the substrate 1 to affect the effective channel length of the thin film transistor during normal operation.
  • the thickness of the carrier injection structure 2 is less than or equal to 500 nm to prevent the carrier injection structure 2 from affecting the effective channel length of the thin film transistor during normal operation, and affecting the switching characteristics of the thin film transistor and the display effect of the display panel.
  • the thin film transistor may further include a bias electrode 3.
  • the carrier injection structure 2 of the thin film transistor is electrically connected to the bias electrode 3, and the bias electrode 3 is connected to the source and drain of the thin film transistor.
  • the very same layer is fabricated or the bias electrode 3 is fabricated in the same layer as the gate G of the thin film transistor.
  • the carrier injection structure 2 needs to inject into the channel region a1 of the active layer P of the thin film transistor the carriers combined with the residual carriers in the channel region a1, due to the carrier injection
  • the structure 2 forms a Schottky contact with the channel region a1 of the active layer P. Therefore, a bias voltage needs to be applied to the carrier injection structure 2 through the bias electrode 3 to offset the difference between the carrier injection structure 2 and the active layer P.
  • the Schottky barrier formed in the channel region a1 realizes that the carrier injection structure 2 injects carriers that recombine with the residual carriers in the channel region a1 into the channel region a1 of the thin film transistor active layer P, thereby reducing
  • the concentration of residual carriers in the channel region a1 of the active layer P of the thin film transistor improves the problem that the residual carriers in the channel region a1 affect the hysteresis characteristics and reliability of the thin film transistor.
  • the carrier injection structure 2 does not need to inject carriers into the channel region a1 of the active layer P of the thin film transistor.
  • the carrier injection structure 2 and the channel of the active layer P can be used.
  • the Schottky barrier between the regions a1 blocks the carrier injection structure 2 injecting carriers into the channel region a1 of the active layer P of the thin film transistor to ensure that the thin film transistor can work normally, or the bias electrode 3
  • the carrier injection structure 2 is loaded with a bias voltage to increase the Schottky barrier between the carrier injection structure 2 and the channel region a1 of the active layer P to block the carrier injection structure 2 to the thin film transistor.
  • the channel region a1 of the source layer P is injected with carriers to ensure the normal operation of the thin film transistor.
  • the production of the bias electrode 3 is realized, which simplifies the manufacturing process of the thin film transistor, which is beneficial to simplify the manufacturing process of the display panel.
  • the bias electrode 3 can pass through the via hole in the insulating layer between the bias electrode 3 and the carrier injection structure 2 The electrical connection with the carrier injection structure 2 is achieved.
  • FIG. 7 is a schematic structural diagram of a display panel provided by this application
  • FIG. 8 is a schematic structural diagram of a pixel unit provided by an embodiment of this application. 7 and 8, the display panel includes a plurality of pixel units 4, each pixel unit 4 includes a pixel drive circuit and an organic light-emitting structure 42, the pixel drive circuit includes the thin film transistor described in the above embodiments, so the embodiment of the present application
  • the provided display panel also has the beneficial effects described in the above embodiments, which will not be repeated here.
  • the display panel may be an organic light emitting display panel, and the display panel may also include a plurality of scan signal lines D12, a plurality of data signal lines D13, a gate driving module D121, and a source driving module D131 , Drive control module D101 and power supply module D102, the pixel unit 4 is arranged in the space formed by the intersection of the scan signal line D12 and the data signal line D13, and the gate drive module D121 is set to respond to the scan drive control signal generated by the drive control module D101 ,
  • the scan signal is input to the pixel drive circuit of the corresponding pixel unit 4 through the scan signal line D12, and the pixel drive circuit is set to communicate with the pixel drive circuit under the action of the scan signal input from the scan signal line D12 electrically connected to the pixel drive circuit
  • the source drive circuit D131 is configured to respond to the data drive control signal generated by the drive control module D101, and input data signals to the pixel
  • the pixel drive circuit is set as an exemplary 7T1C structure, that is, the pixel drive circuit is set to include 7 thin film transistors and 1 capacitor structure.
  • the connection relationship between the thin film transistors and the capacitor structure is shown in Figure 8.
  • the pixel driving circuit can realize the compensation of the threshold voltage of the driving transistor and improve the uniformity of light emission of the display panel.
  • At least the driving transistor T1 in the pixel driving circuit is set as a thin film transistor, the driving transistor T1 is configured to provide a driving current Id to the organic light emitting structure 42, and the organic light emitting structure 42 is configured to emit light in response to the driving current.
  • the display brightness of the organic light emitting structure 42 depends on the magnitude of the driving current provided by the driving transistor T1 to the organic light emitting structure 42.
  • the carrier injection structure 2 is used to inject and source the channel region a1 of the active layer P of the driving transistor T1 when the driving transistor T1 is not working.
  • A2 or the drain region a3 is doped with carriers of the opposite type, that is, the carriers injected into the channel region a1 by the carrier injection structure 2 can recombine with the residual carriers in the channel region a1, reducing drive
  • the concentration of residual carriers in the channel region a1 of the active layer P of the transistor T1 improves the problem that the residual carriers in the channel region a1 affect the hysteresis characteristics and reliability of the thin film transistor, thereby improving the display afterimage on the display panel Or brightness degradation and other issues, optimize the display effect of the display panel.
  • the Schottky barrier formed between the carrier structure and the channel region a1 is used to prevent the carrier injection structure 2 from injecting carriers into the channel region a1, which affects driving.
  • the normal working process of the transistor T1 affects the display effect of the display panel.
  • the remaining transistors in the pixel driving circuit can also be set as the thin film transistors of the above-mentioned embodiment to improve the problem that residual carriers in the channel region affect the hysteresis characteristics of the thin film transistor and improve the thin film transistor The stability of work, optimize the display effect of the display panel.
  • the embodiments of the present application do not limit the number of thin film transistors and capacitor structures in the pixel driving circuit, and the number of thin film transistors and capacitor structures in the pixel driving circuit can be set according to actual needs.
  • the drawings illustrated in the embodiments of the present application only exemplarily represent the sizes of multiple structures, and do not represent the actual sizes of multiple structures in the thin film transistor and the display panel.
  • FIG. 9 is a schematic structural diagram of a display device provided in an embodiment of the present application.
  • the display device 91 includes the display panel 92 in the above-mentioned embodiment. Therefore, the display device 91 provided in the embodiment of the present application also has the beneficial effects described in the above-mentioned embodiment, which will not be repeated herein.
  • the display device may be an electronic device such as a mobile phone terminal, a tablet computer, a vehicle-mounted display device, a mobile phone, or a wearable device, and the embodiment of the present application does not limit the form of the display device.

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Abstract

一种薄膜晶体管、显示面板和显示装置，该薄膜晶体管包括衬底（1）；位于衬底（1）上的栅极（G）；位于所述衬底（1）上的有源层（P），有源层（P）包括沟道区（a1）、位于沟道区（a1）第一侧的源区（a2）以及位于沟道区（a1）第二侧的漏区（a3）；位于有源层（P）远离栅极（G）一侧的载流子注入结构（2），构成载流子注入结构（2）的材料为导体材料；载流子注入结构（2）与有源层（P）的沟道区（a1）形成肖特基接触，载流子注入结构（2）设置为向有源层（P）的沟道区（a1）注入与源区（a2）或漏区（a3）的掺杂载流子类型相反的载流子。

Description

薄膜晶体管、显示面板和显示装置
本申请要求在2019年05月15日提交中国专利局、申请号为201910403541.1的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，例如涉及一种薄膜晶体管、显示面板和显示装置。
背景技术
薄膜晶体管(Thin Film Transistor，TFT)技术是平板显示技术的核心技术之一，薄膜晶体管自身的特性直接影响显示面板的显示效果，因此薄膜晶体管的优劣对于显示面板显示效果的优化至关重要。
薄膜晶体管在工作一段时间后，薄膜晶体管的有源层的沟道区会存在残留的载流子，而沟道区的残留载流子会影响薄膜晶体管的迟滞特性和可靠性，从而导致显示面板存在显示残影或亮度退化等问题，影响显示面板的显示效果。
发明内容
本申请提供一种薄膜晶体管、显示面板和显示装置，有效降低了薄膜晶体管有源层沟道区的残留载流子的浓度，改善了沟道区的残留载流子影响薄膜晶体管的迟滞特性和可靠性的问题，优化了显示面板的显示效果。
本申请实施例提供了一种薄膜晶体管，包括：
衬底；
位于所述衬底上的栅极；
位于所述衬底上的有源层，所述有源层包括沟道区、位于所述沟道区第一侧的源区以及位于所述沟道区第二侧的漏区；
位于所述有源层远离所述栅极一侧的载流子注入结构，构成所述载流子注入结构的材料为导体材料；
所述载流子注入结构与所述有源层的沟道区形成肖特基接触，所述载流子注入结构设置为向所述有源层的沟道区注入与所述源区或漏区的掺杂载流子类型相反的载流子。
本申请实施例还提供了一种显示面板，包括：
多个像素单元，每个所述像素单元包括像素驱动电路和有机发光结构，所述像素驱动电路包括本申请任意实施例提供的薄膜晶体管；
所述像素驱动电路中至少驱动晶体管为所述薄膜晶体管，所述驱动晶体管设置为向所述有机发光结构提供驱动电流，所述有机发光结构设置为响应所述驱动电流发光。
本申请实施例还提供了一种显示装置，包括本申请任意实施例提供的显示面板。
附图说明
图1为本申请实施例提供的一种薄膜晶体管的俯视结构示意图；
图2为本申请实施例提供的沿图1中AA’方向的剖面结构示意图；
图3为本申请实施例提供的另一种薄膜晶体管的俯视结构示意图；
图4为本申请实施例提供的沿图3中BB’方向的剖面结构示意图；
图5为本申请实施例提供的另一种薄膜晶体管的俯视结构示意图；
图6为本申请实施例提供的沿图5中CC’方向的剖面结构示意图；
图7为本申请实施例提供的一种显示面板的结构示意图；
图8为本申请实施例提供的一种像素单元的结构示意图；
图9为本申请实施例提供的一种显示装置的结构示意图。
具体实施方式
下面结合附图和实施例对本申请进行说明。本文所描述的具体实施例仅仅用于解释本申请，而非对本申请的限定。为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。贯穿本说明书中，相同或相似的附图标号代表相同或相似的结构、元件或流程。而且，为了在附图中体现多个结构之间的相对位置关系以及每个结构自身的特点，对本申请实施例中的多个俯视结构示意图添加透视效果。
本申请实施例提供了一种薄膜晶体管，薄膜晶体管包括衬底、位于衬底上的有源层和栅极、以及位于有源层远离栅极一侧的载流子注入结构，有源层包括沟道区、位于沟道区第一侧的源区以及位于沟道区第二侧的漏区，构成载流子注入结构的材料为导体材料。载流子注入结构与有源层的沟道区形成肖特基接触，载流子注入结构设置为向有源层的沟道区注入与源区或漏区的掺杂载流子类型相反的载流子。
薄膜晶体管在工作一段时间后，薄膜晶体管的有源层的沟道区会存在残留的载流子，而沟道区的残留载流子会影响薄膜晶体管的迟滞特性和可靠性，从而导致显示面板存在显示残影或亮度退化等问题，影响显示面板的显示效果。
本申请实施例提供的薄膜晶体管包括衬底、位于衬底上的有源层和栅极、以及位于有源层远离栅极一侧的载流子注入结构，有源层包括沟道区、位于沟道区第一侧的源区以及位于沟道区第二侧的漏区，构成载流子注入结构的材料为导体材料，载流子注入结构与有源层的沟道区形成肖特基接触，载流子注入结构设置为向有源层的沟道区注入与源区或漏区的掺杂载流子类型相反的载流子，这样，有利于实现在薄膜晶体管不工作时，载流子注入结构向沟道区注入的载流子能够与沟道区的残留载流子复合，有效降低了薄膜晶体管有源层沟道区的残留载流子的浓度，改善了沟道区的残留载流子影响薄膜晶体管的迟滞特性和可靠性的问题，进而改善了显示面板存在的显示残影或亮度退化等问题，优化了显示面板的显示效果。同时有利于实现在薄膜晶体管工作时，利用载流子注入结构与沟道区之间形成的肖特基势垒避免载流子注入结构向沟道区注入载流子而影响薄膜晶体管的正常工作过程。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。图1为本申请实施例提供的一种薄膜晶体管的俯视结构示意图，图2为本申请实施例提供的沿图1中AA’方向的剖面结构示意图。结合图1和图2，薄膜晶体管包括衬底1、位于衬底1上的有源层P和栅极G、以及位于有源层P远离栅极G一侧的载流子注入结构2，有源层P包括沟道区a1、位于沟道区a1第一侧的源区a2以及位于沟道区a1第二侧的漏区a3，沟道区a1即为有源层P对应薄膜晶体管的栅极G设置的部分，薄膜晶体管还包括源极S和漏极D，源区a2即为有源层P对应源极S设置的部分，源极S设置在源区a2上方，漏区a3即为有源层P对应漏极D设置的部分，漏极D设置在漏区a3上方。设置构成载流子注入结构2的材料为导体材料，载流子注入结构2与有源层P的沟道区a1形成肖特基接触，载流子注入结构2设置为向有源层P的沟道区a1注入与源区a2或漏区a3的掺杂载流子类型相反的载流子。
一实施例中，结合图1和图2，薄膜晶体管在工作一段时间后，薄膜晶体管的有源层P的沟道区a1会存在残留的载流子，而沟道区a1的残留载流子会影响薄膜晶体管的迟滞特性和可靠性，即沟道区a1的残留载流子会使得薄膜晶体管的栅极G电位由正电位变化到负电位的时间和由负电位变化到正电位的时间不同，导致薄膜晶体管存在迟滞问题，迟滞问题又会导致薄膜晶体管的工作状态不稳定，影响薄膜晶体管的可靠性，从而导致显示面板存在显示残影或亮度退化等问题，影响显示面板的显示效果。
薄膜晶体管在工作一段时间后，薄膜晶体管的有源层P的沟道区a1的残留载流子与源区a2或漏区a3的掺杂载流子类型相同，设置载流子注入结构2与有源层P的沟道区a1形成肖特基接触，载流子注入结构2设置为向有源层P的沟道区a1注入与源区a2或漏区a3的掺杂载流子类型相反的载流子，有利于实现在薄膜晶体管不工作时，利用载流子注入结构2向薄膜晶体管的有源层P的沟道区a1注入与源区a2或漏区a3的掺杂载流子类型相反的载流子，薄膜晶体管的有源层P的沟道区a1的残留载流子又与源区a2或漏区a3的掺杂载流子类型相同，即载流子注入结构2向沟道区a1注入的载流子能够与沟道区a1的残留载流子复合，有效降低了薄膜晶体管有源层P沟道区a1的残留载流子的浓度，改善了沟道区a1的残留载流子影响薄膜晶体管的迟滞特性和可靠性的问题，进而改善了显示面板存在的显示残影或亮度退化等问题，优化了显示面板的显示效果。同时有利于实现在薄膜晶体管工作时，利用载流子注入结构2与沟道区a1之间形成的肖特基势垒避免载流子注入结构2向沟道区a1注入载流子而影响薄膜晶体管的正常工作过程。
可选地，可以设置构成载流子注入结构2的材料为金属材料或者导电氧化物材料，例如可以设置构成载流子注入结构2的材料为金(Au)和铂(Pt)等金属材料，或者设置构成载流子注入结构2的材料为铟锡氧(Indium Tin Oxide，ITO)和铝锌氧(Aluminium Zinc Oxide，AZO)等导电氧化物材料。示例性地，可以设置构成有源层P的材料包括硅基半导体材料、氧化物半导体材料或者有机半导体材料中的至少一种。
由金属材料或者导电氧化物材料构成的载流子注入结构2能够与有源层P的沟道区a1形成肖特基接触，有利于实现在薄膜晶体管不工作时，利用载流子注入结构2向沟道区a1注入的载流子与沟道区a1的残留载流子复合，降低薄膜晶体管的有源层P的沟道区a1的残留载流子的浓度，改善沟道区a1的残留载流子影响薄膜晶体管的迟滞特性和可靠性的问题，进而改善显示面板存在显示残影或亮度退化等问题，优化显示面板的显示效果。另外，载流子注入结构2与有源层P的沟道区a1形成肖特基接触，也有利于实现在薄膜晶体管工作时，利用载流子结构与沟道区a1之间形成的肖特基势垒避免载流子注入结构2向沟道区a1注入载流子，影响薄膜晶体管的正常工作过程。
可选地，源区a2或漏区a3的掺杂载流子为电子时，可以设置载流子注入结构2的功函数大于沟道区a1的功函数，或者当源区a2或漏区a3的掺杂载流子为空穴时，载流子注入结构2的功函数小于沟道区a1的功函数。
当薄膜晶体管为N型薄膜晶体管，即薄膜晶体管的源区a2或漏区a3的掺杂载流子为电子时，可以设置载流子注入结构2为空穴注入结构，即载流子注 入结构2可以向有源层P的沟道区a1注入空穴以复合沟道区a1的残留载流子，即残留电子，设置载流子注入结构2的功函数大于沟道区a1的功函数，以使载流子注入结构2与有源层P的沟道区a1形成肖特基接触。同样的，当薄膜晶体管为P型薄膜晶体管，即薄膜晶体管的源区a2或漏区a3的掺杂载流子为空穴时，可以设置载流子注入结构2为电子注入结构，即载流子注入结构2可以向有源层P的沟道区a1注入电子以复合沟道区a1的残留载流子，即残留空穴，设置载流子注入结构2的功函数小于沟道区a1的功函数，以使载流子注入结构2与有源层P的沟道区a1形成肖特基接触。
结合图1和图2，可以示例性地设置薄膜晶体管为顶栅结构的薄膜晶体管，载流子注入结构2位于有源层P远离栅极G的一侧，即载流子注入结构2位于有源层P的下方并被有源层P覆盖，有利于在薄膜晶体管正常工作时，避免载流子注入结构2的设置影响薄膜晶体管的正常工作。可选地，设置载流子注入结构2不与源区a2或漏区a3接触，同样有利于在薄膜晶体管正常工作时，避免载流子注入结构2的设置影响薄膜晶体管的正常工作。
结合图1和图2，当薄膜晶体管为顶栅结构的薄膜晶体管时，沿垂直于衬底1的方向，可以设置载流子注入结构2的截面为梯形截面，即沿垂直于衬底1的方向，设置载流子注入结构2的截面的上边缘与两侧边缘之间形成的夹角均大于90°。若由于刻蚀工艺的问题使得沿垂直于衬底1的方向，载流子注入结构2的截面为矩形，即截面的上边缘与两侧边缘之间形成的夹角近似为90°，在后续有源层P成膜的过程中，在载流子注入结构2的边角位置，即上边缘与两侧边缘连接的位置有可能存在有源层P成膜不连续的问题，这就对有源层P成膜工艺的爬坡能力，即台阶覆盖能力提出了较高的要求。本申请实施例可以通过控制载流子注入结构2的刻蚀工艺调整载流子注入结构2沿垂直于衬底1的方向的截面的相邻边缘之间的夹角，使得顶栅结构的薄膜晶体管，沿垂直于衬底1的方向，载流子注入结构2的截面为梯形截面，有效降低了薄膜晶体管的有源层P出现截断问题的概率。
可选地，结合图1和图2，可以设置载流子注入结构2为图案化结构，示例性地设置沿垂直于衬底1的方向，载流子注入结构2的截面为梯形截面，以降低薄膜晶体管的有源层P出现截断问题的概率。
图3为本申请实施例提供的另一种薄膜晶体管的俯视结构示意图，图4为本申请实施例提供的沿图3中BB’方向的剖面结构示意图，与图1和图2所示结构的薄膜晶体管不同的是，图3和图4所示的薄膜晶体管也可以设置载流子注入结构2为面状结构，同样可以设置沿垂直于衬底1的方向，载流子注入结构2的截面为梯形截面，以降低薄膜晶体管的有源层P出现截断问题的概率。 同样的，载流子注入结构2不与源区a2或漏区a3接触，有利于在薄膜晶体管正常工作时，避免载流子注入结构2的设置影响薄膜晶体管的正常工作。
由于薄膜晶体管的有源层P的沟道区a1在受到光照时会产生光生载流子，影响薄膜晶体管的开关特性，因此，对于有机发光显示面板，设置有薄膜晶体管的阵列基板设置于有机发光结构的下方，而在有机发光显示面板中采用顶栅结构的薄膜晶体管，无需增加新的遮光结构，利用薄膜晶体管的栅极G即可充当沟道区a1的遮光结构，改善薄膜晶体管的有源层P沟道区a1受光照产生光生载流子，影响薄膜晶体管的开关特性的问题。
图5为本申请实施例提供的另一种薄膜晶体管的俯视结构示意图，图6为本申请实施例提供的沿图5中CC’方向的剖面结构示意图。结合图5和图6，也可以是设置薄膜晶体管为底栅结构的薄膜晶体管，载流子注入结构2位于有源层P远离栅极G的一侧，即载流子注入结构2位于有源层P的上方，有利于在薄膜晶体管正常工作时，避免载流子注入结构2的设置影响薄膜晶体管的正常工作。同样的，可以设置载流子注入结构2不与源区a2或漏区a3接触，有利于在薄膜晶体管正常工作时，避免载流子注入结构2的设置影响薄膜晶体管的正常工作。
示例性地，结合图5和图6，同样可以设置载流子注入结构2为图案化结构，示例性地设置沿垂直于衬底1的方向，载流子注入结构2的界面为两个梯形截面。也可以设置载流子注入结构2为面状结构，可以设置沿垂直于衬底1的方向，载流子注入结构2的截面为梯形截面，对于底栅结构的薄膜晶体管，对载流子注入结构2沿垂直于衬底1的方向的截面的形状不作限定。
由于薄膜晶体管的有源层P的沟道区a1在受到光照时会产生光生载流子，影响薄膜晶体管的开关特性，因此，对于液晶显示面板等需要背光源的显示面板，背光源位于设置有薄膜晶体管的阵列基板远离出光侧的一侧，背光源发出的光线照射到薄膜晶体管的有源层P的沟道区a1产生光生载流子，而在液晶显示面板等需要背光源的显示面板中采用底栅结构的薄膜晶体管，无需增加新的遮光结构，利用薄膜晶体管的栅极G即可充当沟道区a1的遮光结构，改善背光源发出的光线照射到薄膜晶体管的有源层P的沟道区a1产生光生载流子，影响薄膜晶体管的开关特性的问题。
本申请实施例对薄膜晶体管中载流子注入结构2的数量不作限定，确保载流子注入结构2位于有源层P远离栅极G的一侧，且不与源区a2或漏区a3接触即可。
可选地，结合图1至图6，可以设置沿垂直于衬底1的方向，载流子注入结构2的厚度大于或等于5nm。一实施例中，载流子注入结构2沿垂直于衬底1 的方向的厚度过小会导致载流子注入结构2的载流子注入效果较差，对沟道区a1的残留载流子影响薄膜晶体管的迟滞特性和可靠性的问题的改善效果较差。
结合图1至图4，在薄膜晶体管为顶栅结构的薄膜晶体管的情况下，可以设置沿垂直于衬底1的方向，载流子注入结构2的厚度小于或等于500nm。，对于顶栅结构的薄膜晶体管，载流子注入结构2沿垂直于衬底1的方向的厚度过大会影响薄膜晶体管正常工作时的有效沟道长度，设置沿垂直于衬底1的方向，载流子注入结构2的厚度小于或等于500nm，以避免载流子注入结构2影响薄膜晶体管正常工作时的有效沟道长度，影响薄膜晶体管的开关特性和显示面板的显示效果。
可选地，结合图1至图5，薄膜晶体管还可以包括偏置电极3，薄膜晶体管的载流子注入结构2与偏置电极3电连接，偏置电极3与薄膜晶体管的源极和漏极同层制作或者偏置电极3与薄膜晶体管的栅极G同层制作。
，在薄膜晶体管不工作时，载流子注入结构2需要向薄膜晶体管的有源层P的沟道区a1注入与沟道区a1的残留载流子复合的载流子，由于载流子注入结构2与有源层P的沟道区a1形成肖特基接触，因此需要通过偏置电极3向载流子注入结构2加载偏置电压以抵消载流子注入结构2与有源层P的沟道区a1形成的肖特基势垒，实现载流子注入结构2向薄膜晶体管有源层P的沟道区a1注入与沟道区a1的残留载流子复合的载流子，进而降低薄膜晶体管的有源层P的沟道区a1的残留载流子的浓度，改善沟道区a1的残留载流子影响薄膜晶体管的迟滞特性和可靠性的问题。
在薄膜晶体管正常工作时，载流子注入结构2无需向薄膜晶体管的有源层P的沟道区a1注入载流子，此时可以利用载流子注入结构2与有源层P的沟道区a1之间的肖特基势垒阻挡载流子注入结构2向薄膜晶体管的有源层P的沟道区a1注入载流子以确保薄膜晶体管能够正常工作，也可以通过偏置电极3向载流子注入结构2加载偏置电压，以增大载流子注入结构2与有源层P的沟道区a1之间的肖特基势垒阻挡载流子注入结构2向薄膜晶体管的有源层P的沟道区a1注入载流子，确保薄膜晶体管正常工作。
设置偏置电极3与薄膜晶体管的源极和漏极，即源极S和漏极D同层制作或者偏置电极3与薄膜晶体管的栅极G同层制作，利用薄膜晶体管原本膜层即可实现偏置电极3的制作，简化了薄膜晶体管的制程，进而有利于简化显示面板的制程，偏置电极3可以通过位于偏置电极3和载流子注入结构2之间绝缘层中的过孔实现与载流子注入结构2的电连接。
本申请实施例还提供了一种显示面板，图7为本申请提供的一种显示面板的结构示意图，图8为本申请实施例提供的一种像素单元的结构示意图。结合 图7和图8，显示面板包括多个像素单元4，每个像素单元4包括像素驱动电路和有机发光结构42，像素驱动电路包括上述实施例中所述的薄膜晶体管，因此本申请实施例提供的显示面板也具备上述实施例中所描述的有益效果，本文不再赘述。
示例性地，结合图7和图8，显示面板可以是有机发光显示面板，显示面板还可以包括多条扫描信号线D12、多条数据信号线D13、栅极驱动模块D121、源极驱动模块D131、驱动控制模块D101和电源供给模块D102，像素单元4设置于扫描信号线D12与数据信号线D13交叉设置形成的空间内，栅极驱动模块D121设置为响应驱动控制模块D101产生的扫描驱动控制信号，通过扫描信号线D12向对应的像素单元4的像素驱动电路输入扫描信号，像素驱动电路设置为在与像素驱动电路电连接的扫描信号线D12输入的扫描信号的作用下，连通与像素驱动电路对应电连接的数据信号线D13，源极驱动电路D131设置为响应驱动控制模块D101产生的数据驱动控制信号，通过数据信号线D13向对应的像素单元4的像素驱动电路输入数据信号，电源供给模块D102设置为向像素驱动电路提供第一电源信号VDD和第二电源信号VSS，显示面板依此实现显示功能。
结合图7和图8，示例性地设置像素驱动电路为7T1C结构，即设置像素驱动电路包括7个薄膜晶体管和1个电容结构，薄膜晶体管与电容结构之间的连接关系如图8所示，该像素驱动电路能够实现对驱动晶体管阈值电压的补偿，提高显示面板的发光均匀性。
设置像素驱动电路中至少驱动晶体管T1为薄膜晶体管，驱动晶体管T1设置为向有机发光结构42提供驱动电流Id，有机发光结构42设置为响应驱动电流发光。一实施例中，有机发光结构42的显示亮度取决于驱动晶体管T1向有机发光结构42提供的驱动电流的大小。结合图1至图8，显示面板进行显示画面的切换时，驱动晶体管T1的有源层P的沟道区a1存在残留载流子必然会影响切换后显示画面对应的驱动晶体管T1产生的驱动电流的大小，进而影响切换后画面的显示亮度，导致显示面板存在残影问题。
通过设置像素驱动电路中至少驱动晶体管T1为上述实施例的薄膜晶体管，在驱动晶体管T1不工作时利用载流子注入结构2向驱动晶体管T1的有源层P的沟道区a1注入与源区a2或漏区a3的掺杂载流子类型相反的载流子，即载流子注入结构2向沟道区a1注入的载流子能够与沟道区a1的残留载流子复合，降低驱动晶体管T1的有源层P的沟道区a1的残留载流子的浓度，改善沟道区a1的残留载流子影响薄膜晶体管的迟滞特性和可靠性的问题，进而改善显示面板存在显示残影或亮度退化等问题，优化显示面板的显示效果。另外，有利于实 现在驱动晶体管T1工作时，利用载流子结构与沟道区a1之间形成的肖特基势垒避免载流子注入结构2向沟道区a1注入载流子，影响驱动晶体管T1的正常工作过程，影响显示面板的显示效果。
示例性地，如图8所示，也可以设置像素驱动电路中的其余晶体管为上述实施例的薄膜晶体管，以改善沟道区的残留载流子影响薄膜晶体管的迟滞特性的问题，提高薄膜晶体管工作的稳定性，优化显示面板的显示效果。
本申请实施例对像素驱动电路中薄膜晶体管和电容结构的数量不作限定，可以根据实际需求对像素驱动电路中薄膜晶体管和电容结构的数量进行设置。本申请实施例示附图只是示例性地表示多个结构的尺寸，并不代表薄膜晶体管以及显示面板中多个结构的实际尺寸。
本申请实施例还提供的一种显示装置，图9为本申请实施例提供的一种显示装置的结构示意图。如图9所示，显示装置91包括上述实施例中的显示面板92，因此本申请实施例提供的显示装置91也具备上述实施例中所描述的有益效果，本文不再赘述。示例性地，显示装置可以是手机终端、平板电脑、车载显示装置手机或可穿戴设备等电子设备，本申请实施例对显示装置的形式不作限定。

Claims (10)

  1. 一种薄膜晶体管，包括：
    衬底；
    位于所述衬底上的栅极；
    位于所述衬底上的有源层，所述有源层包括沟道区、位于所述沟道区第一侧的源区以及位于所述沟道区第二侧的漏区；
    位于所述有源层远离所述栅极一侧的载流子注入结构，构成所述载流子注入结构的材料为导体材料；
    所述载流子注入结构与所述有源层的沟道区形成肖特基接触，所述载流子注入结构设置为向所述有源层的沟道区注入与所述源区或所述漏区的掺杂载流子类型相反的载流子。
  2. 根据权利要求1所述的薄膜晶体管，其中，构成所述载流子注入结构的材料为金属材料或者导电氧化物材料。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述源区或所述漏区的掺杂载流子为电子且所述载流子注入结构的功函数大于所述沟道区的功函数；或者，所述源区或所述漏区的掺杂载流子为空穴且所述载流子注入结构的功函数小于所述沟道区的功函数。
  4. 根据权利要求1所述的薄膜晶体管，其中，所述薄膜晶体管为顶栅结构的薄膜晶体管，沿垂直于所述衬底的方向，所述载流子注入结构的截面为梯形截面。
  5. 根据权利要求1所述的薄膜晶体管，其中，沿垂直于所述衬底的方向，所述载流子注入结构的厚度大于或等于5nm；
    在所述薄膜晶体管为顶栅结构的薄膜晶体管的情况下，沿垂直于所述衬底的方向，所述载流子注入结构的厚度小于或等于500nm。
  6. 根据权利要求1所述的薄膜晶体管，还包括：
    位于所述源区上方的源极和位于所述漏区上方的漏极；
    偏置电极，所述载流子注入结构与所述偏置电极电连接，所述偏置电极与所述源极和所述漏极同层制作或者所述偏置电极与所述栅极同层制作。
  7. 根据权利要求1所述的薄膜晶体管，其中，所述载流子注入结构为面状结构或图案化结构。
  8. 根据权利要求1所述的薄膜晶体管，其中，所述载流子注入结构不与所述源区或所述漏区接触。
  9. 一种显示面板，包括：
    多个像素单元，每个像素单元包括像素驱动电路和有机发光结构，所述像素驱动电路包括如权利要求1-8任一项所述的薄膜晶体管；
    所述像素驱动电路中至少驱动晶体管为所述薄膜晶体管，所述驱动晶体管设置为向所述有机发光结构提供驱动电流，所述有机发光结构设置为响应所述驱动电流发光。
  10. 一种显示装置，包括如权利要求9所述的显示面板。
PCT/CN2019/124999 2019-05-15 2019-12-13 薄膜晶体管、显示面板和显示装置 Ceased WO2020228316A1 (zh)

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