WO2020228075A1 - 显示面板及其制作方法 - Google Patents

显示面板及其制作方法 Download PDF

Info

Publication number
WO2020228075A1
WO2020228075A1 PCT/CN2019/089948 CN2019089948W WO2020228075A1 WO 2020228075 A1 WO2020228075 A1 WO 2020228075A1 CN 2019089948 W CN2019089948 W CN 2019089948W WO 2020228075 A1 WO2020228075 A1 WO 2020228075A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
array substrate
polarizer
display panel
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/089948
Other languages
English (en)
French (fr)
Inventor
余朋飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US16/621,923 priority Critical patent/US20210325721A1/en
Publication of WO2020228075A1 publication Critical patent/WO2020228075A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133528—Polarisers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/13356—Structural association of cells with optical devices, e.g. polarisers or reflectors characterised by the placement of the optical elements
    • G02F1/133567—Structural association of cells with optical devices, e.g. polarisers or reflectors characterised by the placement of the optical elements on the back side
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/28—Adhesive materials or arrangements

Definitions

  • the invention relates to the field of display, in particular to a display panel and a manufacturing method thereof.
  • the current low-temperature polysilicon (LTPS) product array substrate consists of a single switching element thin film transistor (Thin Film Transistor, TFT), storage capacitor (Cst) and pixel transparent electrode (Pixel Electrode), use ion implantation to enhance the semiconductor performance of thin film transistors, realize the charging and discharging process of the pixel electrode (Pixel Electrode) under the action of the electric field of the scan line (Gate), and adjust the lower plate voltage of the storage capacitor (Cst) to control The rotation angle of the liquid crystal molecules, so as to realize the colorful display effect of the liquid crystal display products.
  • TFT Thin Film Transistor
  • Cst storage capacitor
  • pixel transparent electrode Pixel Electrode
  • the low-temperature polysilicon array substrates of the existing liquid crystal displays always have a light shielding layer (LS) under the thin film transistor.
  • the light shielding layer will affect the flatness under the semiconductor channel region of the thin film transistor, making it impossible to maintain a completely flat state.
  • the purpose of the present invention is to provide a display panel and a manufacturing method thereof, by removing the shielding layer (LS) on the existing array substrate to maintain the flatness under the semiconductor channel region of the thin film transistor, and the polarization corresponding to the thin film transistor A light-shielding layer is added on the film.
  • a light-shielding layer is attached to the outside of the polarizer to block the light source of the backlight, so as to protect the semiconductor channel area of the thin film transistor from the influence of light, and save the production of the light-shielding layer.
  • one embodiment of the present invention provides a display panel including an array substrate, a backlight source and an array substrate polarizer.
  • the array substrate has a plurality of thin film transistors; the backlight is provided under the array substrate to provide a light source; the array substrate polarizer is provided on the side of the array substrate facing the backlight, The array substrate polarizer has a light shielding part corresponding to the thin film transistor.
  • the array substrate polarizer includes a polarizer body; the shading portion is formed on a side of the polarizer body away from the array substrate.
  • the array substrate polarizer includes a first glue layer and a second glue layer.
  • the first adhesive layer is used for pasting the polarizer body and the array substrate; the second adhesive layer is used for pasting the polarizer body and the backlight.
  • the array substrate includes a substrate layer, a buffer layer and a driving circuit layer.
  • the substrate layer is provided on the side of the array substrate polarizer with the light shielding portion;
  • the buffer layer is provided on the surface on one side of the substrate layer;
  • the driving circuit layer is provided on the back of the buffer layer.
  • One side of the substrate layer; the thin film transistor is arranged in the drive circuit layer.
  • the thin film transistor includes an active layer, a gate insulating layer, a gate layer, an interlayer insulating layer, and a source and drain layer that are stacked.
  • the active layer is provided on the side of the array substrate polarizer with a light shielding portion;
  • the gate insulating layer is provided on the side of the gate layer facing away from the array substrate polarizer;
  • the gate Layer is provided on the side of the gate insulating layer away from the active layer;
  • the interlayer insulating layer is provided on the side of the gate layer away from the gate insulating layer;
  • the source and drain layers are provided on the side The interlayer insulating layer faces away from the gate layer.
  • the light shielding portion corresponds to the active layer.
  • the active layer includes a doped region and a semiconductor channel region; the light shielding portion corresponds to the semiconductor channel region.
  • a manufacturing method of a display panel which includes the following steps:
  • the backlight is assembled on the lower surface of the array substrate.
  • the array substrate polarizer includes a polarizer body, and a first adhesive layer provided on one side of the polarizer body and a second adhesive layer provided on the other side of the polarizer body;
  • the step of attaching to the lower surface of the array substrate includes attaching the array substrate polarizer to the lower surface of the array substrate through the first adhesive layer; and assembling the backlight on the array substrate In the step of the lower surface of the substrate, the backlight is assembled on the lower surface of the array substrate through the second adhesive layer.
  • manufacturing the thin film transistor includes the steps:
  • the active layer including a semiconductor channel region and a doped region
  • the light-shielding part is attached to the side of the array substrate polarizer away from the array substrate, and the light-shielding part corresponds to the semiconductor channel region.
  • the beneficial effect of the present invention is to provide a display panel and a manufacturing method thereof.
  • the shielding layer (LS) on the existing array substrate is removed to maintain the flatness under the semiconductor channel region of the thin film transistor, and the thin film transistor corresponds to A light-shielding layer is added to the polarizer.
  • a light-shielding layer is attached to the outside of the polarizer to block the light source of the backlight, so as to protect the semiconductor channel area of the thin film transistor from the influence of light and save the production of the light-shielding layer.
  • the cost of the photomask is reduced and the production cycle of the array substrate is shortened, thereby shortening the production cycle of the overall manufacturing process of the display panel.
  • FIG. 1 is a schematic structural diagram of a display panel in an embodiment of the present invention
  • Figure 2 is a bottom view of a display panel in an embodiment of the invention.
  • FIG. 3 is a schematic diagram of the structure of the color filter substrate polarizer in an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a display panel in another embodiment of the invention.
  • FIG. 5 is a schematic diagram of the structure of the array substrate in an embodiment of the invention.
  • FIG. 6 is a flowchart of a manufacturing method of a display panel in an embodiment of the present invention.
  • FIG. 7 is a flow chart of manufacturing the thin film transistor in an embodiment of the present invention.
  • FIG. 8 is a flow chart of manufacturing the array substrate in an embodiment of the invention.
  • Liquid crystal layer 6. Polarizer of color film substrate, 10. Thin film transistor, 11. Semiconductor channel region,
  • Polarizer body 204, second adhesive layer, 205, protective film.
  • the component can be directly placed on the other component; there may also be an intermediate component on which the component is placed , And the intermediate component is placed on another component.
  • a component is described as “installed to” or “connected to” another component, both can be understood as directly “installed” or “connected”, or a component is “installed to” or “connected to” through an intermediate component Another component.
  • a display panel 100 which includes an array substrate 1, a backlight source 3, and an array substrate polarizer 2 located between the two.
  • the array substrate 1 has a plurality of thin film transistors 10; the backlight source 3 is provided under the array substrate 1 to provide a light source; and the array substrate polarizer 2 is provided on the array substrate 1 facing all directions.
  • the array substrate polarizer 2 has a light shielding portion 20 corresponding to the thin film transistor 10 for shielding light from the backlight source 3 from entering the thin film transistor 10.
  • the array substrate polarizer 2 has a light shielding portion 20 to shield the light from the light source, which can replace the shielding layer (LS) in the existing array substrate to protect the thin film transistor 10 from the influence of light.
  • LS shielding layer
  • the array substrate polarizer 2 includes a polarizer body 203; the light shielding portion 20 is formed on a side of the polarizer body 203 away from the array substrate 1.
  • the array substrate polarizer 2 further includes a first adhesive layer 202 for pasting the polarizer body 203 and the array substrate 1; and a second adhesive layer 204 for pasting the polarizer body 203 and the array substrate 1 Backlight 3.
  • a release paper 202 is attached to the side of the first adhesive layer 202
  • a protective film 205 is attached to one side of the second adhesive layer 204.
  • the display panel 100 further includes a color filter substrate 4 disposed opposite to the array substrate 1, and located between the array substrate 1 and the color filter substrate 4 The liquid crystal layer5.
  • the display panel 100 further includes a color filter substrate polarizer 6, and the color filter substrate polarizer 6 is disposed on the surface of the color filter substrate 4 away from the array substrate polarizer 2.
  • the color filter substrate 4 includes a color filter. The polarization position of the array substrate polarizer 2 and the color filter substrate 4 are relatively perpendicular to each other. The light passes through the array substrate polarizer 2 to select a portion of the parallel light to enter the liquid crystal cell 1, and then passes through the liquid crystal layer 5. After being deflected by 90 degrees, it can be emitted through the color filter substrate 4.
  • the area of the array substrate 1 is the same as the area of the color filter substrate 4, so that the two can be easily aligned.
  • the array substrate 1 further includes a substrate layer 111, a buffer layer 112 and a driving circuit layer 113.
  • the substrate layer 11 is provided on the side of the array substrate polarizer 2 with the light shielding portion 20; the buffer layer 112 is provided on the surface on the side of the substrate layer 111; the drive circuit layer 113 is provided on The buffer layer 112 is a side away from the substrate layer 111, and the thin film transistor 10 is disposed in the driving circuit layer 113.
  • the material of the substrate layer 111 includes a flexible polyimide substrate; the buffer layer 112 includes a single-layer or multi-layer structure, and the material of the buffer layer 112 is generally SiOx, SiNx or a mixture thereof.
  • the substrate layer 111 or the buffer layer 112 plays a role of buffer protection.
  • the array substrate 1 further includes a flat layer 114, an anode layer 115, and a pixel definition layer 116.
  • the flat layer 114 is provided on the surface of the driving circuit layer 113 away from the substrate;
  • the anode layer 115 is provided on the surface of the flat layer 114 away from the driving circuit layer 113,
  • the anode layer 115 is electrically connected to the driving circuit layer 113 for transmitting electrical signals;
  • the pixel definition layer 116 is provided on the surface of the anode layer 115 away from the flat layer 114.
  • the pixel defining layer 116 is also provided with an organic light-emitting layer (not shown), the organic light-emitting layer is arranged opposite to the anode layer 115, and the organic light-emitting layer passes through the pixel defining layer 116 and is connected to the anode layer. 115, enabling the organic light-emitting layer to obtain an electrical signal to emit light.
  • the thin film transistor 10 includes an active layer 101, a gate insulating layer 102, a gate layer 103, an interlayer insulating layer 104, and a source and drain layer 105.
  • the active layer 101 is provided on the side of the buffer layer 112 away from the substrate layer 111, that is, on the side of the array substrate polarizer 2 with the light shielding portion 20;
  • the gate insulating layer 102 is provided on the side of the active layer 101 away from the buffer layer 112, that is, on the side of the gate layer 101 away from the polarizer 2 of the array substrate;
  • the gate layer 103 is provided on the gate The side of the polar insulating layer 102 away from the active layer 101;
  • the interlayer insulating layer 104 is provided on the side of the gate layer 103 away from the gate insulating layer 102;
  • the source-drain layer 105 is provided on the side The interlayer insulating layer 104 faces away from the gate layer 103.
  • the light shielding portion 20 corresponds the side
  • the active layer 101 includes a doped region 12 and a semiconductor channel region 11, and the light shielding portion 20 corresponds to the semiconductor channel region 11. More specifically, the source 31 is electrically connected to the source region of the doped region 12 through the first via 21, and the drain 32 is electrically connected to the drain of the doped region 12 through the second via 22. Area electrical connection.
  • the above-mentioned active layer 101 is used to form a low-temperature polysilicon type array substrate.
  • the material of the source-drain layer 105 includes a semiconductor. When the source-drain layer 105 is fabricated, doping treatment is performed on both sides of the source-drain layer 105 to form the doped region 12 without doping.
  • the impurity region is the semiconductor channel region 11 for forming ion implantation channels.
  • the light shielding portion 20 is provided corresponding to the semiconductor channel region 11 for shielding light, so as to protect the semiconductor channel region 11 from light.
  • a manufacturing method of the display panel 100 is provided, which includes steps S1-S3.
  • Step S1 fabricate an array substrate 1 having a plurality of thin film transistors 10.
  • Step S2 Provide an array substrate polarizer 2 and attach the array substrate polarizer 2 to the lower surface of the array substrate 1; form a light shielding portion 20 on one side of the array substrate polarizer 1 and the light shielding portion 20 corresponds to the thin film transistor 10.
  • Step S3 Assemble the backlight source 3 on the lower surface of the array substrate 1.
  • the array substrate polarizer 2 includes a polarizer body 203, a first adhesive layer 202 provided on one side of the polarizer body 203, and a second adhesive layer 204 provided on the other side of the polarizer body;
  • the step of attaching the array substrate polarizer 2 to the lower surface of the array substrate 1 includes attaching the array substrate polarizer 2 to the lower surface of the array substrate 1 through the first adhesive layer 202;
  • the backlight source 3 is assembled on the lower surface of the array substrate 1 through the second adhesive layer 204.
  • a release paper 201 is attached to one side of the first adhesive layer 202, and the polarizer body 203 is away from the release paper 201
  • the paper 201 includes a plurality of light-shielding parts 20 on one side, and a protective film 205 is attached to one side of the second adhesive layer 204 to form the polarizer 2 of the array substrate.
  • the schematic diagram of the structure is shown in FIG. 3. When using the array substrate polarizer 2, the release paper 201 and the protective film 205 need to be torn off.
  • the present invention maintains the flatness under the semiconductor channel region 11 of the thin film transistor 10 by removing the shielding layer (LS) on the existing array substrate, and adds a light shielding portion 20 on the polarizer 2 of the array substrate corresponding to the thin film transistor 10 In order to protect the thin film transistor 10 from the influence of light, the production cost and time can be saved.
  • manufacturing the thin film transistor 10 of the array substrate 1 includes the following steps:
  • Step S11 fabricating an active layer 101 on the upper surface of the buffer layer 112, and doping the active layer 101 to form a semiconductor channel region 12 and a doped region 11 on the active layer 101;
  • Step S12 fabricate a gate insulating layer 102 on the side of the active layer 101 facing away from the polarizer 2 of the array substrate;
  • Step S13 fabricating a gate layer 103 on the side of the gate insulating layer 102 away from the active layer 102 and patterning it;
  • Step S14 forming an interlayer insulating layer 104 on the side of the gate layer 103 away from the gate insulating layer 102, and forming a first via 21 and a second via 22 on the upper surface of the interlayer insulating layer 104 , Wherein the bottom of the first via 21 is the source region of the doped region 11, and the bottom of the second via 22 is the drain region of the doped region 11; and
  • Step S15 Fabricate a source/drain layer 105 on the side of the interlayer insulating layer 104 away from the gate layer 103 and pattern it.
  • the source/drain layer 105 fills the first via 21 and the second Two vias 22, a source 31 is formed at the opposite position of the first via 21, and a drain 32 is formed at the opposite position of the second via 22.
  • the light shielding portion 20 is attached to the side of the array substrate polarizer 2 away from the array substrate 1, and the light shielding portion 20 corresponds to the active layer
  • the semiconductor channel region 11 of 101 is to protect the semiconductor channel region 11 from light.
  • the manufacturing of the array substrate 1 includes steps S21-S26.
  • Step S21 Provide a backing layer 111; the material of the backing layer 111 is polyimide (PI) or other buffer materials to play a role of buffer protection.
  • PI polyimide
  • Step S22 fabricate a buffer layer 112 on the upper surface of the substrate layer 111; the buffer layer 112 includes a single-layer or multi-layer structure, and the material of the buffer layer 112 is generally SiOx, SiNx or a mixture thereof.
  • the substrate layer 111 or the buffer layer 112 plays a role of buffer protection.
  • Step S23 Fabricate a driving circuit layer 113 on the side of the buffer layer 112 away from the substrate layer 111; the driving circuit layer 113 has a plurality of thin film transistors 10.
  • Step S24 forming a flat layer 114 on the side of the driving circuit layer 113 away from the buffer layer 112.
  • Step S25 forming an anode layer 115 on the side of the flat layer 114 away from the driving circuit layer 113.
  • the anode layer 115 is electrically connected to the source/drain layer 105 for transmitting electrical signals.
  • Step S26 fabricate a pixel definition layer 116 on the side of the anode layer 115 away from the flat layer 114 and expose the anode layer 115.
  • the pixel defining layer 116 is also provided with an organic light-emitting layer (not shown), the organic light-emitting layer is arranged opposite to the anode layer, and the organic light-emitting layer passes through the pixel defining layer 116 and is connected to the anode layer 115 , So that the organic light-emitting layer obtains an electrical signal to emit light.
  • the beneficial effect of the present invention is to provide a display panel and a manufacturing method thereof.
  • the shielding layer (LS) on the existing array substrate is removed to maintain the flatness under the semiconductor channel region of the thin film transistor, and the thin film transistor corresponds to
  • a light-shielding layer is added to the polarizer of the liquid crystal display product.
  • a light-shielding layer is attached to the outside of the polarizer to block the light source of the backlight, so as to protect the semiconductor channel area of the thin film transistor from the influence of light and save production
  • the cost of the mask of the light-shielding layer shortens the production cycle of the array substrate, thereby shortening the production cycle of the overall manufacturing process of the display panel.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示面板（100）及其制作方法。显示面板（100）包括阵列基板（1）、背光源（3）和阵列基板偏光片（2）。阵列基板（1）具有若干薄膜晶体管（10）；背光源（3）设于阵列基板（1）下方，用以提供光源；阵列基板偏光片（2）设于阵列基板（1）朝向背光源（3）的一面，其具有遮光部（20），遮光部（20）对应于薄膜晶体管（10）。显示面板（100）的制作方法包括步骤：制作阵列基板（1）、制作阵列基板偏光片（2）、贴附阵列基板偏光片（2）和贴附背光源（3）。通过去除现有阵列基板上的屏蔽层（LS）以保持薄膜晶体管（10）的半导体沟道区域（11）下方的平整度，并且在薄膜晶体管（10）相对应的阵列基板偏光片（2）上增加遮光部（20）以保护薄膜晶体管（10）的半导体沟道区域（11）免受光线的影响，可节约生产成本和时间。

Description

显示面板及其制作方法 技术领域
本发明涉及显示领域，尤其涉及一种显示面板及其制作方法。
 背景技术
目前低温多晶硅（LTPS）产品阵列基板由单独的开关元件薄膜晶体管（Thin Film Transistor，TFT）与储存电容(Cst)及像素透明电极(Pixel Electrode)组成，利用离子注入的方式增强薄膜晶体管半导体性能，在扫描线（Gate）的电场作用下实现像素透明电极（Pixel Electrode）的充电放电过程，调节储存电容（Cst）下极板电压以控制液晶分子的旋转角度，从而实现液晶显示器产品炫彩的显示效果。
但是现有液晶显示器的低温多晶硅阵列基板都会在薄膜晶体管下方设置遮光层（LS），遮光层会影响薄膜晶体管半导体沟道区域下方的平整度，使之不能保持完全的平坦状态。
因此，有必要提供一种新的显示面板及其制作方法，以克服现有技术中存在的问题。
 技术问题
本发明的目的在于，提供一种显示面板及其制作方法，通过去除现有阵列基板上的屏蔽层（LS）以保持薄膜晶体管半导体沟道区域下方的平整度，并且在薄膜晶体管相对应的偏光片上增加遮光层，利用液晶显示器产品偏光片贴附后，在偏光片外侧贴附遮光层以遮挡背光源的光源，以保护薄膜晶体管半导体沟道区域免受光线的影响，同时节省制作遮光层的光罩成本并缩短阵列基板的生产周期，从而缩短显示面板整体制程的生产周期。
 技术解决方案
为了解决上述问题，本发明其中一实施例中提供一种显示面板，包括阵列基板、背光源和阵列基板偏光片。具体地讲，所述阵列基板具有若干薄膜晶体管；所述背光源设于所述阵列基板下方，用以提供光源；所述阵列基板偏光片设于所述阵列基板朝向所述背光源的一面，所述阵列基板偏光片具有遮光部，所述遮光部对应于所述薄膜晶体管。
进一步地，所述阵列基板偏光片包括偏光片本体；所述遮光部形成于所述偏光片本体远离所述阵列基板的一面。
进一步地，所述阵列基板偏光片包括第一胶层和第二胶层。所述第一胶层用以粘贴所述偏光片本体以及所述阵列基板；所述第二胶层用以粘贴所述偏光片本体以及所述背光源。
进一步地，所述阵列基板包括衬底层、缓冲层和驱动电路层。具体地讲，所述衬底层设于所述阵列基板偏光片具有遮光部的一面；所述缓冲层设于所述衬底层一侧的表面；所述驱动电路层设于所述缓冲层背离所述衬底层的一面；所述薄膜晶体管设于所述驱动电路层内。
进一步地，所述薄膜晶体管包括层叠设置的有源层、栅极绝缘层、栅极层、层间绝缘层和源漏极层。具体地讲，所述有源层设于所述阵列基板偏光片具有遮光部的一面；所述栅极绝缘层设于所述栅极层背离所述阵列基板偏光片的一面；所述栅极层设于所述栅极绝缘层背离所述有源层的一面；所述层间绝缘层设于所述栅极层背离所述栅极绝缘层的一面；所述源漏极层设于所述层间绝缘层背离所述栅极层的一面。
进一步地，所述遮光部对应于所述有源层。
进一步地，所述有源层包括掺杂区域和半导体沟道区域；所述遮光部对应于所述半导体沟道区域。
本发明又一实施例中提供一种显示面板的制作方法，包括如下步骤：
制作一阵列基板，所述阵列基板具有若干薄膜晶体管；
提供一阵列基板偏光片，将所述阵列基板偏光片贴附于所述阵列基板的下表面；在所述阵列基板偏光片的一面形成遮光部，所述遮光部对应于所述薄膜晶体管；以及
将所述背光源组装于所述阵列基板的下表面。
进一步地，所述阵列基板偏光片包括偏光片本体，以及设于所述偏光片本体一面的第一胶层和设于偏光片本体另一面的第二胶层；在将所述阵列基板偏光片贴附于所述阵列基板的下表面步骤中，包括通过所述第一胶层将所述阵列基板偏光片贴附于所述阵列基板的下表面；在将所述背光源组装于所述阵列基板的下表面步骤中，通过所述第二胶层将所述背光源组装于所述阵列基板的下表面。
进一步地，制作所述薄膜晶体管包括步骤：
制作一有源层，所述有源层包括半导体沟道区以及掺杂区域；
制作栅极绝缘层于所述有源层背离所述阵列基板偏光片的一面；
制作栅极层于所述栅极绝缘层背离所述有源层的一面并图形化处理；
制作层间绝缘层于所述栅极层背离所述栅极绝缘层的一面；以及
制作源漏极层于所述间绝缘层背离所述栅极层的一面并图形化处理；
在形成所述遮光部步骤中，将所述遮光部贴附于所述阵列基板偏光片远离所述阵列基板的一面，且所述遮光部对应于所述半导体沟道区。
 有益效果
本发明的有益效果在于，提供一种显示面板及其制作方法，通过去除现有阵列基板上的屏蔽层（LS）以保持薄膜晶体管半导体沟道区域下方的平整度，并且在薄膜晶体管相对应的偏光片上增加遮光层，利用液晶显示器产品偏光片贴附后，在偏光片外侧贴附遮光层以遮挡背光源的光源，以保护薄膜晶体管半导体沟道区域免受光线的影响，同时节省制作遮光层的光罩成本并缩短阵列基板的生产周期，从而缩短显示面板整体制程的生产周期。
 附图说明
图1为本发明一实施例中一种显示面板的结构示意图；
图2为本发明一实施例中一种显示面板的仰视图；
图3为本发明一实施例中所述彩膜基板偏光片的结构示意图；
图4为本发明另一实施例中一种显示面板的结构示意图；
图5为本发明一实施例中所述阵列基板的结构示意图；
图6为本发明一实施例中一种显示面板的制作方法的流程图；
图7为本发明一实施例中制作所述薄膜晶体管的流程图；
图8为本发明一实施例中制作所述阵列基板的流程图。
图中部件标识如下：
1、阵列基板，2、阵列基板偏光片，3、背光源，4、彩膜基板，
5、液晶层，6、彩膜基板偏光片，10、薄膜晶体管，11、半导体沟道区域，
12、掺杂区域，20、遮光部，21、第一过孔，22、第二过孔，
31、源极，32、漏极，100、显示面板，101、有源层，
102、栅极绝缘层，103、栅极层，104、层间绝缘层，105、源漏极层，
111、衬底层，112、缓冲层，113、驱动电路层，114、平坦层，
115、阳极层，116、像素定义层，201、离型纸，202、第一胶层，
203、偏光片本体，204、第二胶层，205、保护膜。
 本发明的实施方式
以下结合说明书附图详细说明本发明的优选实施例，以向本领域中的技术人员完整介绍本发明的技术内容，以举例证明本发明可以实施，使得本发明公开的技术内容更加清楚，使得本领域的技术人员更容易理解如何实施本发明。然而本发明可以通过许多不同形式的实施例来得以体现，本发明的保护范围并非仅限于文中提到的实施例，下文实施例的说明并非用来限制本发明的范围。
本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是附图中的方向，本文所使用的方向用语是用来解释和说明本发明，而不是用来限定本发明的保护范围。
在附图中，结构相同的部件以相同数字标号表示，各处结构或功能相似的组件以相似数字标号表示。此外，为了便于理解和描述，附图所示的每一组件的尺寸和厚度是任意示出的，本发明并没有限定每个组件的尺寸和厚度。
当某些组件，被描述为“在”另一组件“上”时，所述组件可以直接置于所述另一组件上；也可以存在一中间组件，所述组件置于所述中间组件上，且所述中间组件置于另一组件上。当一个组件被描述为“安装至”或“连接至”另一组件时，二者可以理解为直接“安装”或“连接”，或者一个组件通过一中间组件“安装至”或“连接至”另一个组件。
请参阅图1、图2所示，本发明其中一实施例中提供一种显示面板100，包括阵列基板1、背光源3和位于两者之间的阵列基板偏光片2。具体地讲，所述阵列基板1具有若干薄膜晶体管10；所述背光源3设于所述阵列基板1下方，用以提供光源；所述阵列基板偏光片2设于所述阵列基板1朝向所述背光源3的一面，所述阵列基板偏光片2具有遮光部20，所述遮光部20对应于所述薄膜晶体管10，用以遮挡所述背光源3的光线进入所述薄膜晶体管10。这样在所述阵列基板偏光片2具有遮光部20以遮挡光源的光线，可代替现有的阵列基板内的屏蔽层（LS），以保护所述薄膜晶体管10免受光线的影响。
请参阅图3所示，所述阵列基板偏光片2包括偏光片本体203；所述遮光部20形成于所述偏光片本体203远离所述阵列基板1的一面。所述阵列基板偏光片2还包括第一胶层202，用以粘贴所述偏光片本体203以及所述阵列基板1；以及第二胶层204，用以粘贴所述偏光片本体203以及所述背光源3。在使用所述阵列基板偏光片2前，为了保持所述第一胶层202和所述第二胶层204的粘性，在所述第一胶层202一侧贴附一离型纸202，在所述第二胶层204一侧贴附一保护膜205。
请参阅图4所示，在其他实施例中，所述显示面板100还包括与所述阵列基板1相对设置的彩膜基板4，及位于所述阵列基板1与所述彩膜基板4之间的液晶层5。并且所述显示面板100还包括彩膜基板偏光片6，所述彩膜基板偏光片6设于所述彩膜基板4背离所述阵列基板偏光片2的表面。所述彩膜基板4包括彩色滤光片。所述阵列基板偏光片2与所述彩膜基板4的偏光位置相对垂直设置，光线经所述阵列基板偏光片2选择部分平行光线进入所述液晶盒1内，经所述液晶层5的进行90度的偏转后可通过所述彩膜基板4射出。其中所述阵列基板1的面积与所述彩膜基板4的面积相同，这样可使得两者对位方便。
请参阅图5所示，在本实施例中，所述阵列基板1还包括衬底层111、缓冲层112和驱动电路层113。具体地讲，所述衬底层11设于所述阵列基板偏光片2具有遮光部20的一面；所述缓冲层112设于所述衬底层111一侧的表面；所述驱动电路层113设于所述缓冲层112背离所述衬底层111的一面，所述薄膜晶体管10设于所述驱动电路层113内。其中，所述衬底层111的材料包括柔性聚酰亚胺衬底；所述缓冲层112包括单层或多层结构，所述缓冲层112的材料一般为SiOx、SiNx或其混合物。所述衬底层111或所述缓冲层112起到缓冲保护的作用。
在本实施例中，所述阵列基板1还包括平坦层114、阳极层115和像素定义层116。具体地讲，所述平坦层114设于所述驱动电路层113远离所述基板一侧的表面；所述阳极层115设于所述平坦层114远离所述驱动电路层113一侧的表面，所述阳极层115电连接至所述驱动电路层113，用以传输电信号；所述像素定义层116设于所述阳极层115远离所述平坦层114一侧的表面。所述像素定义层116上还设有有机发光层（图未示），所述有机发光层与所述阳极层115相对设置，有机发光层穿过所述像素定义层116连接至所述阳极层115，使得所述有机发光层获得电信号，用以发光。
请参阅图5所示，在本实施例中，所述薄膜晶体管10包括有源层101、栅极绝缘层102、栅极层103、层间绝缘层104和源漏极层105。具体地讲，所述有源层101设于所述缓冲层112背离所述衬底层111的一面，亦即设于所述阵列基板偏光片2具有遮光部20的一面；所述栅极绝缘层102设于所述有源层101背离所述缓冲层112的一面，亦即设于所述栅极层101背离所述阵列基板偏光片2的一面；所述栅极层103设于所述栅极绝缘层102背离所述有源层101的一面；所述层间绝缘层104设于所述栅极层103背离所述栅极绝缘层102的一面；所述源漏极层105设于所述层间绝缘层104背离所述栅极层103的一面。其中，所述遮光部20对应于所述有源层101，以保护所述有源层101免受光线的影响。
请参阅图5所示，在本实施例中，所述有源层101包括掺杂区域12和半导体沟道区域11，所述遮光部20对应于所述半导体沟道区域11。更具体的，所述源极31通过第一过孔21与所述掺杂区域12的源极区域电连接，所述漏极32通过第二过孔22与所述掺杂区域12的漏极区域电连接。以上所述有源层101用于形成低温多晶硅型阵列基板。其中，所述源漏极层105的材料包括半导体，当所述源漏极层105制作完成，对所述源漏极层105两侧进行掺杂处理，形成所述掺杂区域12，未掺杂的区域为所述半导体沟道区域11，用于形成离子注入沟道。所述遮光部20对应所述半导体沟道区域11设置用于遮光，以保护所述半导体沟道区域11免受光线的影响。
请再参阅图6所示，本发明其中一实施例中提供一种显示面板100的制作方法，包括步骤S1-S3。
步骤S1：制作一阵列基板1，所述阵列基板1具有若干薄膜晶体管10。
步骤S2：提供一阵列基板偏光片2，将所述阵列基板偏光片2贴附于所述阵列基板1的下表面；在所述阵列基板偏光片1的一面形成遮光部20，所述遮光部20对应于所述薄膜晶体管10。
步骤S3：将所述背光源3组装于所述阵列基板1的下表面。
其中，所述阵列基板偏光片2包括偏光片本体203，以及设于所述偏光片本体203一面的第一胶层202和设于偏光片本体另一面的第二胶层204；在将所述阵列基板偏光片2贴附于所述阵列基板1的下表面步骤中，包括通过所述第一胶层202将所述阵列基板偏光片2贴附于所述阵列基板1的下表面；在将所述背光源3组装于所述阵列基板1的下表面步骤中，通过所述第二胶层204将所述背光源3组装于所述阵列基板1的下表面。
为了保持所述第一胶层202和所述第二胶层204的粘性，在所述第一胶层202一侧贴附一离型纸201，在所述偏光片本体203背离所述离型纸201一面包括若干遮光部20，在所述第二胶层204一侧贴附一保护膜205，形成阵列基板偏光片2，其结构示意图见图3所示。在使用所述阵列基板偏光片2时需将所述离型纸201和所述保护膜205撕除。
本发明通过去除现有阵列基板上的屏蔽层（LS）以保持薄膜晶体管10半导体沟道区域11下方的平整度，并且在薄膜晶体管10相对应的所述阵列基板偏光片2上增加遮光部20以保护薄膜晶体管10免受光线的影响，可节约生产成本和时间。
请参阅图7所示，在本实施例中，制作所述阵列基板1的薄膜晶体管10包括步骤：
步骤S11：制作一有源层101于所述缓冲层112的上表面，并对有源层101进行掺杂，以在有源层101上形成半导体沟道区12以及掺杂区域11；
步骤S12：制作栅极绝缘层102于所述有源层101背离所述阵列基板偏光片2的一面；
步骤S13：制作栅极层103于所述栅极绝缘层102背离所述有源层102的一面并图形化处理；
步骤S14：制作层间绝缘层104于所述栅极层103背离所述栅极绝缘层102的一面，并在所述层间绝缘层104上表面制作第一过孔21、第二过孔22，其中所述第一过孔21的孔底为所述掺杂区域11的源极区域，所述第二过孔22的孔底为所述掺杂区域11的漏极区域；以及
步骤S15：制作源漏极层105于所述层间绝缘层104背离所述栅极层103的一面并图形化处理，所述源漏极层105填充所述第一过孔21和所述第二过孔22，在所述第一过孔21相对位置形成源极31，在所述第二过孔22相对位置形成漏极32。
其中，在形成所述遮光部20步骤中，将所述遮光部20贴附于所述阵列基板偏光片2远离所述阵列基板1的一面，且所述遮光部20对应于所述有源层101的所述半导体沟道区域11，以保护所述半导体沟道区域11免受光线的影响。
请参阅图8所示，在本实施例中，所述制作阵列基板1包括步骤S21-S26。
步骤S21：提供一衬底层111；所述衬底层111的材质为聚酰亚胺（PI）或其他缓冲材质，起到缓冲保护的作用。
步骤S22：制作缓冲层112于所述衬底层111的上表面；所述缓冲层112包括单层或多层结构，所述缓冲层112的材料一般为SiOx、SiNx或其混合物。所述衬底层111或所述缓冲层112起到缓冲保护的作用。
步骤S23：制作驱动电路层113于所述缓冲层112背离所述衬底层111的一面；所述驱动电路层113具有若干薄膜晶体管10。
步骤S24：制作平坦层114于所述驱动电路层113背离所述缓冲层112的一面。
步骤S25：制作阳极层115于所述平坦层114背离所述驱动电路层113的一面。所述阳极层115与所述源漏极层105电连接，用以传输电信号。
步骤S26：制作像素定义层116于所述阳极层115背离所述平坦层114的一面并裸露所述阳极层115。所述像素定义层116上还设有有机发光层（图未示），有机发光层与所述阳极层相对设置，所述有机发光层穿过所述像素定义层116连接至所述阳极层115，使得所述有机发光层获得电信号，用以发光。
本发明的有益效果在于，提供一种显示面板及其制作方法，通过去除现有阵列基板上的屏蔽层（LS）以保持薄膜晶体管的半导体沟道区域下方的平整度，并且在薄膜晶体管相对应的偏光片上增加遮光层，利用液晶显示器产品偏光片贴附后，在偏光片外侧贴附遮光层以遮挡背光源的光源，以保护薄膜晶体管的半导体沟道区域免受光线的影响，同时节省制作遮光层的光罩成本并缩短阵列基板的生产周期，从而缩短显示面板整体制程的生产周期。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种显示面板，包括：
    阵列基板，具有若干薄膜晶体管；
    背光源，设于所述阵列基板下方，用以提供光源；以及
    阵列基板偏光片，设于所述阵列基板朝向所述背光源的一面，所述阵列基板偏光片具有遮光部，所述遮光部对应于所述薄膜晶体管。
  2. 根据权利要求1所述的显示面板，其中，所述阵列基板偏光片包括
    偏光片本体；所述遮光部形成于所述偏光片本体远离所述阵列基板的一面。
  3. 根据权利要求1所述的显示面板，其中，所述阵列基板偏光片包括：
    第一胶层，用以粘贴所述偏光片本体以及所述阵列基板；以及
    第二胶层，用以粘贴所述偏光片本体以及所述背光源。
  4. 根据权利要求1所述的显示面板，其中，所述阵列基板包括：
    衬底层，设于所述阵列基板偏光片具有遮光部的一面；
    缓冲层，设于所述衬底层一侧的表面；以及
    驱动电路层，设于所述缓冲层背离所述衬底层的一面；所述薄膜晶体管设于所述驱动电路层内。
  5. 根据权利要求1所述的显示面板，其中，所述薄膜晶体管包括：
    有源层，设于所述阵列基板偏光片具有遮光部的一面；
    栅极绝缘层，设于所述栅极层背离所述阵列基板偏光片的一面；
    栅极层，设于所述栅极绝缘层背离所述有源层的一面；
    层间绝缘层，设于所述栅极层背离所述栅极绝缘层的一面；以及
    源漏极层，设于所述层间绝缘层背离所述栅极层的一面。
  6. 根据权利要求5所述的显示面板，其中，所述遮光部对应于所述有源层。
  7. 根据权利要求5所述的显示面板，其中，所述有源层包括：
    掺杂区域；以及
    半导体沟道区域；
    所述遮光部对应于所述半导体沟道区域。
  8. 一种显示面板的制作方法，包括如下步骤：
    制作一阵列基板，所述阵列基板具有若干薄膜晶体管；
    提供一阵列基板偏光片，将所述阵列基板偏光片贴附于所述阵列基板的下表面；在所述阵列基板偏光片的一面形成遮光部，所述遮光部对应于所述薄膜晶体管；以及
    将所述背光源组装于所述阵列基板的下表面。
  9. 根据权利要求8所述的显示面板的制作方法，其中，所述阵列基板偏光片包括
    偏光片本体，以及
    第一胶层，设于所述偏光片本体的一面；
    第二胶层，设于偏光片本体的另一面；
    在将所述阵列基板偏光片贴附于所述阵列基板的下表面步骤中，包括通过所述第一胶层将所述阵列基板偏光片贴附于所述阵列基板的下表面；在将所述背光源组装于所述阵列基板的下表面步骤中，通过所述第二胶层将所述背光源组装于所述阵列基板的下表面。
  10. 根据权利要求8所述的显示面板的制作方法，其中，所述制作阵列基板包括步骤：
    制作一有源层，所述有源层包括半导体沟道区以及掺杂区域；
    制作栅极绝缘层于所述有源层背离所述阵列基板偏光片的一面；
    制作栅极层于所述栅极绝缘层背离所述有源层的一面并图形化处理；
    制作层间绝缘层于所述栅极层背离所述栅极绝缘层的一面；以及
    制作源漏极层于所述间绝缘层背离所述栅极层的一面并图形化处理；
    在形成所述遮光部步骤中，将所述遮光部贴附于所述阵列基板偏光片远离所述阵列基板的一面，且所述遮光部对应于所述半导体沟道区。
PCT/CN2019/089948 2019-05-16 2019-06-04 显示面板及其制作方法 Ceased WO2020228075A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/621,923 US20210325721A1 (en) 2019-05-16 2019-06-04 Display panel and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910404859.1 2019-05-16
CN201910404859.1A CN110211970A (zh) 2019-05-16 2019-05-16 显示面板及其制作方法

Publications (1)

Publication Number Publication Date
WO2020228075A1 true WO2020228075A1 (zh) 2020-11-19

Family

ID=67787363

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/089948 Ceased WO2020228075A1 (zh) 2019-05-16 2019-06-04 显示面板及其制作方法

Country Status (3)

Country Link
US (1) US20210325721A1 (zh)
CN (1) CN110211970A (zh)
WO (1) WO2020228075A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116779628B (zh) * 2023-07-31 2024-06-11 惠科股份有限公司 光感应阵列基板及其制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN203433236U (zh) * 2013-09-02 2014-02-12 京东方科技集团股份有限公司 阵列基板及3d显示装置
CN104698525A (zh) * 2015-03-31 2015-06-10 合肥京东方光电科技有限公司 一种偏光片、其制作方法、液晶显示面板及显示装置
US20160197106A1 (en) * 2015-01-06 2016-07-07 Samsung Display Co., Ltd. Photo mask and method of manufacturing thin film transistor using the same
CN106874866A (zh) * 2017-02-13 2017-06-20 京东方科技集团股份有限公司 显示装置及其控制方法
CN107479288A (zh) * 2017-09-06 2017-12-15 深圳市华星光电半导体显示技术有限公司 液晶面板及其制作方法
CN109037242A (zh) * 2018-08-01 2018-12-18 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN203433236U (zh) * 2013-09-02 2014-02-12 京东方科技集团股份有限公司 阵列基板及3d显示装置
US20160197106A1 (en) * 2015-01-06 2016-07-07 Samsung Display Co., Ltd. Photo mask and method of manufacturing thin film transistor using the same
CN104698525A (zh) * 2015-03-31 2015-06-10 合肥京东方光电科技有限公司 一种偏光片、其制作方法、液晶显示面板及显示装置
CN106874866A (zh) * 2017-02-13 2017-06-20 京东方科技集团股份有限公司 显示装置及其控制方法
CN107479288A (zh) * 2017-09-06 2017-12-15 深圳市华星光电半导体显示技术有限公司 液晶面板及其制作方法
CN109037242A (zh) * 2018-08-01 2018-12-18 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板

Also Published As

Publication number Publication date
CN110211970A (zh) 2019-09-06
US20210325721A1 (en) 2021-10-21

Similar Documents

Publication Publication Date Title
JP5101116B2 (ja) 表示装置及びその製造方法
KR101641358B1 (ko) 액정표시장치 및 그의 제조방법
CN202601619U (zh) 一种薄膜晶体管、阵列基板和显示器
JP5674875B2 (ja) 半導体装置
CN110400811A (zh) 阵列基板和显示装置
TWI235014B (en) Organic electroluminescent display device and method of fabricating the same
JP2013187536A (ja) アレイ基板及びその製造方法
JP5384088B2 (ja) 表示装置
WO2015043268A1 (zh) 阵列基板及其制备方法、和显示装置
JP2010206154A (ja) 表示装置
WO2020056803A1 (zh) 显示面板及其制作方法、显示模组
WO2015039389A1 (zh) 阵列基板及其制作方法、显示装置
WO2020107723A1 (zh) 一种阵列基板及显示面板
WO2020124903A1 (zh) 阵列基板及显示面板
US9230995B2 (en) Array substrate, manufacturing method thereof and display device
WO2020211158A1 (zh) 显示面板和薄膜晶体管的制作方法
TWI424237B (zh) 顯示裝置及製造其之方法
JP2009042255A (ja) 液晶表示装置
JP2006516162A (ja) 薄膜トランジスタアレイ基板及びこれを含む液晶表示装置
US7671956B2 (en) Liquid crystal display panel and fabricating method thereof
JP5120828B2 (ja) 薄膜トランジスタ基板とその製造方法、及びこれを有する液晶表示パネルとその製造方法
WO2014190710A1 (zh) 阵列基板、显示装置及阵列基板的制备方法
WO2020228075A1 (zh) 显示面板及其制作方法
CN111564453B (zh) 背板、背板的制备方法和背光模组
JP5405770B2 (ja) 表示装置およびその製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19928779

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19928779

Country of ref document: EP

Kind code of ref document: A1