WO2020224073A1 - 显示面板、显示装置及栅极点电位的补偿方法 - Google Patents

显示面板、显示装置及栅极点电位的补偿方法 Download PDF

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Publication number
WO2020224073A1
WO2020224073A1 PCT/CN2019/099399 CN2019099399W WO2020224073A1 WO 2020224073 A1 WO2020224073 A1 WO 2020224073A1 CN 2019099399 W CN2019099399 W CN 2019099399W WO 2020224073 A1 WO2020224073 A1 WO 2020224073A1
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WIPO (PCT)
Prior art keywords
potential
display panel
detection circuit
dummy
detection
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PCT/CN2019/099399
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English (en)
French (fr)
Inventor
薛炎
韩佰祥
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Publication of WO2020224073A1 publication Critical patent/WO2020224073A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • This application relates to the field of display technology, in particular to a display panel, a display device, and a method for compensating the potential of a grid point.
  • AMOLED Active-matrix Organic light-emitting diode, active matrix organic light-emitting diode or active matrix organic light-emitting diode
  • the horizontal scanning line of the display panel is driven by an external integrated circuit.
  • the external integrated circuit can control the step-by-step turn-on of each row scan line, and use GOA (Gate The Driver on Array method can integrate the row scan driving circuit on the display panel substrate.
  • the number of external integrated circuits can be reduced, thereby reducing the production cost of the display panel, and achieving a narrow frame of the display device.
  • IGZO indium gallium zinc oxide
  • IGZO-GOA circuits has high mobility and good device stability, and is currently widely used in IGZO-GOA circuits.
  • the function of the pull-down sustaining circuit in the GOA circuit is to maintain the Q point, the low level of the level transmission signal Cout(n) and the output signal Out(n).
  • the potential of the gate point (QB point) of the pull-down sustaining circuit is controlled by the inverter, because the TFT (Thin Film Transistor, thin film transistor) has been subjected to stress, Vth (Threshold Voltage, threshold voltage) is easy to be forward biased. If the Vth is positively biased, it will cause the potential of the QB point to decrease. On the one hand, the decrease in the potential of the QB point will reduce the potential maintenance ability of the pull-down sustaining circuit, and on the other hand, it will affect the fall time of the output signal and increase the fall time.
  • the potential of the gate point is easily reduced, resulting in a reduction in the potential maintenance capability of the pull-down sustaining circuit, which in turn affects the output signal of the display panel.
  • the potential of the gate point is easily reduced, resulting in a reduction in the potential maintenance capability of the pull-down sustaining circuit, which in turn affects the output signal of the display panel.
  • the embodiments of the present application provide a display panel, a display device, and a method for compensating the potential of the grid point, which can easily detect the potential of the grid point (QB point), so that the display panel can adjust the potential of the grid point (QB point). Therefore, the sustaining ability of the pull-down sustaining circuit is maintained, the influence on the output signal of the display panel is avoided, and the energy consumption of the display panel is reduced.
  • the present application provides a display panel, the display panel includes a detection circuit, the detection circuit is used to detect the potential of the grid point in the display panel, the first end of the detection circuit A first preset potential is connected, the second end of the detection circuit is connected to the gate point, and the third end of the detection circuit is connected to a dummy detection line, wherein the dummy detection line works on the display panel Input a second preset potential to the third terminal of the detection circuit;
  • the dummy detection line stops inputting the second preset potential, the third terminal and the second terminal of the detection circuit are turned on, and the display panel is used for detecting the dummy detection
  • the potential on the line is used to obtain the potential of the gate point, and compensate the potential of the gate point.
  • the display panel includes a display area and a dummy area, the dummy area is located at the periphery of the display area, and the detection circuit is located in the dummy area.
  • the first end of the detection circuit is connected to a dummy data line, the dummy data line is parallel to the dummy detection line, and the dummy data line inputs the first preset to the first end of the detection circuit Potential.
  • the display panel includes a driving circuit, the driving circuit is respectively connected to the dummy data line and the dummy detection line, and the driving circuit inputs the data to the first end of the detection circuit through the dummy data line.
  • the first preset potential when the display panel is working, the driving circuit inputs the second preset potential to the third terminal of the detection circuit through the dummy detection line, and the third terminal of the detection circuit Terminal and the second terminal are disconnected; when the display panel is closed, the drive circuit stops inputting the second preset potential to the third terminal of the detection circuit, and the display panel is used to pass the drive circuit
  • the potential on the dummy detection line is detected to obtain the potential of the gate point, and the potential of the gate point is compensated.
  • the detection circuit is an N-type transistor
  • the first end of the detection circuit is the gate of the N-type transistor
  • the third end of the detection circuit is the source of the N-type transistor.
  • the second terminal of the detection circuit is the drain of the N-type transistor.
  • the display panel includes GOA circuits, the GOA circuits are located on both sides of the display panel and are located outside the dummy area, the GOA circuit includes an inverter, and the inverter includes a first transistor And a second transistor, the drain and gate of the first transistor are connected to a third preset potential, the source of the first transistor, the source of the second transistor and the gate point are connected, the The gate of the second transistor is connected to point Q, and the drain of the second transistor is connected to a fourth preset potential, wherein the fourth preset potential is smaller than the third preset potential.
  • the display panel includes at least two detection circuits and at least two gate points, and the at least two gate points are connected to the second ends of the at least two detection circuits in a one-to-one correspondence.
  • the present application provides a display device, including a display panel, the display panel includes a detection circuit, the detection circuit is used to detect the potential of the grid point in the display panel, the detection circuit The first end of the detection circuit is connected to a first preset potential, the second end of the detection circuit is connected to the gate point, and the third end of the detection circuit is connected to a dummy detection line, wherein the dummy detection line is Inputting a second preset potential to the third terminal of the detection circuit when the display panel is working;
  • the dummy detection line stops inputting the second preset potential, the third terminal and the second terminal of the detection circuit are turned on, and the display panel is used for detecting the dummy detection
  • the potential on the line is used to obtain the potential of the gate point, and compensate the potential of the gate point.
  • the display panel includes a display area and a dummy area, the dummy area is located at the periphery of the display area, and the detection circuit is located in the dummy area.
  • the first end of the detection circuit is connected to a dummy data line, the dummy data line is parallel to the dummy detection line, and the dummy data line inputs the first preset to the first end of the detection circuit Potential.
  • the display panel includes a driving circuit, the driving circuit is respectively connected to the dummy data line and the dummy detection line, and the driving circuit inputs the data to the first end of the detection circuit through the dummy data line.
  • the first preset potential when the display panel is working, the driving circuit inputs the second preset potential to the third terminal of the detection circuit through the dummy detection line, and the third terminal of the detection circuit Terminal and the second terminal are disconnected; when the display panel is closed, the drive circuit stops inputting the second preset potential to the third terminal of the detection circuit, and the display panel is used to pass the drive circuit
  • the potential on the dummy detection line is detected to obtain the potential of the gate point, and the potential of the gate point is compensated.
  • the detection circuit is an N-type transistor
  • the first end of the detection circuit is the gate of the N-type transistor
  • the third end of the detection circuit is the source of the N-type transistor.
  • the second terminal of the detection circuit is the drain of the N-type transistor.
  • the display panel includes GOA circuits, the GOA circuits are located on both sides of the display panel and are located outside the dummy area, the GOA circuit includes an inverter, and the inverter includes a first transistor And a second transistor, the drain and gate of the first transistor are connected to a third preset potential, the source of the first transistor, the source of the second transistor and the gate point are connected, the The gate of the second transistor is connected to point Q, and the drain of the second transistor is connected to a fourth preset potential, wherein the fourth preset potential is smaller than the third preset potential.
  • the display panel includes at least two detection circuits and at least two gate points, and the at least two gate points are connected to the second ends of the at least two detection circuits in a one-to-one correspondence.
  • the present application provides a method for compensating the potential of a gate point
  • the compensation method is applied to a display panel
  • the display panel includes a detection circuit
  • the detection circuit is used to detect The potential of the gate point
  • the first end of the detection circuit is connected to a first preset potential
  • the second end of the detection circuit is connected to the gate point
  • the third end of the detection circuit is connected to the dummy detection line
  • the dummy detection line inputs a second preset potential to the third terminal of the detection circuit when the display panel is working; when the display panel is closed, the dummy detection line stops inputting the second preset Set the potential, the third terminal and the second terminal of the detection circuit are turned on, and the display panel is used to obtain the potential of the gate point by detecting the potential on the dummy detection line, and to determine the potential of the gate point.
  • Perform compensation includes:
  • the potential of the gate point is compensated according to the compensation potential value.
  • the display panel includes a first transistor, the drain and gate of the first transistor are connected to a third preset potential, and the source of the first transistor is connected to the gate point;
  • the compensating the potential of the gate point according to the compensation potential value includes:
  • the display panel includes a first transistor, the drain and gate of the first transistor are connected to a third preset potential, and the source of the first transistor is connected to the gate point;
  • the compensating the potential of the gate point according to the compensation potential value includes:
  • the display panel includes a display area and a dummy area, the dummy area is located at the periphery of the display area, and the detection circuit is located in the dummy area.
  • the first end of the detection circuit is connected to a dummy data line, the dummy data line is parallel to the dummy detection line, and the dummy data line inputs the first preset to the first end of the detection circuit Potential.
  • the display panel includes a driving circuit, the driving circuit is respectively connected to the dummy data line and the dummy detection line, and the driving circuit inputs the data to the first end of the detection circuit through the dummy data line.
  • the first preset potential when the display panel is working, the driving circuit inputs the second preset potential to the third terminal of the detection circuit through the dummy detection line, and the third terminal of the detection circuit Terminal and the second terminal are disconnected; when the display panel is closed, the drive circuit stops inputting the second preset potential to the third terminal of the detection circuit, and the display panel is used to pass the drive circuit
  • the potential on the dummy detection line is detected to obtain the potential of the gate point, and the potential of the gate point is compensated.
  • the detection circuit is an N-type transistor
  • the first end of the detection circuit is the gate of the N-type transistor
  • the third end of the detection circuit is the source of the N-type transistor.
  • the second terminal of the detection circuit is the drain of the N-type transistor.
  • this application provides a display panel, the display panel includes a detection circuit, the detection circuit is used to detect the potential of the grid point in the display panel, and the first end of the detection circuit is connected to a first preset potential, The second end of the detection circuit is connected to the gate point, and the third end of the detection circuit is connected to the dummy detection line, wherein the dummy detection line inputs the second preset potential to the third end of the detection circuit when the display panel is working; When closed, the dummy detection line stops inputting the second preset potential, and the third terminal and the second terminal of the detection circuit are turned on.
  • the display panel is used to obtain the potential of the gate point by detecting the potential on the dummy detection line. Potential compensation.
  • This application uses the dummy detection line of the detection circuit to detect the potential of the gate point.
  • the potential of the gate point can be detected more conveniently, and then the potential of the gate point can be reasonably compensated, so as to maintain the maintenance ability of the pull-down sustain circuit and avoid influence
  • the output signal of the display panel on the other hand, the dummy detection line in the display panel is reasonably used, which improves the utilization rate of the dummy detection line and reduces the energy consumption of the display panel.
  • FIG. 1 is a schematic structural diagram of an embodiment of a display panel provided by an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of another embodiment of a display panel provided by an embodiment of the present application.
  • Fig. 3 is a schematic structural diagram of an embodiment of the inverter in Fig. 2;
  • Fig. 4 is a schematic structural diagram of an embodiment of the detection circuit in Fig. 2;
  • FIG. 5 is a schematic flowchart of an embodiment of a method for compensating gate point potential provided by an embodiment of the present application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.
  • features defined with “first” and “second” may explicitly or implicitly include one or more features.
  • “multiple” means two or more than two, unless otherwise specifically defined.
  • the embodiment of the present application provides a display panel including a detection circuit, the detection circuit is used to detect the potential of the gate point in the display panel, the first end of the detection circuit is connected to the first preset potential, and the second end of the detection circuit is connected to the gate point Connected, the third end of the detection circuit is connected to the dummy detection line, wherein the dummy detection line inputs the second preset potential to the third end of the detection circuit when the display panel is working; when the display panel is closed, the dummy detection line stops inputting the first Two preset potentials, the third terminal and the second terminal of the detection circuit are turned on, and the display panel is used to obtain the potential of the gate point by detecting the potential on the dummy detection line to compensate the potential of the gate point.
  • the detection circuit is used to detect the potential of the gate point in the display panel
  • the first end of the detection circuit is connected to the first preset potential
  • the second end of the detection circuit is connected to the gate point Connected
  • the third end of the detection circuit is
  • FIG. 1 is a schematic structural diagram of an embodiment of a display panel provided by an embodiment of the present application.
  • the display panel 10 includes a detection circuit 12 for detecting the potential of the grid point 13 in the display panel 10, and the first end of the detection circuit 12 is connected to a first preset potential.
  • the detection circuit 12 is connected to the first preset potential input terminal 129, and the first preset potential input terminal 129 inputs the first preset potential to the first terminal of the detection circuit 12.
  • the second end of the detection circuit 12 is connected to the gate point 13, and the third end of the detection circuit 12 is connected to the dummy detection line 11.
  • the dummy detection line 11 inputs the second input to the third end of the detection circuit 12 when the display panel 10 is working.
  • the preset potential when the display panel 10 is closed, the dummy detection line 11 stops inputting the second preset potential, the third end and the second end of the detection circuit 12 are turned on, and the display panel 10 is used to detect the voltage on the dummy detection line 11
  • the potential is used to obtain the potential of the gate point 13 and compensate the potential of the gate point 13.
  • the number of detection circuits 12 in the display panel 10 can be one or more, which can be determined according to the number of gate points 13.
  • the display panel 10 includes at least two gate points 13 and at least two detection circuits 12, and at least two gate points 13 are connected to the second ends of the at least two detection circuits 12 in a one-to-one correspondence.
  • the detection circuits 12 are respectively used to detect the potentials of the gate points 13 connected thereto.
  • FIG. 2 is a schematic structural diagram of another embodiment of a display panel provided by an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of an embodiment of the inverter in FIG.
  • Figure 4 is a schematic structural diagram of an embodiment of the detection circuit in Figure 2.
  • the display panel 20 includes a driving circuit 26, a GOA circuit 24, and a detection circuit 22.
  • the display panel 20 includes a display area 21 and a dummy area 23, the dummy area 23 is located at the periphery of the display area 21, and the detection circuit 22 is located in the dummy area 23. Specifically, a plurality of dummy pixels are provided in the dummy area 23, the dummy pixels are located on the outermost side of the pixels of the display panel 20, and the detection circuit 22 and the dummy pixels share the same circuit design layout. In this embodiment, the potential of the gate point 251 can be detected while not occupying other areas other than the dummy pixels in the display panel 20.
  • the display panel 20 includes GOA circuits 24, and the GOA circuits 24 are located on both sides of the display panel 20 and are located outside the dummy area 23.
  • the GOA circuit 24 includes an inverter 25.
  • the inverter 25 includes a first transistor T3 and a second transistor T4.
  • the drain and gate of the first transistor T3 are connected to the third preset potential VGH, and the source of the first transistor T3
  • the source and gate of the second transistor T4 are connected to point 251, the gate of the second transistor T4 is connected to point Q, and the drain of the second transistor T4 is connected to a fourth preset potential VGL, where the fourth preset potential VGL Less than the third preset potential VGH.
  • the detection circuit 22 is used to detect the potential of the gate point 251 in the display panel 20.
  • the first end of the detection circuit 22 is connected to a dummy data line 232, the dummy data line 232 is parallel to the dummy detection line 231, and the dummy data line 232 inputs a first preset potential to the first end of the detection circuit 22.
  • the first preset potential is set according to specific conditions, which is not limited in this application.
  • the first end of the detection circuit 22 can also be connected to other circuits or metal wiring, as long as the first end of the detection circuit 22 can be connected to the first preset potential, this application does not limit this. .
  • the second end of the detection circuit 22 is connected to the gate point 251, and the third end of the detection circuit 22 is connected to the dummy detection line 231.
  • the dummy detection line 231 inputs a second preset potential to the third terminal of the detection circuit 22 when the display panel 20 is working, and the second preset potential is set according to specific conditions, such as 1V, which is not limited in this application.
  • the dummy detection line 231 stops inputting the second preset potential
  • the third terminal and the second terminal of the detection circuit 22 are turned on, and the display panel 20 is used to detect the potential on the dummy detection line 231 to obtain a gate.
  • the potential of the pole 251 compensates the potential of the gate 251.
  • the driving circuit 26 is connected to the dummy data line 232 and the dummy detection line 231 respectively.
  • the driving circuit 26 inputs the first preset potential to the first terminal of the detection circuit 22 through the dummy data line 232.
  • the driving circuit 26 inputs the second preset potential to the third terminal of the detection circuit 22 through the dummy detection line 231, and the third terminal and the second terminal of the detection circuit 22 are disconnected.
  • the third terminal and the second terminal of the detection circuit 22 are disconnected by inputting the second preset potential, which can prevent the potential of the gate point 251 from being pulled down by the dummy detection line 231, which affects the normal operation of the display panel 20 jobs.
  • the driving circuit 26 stops inputting the second preset potential to the third terminal of the detection circuit 22.
  • the display panel 20 is used for detecting the potential on the dummy detection line 231 through the driving circuit 26 to obtain the potential of the gate point 251 and to compensate the potential of the gate point 251.
  • the driving circuit 26 obtains the potential of the gate point 251 through its internal analog-to-digital converter.
  • the potential of the dummy detection line 231 is the same as the potential of the gate point 251, and the potential of the gate point 251 can be obtained by detecting the potential of the dummy detection line 231
  • the electric potential can improve the convenience of detecting the electric potential of the gate point 251.
  • the detection circuit 22 is an N-type transistor.
  • the first terminal of the detection circuit 22 is the gate of the N-type transistor
  • the third terminal of the detection circuit 22 is the source of the N-type transistor
  • the second terminal of the detection circuit 22 is the drain of the N-type transistor.
  • the second preset voltage is 1V.
  • the driving circuit 26 uniformly inputs a voltage of 1V to the dummy detection line 231 and inputs a first preset voltage to the dummy data line 232.
  • the dummy detection line 231 inputs a high potential to the source of the N-type transistor
  • the dummy data line 232 inputs a low potential to the gate of the N-type transistor
  • the N-type transistor is turned off, which does not affect the normal operation of the gate point 251.
  • the driving circuit 26 does not input the 1V voltage to the dummy detection line 231, but still inputs the first preset voltage to the dummy data line 232.
  • the dummy detection line 231 inputs a low potential to the source of the N-type transistor, the dummy data line 232 inputs a high potential to the gate of the N-type transistor, the N-type transistor is turned on, and the potential of the dummy detection line 231 is detected by The potential of the gate point 251 can be obtained.
  • this application provides a display panel, the display panel includes a detection circuit, the detection circuit is used to detect the potential of the grid point in the display panel, the first end of the detection circuit is connected to the first preset potential, and the detection circuit The second end is connected to the gate point, and the third end of the detection circuit is connected to the dummy detection line, wherein the dummy detection line inputs the second preset potential to the third end of the detection circuit when the display panel is working; when the display panel is closed, The dummy detection line stops inputting the second preset potential, the third terminal and the second terminal of the detection circuit are turned on, and the display panel is used to obtain the potential of the gate point by detecting the potential on the dummy detection line to compensate the potential of the gate point .
  • This application uses the dummy detection line of the detection circuit to detect the potential of the gate point.
  • the potential of the gate point can be detected more conveniently, and then the potential of the gate point can be reasonably compensated, so as to maintain the maintenance ability of the pull-down sustain circuit and avoid influence
  • the output signal of the display panel on the other hand, the dummy detection line in the display panel is reasonably used, which improves the utilization rate of the dummy detection line and reduces the energy consumption of the display panel.
  • This application also provides a display device, which includes smart devices with display functions such as smart phones, desktop computers, notebook computers, smart watches, and tablet computers.
  • the display device includes the above-mentioned display panel 20.
  • FIG. 5 is a schematic flowchart of an embodiment of a method for compensating the potential of a gate point provided by an embodiment of the present application.
  • the method for compensating the potential of the gate point is applied to the above-mentioned display panel 20, and the structure of the display panel 20 will not be described here.
  • the method for compensating the potential of the gate point 251 specifically includes the following process:
  • the current potential of the gate point 251 is obtained through the dummy detection line 231.
  • the driving circuit 26 detects the current potential of the dummy detection line 231 through the analog-to-digital converter, and uses the current potential of the dummy detection line 231 as the current potential of the gate point 251.
  • the current potential of the acquisition gate point 251 is 10V.
  • S52 Determine the compensation potential value according to the current potential of the gate point and the preset potential of the gate point.
  • the preset potential of the gate point 251 is the potential of the gate point 251 when the threshold voltage of the first transistor T3 does not deviate.
  • the potential of the gate point 251 when the threshold voltage of the first transistor T3 does not deviate is 20V.
  • the compensation potential value is determined according to the current potential of the gate point 251 and the preset potential of the gate point 251. For example, if the potential of the gate point 251 is 10V and the preset potential of the gate point 251 is 20V, the compensation potential value is determined to be 10V. In other embodiments, the compensation potential value may also be determined according to other strategies, which is not limited in this application.
  • S53 Compensate the potential of the gate point according to the compensation potential value.
  • the third preset potential VGH is compensated according to the compensation potential value to compensate the potential of the gate point 251. Specifically, the third preset potential VGH is 20V, and the determined compensation value is 10V, then the third preset potential VGH is adjusted to 30V.
  • the display panel in the embodiment of the present application may also include any other necessary structures, such as a substrate, as required.
  • the buffer layer, interlayer dielectric layer (ILD), etc. are not specifically limited here.
  • each of the above units or structures can be implemented as independent entities, or can be combined arbitrarily, and implemented as the same or several entities.
  • each of the above units or structures please refer to the previous method embodiments. No longer.

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  • Physics & Mathematics (AREA)
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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本申请实施例公开了一种显示面板、显示装置及栅极点电位的补偿方法，该显示面板包括探测电路，探测电路的第一端接入第一预设电位，探测电路的第二端与栅极点连接，探测电路的第三端与虚设探测线连接；显示面板用于通过检测虚设探测线上的电位以获取栅极点的电位。本申请显示面板能够对栅极点电位进行调整。

Description

显示面板、显示装置及栅极点电位的补偿方法 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板、显示装置及栅极点电位的补偿方法。
 背景技术
目前AMOLED（Active-matrix organic light-emitting diode，有源矩阵有机发光二极体或主动矩阵有机发光二极体）显示面板的水平扫描线的驱动是由外接集成电路来实现的。外接集成电路可以控制各级行扫描线的逐级开启，而采用GOA(Gate Driver on Array，阵列基板行驱动)方法，可以将行扫描驱动电路集成在显示面板基板上。能够减少外接集成电路的数量，从而降低了显示面板的生产成本，并且能够实现显示装置的窄边框化。IGZO（indium gallium zinc oxide，铟镓锌氧化物）具有高的迁移率和良好的器件稳定性，目前广泛的应用于IGZO-GOA电路中。GOA电路中下拉维持电路的作用是维持Q点，级传信号Cout(n)及输出信号Out(n)的低电位。在GOA电路工作过程中，下拉维持电路的栅极点（QB点）的电位受反相器控制，由于反相器中TFT（Thin Film Transistor，薄膜晶体管）一直受stress作用，Vth（Threshold Voltage，阈值电压）易正偏。如果Vth正偏，会导致QB点电位降低，QB点电位降低一方面会导致下拉维持电路的电位维持能力降低，另一方面会影响输出信号的下降时间，使下降时间增加。
也即，现有技术中，栅极点电位容易降低，导致下拉维持电路的电位维持能力降低，进而影响显示面板的输出信号。
 技术问题
也即，现有技术中，栅极点电位容易降低，导致下拉维持电路的电位维持能力降低，进而影响显示面板的输出信号。
 技术解决方案
本申请实施例提供一种显示面板、显示装置及栅极点电位的补偿方法，能够较为便捷的探测栅极点（QB点）的电位，以使显示面板能够对栅极点（QB点）电位进行调整，从而保持下拉维持电路的维持能力，避免对显示面板输出信号的影响，且降低显示面板的能耗。
为解决上述问题，第一方面，本申请提供一种显示面板，所述显示面板包括探测电路，所述探测电路用于探测所述显示面板中栅极点的电位，所述探测电路的第一端接入第一预设电位，所述探测电路的第二端与所述栅极点连接，所述探测电路的第三端与虚设探测线连接，其中，所述虚设探测线在所述显示面板工作时向所述探测电路的第三端输入第二预设电位；
在所述显示面板关闭时，所述虚设探测线停止输入所述第二预设电位，所述探测电路的第三端和第二端导通，所述显示面板用于通过检测所述虚设探测线上的电位以获取所述栅极点的电位，对所述栅极点的电位进行补偿。
其中，所述显示面板包括显示区域和虚设区域，所述虚设区域位于所述显示区域的外围，所述探测电路位于所述虚设区域中。
其中，所述探测电路的第一端接入虚设数据线，所述虚设数据线与所述虚设探测线平行，所述虚设数据线向所述探测电路的第一端输入所述第一预设电位。
其中，所述显示面板包括驱动电路，所述驱动电路分别与所述虚设数据线和所述虚设探测线连接，所述驱动电路通过所述虚设数据线向所述探测电路的第一端输入所述第一预设电位，在所述显示面板工作时，所述驱动电路通过所述虚设探测线向所述探测电路的第三端输入所述第二预设电位，所述探测电路的第三端和第二端断开；在所述显示面板关闭时，所述驱动电路停止向所述探测电路的第三端输入所述第二预设电位，所述显示面板用于通过所述驱动电路检测所述虚设探测线上的电位以获取所述栅极点的电位，对所述栅极点的电位进行补偿。
其中，所述探测电路为一N型晶体管，所述探测电路的第一端为所述N型晶体管的栅极，所述探测电路的第三端为所述N型晶体管的源极，所述探测电路的第二端为所述N型晶体管的漏极。
其中，所述显示面板包括GOA电路，所述GOA电路位于所述显示面板的两侧，且位于所述虚设区域的外侧，所述GOA电路包括反相器，所述反相器包括第一晶体管和第二晶体管，所述第一晶体管的漏极和栅极接入第三预设电位，所述第一晶体管的源极、所述第二晶体管的源极以及所述栅极点连接，所述第二晶体管的栅极与Q点连接，所述第二晶体管的漏极接入第四预设电位，其中所述第四预设电位小于所述第三预设电位。
其中，所述显示面板包括至少两个所述探测电路和至少两个所述栅极点，所述至少两个栅极点与所述至少两个探测电路的第二端一一对应连接。
为解决上述问题，第二方面，本申请提供一种显示装置，包括显示面板，所述显示面板包括探测电路，所述探测电路用于探测所述显示面板中栅极点的电位，所述探测电路的第一端接入第一预设电位，所述探测电路的第二端与所述栅极点连接，所述探测电路的第三端与虚设探测线连接，其中，所述虚设探测线在所述显示面板工作时向所述探测电路的第三端输入第二预设电位；
在所述显示面板关闭时，所述虚设探测线停止输入所述第二预设电位，所述探测电路的第三端和第二端导通，所述显示面板用于通过检测所述虚设探测线上的电位以获取所述栅极点的电位，对所述栅极点的电位进行补偿。
其中，所述显示面板包括显示区域和虚设区域，所述虚设区域位于所述显示区域的外围，所述探测电路位于所述虚设区域中。
其中，所述探测电路的第一端接入虚设数据线，所述虚设数据线与所述虚设探测线平行，所述虚设数据线向所述探测电路的第一端输入所述第一预设电位。
其中，所述显示面板包括驱动电路，所述驱动电路分别与所述虚设数据线和所述虚设探测线连接，所述驱动电路通过所述虚设数据线向所述探测电路的第一端输入所述第一预设电位，在所述显示面板工作时，所述驱动电路通过所述虚设探测线向所述探测电路的第三端输入所述第二预设电位，所述探测电路的第三端和第二端断开；在所述显示面板关闭时，所述驱动电路停止向所述探测电路的第三端输入所述第二预设电位，所述显示面板用于通过所述驱动电路检测所述虚设探测线上的电位以获取所述栅极点的电位，对所述栅极点的电位进行补偿。
其中，所述探测电路为一N型晶体管，所述探测电路的第一端为所述N型晶体管的栅极，所述探测电路的第三端为所述N型晶体管的源极，所述探测电路的第二端为所述N型晶体管的漏极。
其中，所述显示面板包括GOA电路，所述GOA电路位于所述显示面板的两侧，且位于所述虚设区域的外侧，所述GOA电路包括反相器，所述反相器包括第一晶体管和第二晶体管，所述第一晶体管的漏极和栅极接入第三预设电位，所述第一晶体管的源极、所述第二晶体管的源极以及所述栅极点连接，所述第二晶体管的栅极与Q点连接，所述第二晶体管的漏极接入第四预设电位，其中所述第四预设电位小于所述第三预设电位。
其中，所述显示面板包括至少两个所述探测电路和至少两个所述栅极点，所述至少两个栅极点与所述至少两个探测电路的第二端一一对应连接。
为解决上述问题，第三方面，本申请提供一种栅极点电位的补偿方法，所述补偿方法应用于显示面板，所述显示面板包括探测电路，所述探测电路用于探测所述显示面板中栅极点的电位，所述探测电路的第一端接入第一预设电位，所述探测电路的第二端与所述栅极点连接，所述探测电路的第三端与虚设探测线连接，其中，所述虚设探测线在所述显示面板工作时向所述探测电路的第三端输入第二预设电位；在所述显示面板关闭时，所述虚设探测线停止输入所述第二预设电位，所述探测电路的第三端和第二端导通，所述显示面板用于通过检测所述虚设探测线上的电位以获取所述栅极点的电位，对所述栅极点的电位进行补偿，所述补偿方法包括：
获取所述栅极点的电位；
根据所述栅极点的当前电位与所述栅极点的预设电位的差值确定补偿电位值；
根据所述补偿电位值对所述栅极点的电位进行补偿。
其中，所述显示面板包括第一晶体管，所述第一晶体管的漏极和栅极接入第三预设电位，所述第一晶体管的源极和所述栅极点连接；
所述根据所述补偿电位值对所述栅极点的电位进行补偿，包括:
根据所述补偿电位值对所述第三预设电位进行补偿，以对所述栅极点的电位进行补偿。
其中，所述显示面板包括第一晶体管，所述第一晶体管的漏极和栅极接入第三预设电位，所述第一晶体管的源极和所述栅极点连接；
所述根据所述补偿电位值对所述栅极点的电位进行补偿，包括:
根据所述补偿电位值对所述第三预设电位进行补偿，以对所述栅极点的电位进行补偿。
其中，所述显示面板包括显示区域和虚设区域，所述虚设区域位于所述显示区域的外围，所述探测电路位于所述虚设区域中。
其中，所述探测电路的第一端接入虚设数据线，所述虚设数据线与所述虚设探测线平行，所述虚设数据线向所述探测电路的第一端输入所述第一预设电位。
其中，所述显示面板包括驱动电路，所述驱动电路分别与所述虚设数据线和所述虚设探测线连接，所述驱动电路通过所述虚设数据线向所述探测电路的第一端输入所述第一预设电位，在所述显示面板工作时，所述驱动电路通过所述虚设探测线向所述探测电路的第三端输入所述第二预设电位，所述探测电路的第三端和第二端断开；在所述显示面板关闭时，所述驱动电路停止向所述探测电路的第三端输入所述第二预设电位，所述显示面板用于通过所述驱动电路检测所述虚设探测线上的电位以获取所述栅极点的电位，对所述栅极点的电位进行补偿。
其中，所述探测电路为一N型晶体管，所述探测电路的第一端为所述N型晶体管的栅极，所述探测电路的第三端为所述N型晶体管的源极，所述探测电路的第二端为所述N型晶体管的漏极。
 有益效果
有益效果：区别于现有技术，本申请提供一种显示面板，显示面板包括探测电路，探测电路用于探测显示面板中栅极点的电位，探测电路的第一端接入第一预设电位，探测电路的第二端与栅极点连接，探测电路的第三端与虚设探测线连接，其中，虚设探测线在显示面板工作时向探测电路的第三端输入第二预设电位；在显示面板关闭时，虚设探测线停止输入第二预设电位，探测电路的第三端和第二端导通，显示面板用于通过检测虚设探测线上的电位以获取栅极点的电位，对栅极点的电位进行补偿。本申请利用探测电路的虚设探测线对栅极点的电位进行探测，一方面可以较为便捷的检测栅极点的电位，进而对栅极点的电位进行合理补偿，从而保持下拉维持电路的维持能力，避免影响显示面板的输出信号；另一方面合理利用显示面板中的虚设探测线，提高了虚设探测线的利用率，减小了显示面板的能耗。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供一种显示面板的一个实施例结构示意图；
图2是本申请实施例提供一种显示面板的另一个实施例结构示意图；
图3是图2中反相器一个实施例结构示意图；
图4是图2中探测电路一个实施例结构示意图；
图5是本申请实施例提供一种栅极点电位的补偿方法的一个实施例流程示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请中，“示例性”一词用来表示“用作例子、例证或说明”。本申请中被描述为“示例性”的任何实施例不一定被解释为比其它实施例更优选或更具优势。为了使本领域任何技术人员能够实现和使用本申请，给出了以下描述。在以下描述中，为了解释的目的而列出了细节。应当明白的是，本领域普通技术人员可以认识到，在不使用这些特定细节的情况下也可以实现本申请。在其它实例中，不会对公知的结构和过程进行详细阐述，以避免不必要的细节使本申请的描述变得晦涩。因此，本申请并非旨在限于所示的实施例，而是与符合本申请所公开的原理和特征的最广范围相一致。
本申请实施例提供一种显示面板，包括探测电路，探测电路用于探测显示面板中栅极点的电位，探测电路的第一端接入第一预设电位，探测电路的第二端与栅极点连接，探测电路的第三端与虚设探测线连接，其中，虚设探测线在显示面板工作时向探测电路的第三端输入第二预设电位；在显示面板关闭时，虚设探测线停止输入第二预设电位，探测电路的第三端和第二端导通，显示面板用于通过检测虚设探测线上的电位以获取栅极点的电位，对栅极点的电位进行补偿。以下进行详细说明。
请参阅图1，图1是本申请实施例提供一种显示面板的一个实施例结构示意图。
本实施例中，显示面板10包括探测电路12，探测电路12用于探测显示面板10中栅极点13的电位，探测电路12的第一端接入第一预设电位。具体的，探测电路12与第一预设电位输入端129连接，第一预设电位输入端129向探测电路12的第一端输入第一预设电位。探测电路12的第二端与栅极点13连接，探测电路12的第三端与虚设探测线11连接，其中，虚设探测线11在显示面板10工作时向探测电路12的第三端输入第二预设电位；在显示面板10关闭时，虚设探测线11停止输入第二预设电位，探测电路12的第三端和第二端导通，显示面板10用于通过检测虚设探测线11上的电位以获取栅极点13的电位，对栅极点13的电位进行补偿。
本实施例中，显示面板10中探测电路12的数量可以为一个或多个，根据栅极点13的数量确定即可。在一个具体的实施方式中，显示面板10包括至少两个栅极点13与至少两个探测电路12，至少两个栅极点13与至少两个探测电路12的第二端一一对应连接，每个探测电路12分别用于探测与其相连接的栅极点13的电位。
为了具体的描述本申请显示面板的结构，请参阅图2，图2是本申请实施例提供一种显示面板的另一个实施例结构示意图；图3是图2中反相器一个实施例结构示意图；图4是图2中探测电路一个实施例结构示意图。
结合图2-4，本实施例中，显示面板20包括驱动电路26、GOA电路24以及探测电路22。
本实施例中，显示面板20包括显示区域21和虚设区域23，虚设区域23位于显示区域21的外围，探测电路22位于虚设区域23中。具体的，虚设区域23中设有多个虚设像素，虚设像素位于显示面板20的像素的最外侧，探测电路22与虚设像素共用同一块电路设计版图。本实施例能够实现检测栅极点251电位的同时，不占用显示面板20中虚设像素以外的其他区域。
本实施例中，显示面板20包括GOA电路24，GOA电路24位于显示面板20的两侧，且位于虚设区域23的外侧。GOA电路24包括反相器25，反相器25包括第一晶体管T3和第二晶体管T4，第一晶体管T3的漏极和栅极接入第三预设电位VGH，第一晶体管T3的源极、第二晶体管T4的源极以及栅极点251连接，第二晶体管T4的栅极与Q点连接，第二晶体管T4的漏极接入第四预设电位VGL，其中，第四预设电位VGL小于第三预设电位VGH。
本实施例中，探测电路22用于探测显示面板20中栅极点251的电位。探测电路22的第一端接入虚设数据线232，虚设数据线232与虚设探测线231平行，虚设数据线232向探测电路22的第一端输入第一预设电位。其中，第一预设电位根据具体情况设置，本申请对此不作限定。在其他实施例中，探测电路22的第一端也可以与其他电路或金属走线连接，只需探测电路22的第一端能够接入第一预设电位即可，本申请对此不作限定。
探测电路22的第二端与栅极点251连接，探测电路22的第三端与虚设探测线231连接。其中，虚设探测线231在显示面板20工作时向探测电路22的第三端输入第二预设电位，第二预设电位根据具体情况设置，例如1V，本申请对此不作限定。在显示面板20关闭时，虚设探测线231停止输入第二预设电位，探测电路22的第三端和第二端导通，显示面板20用于通过检测虚设探测线231上的电位以获取栅极点251的电位，对栅极点251的电位进行补偿。
本实施例中，驱动电路26分别与虚设数据线232和虚设探测线231连接。驱动电路26通过虚设数据线232向探测电路22的第一端输入第一预设电位。在显示面板20工作时，驱动电路26通过虚设探测线231向探测电路22的第三端输入第二预设电位，探测电路22的第三端和第二端断开。在显示面板20工作时，通过输入第二预设电位将探测电路22的第三端和第二端断开，能够避免栅极点251的电位被虚设探测线231拉低，影响显示面板20正常的工作。
在显示面板20关闭时，驱动电路26停止向探测电路22的第三端输入第二预设电位。显示面板20用于通过驱动电路26检测虚设探测线231上的电位以获取栅极点251的电位，对栅极点251的电位进行补偿。具体的，驱动电路26通过其内部的模数转换器获取栅极点251的电位。在显示面板20关闭时，探测电路22的第三端和第二端导通，虚设探测线231的电位与栅极点251的电位相同，通过检测虚设探测线231的电位即可获取栅极点251的电位，能够提高栅极点251电位检测的便捷度。
在一个具体的实施方式中，探测电路22为一N型晶体管。探测电路22的第一端为N型晶体管的栅极，探测电路22的第三端为N型晶体管的源极，探测电路22的第二端为N型晶体管的漏极。例如，第二预设电压为1V。当显示面板20工作时，驱动电路26统一向虚设探测线231输入1V电压，并向虚设数据线232输入第一预设电压。即，此时，虚设探测线231向N型晶体管的源极输入高电位，虚设数据线232向N型晶体管的栅极输入低电位，N型晶体管截止，不影响栅极点251的正常工作。当显示面板20关闭时，驱动电路26不向虚设探测线231输入1V电压，但依然向虚设数据线232输入第一预设电压。即，此时，虚设探测线231向N型晶体管的源极输入低电位，虚设数据线232向N型晶体管的栅极输入高电位，N型晶体管接通，通过检测虚设探测线231的电位即可获取栅极点251的电位。
区别于现有技术，本申请提供一种显示面板，显示面板包括探测电路，探测电路用于探测显示面板中栅极点的电位，探测电路的第一端接入第一预设电位，探测电路的第二端与栅极点连接，探测电路的第三端与虚设探测线连接，其中，虚设探测线在显示面板工作时向探测电路的第三端输入第二预设电位；在显示面板关闭时，虚设探测线停止输入第二预设电位，探测电路的第三端和第二端导通，显示面板用于通过检测虚设探测线上的电位以获取栅极点的电位，对栅极点的电位进行补偿。本申请利用探测电路的虚设探测线对栅极点的电位进行探测，一方面可以较为便捷的检测栅极点的电位，进而对栅极点的电位进行合理补偿，从而保持下拉维持电路的维持能力，避免影响显示面板的输出信号；另一方面合理利用显示面板中的虚设探测线，提高了虚设探测线的利用率，减小了显示面板的能耗。
本申请还提供一种显示装置，显示装置包括智能手机、台式电脑、笔记本电脑、智能手表以及平板电脑等具有显示功能的智能设备。该显示装置包括上述的显示面板20。
请参阅图5，图5是本申请实施例提供一种栅极点电位的补偿方法的一个实施例流程示意图。该栅极点电位的补偿方法应用于上述的显示面板20中，在此不再对显示面板20的结构进行描述。结合图2-5，该栅极点251电位的补偿方法具体包括以下流程，
S51：获取栅极点的当前电位；
本实施例中，在显示面板20关闭时，通过虚设探测线231获取栅极点251的当前电位。具体的，在关闭显示面板20时，驱动电路26通过模数转换器检测虚设探测线231的当前电位，将虚设探测线231的当前电位作为栅极点251的当前电位。例如，获取栅极点251的当前电位为10V。
S52：根据栅极点的当前电位与栅极点的预设电位确定补偿电位值。
本实施例中，栅极点251的预设电位为栅极点251在第一晶体管T3的阈值电压未发生偏离时的电位。例如，栅极点251在第一晶体管T3的阈值电压未发生偏离时的电位为20V。
在一个具体的实施例中，根据栅极点251的当前电位与栅极点251的预设电位确定补偿电位值。例如，获取栅极点251的电位为10V，栅极点251的预设电位为20V，则确定补偿电位值为10V。在其他实施方式中，也可以根据其他策略确定补偿电位值，本申请对此不作限定。
S53：根据补偿电位值对栅极点的电位进行补偿。
在一个具体的实施例中，根据补偿电位值对第三预设电位VGH进行补偿，以对栅极点251的电位进行补偿。具体的，第三预设电位VGH为20V，确定的补偿值为10V，则将第三预设电位VGH调整为30V。
需要说明的是，上述显示面板实施例中仅描述了上述结构，可以理解的是，除了上述结构之外，本申请实施例显示面板中，还可以根据需要包括任何其他的必要结构，例如基板，缓冲层，层间介质层（ILD）等，具体此处不作限定。
具体实施时，以上各个单元或结构可以作为独立的实体来实现，也可以进行任意组合，作为同一或若干个实体来实现，以上各个单元或结构的具体实施可参见前面的方法实施例，在此不再赘述。
以上对本申请实施例所提供的一种显示面板及栅极点电位的补偿方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施例进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施例及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，其中，所述显示面板包括探测电路，所述探测电路用于探测所述显示面板中栅极点的电位，所述探测电路的第一端接入第一预设电位，所述探测电路的第二端与所述栅极点连接，所述探测电路的第三端与虚设探测线连接，其中，所述虚设探测线在所述显示面板工作时向所述探测电路的第三端输入第二预设电位；
    在所述显示面板关闭时，所述虚设探测线停止输入所述第二预设电位，所述探测电路的第三端和第二端导通，所述显示面板用于通过检测所述虚设探测线上的电位以获取所述栅极点的电位，对所述栅极点的电位进行补偿。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板包括显示区域和虚设区域，所述虚设区域位于所述显示区域的外围，所述探测电路位于所述虚设区域中。
  3. 根据权利要求2所述的显示面板，其中，所述探测电路的第一端接入虚设数据线，所述虚设数据线与所述虚设探测线平行，所述虚设数据线向所述探测电路的第一端输入所述第一预设电位。
  4. 根据权利要求3所述的显示面板，其中，所述显示面板包括驱动电路，所述驱动电路分别与所述虚设数据线和所述虚设探测线连接，所述驱动电路通过所述虚设数据线向所述探测电路的第一端输入所述第一预设电位，在所述显示面板工作时，所述驱动电路通过所述虚设探测线向所述探测电路的第三端输入所述第二预设电位，所述探测电路的第三端和第二端断开；在所述显示面板关闭时，所述驱动电路停止向所述探测电路的第三端输入所述第二预设电位，所述显示面板用于通过所述驱动电路检测所述虚设探测线上的电位以获取所述栅极点的电位，对所述栅极点的电位进行补偿。
  5. 根据权利要求2所述的显示面板，其中，所述探测电路为一N型晶体管，所述探测电路的第一端为所述N型晶体管的栅极，所述探测电路的第三端为所述N型晶体管的源极，所述探测电路的第二端为所述N型晶体管的漏极。
  6. 根据权利要求2所述的显示面板，其中，所述显示面板包括GOA电路，所述GOA电路位于所述显示面板的两侧，且位于所述虚设区域的外侧，所述GOA电路包括反相器，所述反相器包括第一晶体管和第二晶体管，所述第一晶体管的漏极和栅极接入第三预设电位，所述第一晶体管的源极、所述第二晶体管的源极以及所述栅极点连接，所述第二晶体管的栅极与Q点连接，所述第二晶体管的漏极接入第四预设电位，其中所述第四预设电位小于所述第三预设电位。
  7. 根据权利要求6所述的显示面板，其中，所述显示面板包括至少两个所述探测电路和至少两个所述栅极点，所述至少两个栅极点与所述至少两个探测电路的第二端一一对应连接。
  8. 一种显示装置，其中，所述显示装置包括显示面板，所述显示面板包括探测电路，所述探测电路用于探测所述显示面板中栅极点的电位，所述探测电路的第一端接入第一预设电位，所述探测电路的第二端与所述栅极点连接，所述探测电路的第三端与虚设探测线连接，其中，所述虚设探测线在所述显示面板工作时向所述探测电路的第三端输入第二预设电位；
    在所述显示面板关闭时，所述虚设探测线停止输入所述第二预设电位，所述探测电路的第三端和第二端导通，所述显示面板用于通过检测所述虚设探测线上的电位以获取所述栅极点的电位，对所述栅极点的电位进行补偿。
  9. 根据权利要求8所述的显示装置，其中，所述显示面板包括显示区域和虚设区域，所述虚设区域位于所述显示区域的外围，所述探测电路位于所述虚设区域中。
  10. 根据权利要求9所述的显示装置，其中，所述探测电路的第一端接入虚设数据线，所述虚设数据线与所述虚设探测线平行，所述虚设数据线向所述探测电路的第一端输入所述第一预设电位。
  11. 根据权利要求10所述的显示装置，其中，所述显示面板包括驱动电路，所述驱动电路分别与所述虚设数据线和所述虚设探测线连接，所述驱动电路通过所述虚设数据线向所述探测电路的第一端输入所述第一预设电位，在所述显示面板工作时，所述驱动电路通过所述虚设探测线向所述探测电路的第三端输入所述第二预设电位，所述探测电路的第三端和第二端断开；在所述显示面板关闭时，所述驱动电路停止向所述探测电路的第三端输入所述第二预设电位，所述显示面板用于通过所述驱动电路检测所述虚设探测线上的电位以获取所述栅极点的电位，对所述栅极点的电位进行补偿。
  12. 根据权利要求9所述的显示装置，其中，所述探测电路为一N型晶体管，所述探测电路的第一端为所述N型晶体管的栅极，所述探测电路的第三端为所述N型晶体管的源极，所述探测电路的第二端为所述N型晶体管的漏极。
  13. 根据权利要求9所述的显示装置，其中，所述显示面板包括GOA电路，所述GOA电路位于所述显示面板的两侧，且位于所述虚设区域的外侧，所述GOA电路包括反相器，所述反相器包括第一晶体管和第二晶体管，所述第一晶体管的漏极和栅极接入第三预设电位，所述第一晶体管的源极、所述第二晶体管的源极以及所述栅极点连接，所述第二晶体管的栅极与Q点连接，所述第二晶体管的漏极接入第四预设电位，其中所述第四预设电位小于所述第三预设电位。
  14. 根据权利要求13所述的显示装置，其中，所述显示面板包括至少两个所述探测电路和至少两个所述栅极点，所述至少两个栅极点与所述至少两个探测电路的第二端一一对应连接。
  15. 一种栅极点电位的补偿方法，其中，所述补偿方法应用于显示面板，所述显示面板包括探测电路，所述探测电路用于探测所述显示面板中栅极点的电位，所述探测电路的第一端接入第一预设电位，所述探测电路的第二端与所述栅极点连接，所述探测电路的第三端与虚设探测线连接，其中，所述虚设探测线在所述显示面板工作时向所述探测电路的第三端输入第二预设电位；在所述显示面板关闭时，所述虚设探测线停止输入所述第二预设电位，所述探测电路的第三端和第二端导通，所述显示面板用于通过检测所述虚设探测线上的电位以获取所述栅极点的电位，对所述栅极点的电位进行补偿，所述补偿方法包括：
    获取所述栅极点的当前电位；
    根据所述栅极点的当前电位与所述栅极点的预设电位的差值确定补偿电位值；
    根据所述补偿电位值对所述栅极点的电位进行补偿。
  16. 根据权利要求15所述的补偿方法，其中，所述显示面板包括第一晶体管，所述第一晶体管的漏极和栅极接入第三预设电位，所述第一晶体管的源极和所述栅极点连接；
    所述根据所述补偿电位值对所述栅极点的电位进行补偿，包括:
    根据所述补偿电位值对所述第三预设电位进行补偿，以对所述栅极点的电位进行补偿。
  17. 根据权利要求15所述的补偿方法，其中，所述显示面板包括显示区域和虚设区域，所述虚设区域位于所述显示区域的外围，所述探测电路位于所述虚设区域中。
  18. 根据权利要求17所述的补偿方法，其中，所述探测电路的第一端接入虚设数据线，所述虚设数据线与所述虚设探测线平行，所述虚设数据线向所述探测电路的第一端输入所述第一预设电位。
  19. 根据权利要求18所述的补偿方法，其中，所述显示面板包括驱动电路，所述驱动电路分别与所述虚设数据线和所述虚设探测线连接，所述驱动电路通过所述虚设数据线向所述探测电路的第一端输入所述第一预设电位，在所述显示面板工作时，所述驱动电路通过所述虚设探测线向所述探测电路的第三端输入所述第二预设电位，所述探测电路的第三端和第二端断开；在所述显示面板关闭时，所述驱动电路停止向所述探测电路的第三端输入所述第二预设电位，所述显示面板用于通过所述驱动电路检测所述虚设探测线上的电位以获取所述栅极点的电位，对所述栅极点的电位进行补偿。
  20. 根据权利要求17所述的补偿方法，其中，所述探测电路为一N型晶体管，所述探测电路的第一端为所述N型晶体管的栅极，所述探测电路的第三端为所述N型晶体管的源极，所述探测电路的第二端为所述N型晶体管的漏极。
PCT/CN2019/099399 2019-05-05 2019-08-06 显示面板、显示装置及栅极点电位的补偿方法 WO2020224073A1 (zh)

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