WO2020220870A1 - 一种超低开关功耗、超低输出端电磁干扰的逆变驱动系统 - Google Patents

一种超低开关功耗、超低输出端电磁干扰的逆变驱动系统 Download PDF

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Publication number
WO2020220870A1
WO2020220870A1 PCT/CN2020/081180 CN2020081180W WO2020220870A1 WO 2020220870 A1 WO2020220870 A1 WO 2020220870A1 CN 2020081180 W CN2020081180 W CN 2020081180W WO 2020220870 A1 WO2020220870 A1 WO 2020220870A1
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Prior art keywords
switching
output
current
power
low
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PCT/CN2020/081180
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English (en)
French (fr)
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周衍
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周衍
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to the technical field of frequency converters, in particular to an inverter drive system with ultra-low switching power consumption and ultra-low output end electromagnetic interference.
  • the inverter since the inverter modulates the output through high-frequency switching, the switching process produces extremely high du/dt at the output, which will generate a large common mode through the parasitic capacitance of the cable and the motor winding to the ground. interference. Therefore, it is necessary to use a sine filter or a shielded power cable in a long-distance and sensitive application environment to electromagnetic interference.
  • the filter size when a lower switching frequency is used, the filter size will be greatly increased, and when a higher switching frequency is used, the switching loss generated by the power switching device will also increase at the same time. At the same time, it not only increases the weight and cost of the system, but also causes problems such as additional reactive power and grounding resistance of the wire shielding layer.
  • the invention uses the combination of the power switch device and the inductor capacitor output circuit to make the power switch circuit work in a state similar to the boundary transmission mode BCM (Boundary Reduction Mode), while maintaining the low-frequency sinusoidal voltage and current output at the output end, the inductor
  • BCM Boundary Reduction Mode
  • the current increases from the reverse switching current to the peak current and then decreases to the reverse switching current in each high-frequency switching cycle. In principle, it provides the output of a sinusoidal voltage circuit with low and higher harmonic components.
  • the zero voltage of the power switching device can be achieved through this current Switching (Zero Voltage Switching, abbreviated ZVS), so as to achieve extremely low switching loss, thereby reducing the heating of power switching devices during high-frequency switching.
  • ZVS Zero Voltage Switching
  • the purpose of the present invention is to provide an inverter drive system with ultra-low switching power consumption and ultra-low electromagnetic interference at the output end.
  • the present invention provides an inverter drive system with ultra-low switching power consumption and ultra-low output end electromagnetic interference, including a three-phase drive system, each phase of the inverter drive system is an independent system, and the output of each phase of the inverter drive system is The AC waveform to be output, each phase inverter drive system includes the following parts: feedback control unit, comparison control unit and power switch circuit;
  • Each feedback control unit calculates the required output setting for the phase through input signals: external input signal u sin (t), output terminal voltage signal u out (t), output terminal current signal i out (t) Current i set (t), and output the output setting current i set (t) required by the phase to the comparison control unit of the inverter drive system of the phase;
  • the input signal of each comparison control unit includes the output set current i set (t) output by the feedback control unit of the inverter drive system and the inductor current i L (t) measured in real time;
  • the output setting current i set (t) and the structural characteristics of the power switch circuit calculate the inductance peak current I peak (t) and the intermediate comparison current I comp (t) required for switching state switching, and set one for zero voltage switching.
  • the switching current I const is compared with the real-time measured inductor current i L (t), the corresponding switching state of the switching device in the power switching circuit is determined through logic calculation, and the switching state signal is output to the inverter drive system of this phase
  • the power switch circuit ;
  • the input signal is the switching state signal output by the comparison control unit of the inverter drive system;
  • the output signal is the output terminal voltage signal u out (t), the output terminal current signal i out (t ) And the inductor current real-time measurement signal i L (t);
  • the inductor current real-time measurement signal i L (t) is fed back to the comparison control unit of the phase inverter drive system, and the output terminal voltage signal u out (t) and The output current signal i out (t) is fed back to the feedback control unit of the phase inverter drive system.
  • the power switch circuit is a half-bridge power switch circuit or a full-bridge power switch circuit.
  • the power switch circuit is a half-bridge power switch circuit
  • each of the half-bridge power switch circuits includes a high-side switch device SW1, a low-side switch device SW2, and a high-side switch device SW1, a low-side switch device.
  • the high-side switching device SW1 and the low-side switching device SW2 are connected in series between the positive and negative ends of the DC power input terminal to form a half-bridge switching circuit.
  • the inductor L1 is connected to the output terminal of the half-bridge switching circuit and the output capacitor C3 and Between C4, the output capacitors C3 and C4 are connected in series between the positive and negative terminals of the DC power input terminal;
  • Both the high-side switching device SW1 and the low-side switching device SW2 are controlled by a zero voltage switching (ZVS) gate driver.
  • ZVS zero voltage switching
  • the input signal of each comparison control unit further includes an output terminal voltage signal u out (t);
  • Each half-bridge power switch circuit also includes a number of intermediate DC power supply input terminals, the intermediate DC power supply input terminal is connected to a number of intermediate DC power supplies; the input voltage of the intermediate DC power supply input terminal is located between +U in and -U in In between, each half-bridge power switch circuit also includes several bidirectional cut-off switching devices SWM and corresponding auxiliary switching capacitors CM. Each intermediate DC power input terminal passes through a bidirectional cut-off switching device SWM and a high-side switching device SW1.
  • the low-side switching device SW2 is connected to one end of the inductive coil L1, and each bidirectional cut-off switching device SWM is connected in parallel with an auxiliary switching capacitor CM; the bidirectional cut-off switching device SWM is controlled by a zero voltage switching (ZVS) gate driver.
  • ZVS zero voltage switching
  • the power switch circuit is a full-bridge power switch circuit
  • each of the full-bridge power switch circuits includes switching devices SW1, SW2, SW3, SW4, SW5, and the switching devices SW1, SW2, SW3,
  • the switching devices SW1 and SW2 are connected in series between the positive and negative terminals of the DC power input terminal, and the switching device SW3 , SW4 are connected in series between the positive and negative ends of the DC power input to form the left and right half bridges in the full-bridge switching circuit;
  • the positive and negative terminals +U in and -U in of the DC power input of the full-bridge power switch circuit are respectively Connected to the positive and negative poles of the DC power supply,
  • the inductor L1 is connected between the output ends of the half-bridge on both sides of the full-bridge switching circuit;
  • the switching device SW5 at the output end is connected to the output
  • the switching devices SW1, SW2, SW3, SW4, SW5 are all controlled by a zero voltage switching (ZVS) gate driver.
  • ZVS zero voltage switching
  • the switching device SW5 when the full-bridge power switch circuit does not need to support boost output, the switching device SW5 is a bidirectional cut-off type power switch device, and the switching devices SW1, SW2, SW3, and SW4 are all unidirectional cut-off type Power switching device; when the full-bridge power switch circuit supports boost output, the switching devices SW3, SW4, and SW5 are all bidirectional cut-off power switching devices, and the switching devices SW1 and SW2 are all unidirectional cut-off power switching devices .
  • the input signal of each comparison control unit further includes an output terminal voltage signal u out (t);
  • Each of the full-bridge power switch circuits also includes a number of intermediate DC power input terminals, which are connected to a number of intermediate DC power sources; the input voltage of the intermediate DC power input terminal is located between +U in and -U in
  • Each of the full-bridge power switch circuits also includes several bidirectional cut-off switching devices SWM and corresponding auxiliary switching capacitors CM.
  • Each intermediate DC power input terminal passes through a bidirectional cut-off switching device SWM and switching devices SW1, SW2. It is connected to one end of the inductance coil L1, and each two-way cut-off switching device SWM is connected in parallel with an auxiliary switching capacitor CM; the two-way cut-off switching device SWM is controlled by a zero voltage switching (ZVS) gate driver.
  • ZVS zero voltage switching
  • the power input terminal of each power switch circuit is: the positive and negative terminals (+U in and -U in ) of the DC power input terminal, and the output terminal voltage u out ( t), that is, the output terminal voltage u out (t) of each phase inverter drive system is;
  • the reference potential of U A is the midpoint potential of the DC power input voltage, that is, half of the input DC power voltage.
  • each feedback control unit establishes a feedback control network through an external input signal u sin (t), an output terminal voltage signal u out (t), and an output terminal current signal i out (t), thereby calculating The required output setting current i set (t) for this phase, namely:
  • i set (t) G(u sin (t), u out (t), i out (t))
  • the output voltage and current can be expressed as:
  • C out is the capacity of the output capacitor.
  • the feedback control unit includes a PID controller; its specific workflow for establishing a feedback control network is:
  • the voltage difference signal is obtained by comparing the external input signal u sin (t) with the output voltage signal u out (t) and input to the PID controller;
  • the power switching devices (SW1 and SW2, or SW1, SW2, SW3, SW4, and SW5) are connected to the output terminal through an inductor L and an output capacitor C out , and their function is similar to a low-pass filter by filtering out high frequency Switch components to obtain the required low-frequency output voltage; make the output end only have very low high-frequency components, realize ultra-low output end electromagnetic interference; reduce the shielding requirements for connecting cables and motors.
  • the inductor current i L (t) has no direct relationship with the output current i out (t) in each switching cycle; in principle, the voltage on the output capacitor C out During the switching period, the inductor is provided with energy for realizing the reverse inductor current, thereby achieving zero voltage switching (ZVS) through the auxiliary switching capacitor connected in parallel to the power switching device. In this way, the characteristics of ultra-low switching loss and ultra-low output end high frequency electromagnetic interference of the power switching device are realized.
  • FIGS 1a-1b are block diagrams of the circuit principle of the present invention.
  • FIG. 2 is a circuit schematic diagram of the feedback control unit in the present invention.
  • Fig. 3 is a circuit schematic diagram of the half-bridge power switch circuit in the first embodiment
  • 4a-4b are the inductor current and the switch state and the switch terminal voltage in the first embodiment
  • Fig. 5 is a circuit schematic diagram of a full-bridge power switch circuit in the second embodiment
  • Figures 6a-6b show the inductor current and the switching state in the case of no need to support boost output in the second embodiment
  • FIG. 7 is the output voltage curve of each phase of the inverter drive system output terminal in the case of supporting boost output in the second embodiment
  • Figure 8 is the inductor current curve in the second embodiment
  • 9a-9d are the inductor current and the switching state in the case of supporting boost output in the second embodiment.
  • FIG. 10 is a circuit schematic diagram of a half-bridge power switch circuit in the third embodiment
  • Figures 11a-11d show the inductor current and the switching state in the third embodiment
  • FIG. 12 is a circuit schematic diagram of a half-bridge power switch circuit in the fourth embodiment.
  • Figures 13a-13d show the inductor current and the switching state in the fourth embodiment
  • FIG. 14 is a schematic circuit diagram of a full-bridge power switch circuit in the fifth embodiment.
  • 15a-15d are the inductor current and the switching state in the case where there is no need to support boost output in the fifth embodiment
  • 16 is a circuit diagram of the full-bridge power switch circuit in the sixth embodiment.
  • Figures 17a-17b show the inductor current and the switching state in the sixth embodiment when there is no need to support boost output
  • 18a and 18b are schematic diagrams of a unidirectional cut-off switching device and a bidirectional cut-off switching device, respectively.
  • the present invention provides an inverter drive system with ultra-low switching power consumption and ultra-low output end electromagnetic interference, including a multi-phase inverter drive system, such as a three-phase inverter drive system; each phase inverter The drive system is an independent system.
  • the output of each phase of the inverter drive system is the desired output AC waveform, such as sinusoidal AC, and the output is connected to an external load, such as a motor;
  • each phase of the inverter drive system includes the following parts :Feedback control unit, comparison control unit and power switch circuit;
  • Each feedback control unit is calculated by input signals: external input signal (can be a sinusoidal voltage signal) u sin (t), output terminal voltage signal u out (t) and output terminal current signal i out (t)
  • the output setting current i set (t) required by the phase is output, and the output setting current i set (t) required by the phase is output to the comparison control unit of the inverter drive system of the phase;
  • the input signal of each comparison control unit includes the output set current i set (t) output by the feedback control unit of the inverter drive system and the inductor current i L (t) measured in real time;
  • the output setting current i set (t) and the structural characteristics of the power switch circuit calculate the inductor peak current I peak (t) and the intermediate comparison current I comp (t) required for switching state switching, and set one for zero voltage
  • the switching current I const of the switch, the direction of the switching current is opposite to the inductor peak current direction, and it is compared with the inductor current i L (t) measured in real time.
  • the switching state of the power switching device is determined by logic calculation, and the The switch state signal is output to the power switch circuit of the inverter drive system of the phase;
  • the input signal is the switching state signal output by the comparison control unit of the inverter drive system;
  • the output signal is the output terminal voltage signal u out (t), the output terminal current signal i out (t ) And the inductor current real-time measurement signal i L (t).
  • the inductor current measurement circuit in the power switch circuit will feed back the inductor current i L (t) measured in real time to the comparison control unit of the phase inverter drive system, and the output terminal voltage and current measurement circuit in the power switch circuit will be measured
  • the output terminal voltage u out (t) and the output terminal current i out (t) are fed back to the feedback control unit of the phase inverter drive system.
  • the power input terminal of the power switch circuit is: the positive and negative terminals (+U in , -U in ) of the input terminal of the DC power supply, and the power output terminal of each power switch circuit is a sinusoidal voltage output, that is, every Phase inverter drive system output terminal voltage u out (t). which is:
  • ⁇ is the angular velocity
  • t is the actual time
  • the reference potential of U A is the midpoint potential of the DC power input voltage, that is, half of the input DC power voltage; for example, each phase drive system in a full bridge circuit that supports boost output
  • the output voltage curve of the output terminal is the time change of the output voltage and the DC input voltage at the output terminal of each phase drive system.
  • the output terminal voltage signal u out (t) input by the feedback control unit is a digital quantization process on a sensor acquisition of the output terminal voltage u out (t) output to the load.
  • the power switching circuit includes switching devices, auxiliary switching capacitors, inductance coils and output capacitors.
  • the capacity of the auxiliary switching capacitors is much smaller than that of the output capacitors; wherein the gate drive module of the switching devices obtains the switching state signals and switches The real-time voltage across the device realizes zero voltage switching (ZVS) of the switching device.
  • ZVS zero voltage switching
  • the feedback control unit has a built-in feedback control system, which is established by an external sinusoidal voltage input signal u sin (t), output terminal voltage signal u out (t), and output terminal current signal i out (t).
  • Feedback control network to calculate the required output set current i set (t) of the phase, namely:
  • i set (t) G(u sin (t), u out (t), i out (t))
  • the output voltage and current can be expressed as:
  • C out is the capacity of the output capacitor
  • the feedback control system includes a PID controller; its specific workflow is:
  • the voltage difference signal is obtained by comparing the sinusoidal voltage input signal u sin (t) with the output voltage signal u out (t) and input to the PID controller;
  • the feedback control unit structure is a basic structure, and its PID controller is a standard feedback controller, and its parameters are matched and set according to the parameters of the specific circuit design; with the development of control system technology, advanced control systems and automatic control systems Adapt to the application of the control system, this feedback control unit can be upgraded and optimized accordingly. But its function in the whole system is still the same as the function of the feedback control unit mentioned above in the whole system, namely:
  • the power switch circuit is divided into a half-bridge power switch circuit (half-bridge circuit for short) and a full-bridge power switch circuit (full-bridge circuit for short).
  • Figure 8 shows the inductor current i L (t) curve obtained by real-time measurement in a full-bridge power switch circuit.
  • the power switch circuit is a half-bridge power switch circuit.
  • Each half-bridge power switch circuit includes a high-side switching device SW1, a low-side switching device SW2, and a high-side switching device SW1.
  • the inductor L1 is connected between the output of the half-bridge switching circuit and the output capacitors C3 and C4.
  • the output capacitors C3 and C4 are connected in series to the positive of the DC power input.
  • both the high-side switching device SW1 and the low-side switching device SW2 are controlled by a zero voltage switching (ZVS) gate driver.
  • ZVS zero voltage switching
  • Each of the comparison control units has a built-in comparator and a logic calculation unit, and sets a switching current I const for zero voltage switching; the output of the feedback control unit sets the current i set (t) and the power switch circuit
  • the structural characteristics calculate the inductor peak current I peak (t), the intermediate comparison current I comp (t) and the switching current I const required for switching state switching, and compare them with the inductor current i L (t) measured in real time. Determine the corresponding switch state to the power switch circuit according to the structure of the half-bridge power switch circuit;
  • Table 3 The working sequence and zero voltage switching (ZVS) process of the half-bridge circuit in the first embodiment in one switching cycle
  • the power switch circuit is a full-bridge power switch circuit.
  • Each of the full-bridge power switch circuits includes switching devices SW1, SW2, SW3, SW4, SW5, and switching devices SW1, SW2 respectively.
  • SW3, SW4, SW5 are connected in parallel with auxiliary switching capacitors C1, C2, C3, C4, C5, inductor L1, and output capacitors C6, C7;
  • switching devices SW1, SW2 are connected in series between the positive and negative terminals of the DC power input, and
  • the switching devices SW3 and SW4 are connected in series between the positive and negative ends of the DC power input to form the left and right half bridges in the full-bridge switching circuit respectively;
  • the DC power input of the full-bridge power switching circuit is connected to the DC power supply, and the inductor coil L1 Connected between the output terminals of the half-bridge on both sides of the full-bridge switching circuit;
  • the switching device SW5 at the output terminal is connected between the output capacitors C6 and C7 and the output terminal of the right half-bridge in the full-bridge switching circuit;
  • the second embodiment is further divided into two sub-embodiments: when the full-bridge power switch circuit does not need to support boost output, the switching device SW5 is a bidirectional cut-off switching device, and the switching devices SW1, SW2, SW3, and SW4 are all It is a unidirectional cut-off switching device; for example, the switching devices SW1, SW2, SW3, and SW4 are MOSFETs or IGBTs with freewheeling diodes, and the switching devices SW5 are two MOSFETs or IGBTs connected in series in opposite directions, respectively, with freewheeling diodes. MOSFET or IGBT are connected in parallel with an auxiliary switching capacitor.
  • the structures of the unidirectional cut-off switch device and the bidirectional cut-off switch device described in the present invention are shown in Figs. 18a and 18b, respectively.
  • the switching devices SW3, SW4, and SW5 are all bidirectional cut-off power switching devices, and the switching devices SW1 and SW2 are both unidirectional cut-off power switching devices; for example, switches
  • the devices SW1 and SW2 are MOSFETs or IGBTs with freewheeling diodes, and the switching devices SW3, SW4 and SW5 are two MOSFETs or IGBTs connected in series in opposite directions respectively with freewheeling diodes.
  • Each MOSFET or IGBT is connected in parallel with an auxiliary switching capacitor.
  • the two-way cut-off power switching device is usually two MOSFETs or IGBTs connected in series in opposite directions with a freewheeling diode;
  • the one-way cut-off power switching device is an ordinary MOSFET or IGBT with a continuous
  • the on-resistance of the two-way cut-off power switch device is larger than that of the ordinary one-way cut-off power switch device. Therefore, if there is no boost output requirement, the one-way cut-off power switch device should be used as much as possible.
  • the switching devices SW1, SW2, SW3, SW4, SW5 are all controlled by a zero-voltage switching (ZVS) gate driver, and the combination of switches can achieve a high inductance average current during the switching cycle.
  • ZVS zero-voltage switching
  • the full-bridge power switch circuit can normally open SW3 and SW4 (off) while normally closed SW5 (on) under the working state of low output power to achieve the same working effect as the half-bridge power switch circuit.
  • the state control method is the same as the half-bridge power switch circuit.
  • Each comparison control unit has a built-in comparator, a logic calculation unit, and sets a switching current I const for zero voltage switching; the logic calculation unit sets the current i set (t) and the full bridge according to the output output by the feedback control unit
  • the structural characteristics of the power switch circuit calculate the inductance peak current I peak (t) and the intermediate comparison current I comp (t) required when the switching state is switched, and compare the real-time measured inductor current i L (t) with the comparator. To compare, determine the corresponding switch state to the power switch circuit according to the structure of the full-bridge power switch circuit, specifically:
  • the inductor current i L (t) changes from the switching current I const in the opposite direction to the output set current i set (t) in a short time Increase to the positive intermediate comparison current I comp (t), so as to achieve a higher inductor average current in the switching cycle through a lower inductor peak current I peak (t); among them, the intermediate comparison current I comp (t) Located between the switching current I const and I peak (t), the direction is the same as the direction of the inductor peak current I peak (t).
  • the power switch circuit is a half-bridge power switch circuit.
  • Fig. 1b The overall principle block diagram is shown in Fig. 1b.
  • the difference between Fig. 1b and Fig. 1a is that, for each of the comparison control units, the input signal also includes the output terminal voltage signal u out (t).
  • each half-bridge power switch circuit also includes several intermediate DC power input terminals. Terminal is connected to several intermediate DC power supplies.
  • there is one intermediate DC power supply input terminal which is represented by U inM1 ; the input voltage U inM1 at the intermediate DC power input terminal is located between +U in and -U in , each half
  • the bridge power switch circuit also includes a two-way cut-off switch device SWM1 and a corresponding auxiliary switch capacitor CM1.
  • Each intermediate DC power input terminal passes through a two-way cut-off switch device SWM1 and a high-side switch device SW1, a low-side switch device SW2 and an inductor.
  • each two-way cut-off switch device SWM1 is connected in parallel with an auxiliary switch capacitor CM1; the two-way cut-off switch device SWM1 is controlled by a zero voltage switch (ZVS) gate driver.
  • ZVS zero voltage switch
  • the power switch circuit is a half-bridge power switch circuit.
  • each half-bridge power switch circuit includes two intermediate DC power input terminals U inM1 and U inM2 , And respectively connected to two intermediate DC power supplies, the input voltages U inM1 and U inM2 are located between +U in and -U in , and U inM1 > U inM2 , each half-bridge power switch circuit includes two bidirectional cutoffs Type switching devices SWM1, SWM2 and the corresponding two auxiliary switching capacitors CM1, CM2, the two intermediate DC power input terminals are respectively connected through a bidirectional cut-off switching device and the high-side switching device SW1, the low-side switching device SW2 and the inductor L1 One end is connected, and each two-way cut-off switch device is connected in parallel with an auxiliary switch capacitor; the two-way cut-off switch devices SWM1 and SWM2 are controlled by a zero voltage switch (ZVS) gate driver.
  • ZVS zero voltage switch
  • the intermediate DC power input terminals can also be other numbers greater than 2, such as n, the circuit structure is also changed accordingly, and the number of bidirectional cut-off switching devices and auxiliary switching capacitors is also It is n; as long as it is satisfied that the input voltages of the n intermediate DC power input terminals are between +U in and -U in .
  • the intermediate DC power supply adjacent to the output terminal voltage value is selected as the intermediate DC power supply.
  • the power switch circuit The control method is the same as the power switch circuit having a single intermediate DC power input terminal in the third embodiment.
  • the switch state in a switching cycle is:
  • the above-mentioned terminal potentials are all based on the intermediate point potential of the DC power supply input terminal, and the voltages u out (t), U inM1 , U inM2 are the voltages from each terminal to the intermediate point between the positive and negative terminals of the DC power supply input terminal.
  • the voltage level relationship is -U in /2 ⁇ U inM2 ⁇ U inM1 ⁇ +U in /2.
  • the power switch circuit is a full-bridge power switch circuit.
  • each full-bridge power switch circuit also includes several intermediate DC power input terminals.
  • the DC power input terminal is connected to several intermediate DC power supplies.
  • Each full-bridge power switch circuit also includes a two-way cut-off switching device SWM1 and a corresponding auxiliary switching capacitor CM1.
  • the intermediate DC power input terminal is connected to one end of the switching devices SW1, SW2 and the inductor L1 through the two-way cut-off switching device SWM1, And the two-way cut-off switch device SWM1 is connected in parallel with the auxiliary switch capacitor CM1; the two-way cut-off switch device SWM1 is controlled by a zero voltage switch (ZVS) gate driver. Moreover, in this embodiment, the full-bridge power switch circuit does not need to support boost output.
  • the power switch circuit is a full-bridge power switch circuit.
  • each full-bridge power switch circuit includes two intermediate DC power input terminals U inM1 and U inM2 , And respectively connected to two intermediate DC power supplies, the input voltages U inM1 and U inM2 are located between +U in and -U in , and U inM1 > U inM2 , each full-bridge power switch circuit includes two bidirectional cut-off Type switching devices SWM1 and SWM2 are connected to the corresponding two auxiliary switching capacitors CM1 and CM2.
  • the two intermediate DC power input terminals are respectively connected to one end of the switching devices SW1, SW2 and the inductor L1 through a bidirectional cut-off switching device, and each The two-way cut-off switch device is connected in parallel with an auxiliary switch capacitor; the two-way cut-off switch devices SWM1 and SWM2 are controlled by a zero voltage switch (ZVS) gate driver.
  • ZVS zero voltage switch
  • the full-bridge power switch circuit does not need to support boost output.
  • the intermediate DC power input terminals can also be other numbers greater than 2, such as n, the circuit structure is also changed accordingly, and the number of bidirectional cut-off switching devices and auxiliary switching capacitors is also It is n; as long as it is satisfied that the input voltages of the n intermediate DC power input terminals are between +U in and -U in .
  • the intermediate DC power supply adjacent to the output terminal voltage value is selected as the intermediate DC power supply.
  • the power switch circuit The control method is the same as the power switch circuit with a single intermediate DC power input terminal in the fifth embodiment.
  • the switch state in a switching cycle is:
  • the above-mentioned terminal potentials are all based on the intermediate point potential of the DC power supply input terminal, and the voltages u out (t), U inM1 , U inM2 are the voltages from each terminal to the intermediate point between the positive and negative terminals of the DC power supply input terminal.
  • the voltage level relationship is -U in /2 ⁇ U inM2 ⁇ U inM1 ⁇ +U in /2.
  • the present invention regards the combination of the power switching device and the inductor as a controllable current source, and provides the required current to the output capacitor and the output load in the manner of high-frequency switching.
  • the output voltage is provided by the current supplied by the inductor and the load.
  • the integral of the difference between the outgoing currents over time is obtained on the capacitor.
  • the power switching circuit can work in the BCM (Boundary Reduction Mode) mode, which in principle achieves both low switching loss and low switching loss.
  • BCM Battery Reduction Mode
  • the characteristics of high-frequency electromagnetic interference at the output It has good compatibility for power switching devices with larger parasitic capacitances (such as Superjunction-MOSFET), and plays an auxiliary role in the wider application of faster power switching devices (such as SiC-MOSEFT and GaN-FET) in the future.
  • the intermediate DC power input and the corresponding two-way cut-off switching device and the corresponding auxiliary switching capacitor are added to the circuit.
  • the voltage across the inductor The switching of makes it possible to achieve a higher average inductor current with a lower peak inductor current, thereby reducing the conduction loss of the system.

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Abstract

一种超低开关功耗、超低输出端电磁干扰的逆变驱动系统，包括多相逆变驱动系统，每相逆变驱动系统为独立系统，且均包括以下部分：反馈控制单元、比较控制单元和功率开关电路。通过功率开关器件与电感电容输出电路的组合，使功率开关电路工作于近似于边界传导模式BCM的状态，在输出端保持低频正弦电压电流输出的同时，使电感电流在每个高频开关周期内由反向的切换电流增长到峰值电流再降低到反向的切换电流。从原理上提供低高次谐波成分的正弦电压电路输出，同时由于电感在每个开关周期的开始和结束时电感电流与电感电流的平均值相反，通过此电流可实现功率开关器件的ZVS开关，从而实现了低开关损耗和低输出端高频电磁干扰。

Description

一种超低开关功耗、超低输出端电磁干扰的逆变驱动系统 技术领域
本发明涉及变频器的技术领域，具体的说是涉及一种超低开关功耗、超低输出端电磁干扰的逆变驱动系统。
背景技术
在常规变频器驱动系统中，由于变频器通过高频开关调制输出，开关过程在输出端产生极高的du/dt，其会通过电缆线、电机绕组的对地寄生电容产生较大的共模干扰。因此在较长距离和对电磁干扰敏感的应用环境中需要使用正弦滤波器或带屏蔽层的动力电缆。在相同输出功率的情况下，当使用较低的开关频率时滤波器尺寸将大幅增大，当使用较高的开关频率时功率开关器件产生的开关损耗也将同时增大。同时不仅增加了系统重量和成本，也产生了诸如附加的无功功率和导线屏蔽层接地电阻等问题。
本发明在通过功率开关器件与电感电容输出电路的组合，使功率开关电路工作于近似于边界传到模式BCM(Boundary Conduction Mode)的状态，在输出端保持低频正弦电压电流输出的同时，使电感电流在每个高频开关周期内由反向的切换电流增长到峰值电流再降低到反向的切换电流。从原理上提供低高次谐波成分的正弦电压电路输出，同时由于电感在每个开关周期的开始和结束时电感电流与电 感电流的平均值相反，通过此电流可实现功率开关器件的零电压开关(Zero Voltage Switching，缩写ZVS)，从而实现极低开关损耗，从而降低功率开关器件在高频开关时的发热。
发明内容
为解决上述背景技术中提出的问题，本发明的目的在于提供一种超低开关功耗、超低输出端电磁干扰的逆变驱动系统。
为实现上述目的，本发明采取的技术方案为：
本发明提供了一种超低开关功耗、超低输出端电磁干扰的逆变驱动系统，包括三相驱动系统，每相逆变驱动系统为独立系统，每相逆变驱动系统的输出端为所需输出的交流波形，每相逆变驱动系统均包括以下部分：反馈控制单元、比较控制单元和功率开关电路；
每个所述反馈控制单元，通过输入信号：外部输入信号u sin(t)、输出端电压信号u out(t)、输出端电流信号i out(t)来计算出该相所需的输出设置电流i set(t)，并将该相所需输出的输出设置电流i set(t)输出到该相逆变驱动系统的比较控制单元；
每个所述比较控制单元，其输入信号包括该相逆变驱动系统的反馈控制单元输出的输出设置电流i set(t)和实时测量的电感电流i L(t)；通过由反馈控制单元输出的输出设置电流i set(t)与功率开关电路的结构特性计算出开关状态切换时所需的电感峰值电流I peak(t)和中间比较电流I comp(t)，设置一个用于零电压开关的切换电流I const，并与实时测量的电感电流i L(t)进行比较，通过逻辑计算确定出功率开关电路中开关器件相应的开关状态，并将开关状态信号输出到该相逆变驱动系统的功率开关电路；
每个所述功率开关电路，其输入信号为该相逆变驱动系统的比较控制单元输出的开关状态信号；其输出信号为输出端电压信号u out(t)、输出端电流信号i out(t)和电感电流实时测量信号i L(t)；所述电感电流实时测量信号i L(t)反馈到该相逆变驱动系统的比较控制单元，所述输出端电压信号u out(t)和输出端电流信号i out(t)反馈到该相逆变驱动系统的反馈控制单元。
在一些实施例中，根据应用需求，所述功率开关电路为半桥功率开关电路或全桥功率开关电路。
在一些实施例中，所述功率开关电路为半桥功率开关电路，每个所述半桥功率开关电路包含高边开关器件SW1、低边开关器件SW2、分别与高边开关器件SW1、低边开关器件SW2并联的辅助开关电容C1和C2、电感线圈L1以及输出电容C3和C4；每个所述半桥功率开关电路的直流电源输入端的正负端+U in和-U in分别与直流电源的正负极相连，高边开关器件SW1与低边开关器件SW2串联于直流电源输入端的正负端之间形成半桥开关电路，电感线圈L1连接于半桥开关电路输出端与输出电容C3和C4之间，输出电容C3与C4串联于直流电源输入端的正负端之间；
高边开关器件SW1和低边开关器件SW2均由零电压开关(ZVS)门极驱动器控制。
在一些实施例中，每个所述比较控制单元，其输入信号还包括输出端电压信号u out(t)；
每个所述半桥功率开关电路还包含若干个中间直流电源输入端，所述中间直流电源输入端与若干个中间直流电源相连；中间直流电源输入端的输入电压位于+U in和-U in之间，每个所述半桥功率开关电路还包含若干个双向截止型开关器件SWM与对应的辅助开关电容 CM，每个中间直流电源输入端通过一个双向截止型开关器件SWM与高边开关器件SW1、低边开关器件SW2和电感线圈L1的一端相连，且每一个双向截止型开关器件SWM与一个辅助开关电容CM并联；双向截止型开关器件SWM由零电压开关(ZVS)门极驱动器控制。
在一些实施例中，所述功率开关电路为全桥功率开关电路，每个所述全桥功率开关电路包含开关器件SW1、SW2、SW3、SW4、SW5，分别与开关器件SW1、SW2、SW3、SW4、SW5并联的辅助开关电容C1、C2、C3、C4、C5，电感线圈L1，以及输出电容C6、C7；开关器件SW1、SW2串联于直流电源输入端的正负端之间，以及开关器件SW3、SW4串联于直流电源输入端的正负端之间分别形成全桥开关电路中的左、右两侧半桥；全桥功率开关电路的直流电源输入端的正负端+U in和-U in分别与直流电源的正负极相连，电感线圈L1连接于全桥开关电路中的两侧半桥输出端之间；输出端的开关器件SW5连接于输出电容C6、C7与全桥开关电路中右侧半桥输出端之间；输出电容C6与C7串联于直流电源输入端的正负端之间；
开关器件SW1、SW2、SW3、SW4、SW5均由零电压开关(ZVS)门极驱动器控制。
在一些实施例中，当全桥功率开关电路无需支持升压输出时，所述开关器件SW5为双向截止型功率开关器件，所述开关器件SW1、SW2、SW3、和SW4均为单向截止型功率开关器件；当全桥功率开关电路支持升压输出时，所述开关器件SW3、SW4和SW5均为双向截止型功率开关器件，所述开关器件SW1和SW2均为单向截止型功率开关器件。
在一些实施例中，每个所述比较控制单元，其输入信号还包括输 出端电压信号u out(t)；
每个所述全桥功率开关电路还包含若干个中间直流电源输入端，所述中间直流电源输入端与若干个中间直流电源相连；中间直流电源输入端的输入电压位于+U in和-U in之间，每个所述全桥功率开关电路还包含若干个双向截止型开关器件SWM与对应的辅助开关电容CM，每个中间直流电源输入端通过一个双向截止型开关器件SWM与开关器件SW1、SW2和电感线圈L1的一端相连，且每一个双向截止型开关器件SWM与一个辅助开关电容CM并联；双向截止型开关器件SWM由零电压开关(ZVS)门极驱动器控制。
在一些实施例中，每个所述功率开关电路的功率输入端为：直流电源输入端的正负端(+U in和-U in)，每个所述功率开关电路的输出端电压u out(t)，即每相逆变驱动系统的输出端电压u out(t)为；
Figure PCTCN2020081180-appb-000001
其中，U A的参考电位为直流电源输入端电压的中间点电位，即输入直流电源电压的一半。
在一些实施例中，每个所述反馈控制单元通过外部输入信号u sin(t)、输出端电压信号u out(t)、输出端电流信号i out(t)建立反馈控制网络，从而计算出该相所需的输出设置电流i set(t)，即：
i set(t)＝G(u sin(t)，u out(t)，i out(t))
其中，输出电压与电流可表达为：
Figure PCTCN2020081180-appb-000002
Figure PCTCN2020081180-appb-000003
其中C out为输出电容的容量。
在一些实施例中，反馈控制单元包括PID控制器；其建立反馈控 制网络的具体工作流程为：
(1)通过对外部输入信号u sin(t)与输出电压信号u out(t)进行比较得出电压差值信号，并输入至PID控制器；
(2)通过计算外部输入信号u sin(t)对时间的导数并与输出电容容量相乘得出输出电容C out充放电电流；
(3)由(1)中PID控制器输出的电压差反馈增量电流与(2)中所得的输出电容充放电电流与当前输出端电流i out(t)相加，其结果为输出设置电流i set(t)，并输入至比较控制单元。
与现有技术相比，本发明的有益效果是：
本发明中，功率开关器件(SW1和SW2，或者SW1、SW2、SW3、SW4和SW5)通过电感L和输出电容C out与输出端相连，其作用类似于低通滤波器，通过滤除高频开关成分，得到所需的低频输出电压；使得输出端只存在非常低的高频成分，实现超低输出端电磁干扰；降低了对连接电缆与电机的屏蔽要求。
由于电感与输出端接有输出电容C out，使得在每个开关周期中电感电流i L(t)与输出电流i out(t)并无直接关系；在原理上通过输出电容C out上的电压在开关周期内向电感提供实现反向电感电流的能量，从而通过并联于功率开关器件上的辅助开关电容实现零电压开关(ZVS)。从而实现功率开关器件的超低开关损耗和超低输出端高频电磁干扰的特性。
附图说明
图1a-图1b为本发明的电路原理框图；
图2为本发明中反馈控制单元的电路原理图；
图3为第一实施例中的半桥功率开关电路的电路原理图；
图4a-图4b为第一实施例中的电感电流与开关状态和开关端电压；
图5为第二实施例中的全桥功率开关电路的电路原理图；
图6a-图6b为第二实施例中无需支持升压输出情况下的电感电流与开关状态；
图7为第二实施例中支持升压输出情况下的各相逆变驱动系统输出端的输出电压曲线；
图8为第二实施例中的电感电流曲线；
图9a-图9d为第二实施例中支持升压输出情况下的电感电流与开关状态；
图10为第三实施例中的半桥功率开关电路的电路原理图；
图11a-图11d为第三实施例中的电感电流与开关状态；
图12为第四实施例中的半桥功率开关电路的电路原理图；
图13a-图13d为第四实施例中的电感电流与开关状态；
图14为第五实施例中的全桥功率开关电路的电路原理图；
图15a-图15d为第五实施例中无需支持升压输出情况下的电感电流与开关状态；
图16为第六实施例中的全桥功率开关电路的电路原理图；
图17a-图17b为第六实施例中无需支持升压输出情况下的电感电流与开关状态；
图18a和图18b分别为单向截止型开关器件与双向截止型开关器件的示意图。
具体实施方式
为使本发明实现的技术手段、创作特征、达成目的与功效易于明 白了解，下面结合附图和具体实施方式，进一步阐述本发明是如何实施的。
如图1a所示，本发明提供了一种超低开关功耗、超低输出端电磁干扰的逆变驱动系统，包括多相逆变驱动系统，例如三相逆变驱动系统；每相逆变驱动系统为独立系统，每相逆变驱动系统的输出端为所需输出的交流波形，如正弦交流，输出端与外部负载连接，负载例如可为电机；每相逆变驱动系统均包括以下部分：反馈控制单元、比较控制单元和功率开关电路；
每个所述反馈控制单元，通过输入信号：外部输入信号(可为正弦电压信号)u sin(t)、输出端电压信号u out(t)和输出端电流信号i out(t)来计算出该相所需的输出设置电流i set(t)，并将该相所需输出的输出设置电流i set(t)输出到该相逆变驱动系统的比较控制单元；
每个所述比较控制单元，其输入信号包括该相逆变驱动系统的反馈控制单元输出的输出设置电流i set(t)和实时测量的电感电流i L(t)；通过由反馈控制单元输出的输出设置电流i set(t)与功率开关电路的结构特性计算出开关状态切换时所需的电感峰值电流I peak(t)、中间比较电流I comp(t)，并设置一个用于零电压开关的切换电流I const，此切换电流的方向与电感峰值电流方向相反，并与实时测量的电感电流i L(t)进行比较，通过逻辑计算确定出功率开关器件所应的开关状态，并将开关状态信号输出到该相逆变驱动系统的功率开关电路；
每个所述功率开关电路，其输入信号为该相逆变驱动系统的比较控制单元输出的开关状态信号；其输出信号为输出端电压信号u out(t)、输出端电流信号i out(t)和电感电流实时测量信号i L(t)。工作时，功率开关电路中电感电流测量电路将实时测量得到的电感电流i L(t)反馈到该相逆变驱动系统的比较控制单元，功率开关电路中输出端电压和 电流测量电路将由测量得到的输出端电压u out(t)和输出端电流i out(t)反馈到该相逆变驱动系统的反馈控制单元。
具体地，所述功率开关电路的功率输入端为：直流电源输入端的正负端(+U in、-U in)，每个所述功率开关电路的功率输出端为正弦电压输出，即为每相逆变驱动系统输出端电压u out(t)。即：
Figure PCTCN2020081180-appb-000004
其中，ω为角速度，t为实际时间，U A的参考电位为直流电源输入端电压的中间点电位，即输入直流电源电压的一半；例如，支持升压输出的全桥电路中各相驱动系统输出端的输出电压曲线(见图7)，为各相驱动系统输出端的输出电压与直流输入电压在时间上的变化。
本发明中，反馈控制单元输入的输出端电压信号u out(t)是对于输出给负载的输出端电压u out(t)的一个传感器采集上的数字量化处理。
本发明中，功率开关电路中包含开关器件、辅助开关电容、电感线圈和输出电容，其辅助开关电容的容量远小于输出电容的容量；其中开关器件的门极驱动模块通过获取开关状态信号和开关器件两端的实时电压实现开关器件的零电压开关(ZVS)。
如图2所示，所述反馈控制单元内建反馈控制系统，通过外部的正弦电压输入信号u sin(t)、输出端电压信号u out(t)、输出端电流信号i out(t)建立反馈控制网络，从而计算出该相所需的输出设置电流i set(t)，即：
i set(t)＝G(u sin(t)，u out(t)，i out(t))
其中，输出电压与电流可表达为：
Figure PCTCN2020081180-appb-000005
Figure PCTCN2020081180-appb-000006
其中C out为输出电容的容量；
反馈控制系统包括PID控制器；其具体工作流程为：
(1)通过对正弦电压输入信号u sin(t)与输出电压信号u out(t)进行比较得出电压差值信号，并输入至PID控制器；
(2)通过计算正弦电压输入信号u sin(t)对时间的导数并与输出电容容量相乘得出输出电容C out充放电电流；
(3)由(1)中PID控制器输出的电压差反馈增量电流与(2)中所得的输出电容充放电电流与当前输出端电流i out(t)相加，其结果为输出设置电流i set(t)，并输入至比较控制单元。
本发明中，反馈控制单元结构为一种基本结构，其PID控制器为标准反馈控制器，其参数根据具体电路设计时的参数进行匹配设置；随着控制系统技术的发展和高级控制系统及自适应控制系统的应用，此反馈控制单元可随之升级与优化。但其在整个系统中的作用依旧与上述所述反馈控制单元在整个系统中的作用相同，即：
通过输入信号——正弦电压输入信号u sin(t)、输出端电压信号u out(t)、输出端电流信号i out(t)；计算出输出信号——输出设置电流i set(t)；并将其输入至比较控制单元。从而使整个系统稳定工作，并输出与正弦电压输入信号u sin(t)对应的输出端电压信号u out(t)。
本发明中，根据应用需求，功率开关电路分为半桥功率开关电路(简称半桥电路)和全桥功率开关电路(简称全桥电路)。例如，图8为全桥功率开关电路中，实时测量得到的电感电流i L(t)曲线。以下描述本发明提供的逆变驱动系统在功率开关电路不同情况下的几个具体实施例。
第一实施例中，功率开关电路为半桥功率开关电路。
其整体的原理框图如图1a所示，功率开关电路原理如图3所示，每个所述半桥功率开关电路包含高边开关器件SW1、低边开关器件SW2、分别与高边开关器件SW1、低边开关器件SW2并联的辅助开关电容C1和C2、电感线圈L1以及输出电容C3和C4；半桥功率开关电路的直流电源输入端与直流电源相连，高边开关器件SW1与低边开关器件SW2串联于直流电源输入端的正负端之间形成半桥开关电路，电感线圈L1连接于半桥开关电路输出端与输出电容C3和C4之间，输出电容C3与C4串联于直流电源输入端的正负端之间；高边开关器件SW1和低边开关器件SW2均由零电压开关(ZVS)门极驱动器控制。
每个所述比较控制单元内建比较器、逻辑计算单元，并设置一个用于零电压开关的切换电流I const；通过由反馈控制单元输出的输出设置电流i set(t)与功率开关电路的结构特性计算出开关状态切换时所需的电感峰值电流I peak(t)、中间比较电流I comp(t)和切换电流I const，并与实时测量得到的电感电流i L(t)进行比较，根据半桥功率开关电路的结构确定对应的开关状态到功率开关电路；
以输出设置电流i set(t)为正电流(i set(t)＞0A)为例(如图4a所示)，由于辅助开关电容的容量非常小，其零电压开关(ZVS)的时间与过程中的电感电流的变化可忽略不计。整个开关过程可简化为以下两部分：
Figure PCTCN2020081180-appb-000007
Figure PCTCN2020081180-appb-000008
在第一实施例中的每个半桥功率开关电路中，电感峰值电流I peak(t)与输出设置电流i set(t)的计算关系如表1所示：
表1 电感峰值电流I peak(t)与输出设置电流i set(t)关系表
  电感峰值电流 电感反向切换电流
i set(t)＞0A I peak(t)＝2·i set(t)+I const -I const
i set(t)＝0A I peak(t)＝I const -I const
i set(t)＜0A I peak(t)＝2·i set(t)-I const I const
对应的开关状态如图4a、图4b所示，具体情况统计见表2所示：[状态0为关断，1为导通]
表2 由第一实施例中的半桥电路的结构确定对应的开关状态
Figure PCTCN2020081180-appb-000009
其在一个开关周期内的工作时序如表3所示：[状态0为关断，1为导通]
表3 第一实施例中的半桥电路一个开关周期内的工作时序与零电压开关(ZVS)过程
Figure PCTCN2020081180-appb-000010
第二实施例中，功率开关电路为全桥功率开关电路。
其整体的原理框图如图1a所示，功率开关电路原理如图5所示，每个所述全桥功率开关电路包含开关器件SW1、SW2、SW3、SW4、SW5，分别与开关器件SW1、SW2、SW3、SW4、SW5并联的辅助开关电容C1、C2、C3、C4、C5，电感线圈L1，以及输出电容C6、C7；开关器件SW1、SW2串联于直流电源输入端的正负端之间，以及开关器件SW3、SW4串联于直流电源输入端的正负端之间分别形成全桥开关电路中的左、右两侧半桥；全桥功率开关电路的直流电源输入端与直流电源相连，电感线圈L1连接于全桥开关电路中的两侧半桥输出端之间；输出端的开关器件SW5连接于输出电容C6、C7与全桥开关电路中右侧半桥输出端之间；输出电容C6与C7串联于直流电源输入端的正负端之间。
第二实施例又分为两个子实施例：当全桥功率开关电路无需支持升压输出时，所述开关器件SW5为双向截止型开关器件，所述开关器件SW1、SW2、SW3、和SW4均为单向截止型开关器件；例如，开关器件SW1、SW2、SW3、和SW4均为MOSFET或IGBT配合续流二极管，开关器件SW5为两个相向串联的MOSFET或IGBT分别配合续流二极管，每个MOSFET或IGBT分别并联一个辅助开关电容。本发明中所述的单向截止型开关器件和双向截止型开关器件的结构分别如图18a和图18b所示。
当全桥功率开关电路支持升压输出时，所述开关器件SW3、SW4和SW5均为双向截止型功率开关器件，所述开关器件SW1和SW2均为单向截止型功率开关器件；例如，开关器件SW1和SW2均为MOSFET或IGBT配合续流二极管，开关器件SW3、SW4和SW5为两个相向串联的MOSFET或IGBT分别配合续流二极管，每个MOSFET或IGBT分别并联一个辅助开关电容。
本发明中，如图18a和图18b所示，双向截止型功率开关器件其 通常为两个相向串联的MOSFET或IGBT配合续流二极管；单向截止型功率开关器件为普通的MOSFET或IGBT配合续流二极管；双向截止型功率开关器件的导通电阻原则上比普通的单向截止型功率开关器件要大，因此如无升压输出需求应尽量使用单向截止型功率开关器件。
开关器件SW1、SW2、SW3、SW4、SW5均由零电压开关(ZVS)门极驱动器控制，通过的开关组合可在开关周期内实现高电感平均电流。
以输出设置电流i set(t)为正电流(i set(t)＞0A)为例(如图6a所示)，由于辅助开关电容的容量非常小，其零电压开关(ZVS)的时间与过程中的电感电流的变化可忽略不计。整个开关过程可简化为以下四部分：
Figure PCTCN2020081180-appb-000011
Figure PCTCN2020081180-appb-000012
Figure PCTCN2020081180-appb-000013
Figure PCTCN2020081180-appb-000014
第二实施例中，全桥功率开关电路在较小输出功率的工作状态下可通常开SW3和SW4(关断)同时常闭SW5(导通)达到与半桥功率开关电路相同的工作效果，其状态控制方式与半桥功率开关电路相同。
每个所述比较控制单元内建比较器、逻辑计算单元，并设置一个用于零电压开关的切换电流I const；逻辑计算单元根据反馈控制单元输出的输出设置电流i set(t)与全桥功率开关电路的结构特性计算出开关状态切换时所需的电感峰值电流I peak(t)和中间比较电流I comp(t)，并 与实时测量得到的电感电流i L(t)通过比较器进行比较，根据全桥功率开关电路的结构确定对应的开关状态到功率开关电路，具体为：
在每个全桥功率开关电路中，通过对电感施加直流输入电压U in使电感电流i L(t)在很短的时间内从与输出设置电流i set(t)方向相反的切换电流I const增长到正向的中间比较电流I comp(t)，从而通过较低的电感峰值电流I peak(t)在开关周期内实现较高的电感平均电流；其中，中间比较电流I comp(t)大小位于切换电流I const与I peak(t)之间，方向与电感峰值电流I peak(t)的方向相同。
由于电感电流由反向的切换电流-I const增长到正向的中间比较电流I comp(t)的时间非常短，此过程中对整个开关周期内的电感平均电流的影响可被忽略，电感峰值电流I peak(t)与输出设置电流i set(t)的计算关系如表4所示：
表4 电感峰值电流I peak(t)与输出设置电流i set(t)关系表
  电感峰值电流 电感反向电流
i set(t)＞0A I peak(t)≈2·i set(t)-I comp(t) -I const
i set(t)＝0A I peak(t)＝I const -I const
i set(t)＜0A I peak(t)≈2·i set(t)-I comp(t) I const
第二实施例中，无需支持升压输出的全桥功率开关电路的结构对应的开关状态如图6a、图6b所示，具体情况统计见表5所示：[状态0为关断，1为导通]
表5 第二实施例中无需支持升压输出的全桥功率开关电路的结构对应的开关状态
Figure PCTCN2020081180-appb-000015
其在一个开关周期内的工作时序如表6所示：[状态0为关断，1为导通]
表6 第二实施例中无需升压支持输出的全桥功率开关电路中一个开关周期内的工作时序与零电压开关(ZVS)过程
Figure PCTCN2020081180-appb-000016
第二实施例中，支持升压输出的全桥功率开关电路的结构对应的开关状态如图9a、图9b、图9c和图9d所示，具体情况统计见表7和表8所示：[状态0为关断，1为导通]
表7 第二实施例中支持升压输出的全桥功率开关电路的结构对应的开关状态(一)
Figure PCTCN2020081180-appb-000017
表8 第二实施例中支持升压输出的全桥功率开关电路的结构对应的开关状态(二)
Figure PCTCN2020081180-appb-000018
第三实施例中，功率开关电路为半桥功率开关电路。
其整体的原理框图如图1b所示，图1b与图1a的区别在于，每个所述比较控制单元，其输入信号还包括输出端电压信号u out(t)。
其功率开关电路原理如图10所示，与第一实施例中的半桥功率开关电路的区别在于，每个半桥功率开关电路还包含若干个中间直流电源输入端，所述中间直流电源输入端与若干个中间直流电源相连，本实施例中，中间直流电源输入端为一个，用U inM1表示；中间直流 电源输入端的输入电压U inM1位于+U in和-U in之间，每个半桥功率开关电路还包含一个双向截止型开关器件SWM1与对应的辅助开关电容CM1，每个中间直流电源输入端通过一个双向截止型开关器件SWM1与高边开关器件SW1、低边开关器件SW2和电感线圈L1的一端相连，且每一个双向截止型开关器件SWM1与一个辅助开关电容CM1并联；双向截止型开关器件SWM1由零电压开关(ZVS)门极驱动器控制。
其工作原理与第一实施例类似，但因为加入了中间直流电源U inM1，在实时比较电感电流i L(t)与电感峰值电流I peak(t)、中间比较电流I comp(t)和与切换电流I const的大小时，还需结合输出端电压u out(t)所处的电压范围。
具体地，其在一个开关周期内的开关状态为：
当i set(t)＞0A和u out(t)＞U inM1，此时I peak(t)＞0A、I comp(t)＞0A、切换电流为-I const，如图11a和表9所示：
表9 第三实施例中的半桥功率开关电路的结构对应的开关状态(一)
时间区间 比较触发条件 电感电流范围 SW1 SWM1 SW2
(0，t 0] i L(t)≤-I const -I const＜i L(t)≤I peak(t) 1 0 0
(t 0，t 1] i L(t)≥I peak(t) I comp(t)≤i L(t)＜I peak(t) 0 1 0
(t 1，T] i L(t)≤I comp(t) -I const≤i L(t)＜I comp(t) 0 0 1
当i set(t)＜0A和u out(t)＞U inM1，此时I peak(t)＜0A、I comp(t)＜0A、切换电流为I const，如图11b和表10所示：
表10 第三实施例中的半桥功率开关电路的结构对应的开关状态(二)
时间区间 比较触发条件 电感电流范围 SW1 SWM1 SW2
(0，t 0] i L(t)≥I const I comp(t)≤i L(t)＜I const 0 0 1
(t 0，t 1] i L(t)≤I comp(t) I peak(t)≤i L(t)＜I comp(t) 0 1 0
(t 1，T] i L(t)≤I peak(t) I peak(t)＜i L(t)≤I const 1 0 0
当i set(t)＞0A和u out(t)＜U inM1，此时I peak(t)＞0A、I comp(t)＞0A、切换电流为-I const，如图11c和表11所示：
表11 第三实施例中的半桥功率开关电路的结构对应的开关状态(三)
时间区间 比较触发条件 电感电流范围 SW1 SWM1 SW2
(0，t 0] i L(t)≤-I const -I const＜i L(t)≤I comp(t) 1 0 0
(t 0，t 1] i L(t)≥I comp(t) I comp(t)＜i L(t)≤I peak(t) 0 1 0
(t 1，T] i L(t)≥I peak(t) -I const≤i L(t)＜I peak(t) 0 0 1
当i set(t)＜0A和u out(t)＜U inM1，此时I peak(t)＜0A、I comp(t)＜0A、切换电流为I const，如图11d和表12所示：
表12 第三实施例中的半桥功率开关电路的结构对应的开关状态(四)
时间区间 比较触发条件 电感电流范围 SW1 SWM1 SW2
(0，t 0] i L(t)≥I const I peak(t)≤i L(t)＜I const 0 0 1
(t 0，t 1] i L(t)≤I peak(t) I peak(t)＜i L(t)≤I comp(t) 0 1 0
(t 1，T] i L(t)≥I comp(t) I comp(t)＜i L(t)≤I const 1 0 0
第四实施例中，功率开关电路为半桥功率开关电路。
其整体的原理框图如图1b所示，功率开关电路原理如图12所示，与第三实施例的区别在于，每个半桥功率开关电路包含两个中间直流电源输入端U inM1和U inM2，并分别与两个中间直流电源相连，其输入电压U inM1和U inM2均位于+U in和-U in之间，且U inM1＞U inM2，每个半桥功率开关电路包含两个双向截止型开关器件SWM1、SWM2与对应的两个辅助开关电容CM1、CM2，两个中间直流电源输入端分别通过一个双向截止型开关器件与高边开关器件SW1、低边开关器件SW2和电感线圈L1的一端相连，且每一个双向截止型开关器件与一个辅助开关电容并联；双向截止型开关器件SWM1、SWM2由零电压开关(ZVS)门极驱动器控制。
可以理解的是，其他实施例中，中间直流电源输入端也可以为大于2的其它个数，如n个，则电路结构也相应的变化，双向截止型开 关器件与辅助开关电容的个数也为n个；只要满足n个中间直流电源输入端的输入电压均位于+U in和-U in之间即可。
第四实施例中，当输出端电压u out(t)大于或小于各中间直流电源输入端电压时，选择与输出端电压值相邻的中间直流电源作为中间直流电源，此时功率开关电路的控制方式与上述第三实施例中拥有单个中间直流电源输入端的功率开关电路相同。
其他情况下，在一个开关周期内的开关状态为：
当i set(t)＞0A和U inM2＜u out(t)＜U inM1，此时I peak(t)＞0A、I comp(t)＞0A、切换电流为-I const，如图13a和表13所示：
表13 第四实施例中的半桥功率开关电路的结构对应的开关状态(一)
时间区间 比较触发条件 电感电流范围 SW1 SWM1 SWM2 SW2
(0，t 0] i L(t)≤-I const -I const＜i L(t)≤I comp(t) 1 0 0 0
(t 0，t 1] i L(t)≥I comp(t) I comp(t)＜i L(t)≤I peak(t) 0 1 0 0
(t 1，t 2] i L(t)≥I peak(t) I comp(t)≤i L(t)＜I peak(t) 0 0 1 0
(t 2，T] i L(t)≤I comp(t) -I const≤i L(t)＜I comp(t) 0 0 0 1
当i set(t)＜0A和U inM2＜u out(t)＜U inM1，此时I peak(t)＜0A、I comp(t)＜0A、切换电流为I const，如图13b和表14所示：
表14 第四实施例中的半桥功率开关电路的结构对应的开关状态(二)
时间区间 比较触发条件 电感电流范围 SW1 SWM1 SWM2 SW2
(0，t 0] i L(t)≥I const I comp(t)≤i L(t)＜I const 0 0 0 1
(t 0，t 1] i L(t)≤I comp(t) I peak(t)≤i L(t)＜I comp(t) 0 0 1 0
(t 1，t 2] i L(t)≤I peak(t) I peak(t)＜i L(t)≤I comp(t) 0 1 0 0
(t 2，T] i L(t)≥I comp(t) I comp(t)＜i L(t)≤I const 1 0 0 0
上述各端点电势均以直流电源输入端的中间点电位为参考点，其电压u out(t)、U inM1、U inM2均为各端到直流电源输入端的正负端间的中间点的电压，其电压高低关系为-U in/2＜U inM2＜U inM1＜+U in/2。
第五实施例中，功率开关电路为全桥功率开关电路。
其整体的原理框图如图1b所示，功率开关电路原理如图14所示，与第二实施例的区别在于，每个全桥功率开关电路还包含若干个中间直流电源输入端，所述中间直流电源输入端与若干个中间直流电源相连，本实施例中，中间直流电源输入端为一个，用U inM1表示；中间直流电源输入端的输入电压U inM1位于+U in和-U in之间，每个全桥功率开关电路还包含一个双向截止型开关器件SWM1与对应的辅助开关电容CM1，中间直流电源输入端通过双向截止型开关器件SWM1与开关器件SW1、SW2和电感线圈L1的一端相连，且双向截止型开关器件SWM1与辅助开关电容CM1并联；双向截止型开关器件SWM1由零电压开关(ZVS)门极驱动器控制。且该实施例中，全桥功率开关电路无需支持升压输出。
其工作原理与第二实施例类似，但因为加入了中间直流电源U inM1，在实时比较电感电流i L(t)与电感峰值电流I peak(t)、中间比较电流I comp(t)和与切换电流I const的大小时，还需结合输出端电压u out(t)所处的电压范围。
具体地，其在一个开关周期内的开关状态为：
当i set(t)＞0A和u out(t)＞U inM1，此时I peak(t)＞0A、I comp(t)＞0A、切换电流为-I const，如图15a与表15所示：
表15 第五实施例中的全桥功率开关电路的结构对应的开关状态(一)
Figure PCTCN2020081180-appb-000019
当i set(t)＜0A和u out(t)＞U inM1，此时I peak(t)＜0A、I comp(t)＜0A、切换电流为I const，如图15b与表16所示：
表16 第五实施例中的全桥功率开关电路的结构对应的开关状态(二)
Figure PCTCN2020081180-appb-000020
当i set(t)＞0A和u out(t)＜U inM1，此时I peak(t)＞0A、I comp(t)＞0A、切换电流为-I const，如图15c与表17所示：
表17 第五实施例中的全桥功率开关电路的结构对应的开关状态(三)
Figure PCTCN2020081180-appb-000021
当i set(t)＜0A和u out(t)＜U inM1，此时I peak(t)＜0A、I comp(t)＜0A、切换电流为I const，如图15d与表18所示：
表18 第五实施例中的全桥功率开关电路的结构对应的开关状态(四)
Figure PCTCN2020081180-appb-000022
第六实施例中，功率开关电路为全桥功率开关电路。
其整体的原理框图如图1b所示，功率开关电路原理如图16所示，与第五实施例的区别在于，每个全桥功率开关电路包含两个中间直流电源输入端U inM1和U inM2，并分别与两个中间直流电源相连，其输入电压U inM1和U inM2均位于+U in和-U in之间，且U inM1＞U inM2，每个全桥功率开关电路包含两个双向截止型开关器件SWM1、SWM2与对应的两个辅助开关电容CM1、CM2，两个中间直流电源输入端分别通过一个双向截止型开关器件与开关器件SW1、SW2和电感线圈L1的一端相连，且每一个双向截止型开关器件与一个辅助开关电容并联；双向截止型开关器件SWM1、SWM2由零电压开关(ZVS)门极驱动器控制。且该实施例中，全桥功率开关电路无需支持升压输出。
可以理解的是，其他实施例中，中间直流电源输入端也可以为大于2的其它个数，如n个，则电路结构也相应的变化，双向截止型开关器件与辅助开关电容的个数也为n个；只要满足n个中间直流电源输入端的输入电压均位于+U in和-U in之间即可。
第六实施例中，当输出端电压u out(t)大于或小于各中间直流电源 输入端电压时，选择与输出端电压值相邻的中间直流电源作为中间直流电源，此时功率开关电路的控制方式与上述第五实施例中拥有单个中间直流电源输入端的功率开关电路相同。
其他情况下，在一个开关周期内的开关状态为：
当i set(t)＞0A和U inM2＜u out(t)＜U inM1，此时I peak(t)＞0A、I comp(t)＞0A、切换电流为-I const，如图17a与表19所示：
表19 第六实施例中的全桥功率开关电路的结构对应的开关状态(一)
Figure PCTCN2020081180-appb-000023
当i set(t)＜0A和U inM2＜u out(t)＜U inM1，此时I peak(t)＜0A、I comp(t)＜0A、切换电流为I const，如图17b与表20所示：
表20 第六实施例中的全桥功率开关电路的结构对应的开关状态(二)
Figure PCTCN2020081180-appb-000024
上述各端点电势均以直流电源输入端的中间点电位为参考点，其 电压u out(t)、U inM1、U inM2均为各端到直流电源输入端的正负端间的中间点的电压，其电压高低关系为-U in/2＜U inM2＜U inM1＜+U in/2。
综上，本发明通过将功率开关器件与电感的组合看作可控电流源，以高频开关的方式对输出电容和输出负载提供所需电流，输出端电压由电感所供给的电流和由负载流出的电流的差值对时间的积分在电容上获得。
通过电容对输出电压变化率的牵制，以及电感瞬时电流与输出电流的解耦，使功率开关电路在边界传到模式BCM(Boundary Conduction Mode)下工作，从原理上同时实现了低开关损耗和低输出端高频电磁干扰的特性。对于有较大寄生电容的功率开关器件(例如Superjunction-MOSFET)有着良好的兼容性，对于未来更快速的功率开关器件(例如SiC-MOSEFT和GaN-FET)的广泛应用起到辅助作用。
并且，上述的第三至第六实施例中，均在电路中加入了中间直流电源输入及对应的双向截止型开关器件与对应的辅助开关电容，在这样的结构下，通过对电感两端电压的切换，使得能够以较低的电感峰值电流实现较高的电感平均电流，从而降低系统的导通损耗。
最后说明的是，以上实施例仅用以说明本发明的技术方案而非限制，尽管参照较佳实施例对本发明进行了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或者等同替换，而不脱离本发明技术方案的宗旨和范围，其均应涵盖在本发明的权利要求范围中。

Claims (10)

  1. 一种超低开关功耗、超低输出端电磁干扰的逆变驱动系统，其特征在于，包括多相逆变驱动系统，每相逆变驱动系统为独立系统，每相逆变驱动系统的输出端为所需输出的交流波形，每相逆变驱动系统均包括以下部分：反馈控制单元、比较控制单元和功率开关电路；
    每个所述反馈控制单元，通过输入信号：外部输入信号u sin(t)、输出端电压信号u out(t)、输出端电流信号i out(t)来计算出该相所需的输出设置电流i set(t)，并将该相所需输出的输出设置电流i set(t)输出到该相逆变驱动系统的比较控制单元；
    每个所述比较控制单元，其输入信号包括该相逆变驱动系统的反馈控制单元输出的输出设置电流i set(t)和电感电流实时测量信号i L(t)；通过由反馈控制单元输出的输出设置电流i set(t)与功率开关电路的结构特性计算出开关状态切换时所需的电感峰值电流I peak(t)和中间比较电流I comp(t)，设置一个用于零电压开关的切换电流I const，并与实时测量的电感电流i L(t)进行比较，通过逻辑计算确定出功率开关电路中开关器件相应的开关状态，并将开关状态信号输出到该相逆变驱动系统的功率开关电路；
    每个所述功率开关电路，其输入信号为该相逆变驱动系统的比较控制单元输出的开关状态信号；其输出信号为输出端电压信号u out(t)、输出端电流信号i out(t)和电感电流实时测量信号i L(t)；所述电感电流实时测量信号i L(t)反馈到该相逆变驱动系统的比较控制单元，所述输出端电压信号u out(t)和输出端电流信号i out(t)反馈到该相逆变驱动系统的反馈控制单元。
  2. 根据权利要求1所述的一种超低开关功耗、超低输出端电磁干扰的逆变驱动系统，其特征在于，根据应用需求，所述功率开关电 路为半桥功率开关电路或全桥功率开关电路。
  3. 根据权利要求2所述的一种超低开关功耗、超低输出端电磁干扰的逆变驱动系统，其特征在于，所述功率开关电路为半桥功率开关电路，每个所述半桥功率开关电路包含高边开关器件SW1、低边开关器件SW2、分别与高边开关器件SW1、低边开关器件SW2并联的辅助开关电容C1和C2、电感线圈L1以及输出电容C3和C4；每个所述半桥功率开关电路的直流电源输入端的正负端+U in和-U in分别与直流电源的正负极相连，高边开关器件SW1与低边开关器件SW2串联于直流电源输入端的正负端之间形成半桥开关电路，电感线圈L1连接于半桥开关电路输出端与输出电容C3和C4之间，输出电容C3与C4串联于直流电源输入端的正负端之间；
    高边开关器件SW1和低边开关器件SW2均由零电压开关(ZVS)门极驱动器控制。
  4. 根据权利要求3所述的一种超低开关功耗、超低输出端电磁干扰的逆变驱动系统，其特征在于，每个所述比较控制单元，其输入信号还包括输出端电压信号u out(t)；
    每个所述半桥功率开关电路还包含若干个中间直流电源输入端，所述中间直流电源输入端与若干个中间直流电源相连；中间直流电源输入端的输入电压位于+U in和-U in之间，每个所述半桥功率开关电路还包含若干个双向截止型开关器件SWM与对应的辅助开关电容CM，每个中间直流电源输入端通过一个双向截止型开关器件SWM与高边开关器件SW1、低边开关器件SW2和电感线圈L1的一端相连，且每一个双向截止型开关器件SWM与一个辅助开关电容CM并联；双向截止型开关器件SWM由零电压开关(ZVS)门极驱动器控制。
  5. 根据权利要求2所述的一种超低开关功耗、超低输出端电磁干扰的逆变驱动系统，其特征在于，所述功率开关电路为全桥功率开关电路，每个所述全桥功率开关电路包含开关器件SW1、SW2、SW3、SW4、SW5，分别与开关器件SW1、SW2、SW3、SW4、SW5并联的辅助开关电容C1、C2、C3、C4、C5，电感线圈L1，以及输出电容C6、C7；开关器件SW1、SW2串联于直流电源输入端的正负端之间，以及开关器件SW3、SW4串联于直流电源输入端的正负端之间分别形成全桥开关电路中的左、右两侧半桥；全桥功率开关电路的直流电源输入端的正负端+U in和-U in分别与直流电源的正负极相连，电感线圈L1连接于全桥开关电路中的两侧半桥输出端之间；输出端的开关器件SW5连接于输出电容C6、C7与全桥开关电路中右侧半桥输出端之间；输出电容C6与C7串联于直流电源输入端的正负端之间；
    开关器件SW1、SW2、SW3、SW4、SW5均由零电压开关(ZVS)门极驱动器控制。
  6. 根据权利要求5所述的一种超低开关功耗、超低输出端电磁干扰的逆变驱动系统，其特征在于，当全桥功率开关电路无需支持升压输出时，所述开关器件SW5为双向截止型功率开关器件，所述开关器件SW1、SW2、SW3、和SW4均为单向截止型功率开关器件；当全桥功率开关电路支持升压输出时，所述开关器件SW3、SW4和SW5均为双向截止型功率开关器件，所述开关器件SW1和SW2均为单向截止型功率开关器件。
  7. 根据权利要求5所述的一种超低开关功耗、超低输出端电磁干扰的逆变驱动系统，其特征在于，每个所述比较控制单元，其输入信号还包括输出端电压信号u out(t)；
    每个所述全桥功率开关电路还包含若干个中间直流电源输入端，所述中间直流电源输入端与若干个中间直流电源相连；中间直流电源输入端的输入电压位于+U in和-U in之间，每个所述全桥功率开关电路还包含若干个双向截止型开关器件SWM与对应的辅助开关电容CM，每个中间直流电源输入端通过一个双向截止型开关器件SWM与开关器件SW1、SW2和电感线圈L1的一端相连，且每一个双向截止型开关器件SWM与一个辅助开关电容CM并联；双向截止型开关器件SWM由零电压开关(ZVS)门极驱动器控制。
  8. 根据权利要求1所述的一种超低开关功耗、超低输出端电磁干扰的逆变驱动系统，其特征在于，每个所述功率开关电路的功率输入端为：直流电源输入端的正负端(+U in和-U in)，每个所述功率开关电路的输出端电压u out(t)，即每相逆变驱动系统的输出端电压u out(t)为；
    Figure PCTCN2020081180-appb-100001
    其中，U A的电势参考点为直流电源输入端电压的中间点电位，即输入直流电源电压的一半。
  9. 根据权利要求1所述的一种超低开关功耗、超低输出端电磁干扰的逆变驱动系统，其特征在于，每个所述反馈控制单元通过外部输入信号u sin(t)、输出端电压信号u out(t)、输出端电流信号i out(t)建立反馈控制网络，从而计算出该相所需的输出设置电流i set(t)，即：
    i set(t)＝G(u sin(t)，u out(t)，i out(t))
    其中，输出电压与电流可表达为：
    Figure PCTCN2020081180-appb-100002
    Figure PCTCN2020081180-appb-100003
    其中C out为输出电容的容量。
  10. 根据权利要求9所述的一种超低开关功耗、超低输出端电磁干扰的逆变驱动系统，其特征在于，反馈控制单元包括PID控制器；其建立反馈控制网络的具体工作流程为：
    (1)通过对外部输入信号u sin(t)与输出电压信号u out(t)进行比较得出电压差值信号，并输入至PID控制器；
    (2)通过计算外部输入信号u sin(t)对时间的导数并与输出电容容量相乘得出输出电容C out充放电电流；
    (3)由(1)中PID控制器输出的电压差反馈增量电流与(2)中所得的输出电容充放电电流与当前输出端电流i out(t)相加，其结果为输出设置电流i set(t)，并输入至比较控制单元。
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