WO2020216373A1 - 一种垂直集成单元二极管芯片 - Google Patents

一种垂直集成单元二极管芯片 Download PDF

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WO2020216373A1
WO2020216373A1 PCT/CN2020/086882 CN2020086882W WO2020216373A1 WO 2020216373 A1 WO2020216373 A1 WO 2020216373A1 CN 2020086882 W CN2020086882 W CN 2020086882W WO 2020216373 A1 WO2020216373 A1 WO 2020216373A1
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conductivity type
diode
pad
mesa structure
type pad
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PCT/CN2020/086882
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English (en)
French (fr)
Inventor
闫春辉
蒋振宇
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深圳第三代半导体研究院
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Publication of WO2020216373A1 publication Critical patent/WO2020216373A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/642—Heat extraction or cooling elements characterized by the shape

Definitions

  • the invention relates to the field of semiconductor materials and device technology, especially semiconductor optoelectronic devices.
  • the first prior art is the Proc.ofSPIEVol.10021100210X-12016 conference paper, as shown in Figures 1-3, where Figure 1 is a structural diagram of a vertical LED chip, where the p-type electrode is connected to the electrode on the back (backmetalAu), and the black part
  • the box on the edge and the three finger-shaped leads in the middle represent the second conductivity type electrodes, which are led out by the two large N-pad wires below. Therefore, the current diffusion of the entire chip is mainly limited by the n-type metal wire.
  • Fig. 2 shows the near-field analysis diagram of the vertical chip and the normalized current distribution diagram on the center line of the prior art 1.
  • the size of the chip is 1.2mm ⁇ 1.2mm. It can be seen from the near-field graph that the current distribution of the chip is still very uneven.
  • the area close to the n-electrode line has high light intensity and high current density, while the area far away from the n-electrode line has low light intensity and low current density.
  • the normalized distribution map shows that the area with smaller current density is less than 70% of the larger area. Therefore, the LED luminous efficiency, heat dissipation and stability under high current will be severely restricted.
  • the present invention proposes a vertically integrated unit with high lumen efficiency and large lumen density output. Diode chip.
  • the present invention provides a vertically integrated unit diode chip, including a first conductivity type electrode, a second conductivity type electrode, and a diode mesa structure on the first conductivity type electrode.
  • the diode mesa structure further includes the first conductivity type.
  • the pad and the second conductivity type pad where the first conductivity type pad and the second conductivity type pad are on the same side of the diode mesa structure, the first conductivity type electrode is connected to the first conductivity type pad, and the second conductivity type The electrode is connected to the second conductivity type pad; wherein, the second conductivity type electrode is an n electrode, the first conductivity type pad is a p pad, and the second conductivity type pad is an n pad; the first conductivity type pad and The thickness of the second conductive type pad is 0.001 ⁇ m to 20 ⁇ m, and the width is 10 ⁇ m to 100 ⁇ m.
  • the present invention also provides a vertically integrated unit diode chip, which includes a first conductivity type electrode, a second conductivity type electrode, and a diode mesa structure on the first conductivity type electrode.
  • the diode mesa structure further includes a first conductivity type electrode.
  • the second conductivity type electrode is connected to the second conductivity type pad.
  • the present invention also provides a vertically integrated unit diode chip, which includes a first conductivity type electrode, a second conductivity type electrode, and a diode mesa structure on the first conductivity type electrode.
  • the diode mesa structure further includes a first conductivity type electrode.
  • a pad of a conductivity type and a pad of a second conductivity type wherein the pad of the first conductivity type and the pad of the second conductivity type are on the same side of the diode mesa structure, the electrode of the first conductivity type is connected to the pad of the first conductivity type, and The second conductivity type electrode is connected to the second conductivity type pad; the thickness of the first conductivity type pad and the second conductivity type pad are 0.001 ⁇ m to 20 ⁇ m, and the width is 10 ⁇ m to 100 ⁇ m; the second conductivity type electrode is connected to the first conductivity type pad.
  • the two conductive type pads are connected by a linear electrode line, the width of the linear electrode line is 0.001 micrometers to 20 micrometers, and the thickness is 0.001 micrometers to 10 micrometers.
  • the vertically mounted integrated unit diode chip used in the present invention breaks through the limitations of the existing vertical LED technology at the three levels of light, electricity and heat through the nano-micron size structure effect.
  • the size design of the unit diode chip is controlled within the current diffusion length. Its high degree of freedom geometric optimization design method can simultaneously solve the problem of uneven current diffusion of the n-electrode and p-electrode that plagues the design of the LED unit diode chip.
  • the nano-microstructure of each diode unit, the hole structure and the groove structure inside the mesa can increase the effective light extraction area, thereby improving the light extraction efficiency; the reduction of the integrated unit diode chip size and the interior of the mesa
  • the hole structure brings a larger heat dissipation area and better heat dissipation performance. It can allow the injection of super current density without affecting its stability, thereby greatly improving the lumen output of the integrated unit diode chip per unit area and reducing the lumen cost.
  • FIG. 1 is a structural diagram of a diode unit in the prior art.
  • Fig. 2 is a structural diagram of a diode unit in the prior art.
  • FIG. 3 is a top view of a diode mesa structure provided by Embodiment 1 of the present invention.
  • Embodiment 4 is a top view of a diode mesa structure provided by Embodiment 1 of the present invention.
  • FIG. 5 is a top view of a diode mesa structure provided by Embodiment 1 of the present invention.
  • FIG. 6 is a top view of a diode mesa structure provided by Embodiment 1 of the present invention.
  • FIG. 7 is a top view of a diode mesa structure provided by Embodiment 1 of the present invention.
  • Fig. 8 is a schematic diagram of a diode unit provided by embodiment 1-2 of the present invention.
  • FIG. 9 is a three-dimensional view of a vertically integrated unit diode chip provided by Embodiment 3 of the present invention.
  • FIG. 10 is a three-dimensional view of a vertically integrated unit diode chip provided by Embodiment 3 of the present invention.
  • Second conductivity type electrode 1 insulating dielectric layer 2, second conductivity type layer 3, quantum well active area (MQW) 4, first conductivity type layer 5, mirror 6, protective metal layer 7, substrate 8, back surface Electrode 9, first conductivity type pad 10, second conductivity type pad 11, linear electrode line 12, mesa structure 13, diode unit 14, trench structure 15, and hole structure 16.
  • MQW quantum well active area
  • embodiments of the present invention provide a vertically mounted integrated unit diode with high lumen efficiency and large lumen density output. The present invention will be described in detail with reference to the drawings.
  • a vertically integrated unit diode chip including:
  • the first conductivity type electrode, the second conductivity type electrode and the diode mesa structure located on the first conductivity type electrode, the diode mesa structure includes n diode units and a trench structure, where n ⁇ 2; the area of the mesa structure depends on the current The diffusion length is determined; the diode mesa structure further includes a first conductivity type pad and a second conductivity type pad, wherein the first conductivity type pad and the second conductivity type pad are on the same side of the mesa structure, and the first conductivity type electrode It is connected to the first conductivity type pad, and the second conductivity type electrode is connected to the second conductivity type pad.
  • the diode mesa structure further includes an insulating dielectric layer, a first conductivity type layer, a second conductivity type layer, and a quantum well active region located on the first conductivity type layer, a second conductivity type layer and a second conductivity type electrode Ohmic contact.
  • the number of the first conductivity type pads is greater than or equal to 1, and the shape can be: semicircle, circle, rectangle, triangle, regular or irregular straight polygon, or irregular polygon with one or more arc sides, thickness It is 0.001 microns to 20 microns, and the width is: 10 microns to 100 microns, located at any edge, mesa vertex, middle of the mesa or any other position of the mesa of the diode mesa structure.
  • the first conductive type pad may be arranged from the first side of the mesa structure and have the same width as the mesa structure. When the width of the mesa structure is the same, the width of the first conductive type pad is 10 ⁇ m-100 ⁇ m, and the length is 10 ⁇ m-10000 ⁇ m.
  • the shape of the pads of the second conductivity type can be: semicircle, circle, rectangle, triangle, irregular straight polygon, or irregular polygon with one or more arc sides, the number of pads is greater than or equal to 1, located in Any edge, apex of the mesa, the middle of the mesa or other arbitrary positions on the mesa of the mesa structure.
  • the second conductive type pads may be arranged from the second side of the mesa structure and have the same width as the mesa structure. When the width is the same as the mesa structure, the width of the second conductive type pad is 10 ⁇ m-100 ⁇ m, and the length is 10 ⁇ m-10000 ⁇ m. The thickness of the pad is 0.001 to 20 microns, and the width is 10 to 100 microns.
  • the second conductive type electrode and the second conductive type pad are connected by a linear electrode line.
  • the linear electrode line has a width of 0.001 ⁇ m to 20 ⁇ m and a thickness of 0.001 ⁇ m to 10 ⁇ m. Part or all of the design adopts a non-linear layout. Straight line layout includes broken line layout and curved layout.
  • the linear electrode line is made of linear metal and/or indium tin oxide material. The metal material is aluminum, silver, titanium, nickel, gold, platinum, chromium, or any two or more of the above metals Alloy.
  • the diode mesa structure includes a hole structure.
  • the diode unit is connected in parallel.
  • the shape of the diode unit is: triangle, square, rectangle, pentagon, hexagon, circle, and any custom shape.
  • the number of diode units is 2 ⁇ 1000 Billion.
  • the diode mesa structure includes a trench structure, the trench structure is located between the diode units, and the trench depth reaches the second conductivity type layer or the quantum well active region or the first conductivity type layer.
  • the shape of the groove in the diode mesa structure is quadrilateral, concentric rings, cross and other arbitrary curved shapes.
  • a reflector and a protective metal layer are arranged between the diode mesa structure and the substrate, and the thickness of the substrate is 1 nanometer-250 microns.
  • This embodiment provides a vertically integrated unit diode chip, including: a second conductivity type electrode 1, a second conductivity type pad 11, a first conductivity type pad 10, a linear electrode line 12, a diode mesa structure 13, a diode unit 14 and groove 15.
  • the diode mesa structure includes 6 rows of 52 square diode units 14 of equal size and uniform distribution.
  • the length of the diode units 14 along the X-axis direction is 40 microns.
  • the diode mesa structure adopts a square arrangement, the connection mode of the diode units is parallel, and the size of the mesa structure is smaller than the diffusion length of the current injection.
  • the shape of the diode unit is a rectangle and is arranged in a uniform and symmetrical arrangement.
  • the second conductivity type electrode is an n electrode
  • the first conductivity type pad is a p pad
  • the second conductivity type pad is an n pad.
  • the length of the diode unit in the X-axis direction is 100 microns; in other preferred embodiments, the length of the diode unit in the X-axis direction is 10 microns; in other preferred embodiments, the length of the diode unit in the X-axis direction is 1 Micrometers.
  • the first conductivity type pad 10 and the second conductivity type pad 11 are on the same side of the mesa structure, and the second conductivity type electrode 1 and the second conductivity type pad 11 are connected by a linear electrode line 12.
  • the shapes of the second conductivity type pad 11 and the first conductivity type pad 10 are irregular polygons with one side arc, and the numbers of the second conductivity type pads and the first conductivity type pads are both It is 1, located on the short edge of the mesa structure.
  • the shapes of the second conductivity type pad 11 and the first conductivity type pad 10 are irregular polygons with an arc on one side, and the shape of the pads can also be semicircular, circular, rectangular, or triangular. , Irregular straight polygons, or other irregular polygons with one or more arc-shaped sides, are not limited to the display in Figure 4.
  • the numbers of the second conductivity type pads and the first conductivity type pads are both 1, the second conductivity type pads are located on the short edges of the mesa structure, and the first conductivity type pads are located on the long edges of the mesa structure.
  • the second conductivity type pad 11 is an irregular polygon with an arc-shaped side and is located on the short edge of the mesa structure.
  • the first conductivity type pad 10 is a regular hexagon and is located at the apex of the mesa.
  • the numbers of the second conductivity type pads and the first conductivity type pads are both 1.
  • the shape of the second conductive type pad 11 is a rectangle with the first conductive type pad arranged from the short side of the mesa structure and the same width as the mesa structure.
  • the shape of the first conductive type pad 10 is a rectangle arranged from the short side of the mesa structure and the same width as the mesa structure.
  • the numbers of the second conductivity type pads and the first conductivity type pads are both 1.
  • the thickness of the pad is 0.001 to 20 microns, and the width is 10 to 100 microns.
  • the width of the electrode lines is 0.001-20 microns, and the thickness is 0.001-10 microns.
  • the electrode lines are made of indium tin oxide material and are designed in a straight line layout.
  • the shape of the groove 15 is a cross, the cross-sectional shape is a rectangle, and the grooves 15 are evenly distributed in the horizontal direction.
  • the diode mesa structure further includes an insulating dielectric layer 2, a first conductivity type layer 5, a second conductivity type layer 3, and a quantum well active region 4 on the first conductivity type layer.
  • At least one sidewall surface of the diode unit 14 has grooves distributed from the bottom to the top of the mesa.
  • the cross-sectional shape of the trench on the sidewall of the diode unit is triangular, the width of the trench on the sidewall is 0.5 nanometers-10 microns, and the depth is 0.5 nanometers-10 microns. Since the current diffusion length of the diode chip is inversely proportional to the square root of the current density, under the injection of large current, the current diffusion length is shorter, resulting in more uneven current diffusion of the chip, lower efficiency, and more difficult heat dissipation.
  • the vertical mounting integrated unit light-emitting diode structure design can flexibly change the size and shape of the diode mesa structure, obtain the best current diffusion and heat dissipation performance under the specified operating current, and greatly increase the injection current density of the chip, thereby increasing Lumen output per unit area.
  • This embodiment provides a vertically integrated unit diode chip, as shown in FIG. 7, comprising: a second conductivity type electrode 1, a second conductivity type pad 11, a first conductivity type pad 10, a linear electrode line 12, a diode
  • the mesa structure 13 the diode unit 14 and the trench 15.
  • the diode mesa structure includes 6 rows of 52 square diode units 14 uniformly distributed in size, and the length of the diode units 14 along the X axis direction is 40 microns.
  • the diode mesa structure adopts a square arrangement, the diode units are connected in parallel, and the size of the mesa structure is smaller than the diffusion length of current injection.
  • the shape of the diode unit is a regular rectangle and is arranged in a uniform and symmetrical arrangement.
  • the length of the diode unit in the X-axis direction is 10 nanometers, and in other preferred embodiments, the length of the diode unit in the X-axis direction is 100 nanometers.
  • the first conductivity type pad 10 and the second conductivity type pad 11 are on the same side of the mesa structure, and the second conductivity type electrode 1 and the second conductivity type pad 11 are connected by a linear electrode line 12.
  • the shape of the second conductivity type pad 11 and the first conductivity type pad 10 is an arc-shaped irregular polygon.
  • the shape of the pad can also be a semicircle, a circle, a rectangle, a triangle, an irregular straight polygon, or other shapes.
  • One or more irregular polygons with arc-shaped sides are not limited to the display in FIG. 3.
  • the number of pads is all 1, located at the edge of the mesa structure, the thickness of the pad is 0.001 to 20 microns, and the width is: 10 to 100 microns.
  • the width of the electrode lines is 0.001-20 microns, and the thickness is 0.001-10 microns.
  • the electrode lines are made of indium tin oxide material and are designed in a straight line layout.
  • the shape of the groove 15 is a cross, the cross-sectional shape is a rectangle, and the grooves 15 are evenly distributed in the horizontal direction.
  • a hole structure 16 is added to each diode unit.
  • the hole structure includes a hole unit, the hole unit is circular, and the diameter of the hole unit is 0.001 ⁇ m to 20 ⁇ m.
  • the hole units are arranged symmetrically, asymmetrically, periodically, non-periodically or randomly.
  • the shape of the hole unit can also be a triangle, a square, a rectangle, a pentagon, a hexagon, a circle, and other arbitrary defined shapes, and is not limited to the shape shown in FIG. 7.
  • the diode mesa structure further includes an insulating dielectric layer 2, a first conductivity type layer 5, a second conductivity type layer 3, a quantum well active region 4 located on the first conductivity type layer, and a mirror 6.
  • the first conductivity type layer is a p-GaN layer
  • the second conductivity type layer is an n-GaN layer.
  • the trench depth of the diode unit is up to the p-GaN layer, and the trench depth of the diode unit can also be up to the n-GaN layer or quantum
  • the active region of the well is not limited to that shown in FIG. 8.
  • the vertical mounting integrated unit light-emitting diode structure design can flexibly change the size and shape of the diode mesa structure, obtain the best current diffusion and heat dissipation performance under the specified operating current, and greatly increase the injection current density of the chip, thereby increasing Lumen output per unit area.
  • This embodiment provides a vertical integrated unit diode chip, as shown in FIG. 9, comprising: a second conductivity type electrode 1, a second conductivity type pad 11, a first conductivity type pad 10, a linear electrode line 12, a diode
  • the mesa structure 13 the diode unit 14 and the trench 15.
  • the diode mesa structure includes 6 rows of 6 rectangular diode units 14 of different sizes, and the length of the diode units 14 along the X-axis direction is 80 microns.
  • the diode mesa structure adopts a rectangular arrangement, the diode units are connected in parallel, and the size of the mesa structure is smaller than the diffusion length of current injection.
  • the shape of the diode unit is rectangular, and is arranged in a non-uniform symmetrical arrangement.
  • the first conductivity type pad 10 and the second conductivity type pad 11 are on the same side of the mesa structure, and the second conductivity type electrode 1 and the second conductivity type pad 11 are connected by a linear electrode line 12.
  • the second conductivity type pad 11 and the first conductivity type pad 10 are rectangular in shape, and the pad shape can also be semicircular, circular, triangular, irregular straight polygon, or irregular with one or more sides of arc. Regular polygons are not limited to the display in Figure 3.
  • the number of pads is all 1, located at the edge of the mesa structure, the thickness of the pad is 0.001 to 20 microns, and the width is: 10 to 100 microns.
  • the width of the electrode lines is 0.001-20 microns, and the thickness is 0.001-10 microns.
  • the electrode lines are made of indium tin oxide material and are designed in a straight line layout.
  • the shape of the groove 15 is a cross, the cross-sectional shape is a rectangle, and the grooves 15 are evenly distributed in
  • the diode mesa structure further includes an insulating dielectric layer 2, a first conductivity type layer 5, a second conductivity type layer 3, a quantum well active region 4 located on the first conductivity type layer, and a mirror 6.
  • the trench depth of the diode unit is up to the p-GaN layer, and the trench depth of the diode unit can also be up to the n-GaN layer or the quantum well active region, which is not limited to that shown in FIG. 8.
  • the diode mesa structure includes 4 rows of 30 ladder-shaped diode units of equal size uniformly distributed, and the length of the diode units along the X-axis direction is 40 microns.
  • the size of the mesa structure is smaller than the diffusion length of the current injection.
  • the shape of the diode unit is a trapezoid and is arranged in a uniform and symmetrical arrangement.
  • the angle between the sidewall of the diode unit and the horizontal plane is greater than 0 degrees and less than or equal to 90 degrees, and the shape of the sidewall of the diode unit is trapezoidal.
  • the vertical mounting integrated unit light-emitting diode structure design can flexibly change the size and shape of the diode mesa structure, obtain the best current diffusion and heat dissipation performance under the specified operating current, and greatly increase the injection current density of the chip, thereby increasing Lumen output per unit area.
  • the length design of the diode unit of the present invention is controlled within the current diffusion length, and the optimized geometric design with a certain degree of freedom can further improve the light extraction efficiency, and can simultaneously solve the second conductivity type electrode that troubles the design of the diode chip of the LED unit And the problem of uneven current diffusion of p-type electrode, resulting in higher photoelectric conversion efficiency / lumen efficiency
  • each diode unit of the present invention increases the light exit area of the sidewall, thereby improving the light extraction efficiency.
  • the design of the integrated unit diode chip of the present invention can realize ultra-uniform current injection, thereby obtaining higher efficiency, better wavelength uniformity, narrower half-width of the emission spectrum, and better heat dissipation uniformity Performance and better device stability.
  • the pads of the first conductivity type and the pads of the second conductivity type are on the same side, which facilitates the simplification of the subsequent packaging process and obtains more cost-effective products.
  • the integrated unit diode chip of the present invention is suitable for UVC, UVA, UVB, violet, blue, green, yellow, red, infrared, and other color LED products, and can be used for LED lighting, backlighting, display, plants Lighting, medical and other semiconductor light-emitting device applications.

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Abstract

一种垂直集成单元二极管芯片，包括第一导电类型电极、第二导电类型电极（1）及位于第一导电类型电极上的二极管台面结构（13），二极管台面结构（13）还包括第一导电类型焊盘（10）和第二导电类型焊盘（11），其中第一导电类型焊盘（10）与第二导电类型焊盘（11）在二极管台面结构（13）的同一侧，第一导电类型电极与第一导电类型焊盘（10）连接，第二导电类型电极（1）与第二导电类型焊盘（11）连接。所述垂直集成单元二极管芯片解决了现有技术存在的二极管结构在流明效率、流明密度输出、流明成本三个重要的参数上局限性的技术问题，提高了单位面积芯片的流明输出，降低了流明成本。

Description

一种垂直集成单元二极管芯片 【技术领域】
本发明涉及半导体材料和器件工艺领域，特别是半导体光电器件。
【背景技术】
常规的垂直结构LED芯片中，电流扩散主要依靠n电极侧，有电极引线型引线或钻孔型的引线，但总体电流扩散仍不均匀，导致发光效率的损失，散热也不均匀，从而影响单元二极管芯片的效率和稳定性。从而限制了垂直大功率LED芯片提供单位面积流明输出更高的产品。电流扩散的不均匀、热扩散的不均匀和光提取的不均匀，导致其在流明效率、流明密度输出、流明成本三个重要的参数上有极大的局限性，目前市场上的垂直LED芯片技术无法提供有效的解决方案。
现有技术一为Proc.ofSPIEVol.10021100210X-12016会议论文，如图1-3所示，其中，图1为垂直LED芯片的结构图，其中p型电极与背面的电极相连(backmetalAu)，黑色部分边缘的方框与中间3根手指型引线代表了第二导电类型电极，通过下方的两个大的N-pad打线引出。因此整个芯片的电流扩散，主要为n型金属线所限制。
图2展示了现有技术一的垂直芯片的近场分析图和中线上归一化的电流分布图，芯片的尺寸为1.2mm×1.2mm。近场图中可见，芯片的电流分布仍然十分不均匀，靠近n电极线的区域光强很大，电流密度大，而远离n电极线的区域光强较小，电流密度小。归一化的分布图显示，电流密度较小的区域不到较大区域的70％。因此，大电流下的LED光效、散热和稳定性都会受到严重的限制。
【发明内容】
本发明为解决现有技术存在的二极管结构流明效率、流明密度输出、流明成本三个重要的参数上有极大局限性的技术问题，提出一种流明效率高、流明密度输出大的垂直集成单元二极管芯片。
为实现上述目的，本发明提供一种垂直集成单元二极管芯片，包括 第一导电类型电极、第二导电类型电极及位于第一导电类型电极上的二极管台面结构，二极管台面结构还包括第一导电类型焊盘和第二导电类型焊盘，其中第一导电类型焊盘与第二导电类型焊盘在二极管台面结构的同一侧，第一导电类型电极与第一导电类型焊盘连接，第二导电类型电极与第二导电类型焊盘连接；其中，第二导电类型电极为n电极，第一导电类型焊盘为p焊盘，第二导电类型焊盘为n焊盘；第一导电类型焊盘和第二导电类型焊盘的厚度为0.001微米～20微米，宽度为10微米～100微米。
为实现上述目的，本发明还提供一种垂直集成单元二极管芯片，其中，包括第一导电类型电极、第二导电类型电极及位于第一导电类型电极上的二极管台面结构，二极管台面结构还包括第一导电类型焊盘和第二导电类型焊盘，其中第一导电类型焊盘与第二导电类型焊盘在二极管台面结构的同一侧，第一导电类型电极与第一导电类型焊盘连接，第二导电类型电极与第二导电类型焊盘连接。
为实现上述目的，本发明还提供一种垂直集成单元二极管芯片，其中，包括第一导电类型电极、第二导电类型电极及位于第一导电类型电极上的二极管台面结构，二极管台面结构还包括第一导电类型焊盘和第二导电类型焊盘，其中第一导电类型焊盘与第二导电类型焊盘在二极管台面结构的同一侧，第一导电类型电极与第一导电类型焊盘连接，第二导电类型电极与第二导电类型焊盘连接；第一导电类型焊盘和第二导电类型焊盘的厚度为0.001微米～20微米，宽度为10微米～100微米；第二导电类型电极与第二导电类型焊盘由线条型电极线连接，线条型电极线的宽度为0.001微米～20微米，厚度为0.001微米～10微米。
本发明所采用的垂直装集成单元二极管芯片，通过纳微米尺寸结构效应，在光、电、热三个层面突破现有垂直LED技术的局限性。单元二极管芯片的尺寸设计控制在电流扩散长度以内，其较高自由度的几何优化设计方式，可同时解决困扰LED单元二极管芯片设计的n-电极和p-电极电流扩散不均匀的问题，从而得到更高的光电转换效率/流明效率；每个二极管单元的纳米微结构，台面内部的孔结构和沟槽结构可增加有 效出光面积，从而提升光萃取效率；集成单元二极管芯片尺寸的缩小和台面内部的孔结构，带来更大的散热面积，具备更佳的散热性能，可以允许超大电流密度的注入而不影响其稳定性，从而极大的提高单位面积集成单元二极管芯片的流明输出，降低流明成本。
【附图说明】
图1是现有技术的二极管单元结构图。
图2是现有技术的二极管单元结构图。
图3是本发明实施例1提供的一种二极管台面结构俯视图。
图4是本发明实施例1提供的一种二极管台面结构的俯视图。
图5是本发明实施例1提供的一种二极管台面结构的俯视图。
图6是本发明实施例1提供的一种二极管台面结构的俯视图。
图7是本发明实施例1提供的一种二极管台面结构的俯视图。
图8是本发明实施例1-2提供的二极管单元的示意图。
图9是本发明实施例3提供的垂直集成单元二极管芯片的三维图。
图10是本发明实施例3提供的垂直集成单元二极管芯片的三维图。
第二导电类型电极1，绝缘介质层2，第二导电类型层3，量子阱有源区(MQW)4，第一导电类型层5，反射镜6，保护金属层7，衬底8，背面电极9，第一导电类型焊盘10，第二导电类型焊盘11，线条型电极线12，台面结构13，二极管单元14，沟槽结构15，孔结构16。
【具体实施方式】
下面结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护范围。
鉴于现有的二极管结构流明效率、流明密度输出、流明成本三个重要的参数上极大的局限性，本发明实施例提供一种流明效率高、流明密度输出大的垂直装集成单元二极管，以下结合附图对本发明进行详细说 明。
一种垂直集成单元二极管芯片，包括：
第一导电类型电极，第二导电类型电极及位于所述第一导电类型电极上的二极管台面结构，二极管台面结构包括n个二极管单元和沟槽结构，其中，n≥2；台面结构面积根据电流扩散长度确定；所述二极管台面结构还包括第一导电类型焊盘、第二导电类型焊盘，其中第一导电类型焊盘与第二导电类型焊盘在台面结构同一侧，第一导电类型电极与第一导电类型焊盘连接，第二导电类型电极与第二导电类型焊盘连接。二极管台面结构还包括绝缘介质层，第一导电类型层，第二导电类型层，及位于所述第一导电类型层上的量子阱有源区，第二导电类型层与及第二导电类型电极欧姆接触。
第一导电类型焊盘个数大于或等于1，形状可以为：半圆形，圆形，矩形，三角形，规则或不规则直线多边形，或一条或多条边为弧形的不规则多边形，厚度为0.001微米～20微米，宽度为：10微米～100微米，位于二极管台面结构任意边沿、台面顶点、台面中间或台面其它任意位置。第一导电类型焊盘可以从台面结构第一边设置且与台面结构等宽。当与台面结构等宽时，所述第一导电类型焊盘宽度为10微米～100微米，长度为10微米-10000微米。
第二导电类型焊盘形状可以为：半圆形，圆形，矩形，三角形，不规则直线多边形，或一条或多条边为弧形的不规则多边形，焊盘个数大于或等于1，位于所述台面结构任意边沿、台面顶点、台面中间或台面其它任意位置。第二导电类型焊盘可以从台面结构第二边设置且与台面结构等宽。当与台面结构等宽时，所述第二导电类型焊盘宽度为10微米～100微米，长度为10微米-10000微米。焊盘厚度为0.001微米～20微米，宽度为：10微米～100微米。
第二导电类型电极与第二导电类型焊盘由线条型电极线连接，线条型电极线宽度为0.001微米～20微米，厚度为0.001微米～10微米，部分或全部设计采用非直线布局，其中非直线布局包括折线布局，曲线布局，线条型电极线采用线条形金属和/或氧化铟锡材料，金属材料为铝、 银、钛、镍、金、铂、铬，或以上任意两种以上的金属的合金。
二极管台面结构包括孔结构，二极管单元的连接方式为并联，二极管单元形状为：三角形、正方形、长方形、五边形、六边形、圆形、任意自定义形状，二极管单元数量为2个～1000亿个。
二极管台面结构包括沟槽结构，沟槽结构位于二极管单元之间，沟槽深度至第二导电类型层或量子阱有源区或第一导电类型层。二极管台面结构内的沟槽形状为四边形、同心圆环、十字形及其它任意曲线形状。二极管台面结构和衬底之间具有反射镜和保护金属层，衬底厚度为1纳米-250微米。
实施例1
本实施例提供一种垂直集成单元二极管芯片，包括：第二导电类型电极1，第二导电类型焊盘11，第一导电类型焊盘10，线条型电极线12，二极管台面结构13，二极管单元14和沟槽15。二极管台面结构包括6排共52个相等大小，均匀分布的正方形二极管单元14，二极管单元14沿X轴方向长度为40微米。二极管台面结构采用正方形排列，二极管单元的连接方式为并联，台面结构的尺寸小于电流注入的扩散长度。二极管单元形状为长方形，按照均匀的对称排列分布。其中第二导电类型电极为n电极，第一导电类型焊盘为p焊盘，第二导电类型焊盘为n焊盘。
在一些优选的实施例中，二极管单元X轴方向长度为100微米；在另一些优选实施例中，二极管单元X轴方向长度10微米；在另一些优选实施例中，二极管X轴方向长度为1微米。
第一导电类型焊盘10与第二导电类型焊盘11在台面结构同一侧，第二导电类型电极1与第二导电类型焊盘11由线条型电极线12连接。
如图3所示，第二导电类型焊盘11和第一导电类型焊盘10形状均为一条边为弧形的不规则多边形，第二导电类型焊盘和第一导电类型焊盘个数均为1，位于台面结构短边边沿。
如图4所示，第二导电类型焊盘11和第一导电类型焊盘10形状均为一条边为弧形的不规则多边形，焊盘形状还可以为半圆形，圆形，矩 形，三角形，不规则直线多边形，或其它一条或多条边为弧形的不规则多边形，并不局限于图4的展示。第二导电类型焊盘和第一导电类型焊盘个数均为1，第二导电类型焊盘位于台面结构短边边沿，第一导电类型焊盘位于台面结构长边边沿。
如图5所示，第二导电类型焊盘11为一条边为弧形的不规则多边形，位于台面结构短边边沿，第一导电类型焊盘10形状为正六边形，位于台面顶点处。第二导电类型焊盘和第一导电类型焊盘个数均为1。
如图6所示，第二导电类型焊盘11形状为第一导电类型焊盘从台面结构短边设置且与台面结构等宽的长方形。第一导电类型焊盘10形状为从台面结构短边设置且与台面结构等宽的长方形。第二导电类型焊盘和第一导电类型焊盘个数均为1。
焊盘厚度为0.001微米～20微米，宽度为：10微米～100微米。电极线的宽度为0.001-20微米，厚度为0.001-10微米，电极线采用氧化铟锡材料，直线布局设计。沟槽15的形状为十字形，横截面形状为长方形，水平方向均匀分布。
如图8所示，二极管台面结构还包括绝缘介质层2，第一导电类型层5，第二导电类型层3，及位于所述第一导电类型层上的量子阱有源区4。
如图10所示，二极管单元14至少有一个侧壁面从台面底部到顶部方向上有沟槽分布。二极管单元侧壁上的沟槽截面形状为三角形，侧壁上的沟槽宽度为0.5纳米-10微米，深度为0.5纳米-10微米。由于二极管芯片的电流扩散长度与电流密度的平方根成反比，因此在大电流的注入下，电流的扩散长度更短，导致芯片的电流扩散更加的不均匀，效率更低，散热更加困难。采用垂直装集成单元发光二极管结构设计，可以灵活的改变二极管台面结构的尺寸、形状，可以获得指定工作电流下最佳的电流扩散和散热性能，并极大的提升芯片的注入电流密度，从而提升单位面积的流明输出。
实施例2
本实施例提供一种垂直集成单元二极管芯片，如图7所示，包括： 第二导电类型电极1，第二导电类型焊盘11，第一导电类型焊盘10，线条型电极线12，二极管台面结构13，二极管单元14和沟槽15。二极管台面结构包括6排共52个等大小均匀分布的正方形二极管单元14，二极管单元14沿X轴方向长度为40微米。二极管台面结构采用正方形排列，二极管单元之间采用并联的连接方式，台面结构的尺寸小于电流注入的扩散长度。二极管单元形状为正长方形，按照均匀的对称排列分布。
在一些优选的实施例中，二极管单元X轴方向长度为10纳米，在另一些优选实施例中，二极管单元X轴方向长度为100纳米。
第一导电类型焊盘10与第二导电类型焊盘11在台面结构同一侧，第二导电类型电极1与第二导电类型焊盘11由线条型电极线12连接。第二导电类型焊盘11和第一导电类型焊盘10形状为一条为弧形的不规则多边形，焊盘形状还可以为半圆形，圆形，矩形，三角形，不规则直线多边形，或其它一条或多条边为弧形的不规则多边形，并不局限于图3的展示。焊盘个数均为1，位于台面结构边沿，焊盘厚度为0.001微米～20微米，宽度为：10微米～100微米。电极线的宽度为0.001-20微米，厚度为0.001-10微米，电极线采用氧化铟锡材料，直线布局设计。沟槽15的形状为十字形，横截面形状为长方形，水平方向均匀分布。
每个二极管单元增设孔结构16，孔结构包括一个孔单元，孔单元为圆形，孔单元直径为0.001微米～20微米。孔单元对称排列，非对称排列，周期性排列，非周期性排列或随机排列。孔单元形状还可以为三角形、正方形、长方形、五边形、六边形、圆形、以及其它任意定义形状，并不局限于图7中展示的形状。
如图8所示，二极管台面结构还包括绝缘介质层2，第一导电类型层5，第二导电类型层3，位于所述第一导电类型层上的量子阱有源区4，反射镜6，保护金属层7，衬底8，背面电极9。其中第一导电类型层为p-GaN层，第二导类型层为n-GaN层，二极管单元的沟槽深度至p-GaN层，二极管单元的沟槽深度还可至n-GaN层或量子阱有源区，并不局限于图8所示。
由于二极管芯片的电流扩散长度与电流密度的平方根成反比，因此 在大电流的注入下，电流的扩散长度更短，导致芯片的电流扩散更加的不均匀，效率更低，散热更加困难。采用垂直装集成单元发光二极管结构设计，可以灵活的改变二极管台面结构的尺寸、形状，可以获得指定工作电流下最佳的电流扩散和散热性能，并极大的提升芯片的注入电流密度，从而提升单位面积的流明输出。
实施例3
本实施例提供一种垂直集成单元二极管芯片，如图9所示，包括：第二导电类型电极1，第二导电类型焊盘11，第一导电类型焊盘10，线条型电极线12，二极管台面结构13，二极管单元14和沟槽15。二极管台面结构包括6排6个大小不一的长方形二极管单元14，二极管单元14沿X轴方向长度为80微米。二极管台面结构采用长方形排列，二极管单元之间采用并联的连接方式，台面结构的尺寸小于电流注入的扩散长度。二极管单元形状为长方形，按照非均匀的对称排列分布。
第一导电类型焊盘10与第二导电类型焊盘11在台面结构同一侧，第二导电类型电极1与第二导电类型焊盘11由线条型电极线12连接。第二导电类型焊盘11和第一导电类型焊盘10形状为矩形，焊盘形状还可以为半圆形，圆形，三角形，不规则直线多边形，或一条或多条边为弧形的不规则多边形，并不局限于图3的展示。焊盘个数均为1，位于台面结构边沿，焊盘厚度为0.001微米～20微米，宽度为：10微米～100微米。电极线的宽度为0.001-20微米，厚度为0.001-10微米，电极线采用氧化铟锡材料，直线布局设计。沟槽15的形状为十字形，横截面形状为长方形，水平方向均匀分布。
如图8所示，二极管台面结构还包括绝缘介质层2，第一导电类型层5，第二导电类型层3，位于所述第一导电类型层上的量子阱有源区4，反射镜6，保护金属层7，衬底8，背面电极9。二极管单元的沟槽深度至p-GaN层，二极管单元的沟槽深度还可至n-GaN层或量子阱有源区，并不局限于图8所示。
本实施例还提供一种垂直集成单元二极管芯片，如图10所示，二极管台面结构包括4排共30个等大小均匀分布的梯形二极管单元，二 极管单元沿X轴方向长度为40微米。台面结构的尺寸小于电流注入的扩散长度。二极管单元形状为梯形，按照均匀的对称排列分布。二极管单元侧壁与水平面夹角角度大于0度且小于等于90度90，二极管单元的侧壁形状为梯形。
由于二极管芯片的电流扩散长度与电流密度的平方根成反比，因此在大电流的注入下，电流的扩散长度更短，导致芯片的电流扩散更加的不均匀，效率更低，散热更加困难。采用垂直装集成单元发光二极管结构设计，可以灵活的改变二极管台面结构的尺寸、形状，可以获得指定工作电流下最佳的电流扩散和散热性能，并极大的提升芯片的注入电流密度，从而提升单位面积的流明输出。
本发明的实施例提供的垂直集成单元发光二极管，具有以下有益效果：
(1)本发明的二极管单元的长度设计控制在电流扩散长度以内，优化的具备一定自由度的几何设计可以更进一步的提升出光效率，可同时解决困扰LED单元二极管芯片设计的第二导电类型电极和p型电极电流扩散不均匀的问题，从而得到更高的光电转换效率/流明效率
(2)本发明的每个二极管单元的微纳结构增加侧壁的出光面积，从而提升光萃取效率。
(3)本发明的集成单元二极管芯片尺寸的优化，带来更大的侧壁散热面积，具备更佳的散热性能，允许超大电流密度的注入而不影响其稳定性，极大的提高单位面积单元二极管芯片的流明输出，降低流明成本。
(4)本发明的集成单元二极管芯片的设计，可以实现超均匀的电流注入，因此而获得更高的效率、更好的波长均匀性、发光谱更窄的半高宽、更好的散热均匀性和更好的器件稳定性。
(5)本发明的集成单元二极管的设计中，第一导电类型焊盘与第二导电类型焊盘在同一侧，有利于简化后段的封装工艺，获得更高的性价比产品。
(6)本发明的集成单元二极管芯片适于UVC、UVA、UVB、紫光、 蓝光、绿光、黄光、红光、红外光等各色系的LED产品，可用于LED照明，背光，显示，植物照明，医疗和其它半导体发光器件应用领域。
以上所述的具体实施例，对本发明的目的，技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例，并不用于限定本发明的保护范围，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (20)

  1. 一种垂直集成单元二极管芯片，其中，包括第一导电类型电极、第二导电类型电极及位于所述第一导电类型电极上的二极管台面结构，所述二极管台面结构还包括第一导电类型焊盘和第二导电类型焊盘，其中所述第一导电类型焊盘与第二导电类型焊盘在所述二极管台面结构的同一侧，所述第一导电类型电极与所述第一导电类型焊盘连接，所述第二导电类型电极与所述第二导电类型焊盘连接；
    其中，第二导电类型电极为n电极，第一导电类型焊盘为p焊盘，第二导电类型焊盘为n焊盘；
    所述第一导电类型焊盘和所述第二导电类型焊盘的厚度为0.001微米～20微米，宽度为10微米～100微米。
  2. 根据权利要求1所述的垂直集成单元二极管芯片，其中，
    所述第一导电类型焊盘和所述第二导电类型焊盘位于所述二极管台面结构任意边沿、台面顶点、台面中间或台面其它任意位置。
  3. 根据权利要求2所述的垂直集成单元二极管芯片，其中，所述第一导电类型焊盘和第二导电类型焊盘分别位于所述二极管台面结构彼此相对的短边边沿，或者所述第二导电类型焊盘位于所述二极管台面结构的短边边沿，所述第一导电类型焊盘位于所述二极管台面结构的长边边沿，或者所述第二导电类型焊盘位于所述台面结构的短边边沿，所述第一导电类型焊位于所述二极管台面的顶点处。
  4. 根据权利要求2所述的垂直集成单元二极管芯片，其中，所述第一导电类型焊盘和第二导电类型焊盘的形状分别为沿所述二极管台面结构的短边设置且与所述二极管台面结构等宽的长方形、方形、或圆形或其他形状。
  5. 根据权利要求1所述的垂直集成单元二极管芯片，其中，所述第二导电类型电极与所述第二导电类型焊盘由线条型电极线连接，且所述二极管台面结构包括n个二极管单元，所述n个二极管单元呈几何形状排列，其中，n≥2；所述第二导电类型电极延伸到所述二极管单元上。
  6. 根据权利要求5所述的垂直集成单元二极管芯片，其中，所述二极管台面结构包括依次层叠设置的第一导电类型层、量子阱有源区以及第二导电类型层，所述第二导电类型层与及第二导电类型电极欧姆接触。
  7. 根据权利要求6所述的垂直集成单元二极管芯片，其中，所述二极管台面结构包括设置于所述第一导电类型层远离所述量子阱有源区一侧的保护金属层，所述第一导电类型焊盘设置于所述保护金属层上。
  8. 根据权利要求5所述的垂直集成单元二极管芯片，其中，所述二极管单元至少有一个侧壁面从台面底部到顶部方向上设有沟槽，所述二极管单元的侧壁上的沟槽宽度为0.5纳米-10微米，深度为0.5纳米-10微米。
  9. 一种垂直集成单元二极管芯片，其中，包括第一导电类型电极、第二导电类型电极及位于所述第一导电类型电极上的二极管台面结构，所述二极管台面结构还包括第一导电类型焊盘和第二导电类型焊盘，其中所述第一导电类型焊盘与第二导电类型焊盘在所述二极管台面结构的同一侧，所述第一导电类型电极与所述第一导电类型焊盘连接，所述第二导电类型电极与所述第二导电类型焊盘连接。
  10. 根据权利要求9所述的垂直集成单元二极管芯片，其中，所述第一导电类型焊盘和所述第二导电类型焊盘位于所述二极管台面结构任意边沿、台面顶点、台面中间或台面其它任意位置。
  11. 根据权利要求10所述的垂直集成单元二极管芯片，其中，所述第一导电类型焊盘和第二导电类型焊盘分别位于所述二极管台面结构彼此相对的短边边沿，或者所述第二导电类型焊盘位于所述二极管台面结构的短边边沿，所述第一导电类型焊盘位于所述二极管台面结构的长边边沿，或者所述第二导电类型焊盘位于所述台面结构的短边边沿，所述第一导电类型焊位于所述二极管台面的顶点处。
  12. 根据权利要求10所述的垂直集成单元二极管芯片，其中，所述第一导电类型焊盘和第二导电类型焊盘的形状分别为沿所述二极管台面结构的短边设置且与所述二极管台面结构等宽的长方形、方形、或圆形或其他形状。
  13. 根据权利要求12所述的垂直集成单元二极管芯片，其中，所述第一导电类型焊盘和所述第二导电类型焊盘的厚度为0.001微米～20微米，宽度为10微米～100微米。
  14. 根据权利要求9所述的垂直集成单元二极管芯片，其中，所述第二导电类型电极与所述第二导电类型焊盘由线条型电极线连接，且所述二极管台面结构包括n个二极管单元，所述n个二极管单元呈几何形状排列，其中，n≥2；所述第二导电类型电极延伸到所述二极管单元上。
  15. 根据权利要求14所述的垂直集成单元二极管芯片，其中，所述二极管台面结构包括依次层叠设置的第一导电类型层、量子阱有源区以及第二导电类型层，所述第二导电类型层与及第二导电类型电极欧姆接触。
  16. 根据权利要求15所述的垂直集成单元二极管芯片，其中，所述二极管台面结构包括设置于所述第一导电类型层远离所述量子阱有源区一侧的保护金属层，所述第一导电类型焊盘设置于所述保护金属层上。
  17. 根据权利要求15所述的垂直集成单元二极管芯片，其中，所述第一导电类型焊盘为p焊盘，所述第二导电类型焊盘为n焊盘。
  18. 根据权利要求14所述的垂直集成单元二极管芯片，其中，所述二极管单元至少有一个侧壁面从台面底部到顶部方向上设有沟槽，所述二极管单元的侧壁上的沟槽宽度为0.5纳米-10微米，深度为0.5纳米-10微米。
  19. 一种垂直集成单元二极管芯片，其中，包括第一导电类型电极、第二导电类型电极及位于所述第一导电类型电极上的二极管台面结构，所述二极管台面结构还包括第一导电类型焊盘和第二导电类型焊盘，其中所述第一导电类型焊盘与第二导电类型焊盘在所述二极管台面结构的同一侧，所述第一导电类型电极与所述第一导电类型焊盘连接，所述第二导电类型电极与所述第二导电类型焊盘连接；
    所述第一导电类型焊盘和所述第二导电类型焊盘的厚度为0.001微米～20微米，宽度为10微米～100微米；
    所述第二导电类型电极与所述第二导电类型焊盘由线条型电极线 连接，所述线条型电极线的宽度为0.001微米～20微米，厚度为0.001微米～10微米。
  20. 根据权利要求19所述的垂直集成单元二极管芯片，其中，所述线条型电极线采用线条形金属和/或氧化铟锡材料。
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