WO2020215183A1 - Procédés de gravure d'une couche de matériau pour applications semi-conductrices - Google Patents

Procédés de gravure d'une couche de matériau pour applications semi-conductrices Download PDF

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Publication number
WO2020215183A1
WO2020215183A1 PCT/CN2019/083716 CN2019083716W WO2020215183A1 WO 2020215183 A1 WO2020215183 A1 WO 2020215183A1 CN 2019083716 W CN2019083716 W CN 2019083716W WO 2020215183 A1 WO2020215183 A1 WO 2020215183A1
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WIPO (PCT)
Prior art keywords
material layer
etching
open feature
liner
bias power
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PCT/CN2019/083716
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English (en)
Inventor
Jiao YANG
Jon C. Farr
Zhigang Wang
Alfredo GRANADOS
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Applied Materials, Inc.
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Priority to PCT/CN2019/083716 priority Critical patent/WO2020215183A1/fr
Publication of WO2020215183A1 publication Critical patent/WO2020215183A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67109—Apparatus for thermal treatment mainly by convection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/6719—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the processing chambers, e.g. modular processing chambers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67248—Temperature monitoring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68757—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a coating or a hardness or a material

Definitions

  • Embodiments of the present disclosure generally relate to methods for etching a material layer, and more particularly to methods etching a material layer in a substrate using a cyclic etching and deposition process in the semiconductor applications.
  • VLSI very large scale integration
  • ULSI ultra large-scale integration
  • a patterned mask such as a photoresist layer, is commonly used in forming structures, such as gate structure, shallow trench isolation (STI) , bite lines and the like, on a substrate by etching process.
  • the patterned mask is conventionally fabricated by using a lithographic process to optically transfer a pattern having the desired critical dimensions to a layer of photoresist.
  • the photoresist layer is then developed to remove undesired portion of the photoresist, thus creating openings in the remaining photoresist.
  • three dimensional (3D) stacking of semiconductor chips is often utilized to improve performance of the transistors.
  • transistors By arranging transistors in three dimensions instead of conventional two dimensions, multiple transistors may be placed in the integrated circuits (ICs) very close to each other.
  • Three dimensional (3D) stacking of semiconductor chips reduces wire lengths and keeps wiring delay low.
  • designs of the three dimensional (3D) stacking of semiconductor chips often further pushes the geometry limits of the structures against technology limits, the need for accurate process control for the manufacture of small critical dimensional structures with high aspect ratio has become increasingly important. Poor process control during etching process will result in irregular structure profiles and line edge roughness, thus resulting poor line integrity of the formed structures.
  • irregular profiles and growth of the etching by-products formed during etching may gradually block the small openings used to fabricate the small critical dimension structures, thereby resulting in bowed, distorted, toppled, or twisted profiles of the etched structures.
  • a method for etching a material layer on a substrate includes (a) etching at least a portion of a material layer on a substrate in an etch chamber to form an open feature having a bottom surface and sidewalls in the material layer, (b) forming a liner layer on the sidewalls and the bottom surface of the open feature, (c) selectively removing the liner layer formed on the bottom surface of the open feature, and (d) continuingly etching the material layer from the bottom surface of the open feature until a desired depth of the open feature is reached.
  • a method for etching a material layer on a substrate includes (a) supplying a first etching gas mixture to etch a portion of a material layer on a substrate disposed in a processing chamber to form an open feature in the material layer, (b) supplying a liner deposition gas mixture to form a liner layer on the sidewalls and the bottom surface of the open feature, wherein the liner deposition gas mixture comprises a silicon containing gas and a oxygen containing gas, (c) supplying a second etching mixture to selectively remove the liner layer formed on the bottom surface of the open feature, and (d) supplying a third gas mixture to continue etching the material layer from the bottom surface of the open feature until a desired depth of the open feature is reached.
  • a method for etching a material layer on a substrate includes (a) applying a first RF bias power to etching at least a portion of a material layer on the substrate in the etch chamber to form an open feature having a bottom surface and sidewalls in the material layer, (b) applying a second RF bias power to form a liner layer on the sidewalls and the bottom surface of the open feature, wherein the second RF bias power is greater than the first RF bias power, (c) applying a third RF bias power to selectively remove the liner layer formed on the bottom surface of the open feature, wherein the third RF bias power is greater than the second RF bias power, and (d) continuingly etching the material layer from the bottom surface of the open feature until a desired depth of the open feature is reached.
  • Figure 1 depicts an apparatus utilized to performing an etching process in accordance with one embodiment of the disclosure
  • Figure 2 depicts a flow diagram of a method for performing an etching process using a cyclic etching process in accordance with one embodiment of the disclosure.
  • Figure 3A-3F depict one embodiment of a sequence for etching a material layer formed on the method of Figure 2 in accordance with one embodiment of the disclosure.
  • the present disclosure provides methods for etching a material layer for high aspect ratio features formed on or in a substrate for semiconductor devices.
  • the etching process may use a cyclic etching and deposition process to etch the substrate while forming a liner layer as needed. Multiple cycles of the etching and deposition processes may be utilized to control etching profile and feature transfer to a substrate or a material layer disposed on a substrate.
  • Figure 1 is a sectional view of one embodiment of a processing chamber 100 suitable for performing an etching process to etch a material layer on a substrate using cyclic etching and deposition processes.
  • Suitable processing chambers that may be adapted for use with the teachings disclosed herein include, for example, a modified processing chamber available from Applied Materials, Inc. of Santa Clara, California.
  • the processing chamber 100 is shown including a plurality of features that enable superior etching and deposition performance, it is contemplated that other processing chambers may be adapted to benefit from one or more of the features disclosed herein.
  • the processing chamber 100 includes a chamber body 102 and a lid 104 which enclose an interior volume 106.
  • the chamber body 102 is fabricated from aluminum, stainless steel or other suitable material.
  • the chamber body 102 generally includes sidewalls 108 and a bottom 110.
  • a substrate support pedestal access port (not shown) is generally defined in a sidewall 108 and a selectively sealed by a slit valve to facilitate entry and egress of a substrate 101 from the processing chamber 100.
  • An exhaust port 126 is defined in the chamber body 102 and couples the interior volume 106 to a pump system 128.
  • the pump system 128 generally includes one or more pumps and throttle valves utilized to evacuate and regulate the pressure of the interior volume 106 of the processing chamber 100. In one embodiment, the pump system 128 maintains the pressure inside the interior volume 106 at operating pressures typically between about 10 mTorr to about 500 Torr.
  • the lid 104 is sealingly supported on the sidewall 108 of the chamber body 102.
  • the lid 104 may be opened to allow excess to the interior volume 106 of the processing chamber 100.
  • the lid 104 includes a window 142 that facilitates optical process monitoring.
  • the window 142 is comprised of quartz or other suitable material that is transmissive to a signal utilized by an optical monitoring system 140 mounted outside the processing chamber 100.
  • the optical monitoring system 140 is positioned to view at least one of the interior volume 106 of the chamber body 102 and/or the substrate 101 positioned on a substrate support pedestal assembly 148 through the window 142.
  • the optical monitoring system 140 is coupled to the lid 104 and facilitates an integrated deposition process that uses optical metrology to provide information that enables process adjustment to compensate for incoming substrate pattern feature inconsistencies (such as thickness, and the like) , provide process state monitoring (such as plasma monitoring, temperature monitoring, and the like) as needed.
  • One optical monitoring system that may be adapted to benefit from the disclosure is the full-spectrum, interferometric metrology module, available from Applied Materials, Inc., of Santa Clara, California.
  • a gas panel 158 is coupled to the processing chamber 100 to provide process and/or cleaning gases to the interior volume 106.
  • inlet ports 132’, 132” are provided in the lid 104 to allow gases to be delivered from the gas panel 158 to the interior volume 106 of the processing chamber 100.
  • the gas panel 158 is adapted to provide fluorinated process gas through the inlet ports 132’, 132” and into the interior volume 106 of the processing chamber 100.
  • the process gas provided from the gas panel 158 includes at least a fluorinated gas, chlorine, and a carbon containing gas, an oxygen gas, a nitrogen containing gas and a chlorine containing gas.
  • fluorinated and carbon containing gases examples include CHF 3 , CH 2 F 2 and CF 4 .
  • Other fluorinated gases may include one or more of C 2 F, C 4 F 6 , C 3 F 8 and C 5 F 8 .
  • the oxygen containing gas examples include O 2 , CO 2 , CO, N 2 O, NO 2 , O 3 , H 2 O, and the like.
  • the nitrogen containing gas examples include N 2 , NH 3 , N 2 O, NO 2 and the like.
  • the chlorine containing gas examples include HCl, Cl 2 , CCl 4 , CHCl 3 , CH 2 Cl 2 , CH 3 Cl, and the like.
  • Suitable examples of the carbon containing gas include methane (CH 4 ) , ethane (C 2 H 6 ) , ethylene (C 2 H 4 ) , and the like.
  • a showerhead assembly 130 is coupled to an interior surface 114 of the lid 104.
  • the showerhead assembly 130 includes a plurality of apertures that allow the gases flowing through the showerhead assembly 130 from the inlet ports 132’, 132” into the interior volume 106 of the processing chamber 100 in a predefined distribution across the surface of the substrate 101 being processed in the processing chamber 100.
  • a remote plasma source 177 may be optionally coupled to the gas panel 158 to facilitate dissociating gas mixture from a remote plasma prior to entering into the interior volume 106 for processing.
  • a RF source power 143 is coupled through a matching network 141 to the showerhead assembly 130.
  • the RF source power 143 typically is capable of producing up to about 3000 W at a tunable frequency in a range from about 50 kHz to about 200 MHz.
  • the showerhead assembly 130 additionally includes a region transmissive to an optical metrology signal.
  • the optically transmissive region or passage 138 is suitable for allowing the optical monitoring system 140 to view the interior volume 106 and/or the substrate 101 positioned on the substrate support pedestal assembly 148.
  • the passage 138 may be a material, an aperture or plurality of apertures formed or disposed in the showerhead assembly 130 that is substantially transmissive to the wavelengths of energy generated by, and reflected back to, the optical monitoring system 140.
  • the passage 138 includes a window 142 to prevent gas leakage through the passage 138.
  • the window 142 may be a sapphire plate, quartz plate or other suitable material.
  • the window 142 may alternatively be disposed in the lid 104.
  • the showerhead assembly 130 is configured with a plurality of zones that allow for separate control of gas flowing into the interior volume 106 of the processing chamber 100.
  • the showerhead assembly 130 as an inner zone 134 and an outer zone 136 that are separately coupled to the gas panel 158 through separate inlet ports 132’, 132” .
  • the substrate support pedestal assembly 148 is disposed in the interior volume 106 of the processing chamber 100 below the gas distribution (showerhead) assembly 130.
  • the substrate support pedestal assembly 148 holds the substrate 101 during processing.
  • the substrate support pedestal assembly 148 generally includes a plurality of lift pins (not shown) disposed therethrough that are configured to lift the substrate 101 from the substrate support pedestal assembly 148 and facilitate exchange of the substrate 101 with a robot (not shown) in a conventional manner.
  • An inner liner 118 may closely circumscribe the periphery of the substrate support pedestal assembly 148.
  • the substrate support pedestal assembly 148 includes a mounting plate 162, a base 164 and an electrostatic chuck 166.
  • the mounting plate 162 is coupled to the bottom 110 of the chamber body 102 includes passages for routing utilities, such as fluids, power lines and sensor leads, among others, to the base 164 and the electrostatic chuck 166.
  • the electrostatic chuck 166 comprises at least one clamping electrode 180 for retaining the substrate 101 below showerhead assembly 130.
  • the electrostatic chuck 166 is driven by a chucking power source 182 to develop an electrostatic force that holds the substrate 101 to the chuck surface, as is conventionally known.
  • the substrate 101 may be retained to the substrate support pedestal assembly 148 by clamping, vacuum or gravity.
  • At least one of the base 164 or electrostatic chuck 166 may include at least one optional embedded heater 176, at least one optional embedded isolator 174 and a plurality of conduits 168, 170 to control the lateral temperature profile of the substrate support pedestal assembly 148.
  • the conduits 168, 170 are fluidly coupled to a fluid source 172 that circulates a temperature regulating fluid therethrough.
  • the heater 176 is regulated by a power source 178.
  • the conduits 168, 170 and heater 176 are utilized to control the temperature of the base 164, thereby heating and/or cooling the electrostatic chuck 166 and ultimately, the temperature profile of the substrate 101 disposed thereon.
  • the temperature of the electrostatic chuck 166 and the base 164 may be monitored using a plurality of temperature sensors 190, 192.
  • the electrostatic chuck 166 may further comprise a plurality of gas passages (not shown) , such as grooves, that are formed in a substrate support pedestal supporting surface of the chuck 166 and fluidly coupled to a source of a heat transfer (or backside) gas, such as He.
  • a heat transfer (or backside) gas such as He.
  • the backside gas is provided at controlled pressure into the gas passages to enhance the heat transfer between the electrostatic chuck 166 and the substrate 101.
  • the substrate support pedestal assembly 148 is configured as a cathode and includes an electrode 180 that is coupled to a plurality of RF power bias sources 184, 186.
  • the RF bias power sources 184, 186 are coupled between the electrode 180 disposed in the substrate support pedestal assembly 148 and another electrode, such as the showerhead assembly 130 or ceiling (lid 104) of the chamber body 102.
  • the RF bias power excites and sustains a plasma discharge formed from the gases disposed in the processing region of the chamber body 102.
  • the dual RF bias power sources 184, 186 are coupled to the electrode 180 disposed in the substrate support pedestal assembly 148 through a matching circuit 188.
  • the signal generated by the RF bias power 184, 186 is delivered through matching circuit 188 to the substrate support pedestal assembly 148 through a single feed to ionize the gas mixture provided in the plasma processing chamber 100, thereby providing ion energy necessary for performing a deposition or other plasma enhanced process.
  • the RF bias power sources 184, 186 are generally capable of producing an RF signal having a frequency of from about 50 kHz to about 200 MHz and a power between about 0 Watts and about 5000 Watts.
  • An additional bias power source 189 may be coupled to the electrode 180 to control the characteristics of the plasma.
  • the substrate 101 is disposed on the substrate support pedestal assembly 148 in the plasma processing chamber 100.
  • a process gas and/or gas mixture is introduced into the chamber body 102 through the showerhead assembly 130 from the gas panel 158.
  • a vacuum pump system 128 maintains the pressure inside the chamber body 102 while removing deposition by-products.
  • a controller 150 is coupled to the processing chamber 100 to control operation of the processing chamber 100.
  • the controller 150 includes a central processing unit (CPU) 152, a memory 154, and a support circuit 156 utilized to control the process sequence and regulate the gas flows from the gas panel 158.
  • the CPU 152 may be any form of general purpose computer processor that may be used in an industrial setting.
  • the software routines can be stored in the memory 154, such as random access memory, read only memory, floppy, or hard disk drive, or other form of digital storage.
  • the support circuit 156 is conventionally coupled to the CPU 152 and may include cache, clock circuits, input/output systems, power supplies, and the like. Bi-directional communications between the controller 150 and the various components of the processing system 100 are handled through numerous signal cables.
  • Figure 2 is a flow diagram of one embodiment of an etch process 200 that may be practiced in the chamber 100 or other suitable processing chamber.
  • Figures 3A-3F are schematic cross-sectional views of a portion of a composite substrate 101 corresponding to various stages of the process 200.
  • the process 200 may be utilized to form high aspect ratio features, e.g., greater than 10: 1, such as greater than 20: 1, for structures, for semiconductor devices.
  • the process 200 may be beneficially utilized to etch other types of structures as needed.
  • the process 200 begins at operation 202 by transferring (i.e., providing) a substrate, such as the substrate 101, to an etch process chamber, such as the etch chamber 100 depicted in Figure 1.
  • the substrate 101 may have a substantially planar surface, an uneven surface, or a substantially planar surface having a structure formed thereon.
  • the substrate 101 has a patterned mask layer 304 disposed on a material layer 302.
  • the material layer 302 may be utilized to form a gate structure, a shallow trench isolation (STI) structure, a contact structure or an interconnection structure in the front end or back end processes.
  • the method 200 may be performed on the material layer 302 to form features and/or trenches therein.
  • the material layer 302 may be part of the substrate 101 so that the etching process as performed forms the trenches/features into the substrate 101 as needed.
  • the substrate 101 may be a material such as crystalline silicon (e.g., Si ⁇ 100> or Si ⁇ 111>) , silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or non-patterned wafers silicon on insulator (SOI) , carbon doped silicon oxides, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire.
  • crystalline silicon e.g., Si ⁇ 100> or Si ⁇ 111>
  • SOI silicon on insulator
  • the substrate 102 may have various dimensions, such as 200 mm, 300 mm, 450 mm or other diameter wafers, as well as, rectangular or square panels. Unless otherwise noted, embodiments and examples described herein are conducted on substrates with a 200 mm diameter, a 300 mm diameter, or a 450 mm diameter substrate.
  • the substrate 101 may include a buried dielectric layer disposed on a silicon crystalline substrate. In the embodiment depicted herein, the substrate 101 may be a crystalline silicon substrate.
  • the material layer 302 is a silicon containing material layer.
  • the patterned mask layer 304 has an open feature 306 that exposes portions 308 of the material layer 302 for etching.
  • the mask layer 304 may be a hard mask, a photoresist mask or a combination thereof.
  • the open feature 306 in the mask layer 304 is used as an etch mask to form open features 360 in the material layer 302 with desired aspect ratios.
  • the open features 360 described herein may include trenches, vias, openings and the like.
  • the mask layer 304 may be a material selected from a group consisting of silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, amorphous carbon, and combinations thereof.
  • the mask layer 304 is a silicon oxide layer.
  • the mask layer 304 may be a patterned photoresist layer, such as a lithographically patterned mask or fabricated by other materials.
  • the photoresist layer may is a positive tone photoresist, a negative tone photoresist, a UV lithography photoresist, an i-line photoresist, an e-beam resist (for example, a chemically amplified resist (CAR) ) or other suitable photoresist.
  • the mask layer 304 may be a combination of a photoresist layer disposed on a hardmask layer.
  • the material layer 302 may be a silicon containing material.
  • the material layer 302 may include multiple layers, composite layers, or a single layer. Suitable materials for the silicon containing material include undoped crystalline silicon, amorphous silicon, polycrystalline silicon, microcrystalline silicon, doped crystalline silicon material, and combinations thereof.
  • the material layer 302 may also be a composite layer including silicon oxide/silicon nitride and polysilicon. In an exemplary embodiment depicted herein, the material layer 302 is a silicon material. In some embodiment, the material layer 302 may be part of the substrate 101 as needed.
  • a first etching gas mixture is supplied to etch the material layer 302 to a predetermined depth 310 to expose a portion 312 of the material layer 302, as shown in Figure 3B.
  • the material layer 302 may be etched by supplying the first etching gas mixture into the processing chamber along with a RF source and bias power applied to the processing chamber.
  • the first etching gas mixture supplied at operation 204 etches the material layer 302 to a relatively deeper depth, as compared to other etching operations at the method 200.
  • the first etching gas mixture includes any gas suitable for etching a silicon containing material.
  • the first etching gas mixture may include, but not limited to, an oxygen containing gas along with a halogen containing gas, such as HBr, chlorine gas (Cl 2 ) , nitrogen trifluoride (NF 3 ) , sulfur hexafluoride gas (SF 6 ) , carbon and fluorine containing gas, such as CF 4 , CHF 3 , C 4 F 8 and the like.
  • a halogen containing gas such as HBr, chlorine gas (Cl 2 ) , nitrogen trifluoride (NF 3 ) , sulfur hexafluoride gas (SF 6 ) , carbon and fluorine containing gas, such as CF 4 , CHF 3 , C 4 F 8 and the like.
  • Suitable examples of the oxygen containing gas include O 2 , N 2 O, NO 2 , NO, H 2 O, O 3 and the like.
  • etching gas mixture supplied into the etch chamber.
  • the chamber pressure in the presence of the first etching gas mixture is regulated.
  • a process pressure in the etch chamber is regulated between about 2 mTorr to about 200 mTorr, for example, between about 40 mTorr and about 100 mTorr.
  • RF source and bias power may be applied to maintain a plasma formed from the first etching gas mixture.
  • a RF source power of between about 100 Watts to about 1500 Watts may be applied to an inductively coupled antenna source to maintain a plasma inside the etch chamber.
  • a RF bias power of about less than 100 Watts are applied while supplying the first etching gas mixture.
  • the first etching gas mixture may be flowed into the chamber at a rate between about 50 sccm to about 1000 sccm.
  • a substrate temperature is maintained between about -20 degrees Celsius to about 80 degrees Celsius.
  • the first etching gas mixture is continuously supplied until the predetermined depth 310 is reached, forming the open features 360 (e.g., an opening, a trench, a via, or an aperture) with an aspect ratio greater than 10: 1, such as between about 15: 1 and about 20: 1.
  • the predetermined depth 310 is about 15000 nm and about 25000 nm.
  • the predetermined depth 310 may be between about 30 %and about 60 %, such as between about 40 %and about 50 %, of the total depth 324 (as shown in Figure 3F) to be etched away from the material layer 302.
  • a liner deposition gas mixture is then supplied.
  • the first etching gas mixture is then terminated and switched to the liner deposition gas mixture.
  • the liner deposition gas mixture assists depositing a liner layer 314 on the material layer 302, covering the sidewalls 313 and the bottom surface 312 of the open feature 360 as well as the top surface 315 of the mask layer 304, as shown in Figure 3C.
  • the liner deposition gas mixture includes at least an oxygen containing gas and a silicon containing gas. The oxygen elements from the oxygen containing gas reacts with the silicon elements from the silicon containing gas, forming a silicon oxide layer as the liner layer 314 at the exposed surfaces of the material layer 302 across the substrate 101.
  • the oxygen elements from the oxygen containing gas may also react with the portions of the exposed material layer 302 exposed by the open feature 360, e.g., a polysilicon layer, to form the liner layer 314, such as SiO 2 .
  • the liner layer 314 formed thereon serves as a passivation layer to protect the underlying material layer 302 from being attacked while removing the remaining portion of the material layer 302 from the substrate 101.
  • Suitable examples of the oxygen containing gas include O 2 , N 2 O, NO, CO, CO 2 , and the like.
  • Suitable examples of the silicon containing gas include SiF 4 and Si2F 6 .
  • the liner gas mixture includes SiF 4 and O 2 .
  • Inert gas, such as He and Ar, may also be supplied in the liner gas mixture as needed.
  • the oxygen containing gas may be flowed at a rate between about 50 sccm to about 2000 sccm and the silicon containing gas is supplied at between about 20 sccm and about 2000 sccm.
  • the oxygen containing gas and the silicon containing gas is supplied at a predetermined ratio between about 1: 0.5 and about 2: 1.
  • the liner layer has a thickness between about 50 nm and about 500 nm.
  • a pressure of the oxygen-containing gas in the etch chamber is regulated between about 2 mTorr to about 150 mTorr, for example, between about 40 mTorr to about 100 mTorr.
  • a RF source power may be applied to maintain a plasma.
  • a RF source power of about 200 Watts to about 1500 Watts may be applied to an inductively coupled antenna source to maintain a plasma inside the etch chamber.
  • a RF bias power is supplied at greater than 100 Watts, such as greater than 150 Watts.
  • the RF bias power as supplied to form the liner layer 314 at operation 206 is greater than the RF bias power as supplied to etch the material layer 302 at operation 204.
  • the RF bias power when supplying the liner gas mixture is between about 50 %and about 300 %greater than the RF bias power supplied while etching the material layer 302 at operation 204.
  • the liner layer 314 as formed may be utilized as a protective/passivation layer during the subsequent etching process so as to protect certain locations of the film layers, such as the sidewalls 313 of the open features 360, thus improving and enhancing the interface protection during the etching process, thus allowing the active etching species from the following operations to travel down to the bottom surface 312 of the open feature 360 for further etching without undesired attack on the sidewalls 313 of the material layer 302.
  • a bottom liner breakthrough process is performed to remove the liner layer 314 on the bottom surface 312 of the open feature 360, as shown in Figure 3D.
  • the liner breakthrough process provides reactive species that can reach down to the bottom surface of the liner layer 314 until the liner layer 314 on the bottom surface 312 of the open feature 360 is substantially removed.
  • the liner layer 314 located on the sidewalls 313 of the open feature 360 is substantially maintained intact.
  • the liner layer 314 maintained on the sidewalls 313 may assist protecting the sidewall integrity of the open feature 360 while increasing the aspect ratio of the open feature 360 formed in the material layer 302 during the subsequent etching process.
  • this bottom liner breakthrough process may also be interpreted as a liner bottom surface opening process performed to etch the bottom surface of the liner layer 314, exposing the fresh underlying material layer 302 ready to be etched so as to keep forming the open feature 360 until a desired depth is reached with the desired aspect ratio.
  • the bottom liner breakthrough process is performed by supplying a liner etching gas mixture including at least one of a halogen containing gas and optionally an inert gas is supplied into the processing chamber.
  • the halogen containing gas and/or an inert gas may gently remove the liner layer 314 from the bottom surface 312.
  • the halogen containing gas includes a carbon-fluorine containing gas, such as carbon tetrafluoride (CF 4 ) , C 2 F 4 , C 4 F 8 , C 4 F 6 , CHF 3 , CH 2 F 2 and CH 3 F.
  • the inert gas may be He, Ar, and the like.
  • the liner etching gas mixture includes a carbon tetrafluoride (CF 4 ) , gas and a Ar gas.
  • Several process parameters may also be controlled while supplying the liner etching gas mixture to remove the liner layer 314 from the bottom surface 312.
  • the pressure of the processing chamber may be controlled at between about 20 milliTorr and about 200 milliTorr, such as between about 40 milliTorr and about 100 milliTorr.
  • a substrate temperature is maintained between about -20 degrees Celsius to about 100 degrees Celsius.
  • a RF source power may be applied to maintain a plasma.
  • a RF source power of about 200 Watts to about 1500 Watts may be applied to an inductively coupled antenna source to maintain a plasma inside the etch chamber.
  • a RF bias power is supplied at greater than 150 Watts.
  • the RF bias power as supplied to perform the bottom liner breakthrough process at operation 208 is greater than the RF bias power as supplied to form the liner layer 314 at operation 206 and etch the material layer 302 at operation 204.
  • the RF bias power when supplying the liner etching gas mixture is between about 100 %and about 300 %greater than the RF bias power supplied while forming the liner layer 314 at operation 206 and etching the material layer 302 at operation 204.
  • the greater power level as applied for the RF bias power may increase the directionality of the reactive species from the liner etching gas mixture and assist pulling and accelerating the reactive species toward the bottom surface 312.
  • the reactive species can reach to the bottom to remove the liner layer 314 from the bottom surface 312 without substantially attacking and damaging the liner layer 314 formed on the sidewalls 313.
  • a second etching gas mixture is supplied to continue etching the material layer 302 to a second depth 320, as shown in Figure 3E.
  • the second etching gas mixture may be similar to or the same as the first etching gas mixture at operation 204 to continue etching the material layer 302 while with the sidewall protection from the liner layer 314.
  • the second etching gas mixture may be continuously supplied until the liner layer 314 is consumed and needed to be replenished.
  • the second etching gas mixture may be any suitable gas used for etching a silicon layer.
  • the second etching gas mixture may be selected from a group consisting of gas, such as Cl 2 , HCl, HBr, CF 4 , CHF 3 , NF 3 and SF 6 among others.
  • the second etching gas mixture is the same as the first etching gas mixture including an oxygen containing gas and a halogen containing gas, such as O 2 and HBr.
  • the process parameters regulated while supplying the second etching gas mixture may be similar to or the same as the process parameters regulated while supplying the first etching gas mixture at operation 204.
  • a process pressure in the etch chamber is regulated between about 2 mTorr to about 100 mTorr.
  • RF source power may be applied to maintain a plasma formed from the second etching gas mixture to etch the material layer 302 on the substrate 101.
  • a RF source power of about 150 Watts to about 1500 Watts may be applied to an inductively coupled antenna source to maintain a plasma inside the etch chamber.
  • a RF bias power may be maintained less than 100 Watts to gently etch the material layer 102.
  • the second etching gas mixture may be flowed at a rate between about 50 sccm to about 1000 sccm.
  • a substrate temperature is maintained within a temperature range of about -20 degrees Celsius to about 100 degrees Celsius.
  • the second etching gas mixture may be continuously supplied until a predetermined process time period is reached or until the liner layer 314 is consumed and needed to be replenished.
  • the process may be looped back to operation 206 so that the operation 206 to operation 210 may be repeatedly performed until a desired total/final depth 324 is reached, as shown in Figure 3F.
  • the operation 206 to 210 may be repeatedly (i.e., cyclically) performed, as indicated by the loop 212 in Figure 2, until a desired target depth 324 of the feature 364 is formed in the material layer 302, as shown in Figure 3F.
  • Each cycle of the operation 206 to operation 210 may etch away a depth of between 7000 nm and about 10000 nm of the material layer 302.
  • the desired target depth 324 may be between about 30000 nm and about 45000 nm with an aspect ratio greater than 20: 1, such as between about 30: 1 and about 45: 1.
  • the repeated processes may cyclically and incrementally etch the material layer 302 without over aggressively attacking the material layer 302 while with proper sidewall protection from the liner layer 314.
  • the open feature 364 may have a width 364 less than 1000 nm.
  • the operation 204 to 210 may be repeatedly performed for any times as needed, such as between about 3 times and about 10 times as needed.
  • a cyclic deposition and etching process provides sufficient sidewall deposition/protection during the etching process. By doing so, an improved etching process to obtain features with high aspect ratio and small dimension is obtained.

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Abstract

Des modes de réalisation de la présente invention concernent un appareil et des procédés de gravure d'une couche de matériau au moyen d'un processus de gravure et de dépôt cyclique. Dans un mode de réalisation, un procédé de gravure d'une couche de matériau sur un substrat consiste (a) à graver au moins une partie d'une couche de matériau sur un substrat dans une chambre de gravure pour former un élément ouvert ayant une surface inférieure et des parois latérales dans la couche de matériau, (b) à former une couche de doublure sur les parois latérales et la surface inférieure de l'élément ouvert, (c) à retirer sélectivement la couche de doublure formée sur la surface inférieure de l'élément ouvert, et (d) à graver en continu la couche de matériau à partir de la surface inférieure de l'élément ouvert jusqu'à ce qu'une profondeur souhaitée de l'élément ouvert soit atteinte.
PCT/CN2019/083716 2019-04-22 2019-04-22 Procédés de gravure d'une couche de matériau pour applications semi-conductrices WO2020215183A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11915940B2 (en) 2020-08-18 2024-02-27 Applied Materials, Inc. Method of depositing a pre-etch protective layer

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7977768B2 (en) * 2008-04-01 2011-07-12 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
CN104576728A (zh) * 2013-10-10 2015-04-29 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
US9059254B2 (en) * 2012-09-06 2015-06-16 International Business Machines Corporation Overlay-tolerant via mask and reactive ion etch (RIE) technique
CN104795414A (zh) * 2014-01-17 2015-07-22 南亚科技股份有限公司 一种通过注入氮改性多晶硅层的方法
TWI495009B (zh) * 2010-02-12 2015-08-01 Advanced Micro Fab Equip Inc A Plasma Etching Method with Silicon Insulating Layer
CN105097440A (zh) * 2014-05-23 2015-11-25 中微半导体设备(上海)有限公司 一种深硅刻蚀方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7977768B2 (en) * 2008-04-01 2011-07-12 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
TWI495009B (zh) * 2010-02-12 2015-08-01 Advanced Micro Fab Equip Inc A Plasma Etching Method with Silicon Insulating Layer
US9059254B2 (en) * 2012-09-06 2015-06-16 International Business Machines Corporation Overlay-tolerant via mask and reactive ion etch (RIE) technique
CN104576728A (zh) * 2013-10-10 2015-04-29 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
CN104795414A (zh) * 2014-01-17 2015-07-22 南亚科技股份有限公司 一种通过注入氮改性多晶硅层的方法
CN105097440A (zh) * 2014-05-23 2015-11-25 中微半导体设备(上海)有限公司 一种深硅刻蚀方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11915940B2 (en) 2020-08-18 2024-02-27 Applied Materials, Inc. Method of depositing a pre-etch protective layer

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