WO2020211515A1 - 一种高精度温度传感器 - Google Patents

一种高精度温度传感器 Download PDF

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Publication number
WO2020211515A1
WO2020211515A1 PCT/CN2020/075277 CN2020075277W WO2020211515A1 WO 2020211515 A1 WO2020211515 A1 WO 2020211515A1 CN 2020075277 W CN2020075277 W CN 2020075277W WO 2020211515 A1 WO2020211515 A1 WO 2020211515A1
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Prior art keywords
electrically connected
transistor
switch
emitter
voltage
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PCT/CN2020/075277
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English (en)
French (fr)
Inventor
刘莎莎
吴欣延
夏玥
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珠海晶通科技有限公司
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Publication of WO2020211515A1 publication Critical patent/WO2020211515A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K13/00—Thermometers specially adapted for specific purposes
    • G01K13/20—Clinical contact thermometers for use with humans or animals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K15/00—Testing or calibrating of thermometers
    • G01K15/005—Calibration

Definitions

  • the invention relates to the field of temperature sensors, in particular to a high-precision temperature sensor.
  • the temperature sensor needs to achieve a temperature measurement accuracy of ⁇ 0.1°C within the temperature range of 37°C to 39°C, or below The accuracy of ⁇ 0.2°C is achieved in the temperature range of 37°C and higher than 39°C.
  • a high-precision intelligent temperature sensor is composed of a sensor front-end circuit and an analog-to-digital converter.
  • the sensor front-end circuit measures temperature through a transistor such as a PNP transistor, and converts the temperature signal into a voltage or current that is linear with the temperature signal. Then the voltage or current linearly related to the temperature signal is input to the analog-to-digital converter.
  • the analog-to-digital converter samples the input voltage or current, and then quantizes it to output discrete digital quantities, such as binary codes, or temperature codes Therefore, the higher the quantization accuracy of the analog-to-digital converter, the higher the resolution of the temperature sensor, and the smaller the quantization error in the quantization process.
  • the need for high resolution leads to the more difficult design, workload and power consumption of the ADC Big.
  • a sigma-delta analog-to-digital converter is generally used to design a high-precision temperature sensor, and the analog-to-digital converter quantifies the coefficient value ⁇ representing the temperature.
  • the temperature range of ⁇ is between -273°C and 330°C, but the temperature range of various device models of the commercial chip process line is -40°C to 125°C
  • ⁇ is the coefficient to amplify ⁇ VBE
  • ⁇ VBE is the temperature
  • the voltage is proportional to the linear relationship
  • VBE is the voltage that is inversely proportional to the temperature.
  • the sigma-delta analog-to-digital converter is required to achieve 16-bit resolution, which further increases the difficulty and design of high-precision temperature sensors. Power consumption.
  • the purpose of the present invention is to provide a high-precision temperature sensor with low power consumption and single-point calibration.
  • the present invention provides a high-precision temperature sensor including a sensor front-end circuit and an analog-to-digital converter.
  • the sensor front-end circuit is electrically connected to the analog-to-digital converter.
  • the sensor front-end circuit includes a power supply voltage input terminal VDD, a first current The source circuit, the second current source circuit, the transistor Q1 and the transistor Q2, the power supply voltage input terminal VDD is electrically connected to the input terminals of the first current source circuit and the second current source circuit, and the output terminal of the first current source circuit is connected to the transistor Q1
  • the emitter of the second current source circuit is electrically connected to the emitter of the transistor Q2, the base of the transistor Q1 and the base of the transistor Q2 are grounded, and the collector of the transistor Q1 and the collector of the transistor Q2 are grounded.
  • the digital converter includes a sampling and amplifying circuit and a dynamic capacitance matching module.
  • the sampling and amplifying circuit includes a first switched capacitor array circuit, a voltage input terminal A1, a voltage input terminal A2, and a voltage output terminal A3.
  • the first switched capacitor array circuit includes a plurality of switches S21 A plurality of capacitors C1, the first movable contact of each switch S21 is electrically connected to the voltage input terminal A1, the second movable contact of each switch S21 is electrically connected to the voltage input terminal A2, and the static of each switch S21
  • the contacts are electrically connected to the first end of a capacitor C1, the second end of each capacitor C1 is electrically connected to the voltage output terminal A3, and each switch S21 receives the control signal output by the dynamic capacitor matching module.
  • the analog-to-digital converter also includes a sigma-delta modulator and a digital filter.
  • the voltage output terminal A3 and the voltage output terminal B3 are respectively electrically connected to the sigma-delta modulator, and the sigma-delta modulator is connected to the digital filter.
  • the dynamic matching module outputs the BS value.
  • the dynamic matching module judges the BS value output by the ⁇ - ⁇ modulator and outputs control signals to each switch S21 and S22 respectively.
  • the digital filter counts the BS value output by the ⁇ - ⁇ modulator. Get the coefficient value ⁇ '.
  • K1 is the first amplification factor of the first switched capacitor array circuit
  • K2 is the second amplification factor of the first switched capacitor array circuit
  • K3 is the third amplification factor of the first switched capacitor array circuit
  • ⁇ is the amplification of ⁇ VBE
  • the coefficient of ⁇ VBE is the voltage value in direct proportional linear relationship with temperature
  • VBE is the voltage value in inverse proportional linear relationship with temperature.
  • the ⁇ - ⁇ modulator includes a voltage input terminal A4, a voltage input terminal B4, a voltage output terminal A5, a voltage output terminal B5, an integrating circuit, a comparator U30, and a signal output terminal E.
  • the integrating circuit includes a switch S31, a switch S41, integrating capacitor C3, switch S32, chopper U21, operational amplifier U20, chopper U22, switch S33, switch S43, integrating capacitor C4, switch S42, wherein the voltage input terminal A4 is electrically connected to the voltage output terminal A3, The voltage input terminal B4 is electrically connected to the voltage output terminal B3.
  • the voltage input terminal A4 is electrically connected to the chopper U21
  • the chopper U21 is electrically connected to the operational amplifier U20
  • the operational amplifier U20 is electrically connected to the chopper U22
  • the voltage output terminal A5 and the voltage output terminal B5 are electrically connected to the chopper U22.
  • the comparator U30 is electrically connected to the voltage output terminal A5 and the voltage output terminal B5, and the comparator U30 is electrically connected to the signal output terminal E.
  • the first terminal of the switch S31 and the first terminal of the switch S41 are respectively connected to the voltage input terminals A4, B4 is electrically connected, the second end of switch S33 is electrically connected to the first end of integrating capacitor C3, the second end of integrating capacitor C3 and the second end of switch S31 are electrically connected to comparator U30, and the first end of switch S32 is electrically connected to The first end of the integrating capacitor C3 is electrically connected, the second end of the switch S32 is electrically connected to the integrating capacitor C3, the first end of the switch S41 and the first end of the switch S43 are electrically connected to the voltage input terminal B4, and the second end of the switch S43
  • the terminal is electrically connected to the first terminal of the integrating capacitor C4, the second terminal of the integrating capacitor C4 and the second terminal of the switch S42 are respectively electrically connected to the comparator U30, and the first terminal of the switch S42 is electrically connected to the first terminal of the integrating capacitor C4 ,
  • the second end of the switch S42 is
  • the first current source circuit includes a MOS tube M3 and a single-pole double-throw switch S1.
  • the source of the MOS tube M3 is electrically connected to the power supply voltage input terminal VDD, and the drain of the MOS tube M3 is connected to the static of the single-pole double-throw switch S1.
  • the contacts are electrically connected, the first movable contact of the SPDT switch S1 is electrically connected with the emitter of the transistor Q1, and the second movable contact of the SPDT switch S1 is electrically connected with the emitter of the transistor Q2.
  • the second current source circuit includes MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, single pole double throw switch S2, single pole double throw switch S3, single pole double throw switch S4, single pole Double-throw switch S5, single-pole double-throw switch S6, the power supply voltage input terminal VDD is respectively connected with the source of MOS tube M4, the source of MOS tube M5, the source of MOS tube M6, the source of MOS tube M7, the source of MOS tube M8
  • the source is electrically connected
  • the drain of the MOS transistor M4 is electrically connected to the static contact of the SPDT switch S2
  • the first movable contact of the SPDT switch S2 is electrically connected to the emitter of the transistor Q1
  • the second movable contact is electrically connected with the emitter of the transistor Q2
  • the drain of the MOS transistor M5 is electrically connected with the static contact of the SPDT switch S3, and the first movable contact of the SPDT
  • the static contact of the throw switch S6 is electrically connected, the first movable contact of the SPDT switch S6 is electrically connected with the emitter of the transistor Q1, and the second movable contact of the SPDT switch S6 is electrically connected with the emitter of the transistor Q2,
  • the gate of MOS tube M3 is electrically connected to the gate of MOS tube M4, the gate of MOS tube M4 is electrically connected to the gate of MOS tube M5, the gate of MOS tube M5 is electrically connected to the gate of MOS tube M6, and the gate of MOS tube M6 is electrically connected to MOS
  • the grid of the tube M7 is electrically connected, and the grid of the MOS tube M7 is electrically connected with the grid of the MOS tube M8.
  • the sensor front-end circuit is equipped with a dynamic current mirror matching module.
  • the dynamic current mirror matching module is connected to the SPDT switch S1, SPDT switch S2, SPDT switch S3, SPDT switch S4, SPDT Switch S5 and SPDT switch S6 are electrically connected
  • the sensor front-end circuit is equipped with a bias circuit.
  • the bias circuit includes a MOS tube M1, a MOS tube M2, an operational amplifier U1, a transistor Q3, a resistor R1, a resistor R2, and a transistor Q4.
  • the power supply voltage input terminal VDD is respectively connected to the MOS
  • the source of the tube M1 and the source of the MOS tube M2 are electrically connected, the gate of the MOS tube M1 is electrically connected to the gate of the MOS tube M2, the gate of the MOS tube M2 is electrically connected to the gate of the MOS tube M3, and the MOS tube M1
  • the drain of the transistor Q3 is electrically connected to the emitter of the transistor Q3
  • the drain of the MOS transistor M2 is electrically connected to the first end of the resistor R1
  • the output end of the operational amplifier U1 is electrically connected to the gate of the MOS transistor M1 and the gate of the MOS transistor M2.
  • the out-of-phase input end of the operational amplifier U1 is electrically connected to the emitter of the transistor Q3
  • the non-inverting input end of the operational amplifier U1 is electrically connected to the first end of the resistor R1
  • the second end of the resistor R1 is electrically connected to the emitter of the transistor Q4
  • the base of the transistor Q3 is electrically connected to the first end of the resistor R2
  • the second end of the resistor R2 is grounded to the base of the transistor Q4
  • the collector of the transistor Q3 and the collector of the transistor Q4 are grounded.
  • a further solution is that the area ratio of the transistor Q3 and the transistor Q4 is 1:1, and the area of the transistor Q1 is twice the area of the transistor Q3, and the resistance ratio of the resistor R1 to the resistor R2 is 5:1.
  • the sensor front-end circuit can also be provided with a selector, a voltage output terminal A and a voltage output terminal B.
  • the emitter of the transistor Q2 is electrically connected to the first input terminal of the selector, and the emitter of the transistor Q2 is electrically connected to the The first input terminal is electrically connected, the emitter of the transistor Q1 is electrically connected to the second input terminal of the selector, the first output terminal of the selector is electrically connected to the voltage output terminal A, and the first output terminal of the selector is electrically connected to the voltage output terminal B Electric connection.
  • the invention can output different control signals to the sampling amplifier circuit after the capacitance dynamic matching module judges according to the different values output by the BS, and respectively sample and amplify the voltage generated by the sensor front-end circuit, thereby reducing the energy consumption of the high-precision sensor.
  • the present invention uses the dynamic capacitance matching module to output control signals to the switches S11, S12, S13, and S14 according to the value of BS, so as to control the multiple of the voltage output by the sensor front-end circuit 10 in the next clock cycle. the goal of.
  • the coefficient value ⁇ 'of the present invention is Relative to the coefficient value of the prior art temperature sensor Enlarged by G times, and in the Cartesian coordinate system, the coefficient value ⁇ 'is longitudinally moved by the distance of C on the y-axis coordinate, where So that the resolution of the analog-to-digital converter does not need to reach 16-bit resolution to meet the measurement accuracy of the temperature sensor in a certain temperature zone or certain temperature zones (even covering certain temperature zones at the same time to cover the entire temperature zone).
  • the requirement of ⁇ 0.1°C meets the requirement of measuring accuracy of temperature sensor within ⁇ 0.1°C in a certain temperature zone or a certain temperature zone, while reducing power consumption and reducing the difficulty and workload of analog circuit design.
  • the invention uses a sigma-delta modulator to integrate and judge the voltage output by the sensor front-end circuit and output the BS value.
  • the first current source circuit can provide a stable bias current for the sensor front-end circuit.
  • the second current source circuit can provide a stable bias current for the sensor front-end circuit.
  • the dynamic current mirror matching module of the present invention reduces the current mirror by separately controlling the single pole double throw switch S1, the single pole double throw switch S2, the single pole double throw switch S3, the single pole double throw switch S4, the single pole double throw switch S5, and the single pole double throw switch S6.
  • the current mismatch between the six MOS transistors in the circuit enables accurate voltage output from the emitter of the transistor Q1, and accurate voltage output from the emitter of the transistor Q2.
  • the bias current can provide a stable bias current and bias voltage for the sensor front-end circuit.
  • the selector in the sensor front-end circuit it plays a role in further generating accurate voltage.
  • Fig. 1 is a first structural block diagram of an embodiment of a high-precision temperature sensor of the present invention.
  • Fig. 2 is an electrical schematic diagram of the sensor front-end circuit of an embodiment of the high-precision temperature sensor of the present invention.
  • Fig. 3 is an electrical schematic diagram of a sampling amplifier circuit of an embodiment of the high-precision temperature sensor of the present invention.
  • Fig. 4 is an electrical schematic diagram of the sigma-delta modulator in an embodiment of the high-precision temperature sensor of the present invention.
  • Fig. 5 is a second structural block diagram of an embodiment of the high-precision temperature sensor of the present invention.
  • FIG. 6 is a graph of the relationship between the coefficient value ⁇ of the temperature sensor in the prior art and the temperature.
  • FIG. 7 is a graph of the relationship between the coefficient value ⁇ ′ and the temperature of an embodiment of the high-precision temperature sensor of the present invention.
  • the high-precision temperature sensor of the present invention includes a sensor front-end circuit 10 and an analog-to-digital converter 20.
  • the analog to digital converter 20 used in this embodiment is a sigma-delta analog to digital converter.
  • the sensor front-end circuit 10 includes a power supply voltage input terminal VDD, a first current source circuit 2, a second current source circuit 4, a transistor Q1 and a transistor Q2.
  • the power supply voltage input terminal VDD is respectively connected to the first current source circuit 2 and the second current source circuit
  • the input terminal of 4 is electrically connected, the output terminal of the first current source circuit 2 is electrically connected with the emitter of the transistor Q1, the output terminal of the second current source circuit 4 is electrically connected with the emitter of the transistor Q2, the base of the transistor Q1 and the transistor
  • the base of Q2 is grounded, and the collector of transistor Q1 and the collector of transistor Q2 are grounded.
  • the power supply voltage is input to the sensor front-end circuit 10 through the power supply voltage input terminal VDD.
  • the area ratio of the triode Q1 and the triode Q2 in this embodiment is set to 1:1.
  • the first current source circuit 2 includes a MOS tube M3 and a single-pole double-throw switch S1.
  • the source of the MOS tube M3 is electrically connected to the power supply voltage input terminal VDD, and the drain of the MOS tube M3 is connected to the single-pole double-throw switch.
  • the static contact of the switch S1 is electrically connected, the first moving contact of the SPDT switch S1 is electrically connected with the emitter of the transistor Q1, and the second moving contact of the SPDT switch S1 is electrically connected with the emitter of the transistor Q2.
  • the second current source circuit 4 includes MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, single pole double throw switch S2, single pole double throw switch S3, single pole double throw switch S4, single pole double throw switch S5 , Single-pole double-throw switch S6, the power supply voltage input VDD is electrically connected to the source of MOS tube M4, the source of MOS tube M5, the source of MOS tube M6, the source of MOS tube M7, and the source of MOS tube M8.
  • the drain of MOS tube M4 is electrically connected to the static contact of SPDT switch S2, the first movable contact of SPDT switch S2 is electrically connected to the emitter of transistor Q1, and the second movable contact of SPDT switch S2
  • the point is electrically connected with the emitter of the transistor Q2;
  • the drain of the MOS transistor M5 is electrically connected with the static contact of the SPDT switch S3, and the first movable contact of the SPDT switch S3 is electrically connected with the emitter of the transistor Q1, single pole
  • the second movable contact of the double-throw switch S3 is electrically connected to the emitter of the transistor Q2;
  • the drain of the MOS transistor M6 is electrically connected to the static contact of the SPDT switch S4, and the first movable contact of the SPDT switch S4 is electrically connected to
  • the emitter of the transistor Q1 is electrically connected
  • the second movable contact of the SPDT switch S4 is electrically connected with the emitter of the transistor Q2
  • the gate of the MOS tube M3 is electrically connected to the gate of the MOS tube M4, the gate of the MOS tube M4 is electrically connected to the gate of the MOS tube M5, the gate of the MOS tube M5 is electrically connected to the gate of the MOS tube M6, and the gate of the MOS tube M6 is electrically connected.
  • the pole is electrically connected with the grid of the MOS tube M7, and the grid of the MOS tube M7 is electrically connected with the grid of the MOS tube M8.
  • the sensor front-end circuit 10 is provided with a dynamic current mirror matching module 6, which is respectively connected with a single pole double throw switch S1, a single pole double throw switch S2, a single pole double throw switch S3, a single pole double throw switch S4, and a single pole double throw switch S5.
  • Single-pole double-throw switch S6 is electrically connected.
  • MOS tube M1 MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, and MOS tube M8 form a current mirror circuit and start to work
  • MOS tube M1 MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, and MOS tube M8 form a current mirror circuit and start to work
  • due to the dynamic current mirror matching module in this embodiment 6 is a digital circuit, which can control SPDT switch S1, SPDT switch S2, SPDT switch S3, SPDT switch S4, SPDT switch S5, SPDT switch S6 through 6-digit digital signal.
  • the dynamic current mirror matching module 6 has 1 digital signal and other 5 digital signals inverted, that is, when the static contact of the SPDT switch S1 and the first moving contact are connected, the SPDT switch S2, the SPDT The static contact of the double-throw switch S3, the single-pole double-throw switch S4, the single-pole double-throw switch S5, and the single-pole double-throw switch S6 are conducted with the second movable contact.
  • the dynamic current mirror matching module 6 reduces the current mirror by controlling the SPDT switch S1, SPDT switch S2, SPDT switch S3, SPDT switch S4, SPDT switch S5, SPDT switch S6, respectively.
  • the current mismatch between the six MOS transistors in the circuit enables accurate voltage output from the emitter of the transistor Q1, and accurate voltage output from the emitter of the transistor Q2.
  • the sensor front-end circuit 10 is provided with a bias circuit 5 which is electrically connected to the first current source circuit 2 and the second current source circuit 4 respectively.
  • the bias circuit 5 includes a MOS tube M1, a MOS tube M2, an operational amplifier U1, a transistor Q3, a resistor R1, a resistor R2, and a transistor Q4.
  • the power supply voltage input terminal VDD is respectively connected to the source of the MOS tube M1 and the source of the MOS tube M2.
  • the gate of the MOS tube M1 is electrically connected to the gate of the MOS tube M2, the gate of the MOS tube M2 is electrically connected to the gate of the MOS tube M3, and the drain of the MOS tube M1 is electrically connected to the emitter of the transistor Q3.
  • the drain of the MOS tube M2 is electrically connected to the first end of the resistor R1, the output terminal of the operational amplifier U1 is electrically connected to the gate of the MOS tube M1 and the gate of the MOS tube M2, and the out-of-phase input terminal of the operational amplifier U1 is
  • the emitter of the transistor Q3 is electrically connected, the non-inverting input end of the operational amplifier U1 is electrically connected to the first end of the resistor R1, the second end of the resistor R1 is electrically connected to the emitter of the transistor Q4, and the base of the transistor Q3 is electrically connected to the first end of the resistor R2.
  • One end is electrically connected, the second end of the resistor R2 and the base of the transistor Q4 are grounded, and the collector of the transistor Q3 and the collector of the transistor Q4 are grounded.
  • the area ratio of the triode Q3 and the triode Q4 in the bias circuit 5 is set to 1:1, and the area of the triode Q1 and the triode Q2 is twice the area of the triode Q3 and the triode Q4, so as to generate a stable bias The purpose of the current.
  • the resistance value ratio of the resistor R1 and the resistor R2 is set to 5:1, and the area ratio of the MOS tube M1 and the MOS tube M2 is set to 5:1, which compensates the effect of the forward current gain of the transistor Q3 and the transistor Q4.
  • the bias current 5 in this embodiment is also provided with a chopper U2 and a chopper U3.
  • the chopper U2 and the chopper U3 are respectively electrically connected to the operational amplifier U1, and the chopper U2 and the chopper U3 function as Reduce the effect of the offset voltage (offset) of the operational amplifier U1.
  • the sensor front-end circuit 10 may also be provided with a selector 8, a voltage output terminal A and a voltage output terminal B.
  • the emitter of the transistor Q1 is electrically connected to the first input terminal of the selector 8
  • the emitter of the transistor Q2 is electrically connected to the first input terminal of the selector 8.
  • the two input terminals are electrically connected, the first output terminal of the selector 8 is electrically connected to the voltage output terminal A, the second output terminal of the selector 8 is electrically connected to the voltage output terminal B, and the voltage output terminal A and the voltage output terminal B are respectively connected to the module
  • the digital converter 20 is electrically connected, the selector 8 outputs the voltage VBE to the analog-to-digital converter 20 through the voltage output terminal A, and the selector 8 outputs the voltage VBE2 to the analog-to-digital converter 20 through the voltage output terminal B.
  • the selector 8 in this embodiment is a data selector, which plays the role of keeping the voltage output terminal A always outputting the voltage VBE1 and keeping the voltage output terminal B always outputting the voltage VBE2.
  • the power supply voltage is input to the sensor front-end circuit 10 through the power supply voltage input terminal VDD, and the bias circuit 5 starts to work to provide stable bias voltage and bias current for the sensor front-end circuit 10, from the power supply voltage input
  • the terminal VDD outputs voltage to the current source circuit 2 and the current source circuit 4 respectively.
  • the current I1 flows from the current source circuit 2 into the emitter of the transistor Q1, and the current I2 flows from the current source circuit 4 to the emitter of the transistor Q2.
  • the value of the current I1 The ratio of the value to the current I2 is 1:5, the output voltage VBE1 from the transistor Q1 to the analog-to-digital converter 20, and the output voltage VBE2 from the transistor Q2 to the analog-to-digital converter 20.
  • the voltage VBE1 and the voltage VBE2 have an inverse proportional linear relationship with the temperature.
  • the sensor front-end circuit 10 can convert the temperature to a voltage VBE1 that is inversely proportional to the temperature through the transistor Q1, and the sensor front-end circuit 10 can convert the temperature to a voltage VBE2 that is inversely proportional to the temperature through the transistor Q2.
  • VBE1 and VBE2 have an approximately linear relationship with temperature.
  • the analog-to-digital converter 20 includes a virtual module 21, a ⁇ - ⁇ modulator 30, a digital filter 40, a dynamic capacitance matching module 50, and a transistor Q1 to the virtual Module 21 inputs voltage VBE1, transistor Q2 inputs voltage VBE2 to virtual module 21, virtual module 21 samples and amplifies voltage VBE1 and voltage VBE2, respectively, and outputs them to module conversion circuit 30.
  • ⁇ - ⁇ modulator 30 inputs two voltages After sampling, subtraction, integration, and comparison are processed, the BS value is output to the digital filter 40 and the dynamic capacitor matching module 50 respectively.
  • the dynamic matching capacitor module 50 outputs a control signal to the virtual module 21 according to the received BS value.
  • the digital filter 40 counts the BS value output by the sigma-delta modulator 30 and outputs the coefficient value ⁇ '.
  • the virtual module 21 in this embodiment includes a sampling amplification module 22, a switch S11, a switch S12, a switch S13, a switch S14, a first amplification module 24, a second amplification module 25, a third amplification module 26, and a fourth amplification module 27.
  • the sampling and amplifying module 22 is used for subtracting the received voltage VBE1 and voltage VBE2 to obtain the voltage ⁇ VBE and amplifying the voltage ⁇ VBE by ⁇ times, and the first amplifying module 24 is used for amplifying the input voltage by K1 times;
  • the second amplifying module 25 is used to amplify the input voltage K3 times, the third amplifying module 26 is used to amplify the input voltage K2 times, the fourth amplifying module 27 is used to amplify the input voltage K4 times, switch S11 Used to control whether the sampling amplification module 22 and the first amplification module 24 work, the switch S12 is used to control whether the sampling amplification module 22 and the second amplification module 25 work, the switch S13 is used to control whether the third amplification module 26 works, and the switch S14 is used To control whether the fourth amplifying module 27 works.
  • the dynamic capacitance matching module 50 in this embodiment is a digital circuit, which can output control signals to the switch S11, the switch S12, the switch S13, and the switch S14 by judging the value of the input BS.
  • the dynamic capacitance matching module 50 outputs control signals to the switch S11, the switch S12, the switch S13, and the switch S14 respectively, the switch S11 and the switch S13 are closed, and the sampling and amplifying module 22, the first amplifying module 24 and the third
  • the dynamic capacitance matching module 50 outputs control signals to the switch S11, the switch S12, the switch S13, and the switch S14 according to the value of BS, so as to achieve the purpose of controlling the multiple of the voltage output by the sensor front-end circuit 10 in the next clock cycle.
  • the sampling and amplification functions of each module of the virtual module 21 are actually implemented by the sampling and amplifying circuit 60.
  • the sampling and amplifying circuit 60 includes a first switched capacitor array circuit 61 and a second switched capacitor array circuit 62. , Voltage input terminal A1, voltage input terminal A2, voltage input terminal B1, voltage input terminal B2, voltage output terminal A3, and voltage output terminal B3.
  • the voltage input terminal A1, the voltage input terminal A2 and the voltage input terminal B1, and the voltage input terminal B2 are electrically connected to the emitter of the transistor Q1, the emitter of the transistor Q2 and the ground through the switch, and the switch is controlled by the clock signal ⁇ 1, the clock signal ⁇ 2, When different switches are closed, the voltage input terminal A1, the voltage input terminal A2, the voltage input terminal B1, and the voltage input terminal B2 are respectively connected to the voltage VBE1 or the voltage VBE2 or the ground.
  • the voltage input terminal A1 when the clock signal ⁇ 1 is high level, the voltage input terminal A1 is grounded, and the voltage input terminal A2 is connected to the emitter of the transistor Q2, that is, connected to the voltage VBE2; when the clock signal ⁇ 2 is high level, the voltage input terminal A1 is connected The emitter of the transistor Q2 is connected to the voltage VBE2, and the voltage input terminal A2 is connected to the emitter of the transistor Q1, which is connected to the voltage VBE1.
  • the voltage input terminal B1 when the clock signal ⁇ 1 is at a high level, the voltage input terminal B1 is connected to the emitter of the transistor Q2, that is, to the voltage VBE2, and the voltage input terminal B2 is connected to the emitter of the transistor Q1, that is, to the voltage VBE1;
  • the voltage input terminal B1 When the signal ⁇ 2 is at a high level, the voltage input terminal B1 is grounded, and the voltage input terminal B2 is connected to the emitter of the transistor Q2, that is, connected to the voltage VBE2.
  • the first switched capacitor array circuit 61 includes a plurality of switches S21 and a plurality of sampling capacitors C1.
  • the first movable contact of each switch S21 is electrically connected to the voltage input terminal A1, and the second movable contact of each switch S21 is respectively connected to
  • the voltage input terminal A2 is electrically connected
  • the static contact of each switch S21 is electrically connected to the first end of a sampling capacitor C1
  • the second end of each sampling capacitor C1 is electrically connected to the voltage output terminal A3
  • each switch S21 The control signals output by the dynamic capacitance matching module 50 are respectively received.
  • the multiple switches S21 included in the first switched capacitor array circuit 61 in this embodiment are switches ⁇ S21, 1 ⁇ to switches ⁇ S21, x ⁇ in FIG.
  • the multiple sampling capacitors C1 included in the first switched capacitor array circuit 61 are the sampling capacitors ⁇ C1, 1 ⁇ to the sampling capacitors ⁇ C1, x ⁇ in FIG. 3, where x is the value of the sampling capacitor C1 determined according to different amplification factors. Quantity. For example, if the amplification factor is K2, the number of switches S21 and sampling capacitor C1 is K2, K2 switches S21 are switches ⁇ S21, 1 ⁇ to switches ⁇ S21, K2 ⁇ in Figure 3, and K2 sampling capacitors C1 are shown in Figure 3. The sampling capacitor ⁇ C1, 1 ⁇ to the sampling capacitor ⁇ C1, K2 ⁇ .
  • the second switched capacitor array circuit 62 includes a plurality of switches S22 and a plurality of sampling capacitors C2.
  • the first movable contact of each switch S22 is electrically connected to the voltage input terminal B1, and the second movable contact of each switch S22 is electrically connected to the voltage input terminal B1.
  • the voltage input terminal B2 is electrically connected, the static contact of each switch S22 is electrically connected to the first end of a sampling capacitor C2, the second end of each sampling capacitor C2 is electrically connected to the voltage output terminal B3, and each switch S22
  • the control signals output by the dynamic capacitance matching module 50 are respectively received.
  • the capacitance value of each capacitor C1 is a unit capacitance value
  • the capacitance value of each sampling capacitor C2 is a unit capacitance value.
  • the multiple switches S22 included in the second switched capacitor array circuit 62 in this embodiment are switches ⁇ S22, 1 ⁇ to ⁇ S22, x ⁇ in FIG. 3, where x is determined according to different amplification factors The number of switches S22.
  • the multiple sampling capacitors C2 included in the second switched capacitor array circuit 62 are the sampling capacitors ⁇ C2, 1 ⁇ to the sampling capacitors ⁇ C2, x ⁇ in FIG. 3, where x is the value of the sampling capacitor C2 determined according to different amplification factors. Quantity.
  • magnifications that need to be generated simultaneously in this embodiment are ⁇ K1 and K2, ⁇ K3 and K4, and x is the larger of ( ⁇ K1+K2) and ( ⁇ K3+K4), that is, if ( ⁇ K1+K2)>( ⁇ K3+K4), x takes the value of ( ⁇ K1+K2).
  • the first switched capacitor array 61 and the second switched capacitor array 62 form a differential circuit, which has stronger anti-interference ability.
  • the first switched capacitor array circuit 61 is used for description.
  • the dynamic capacitor matching module 50 determines the input BS value and outputs control signals to the plurality of switches S21.
  • the switch ⁇ S21, 1 ⁇ to switch ⁇ S21, x ⁇ are controlled by the control signal output by the dynamic capacitance matching module 50, and the switch ⁇ S21, 1 ⁇ to switch ⁇ S21, K2 ⁇ ’S static contact and the first moving contact are closed, connected to the voltage input terminal A1, and the voltage input terminal A1 is now connected to ground;
  • switch ⁇ S21, 1 ⁇ to switch ⁇ S21, x ⁇ is controlled by the control signal output by the dynamic capacitance matching module 50, the static contact of the switch ⁇ S21, 1 ⁇ to the switch ⁇ S21, K2 ⁇ is closed with the first moving contact, connected to the voltage input terminal A1, voltage input The terminal A1 is now connected
  • the switch ⁇ S21, 1 ⁇ to switch ⁇ S21, x ⁇ is controlled by the control signal output by the dynamic capacitance matching module 50, and the switch ⁇ S21, (K2+1) ⁇ to switch ⁇ S21, ( ⁇ K1-K2-1) ⁇
  • the static contact and the first moving contact are closed, connected to the voltage input terminal A2, and the voltage input terminal A2 is connected to the voltage VBE2; next, when the clock signal ⁇ 2 is high,
  • the switch ⁇ S21, 1 ⁇ to the switch ⁇ S21, x ⁇ are controlled by the control signal output by the dynamic capacitance matching module 50, and the static of the switch ⁇ S21, (K2+1) ⁇ to the switch ⁇ S21, ( ⁇ K1-K2-1) ⁇
  • the contact is closed with the first movable contact and connected to the voltage input terminal A2.
  • the first switched capacitor array circuit 61 is connected to the capacitor C1 with a quantity of ⁇ K1 through a plurality of switches S21 to simultaneously sample the voltage VBE1 and the voltage VBE2.
  • the output voltage ⁇ VBE is amplified by ⁇ K1 times, and the charge on the sampling capacitor C1 is transferred to the integrating capacitor C3, that is, the output voltage is generated at the voltage output terminal A5 and the voltage output terminal B5 of the integrating circuit 33.
  • the first switched capacitor array circuit 61 is connected to a number of ⁇ K3 capacitors C1 through multiple switches S21 to simultaneously sample the voltage VBE1 and the voltage VBE2, and then output the sampled output
  • the voltage ⁇ VBE is amplified by ⁇ K3 times, and the charge on the sampling capacitor C1 is transferred to the integrating capacitor C3, that is, the output voltage is generated at the voltage output terminal A5 and the voltage output terminal B5 of the integrating circuit 33.
  • the voltage VBE2 is sampled by K2 capacitors connected through multiple switches in the first switched capacitor array circuit 61, and the sampled output voltage VBE2 is amplified by K2 times.
  • the charge on the capacitor C1 is transferred to the integrating capacitor C3, that is, an output voltage is generated at the voltage output terminals A5 and B5 of the integrating circuit 33.
  • a number of K4 capacitors can be connected in the first switched capacitor array circuit 61 to sample the voltage VBE2, and then the sampled output voltage VBE2 is amplified by K4 times, and the sampling capacitor The charge on C1 is transferred to the integrating capacitor C3, that is, an output voltage is generated at the voltage output terminal A5 and the voltage output terminal B5 of the integrating circuit 33.
  • ⁇ is a fixed gain coefficient (determined by the characteristics of the transistor used in the process), and an appropriate number of sampling capacitors C1 is selected according to the actual situation.
  • K1, K2, K3, and K4 are respectively an adjustable amplification factor, which can be achieved by adjusting the number of sampling capacitors C1 connected to the circuit according to different temperature ranges.
  • the sigma-delta modulator 30 includes a voltage input terminal A4, a voltage input terminal B4, an integration circuit 33, a voltage output terminal A5, a voltage output terminal B5, a comparator U30, and a signal output terminal E.
  • the integration circuit 33 includes a switch S31 , Switch S41, integrating capacitor C3, switch S32, chopper U21, operational amplifier U20, chopper U22, switch S33, switch S43, integrating capacitor C4, switch S42, where the voltage input terminal A4 is the same as the voltage in Figure 3
  • the output terminal A3 is electrically connected, and the voltage input terminal B4 is electrically connected to the voltage output terminal B3 in FIG. 3.
  • the voltage input terminal A4 and the voltage input terminal B4 are electrically connected to the chopper U21, the chopper U21 is electrically connected to the operational amplifier U20, the operational amplifier U20 is electrically connected to the chopper U22, and the chopper U22 is electrically connected to the voltage output terminal A5.
  • the comparator U30 is electrically connected to the signal output terminal E
  • the first end of the switch S31 and the second end of the switch S41 are respectively Is electrically connected to the voltage input terminal A4
  • the second end of the switch S33 is electrically connected to the first end of the integrating capacitor C3, the second end of the integrating capacitor C3 and the second end of the switch S31 are electrically connected to the comparator U30
  • the switch S32 The first terminal is electrically connected to the first terminal of the integrating capacitor C3, the second terminal of the switch S32 is electrically connected to the integrating capacitor C3, the first terminal of the switch S41 and the second terminal of the switch S43 are electrically connected to the voltage input terminal B4, respectively.
  • the second end of S43 is electrically connected to the first end of the integrating capacitor C4, the second end of the integrating capacitor C4 and the second end of the switch S42 are respectively electrically connected to the comparator U30, and the first end of the switch S42 is electrically connected to the first end of the integrating capacitor C4. One end is electrically connected, and the second end of the switch S42 is electrically connected to the integrating capacitor C4.
  • switch S32 and switch S42 are closed when the control signal rst is high level
  • switch S31 and switch S41 are closed when the clock signal ⁇ 1 is high level
  • switch S33 and switch S43 are closed when the clock signal ⁇ 2 is high level
  • the device U21 and the chopper U22 play a role in reducing the offset voltage of the operational amplifier U20 when the operational amplifier U20 is working on the operational amplifier, thereby reducing the impact of the offset voltage on the temperature measurement accuracy of the temperature sensor; the operational amplifier U20 has utilization
  • the virtual ground namely the voltage input terminal A4 and the voltage input terminal A5 in FIG. 4, continuously transports the charge at the input terminal to the output terminal as much as possible without damage.
  • the charge is transferred to the selected sampling capacitor C1 and sampling capacitor C2 through the voltage input terminal A1, the voltage input terminal A2, the voltage input terminal B1, the voltage input terminal B2, and the selected switch S21 and switch S22.
  • the switches S33 and S43 are closed, and the charge sampled on the sampling capacitor C1 and the sampling capacitor C2 is transferred to the integrating capacitors C3 and C4 through the voltage input terminal A4 and the voltage input terminal B4.
  • the integrating circuit 33 generates output voltages at the output terminals A5 and B5 and outputs them to the comparator U30.
  • the comparator U30 compares the magnitude of the two input voltage values at the A5 terminal and the B5 terminal and outputs the BS value through the signal output terminal E.
  • the comparator U30 is electrically connected to the dynamic capacitance matching module 50 and the digital filter 40 respectively.
  • the comparator U30 can output the BS value to the dynamic capacitance matching module 50 and the digital filter 40, respectively, and the digital filter 40 inputs The number of BS values with a serial number of 1 is counted, and then the digital filter 40 outputs a coefficient value ⁇ ′, where the number of cycles that the digital filter 40 counts is determined by the resolution of the analog-to-digital converter 30.
  • the analog-to-digital converter 20 starts to work, when the BS value is 0, the switch S11 and the switch S13 are closed, the sampling amplification module 22, the first amplification module 24, and the third amplification module 26 start to work, and output voltage from the emitter of the transistor Q1 VBE1 to the sampling and amplifying circuit 60, from the transistor Q2 output voltage VBE2 to the sampling and amplifying circuit 60, the sampling and amplifying module 22 and the first amplifying module 24 start to work, and at the same time the voltage VBE1 and the voltage VBE2 are sampled and amplified.
  • the output terminal A5 and the voltage output terminal B5 output ⁇ K1 ⁇ VBE; the third amplifying module 26 starts to work, amplifies the voltage -VBE2, and outputs the K2 times the voltage -VBE2, at the voltage output terminal A5 and the voltage output terminal of the integrating circuit 33 B5 outputs -K2 ⁇ VBE2. Then the comparator U30 outputs the BS value to the digital filter 40, and the digital filter 40 outputs the coefficient value ⁇ 'according to the received BS value.
  • Cint is the unit capacitance value of the integration capacitor C3 in FIG. 4, the sampling capacitor ⁇ C1, 1 ⁇ , and the sampling capacitor ⁇ C2, x ⁇ in FIG.
  • ⁇ VBE is the voltage value of the voltage ⁇ VBE
  • K1 is the amplification factor of the first amplification module
  • K2 is the amplification factor of the third amplification module
  • VBE is the voltage value of the voltage VBE2.
  • the switch S12 and the switch S14 are closed, the sampling amplifying module 22, the second amplifying module 25 and the fourth amplifying module 27 start to work, from the emitter output voltage VBE1 of the transistor Q1 to the sampling amplifier circuit 60, from the transistor
  • the emitter output voltage VBE2 of Q2 is sent to the sampling amplifying circuit 60, the sampling amplifying module 22 and the second amplifying module 25 start to work, and the voltage VBE1 and the voltage VBE2 are sampled and amplified at the same time.
  • the voltage output terminal A5 and the voltage output of the integrating circuit 33 The terminal B5 outputs the voltage ⁇ VBE of ⁇ K3 times to the ⁇ - ⁇ modulator 30; the fourth amplifying module 27 starts to work to amplify the voltage -VBE2, and output K4 at the voltage output terminal A5 and the voltage output terminal B5 of the integrating circuit 33 Times the voltage-VBE2 to the ⁇ - ⁇ modulator 30. Then, the BS value is output from the sigma-delta modulator 30 to the digital filter 40, and the digital filter 40 outputs the coefficient value ⁇ 'according to the received BS value.
  • Cint is the unit capacitance value of the integration capacitor C3 in FIG. 4, the sampling capacitor ⁇ C1,1 ⁇ and the sampling capacitor ⁇ C2,1 ⁇ in FIG.
  • ⁇ VBE is the voltage value of the voltage ⁇ VBE
  • K1 is the amplification factor of the first amplification module
  • K2 is the amplification factor of the third amplification module
  • VBE is the voltage value of the voltage VBE2.
  • the analog-to-digital converter 20 in this embodiment is a Sigma-Delta analog-to-digital converter, and the resolution of the existing Sigma-Delta analog-to-digital converter is 16 bits, the accuracy of the temperature sensor in the full temperature range can reach ⁇ 0.1°C, according to the Sigma-Delta ADC analog-to-digital converter, the known formula can be obtained: Among them, ⁇ 'is the coefficient value in this embodiment, Ntotoal is the total clock period of the integrating circuit 33, and N1 is the clock period of the integrating circuit 33 when the BS value is 1.
  • the amplification factor K3 of the second amplification module 25 and the amplification factor K2 of the third amplification module 26 are both 0, and the amplification factor K1 of the first amplification module 24 and the amplification factor K4 of the fourth amplification module 27 are both 1, That is, only the sampling and amplifying module 22, the first amplifying module 24, and the fourth amplifying module work.
  • the structural block diagram shown in FIG. 4 can be obtained, wherein the structural block diagram shown in FIG. 5 is compared with the structural block diagram shown in FIG. 1, the virtual module 21 does not have the second amplification module 25 and the third amplification module 26 , Switch S12 and switch S13.
  • the temperature sensor of this embodiment can redesign the circuit by changing the values of K1, K2, K3, and K4 That is, the temperature sensor of this embodiment can perform single-point calibration, so that the temperature sensor can achieve different temperature measurement accuracy in different temperature ranges without changing the resolution of the analog-to-digital converter 20.
  • Figure 7 is a diagram of the relationship between the coefficient value and temperature of this embodiment, where the coefficient ⁇ 'ranges from 0-1, and the temperature T ranges from 30°C to 45°C, that is, the temperature range of the body temperature zone, and the stability coefficient ⁇ 'It becomes larger as the temperature T increases, and the variation of the coefficient value ⁇ 'in this embodiment with the temperature T is G times the variation of the coefficient value ⁇ with the temperature T in the prior art.
  • the coefficient value ⁇ 'in this embodiment corresponds to the existing coefficient value ⁇ when the temperature T is in the range of 30°C to 45°C and is enlarged by G times, so that the temperature T is in the range of 30°C to 45°C.
  • the resolution of the analog-to-digital converter 20 does not need to reach 16-bit resolution to enable the temperature sensor to meet the temperature measurement accuracy of ⁇ 0.1°C.
  • the resolution of the analog-to-digital converter 20 reaches 12-bit resolution, which also enables the temperature sensor to meet the temperature measurement accuracy requirement of ⁇ 0.1°C, thereby improving the temperature measurement accuracy of the temperature sensor The purpose of reducing the power consumption of the temperature sensor at the same time.
  • the first amplification module 24 and the second amplification module 25 can be adjusted by adjusting the values of K1, K2, K3, and K4.
  • the amplification factors of the third amplification module 26 and the fourth amplification module 27 can achieve the effect of amplification in different temperature ranges, so that users can adjust the values of K1, K2, K3, and K4 for different temperature ranges.
  • the voltage output by the sensor front-end circuit 10 is sampled and amplified, which reduces the need for the resolution of the analog-to-digital converter 20, and enables users to further reduce the cost of redesigning the temperature sensor according to the requirements for temperature measurement accuracy in different temperature ranges Therefore, the temperature sensor can also achieve different temperature measurement accuracy in different temperature ranges without changing the resolution of the analog-to-digital converter 20.
  • the high-precision temperature sensor of the present invention can be applied to human body temperature detection, because the capacitance dynamic matching module judges according to the different values output by the BS, and then outputs different control signals to the sampling amplifier circuit, respectively sampling and amplifying the voltage generated by the sensor front-end circuit , To achieve the purpose of reducing the energy consumption of high-precision sensors.

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Abstract

一种高精度温度传感器，包括模数转换器（20），模数转换器（20）包括采样放大电路（60），采样放大电路（60）包括第一开关电容阵列电路（61）、电压输入端A1、电压输入端A2、电压输出端A3，第一开关电容阵列电路（61）包括多个开关S21、多个采样电容C1，每一开关S21的第一动触点分别与电压输入端A1电连接，每一开关S21的第二动触点分别与电压输入端A2电连接，每一开关S21的静触点分别与一个采样电容C1的第一端电连接，每一采样电容C1的第二端分别与电压输出端A3电连接。

Description

一种高精度温度传感器 技术领域
本发明涉及温度传感器领域，具体是一种高精度温度传感器。
背景技术
随着物联网时代的到来，各种可穿戴和可植入生物的医学设备开始长期用于检测人体健康，其中，应用温度传感器对人体体温进行测量，更是一项检测人体健康的重要手段。因此，人们对应用于体温测试的温度传感器测温精度的要求越来越高，例如，需要温度传感器在37℃至39℃这个温度范围内达到±0.1℃的测温精度，或者，在低于37℃和高于39℃的温度范围内达到±0.2℃的精度。
通常，高精度智能温度传感器是由传感器前端电路和模数转换器组成，其中，传感器前端电路通过晶体管例如PNP型晶体管进行测量温度，将温度信号转换为与温度信号成线性关系的电压或电流，然后将与温度信号成线性关系的电压或电流输入给模数转换器，模数转换器对输入的电压或电流进行采样，然后进行量化处理后输出离散的数字量，例如二进制编码，即温度码，所以，模数转换器量化的精度越高即温度传感器分辨率越高，量化过程中的量化误差越小，高分辨率的需求导致模数转换器的设计难度、工作量和功耗消耗越大。
现有技术中，一般采用sigma-delta模数转换器来设计高精度温度传感器，该模数转换器对表征温度的系数值μ进行量化，
Figure PCTCN2020075277-appb-000001
其中，μ的温度范围在-273℃至330℃之间，但是商用芯片工艺线各种器件模型的温度范围为-40℃至125℃，α为对ΔVBE进行放大的系数，ΔVBE为与温度成正比例线性关系的电压，VBE为与温度成反比例线性关系的电压。为了满足温度传感器在温度范围为-40℃至125℃内达到±0.1℃的测温精度，需sigma-delta模数转换器达到16位的分辨率，进一步增加了高精度温度传感器的设计难度和功耗。
技术问题
本发明的目的是提供一种低功耗、可单点校准的高精度温度传感器。
技术解决手段
为了实现上述的目的，本发明提供的一种高精度温度传感器包括传感器前端电路和模数转换器，传感器前端电路与模数转换器电连接，传感器前端电路包括电源电压输入端VDD、第一电流源电路、第二电 流源电路、三极管Q1以及三极管Q2，电源电压输入端VDD分别与第一电流源电路以及第二电流源电路的输入端电连接，第一电流源电路的输出端与三极管Q1的发射极电连接，第二电流源电路的输出端与三极管Q2的发射极电连接，三极管Q1的基极和三极管Q2的基极接地，三极管Q1的集电极和三极管Q2的集电极接地，模数转换器包括采样放大电路和动态电容匹配模块，采样放大电路包括第一开关电容阵列电路、电压输入端A1、电压输入端A2、电压输出端A3，第一开关电容阵列电路包括多个开关S21、多个电容C1，每一开关S21的第一动触点分别与电压输入端A1电连接，每一开关S21的第二动触点分别与电压输入端A2电连接，每一开关S21的静触点分别与一个电容C1的第一端电连接，每一电容C1的第二端分别与电压输出端A3电连接，每一开关S21分别接收动态电容匹配模块输出的控制信号。
进一步的方案是，模数转换器还包括Σ-Δ调制器、数字滤波器，电压输出端A3和电压输出端B3分别与Σ-Δ调制器电连接，Σ-Δ调制器分别向数字滤波器和动态匹配模块输出BS值，动态匹配模块通过判断Σ-Δ调制器输出的BS值，分别向每一开关S21、S22输出控制信号，数字滤波器对Σ-Δ调制器输出的BS值进行计数得到系数值μ’。
进一步的方案是，系数值μ’为
Figure PCTCN2020075277-appb-000002
其中，K1为第一开关电容阵列电路的第一放大系数，K2为第一开关电容阵列电路的第二放大系数，K3为第一开关电容阵列电路的第三放大系数，α为对ΔVBE进行放大的系数，ΔVBE为与温度成正比例线性关系的电压值，VBE为与温度成反比例线性关系的电压值。
进一步的方案是，Σ-Δ调制器包括电压输入端A4、电压输入端B4、电压输出端A5、电压输出端B5、积分电路、比较器U30、信号输出端E，积分电路包括开关S31、开关S41、积分电容C3、开关S32、斩波器U21、运算放大器U20、斩波器U22、开关S33、开关S43、积分电容C4、开关S42，其中，电压输入端A4与电压输出端A3电连接，电压输入端B4与电压输出端B3电连接。电压输入端A4与斩波器U21电连接，斩波器U21与运算放大器U20电连接，运算放大器U20与斩波器U22电连接，电压输出端A5和电压输出端B5分别和斩波器U22电连接，比较器U30分别与电压输出端A5和电压输出端B5电连接，比较器U30与信号输出端E电连接,开关S31的第一端和开关S41的第一端分别和电压输入端A4、B4电连接，开关S33的第二端与积分电容C3的第一端电连接，积分电容C3的第二端和开关S31的第二端分 别与比较器U30电连接，开关S32的第一端与积分电容C3的第一端电连接，开关S32的第二端与积分电容C3电连接,开关S41的第一端和开关S43的第一端分别和电压输入端B4电连接，开关S43的第二端与积分电容C4的第一端电连接，积分电容C4的第二端和开关S42的第二端分别与比较器U30电连接，开关S42的第一端与积分电容C4的第一端电连接，开关S42的第二端与积分电容C4电连接。
进一步的方案是，第一电流源电路包括MOS管M3和单刀双掷开关S1，MOS管M3的源极与电源电压输入端VDD电连接，MOS管M3的漏极与单刀双掷开关S1的静触点电连接，单刀双掷开关S1的第一动触点与三极管Q1的发射极电连接，单刀双掷开关S1的第二动触点与三极管Q2的发射极电连接。
进一步的方案是，第二电流源电路包括MOS管M4、MOS管M5、MOS管M6、MOS管M7、MOS管M8、单刀双掷开关S2、单刀双掷开关S3、单刀双掷开关S4、单刀双掷开关S5、单刀双掷开关S6，电源电压输入端VDD分别与MOS管M4的源极、MOS管M5的源极、MOS管M6的源极、MOS管M7的源极、MOS管M8的源极电连接，MOS管M4的漏极与单刀双掷开关S2的静触点电连接，单刀双掷开关S2的第一动触点与三极管Q1的发射极电连接，单刀双掷开关S2的第二动触点与三极管Q2的发射极电连接，MOS管M5的漏极与单刀双掷开关S3的静触点电连接，单刀双掷开关S3的第一动触点与三极管Q1的发射极电连接，单刀双掷开关S3的第二动触点与三极管Q2的发射极电连接，MOS管M6的漏极与单刀双掷开关S4的静触点电连接，单刀双掷开关S4的第一动触点与三极管Q1的发射极电连接，单刀双掷开关S4的第二动触点与三极管Q2的发射极电连接，MOS管M7的漏极与单刀双掷开关S5的静触点电连接，单刀双掷开关S5的第一动触点与三极管Q1的发射极电连接，单刀双掷开关S5的第二动触点与三极管Q2的发射极电连接，MOS管M8的漏极与单刀双掷开关S6的静触点电连接，单刀双掷开关S6的第一动触点与三极管Q1的发射极电连接，单刀双掷开关S6的第二动触点与三极管Q2的发射极电连接，MOS管M3的栅极与MOS管M4栅极电连接，MOS管M4栅极与MOS管M5栅极电连接，MOS管M5栅极与MOS管M6栅极电连接，MOS管M6栅极与MOS管M7栅极电连接，MOS管M7栅极与MOS管M8栅极电连接。
进一步的方案是，传感器前端电路设有动态电流镜匹配模块，动态电流镜匹配模块分别与单刀双掷开关S1、单刀双掷开关S2、单刀双掷开关S3、单刀双掷开关S4、单刀双掷开关S5、单刀双掷开关S6电连接
进一步的方案是，传感器前端电路设有偏置电路，偏置电路包括MOS管M1、MOS管M2、运算放大器U1、三极管Q3、电阻R1、电阻R2、三极管Q4，电源电压输入端VDD分别与MOS管M1的源极以及MOS管M2的源极电连接，MOS管M1的栅极与MOS管M2的栅极电连接，MOS管M2的栅极与MOS管M3的栅极电连接，MOS管M1的漏极与三极管Q3的发射极电连接，MOS管M2的漏极与电阻R1的第一端电连接，运算放大器U1的输出端分别与MOS管M1的栅极以及MOS管M2的栅极电连接，运算放大器U1的异相输入端与三极管Q3的发射极电连接，运算放大器U1的同相输入端与电阻R1的第一端电连接，电阻R1的第二端与三极管Q4的发射极电连接，三极管Q3的基极与电阻R2的第一端电连接，电阻R2的第二端与三极管Q4的基极接地，三极管Q3的集电极与三极管Q4的集电极接地。
进一步的方案是，三极管Q3和三极管Q4的面积比例为1:1，且三极管Q1的面积为三极管Q3的面积的2倍，电阻R1与电阻R2的电阻值比例为5:1。
进一步的方案是，传感器前端电路还可以设有选择器、电压输出端A以及电压输出端B，三极管Q2的发射极与选择器的第一输入端电连接，三极管Q2的发射极与选择器的第一输入端电连接，三极管Q1的发射极与选择器的第二输入端电连接，选择器的第一输出端与电压输出端A电连接，选择器的第一输出端与电压输出端B电连接。
有益效果
本发明能够通过电容动态匹配模块根据BS输出的不同值进行判断后向采样放大电路输出不同的控制信号，分别对传感器前端电路产生的电压进行采样放大，从而降低高精度传感器的能耗。
并且，本发明通过动态电容匹配模块根据BS的值对开关S11、开关S12、开关S13、以及开关S14输出控制信号，达到对下一时钟周期时传感器前端电路10输出的电压进行放大的倍数进行控制的目的。
本发明的系数值μ’为
Figure PCTCN2020075277-appb-000003
相对于相对现有技术的温度传感器的系数值
Figure PCTCN2020075277-appb-000004
放大了G倍，且在直 角坐标系上来说，系数值μ’在y轴的坐标上纵向移动了C的距离值，其中
Figure PCTCN2020075277-appb-000005
使得模数转换器的分辨率不用达到16位分辨率也能满足使温度传感器在所需的某一或某几温度区(甚至同时覆盖某几温区可实现覆盖全温区)的测量精度为±0.1℃的要求，达到满足温度传感器测量精度在所需的某一或某几温区为±0.1℃要求的同时降低功耗以及减小模拟电路设计难度和工作量的目的。
本发明使用Σ-Δ调制器能够对传感器前端电路输出的电压进行积分和判断处理后输出BS值。
此外，通过第一电流源电路能够为传感器前端电路提供稳定的偏置电流。另外，通过第二电流源电路能够为传感器前端电路提供稳定的偏置电流。
本发明的动态电流镜匹配模块通过分别控制单刀双掷开关S1、单刀双掷开关S2、单刀双掷开关S3、单刀双掷开关S4、单刀双掷开关S5、单刀双掷开关S6降低了电流镜电路中六个MOS管之间电流的不匹配，使得从三极管Q1的发射极能够输出精确的电压，从三极管Q2的发射极也能够输出精确的电压。
此外，偏置电流能够为传感器前端电路提供稳定的偏置电流和偏置电压。另外，，通过在传感器前端电路设有选择器，起到进一步产生精确的电压的作用。
附图说明
图1是本发明的高精度温度传感器实施例的第一结构框图。
图2是本发明的高精度温度传感器实施例的传感器前端电路的电原理图。
图3是本发明的高精度温度传感器实施例的采样放大电路的电原理图。
图4是本发明的高精度温度传感器实施例的Σ-Δ调制器的电原理图。
图5是本发明的高精度温度传感器实施例的第二结构框图。
图6是现有技术的温度传感器的系数值μ与温度之间的关系图。
图7是本发明的高精度温度传感器实施例的系数值μ′与温度之间的关系图。
本发明的实施方式
参见图1，本发明的高精度温度传感器包括传感器前端电路10以及模数转换器20。本实施例中采用的模数转换器20为sigma-delta模数转换器。
传感器前端电路10包括电源电压输入端VDD、第一电流源电路2、第二电流源电路4、三极管Q1以及三极管Q2，电源电压输入端VDD分别与第一电流源电路2以及第二电流源电路4的输入端电连接，第一电流源电路2的输出端与三极管Q1的发射极电连接，第二电流源电路4的输出端与三极管Q2的发射极电连接，三极管Q1的基极和三极管Q2的基极接地，三极管Q1的集电极和三极管Q2的集电极接地。电源电压通过电源电压输入端VDD向传感器前端电路10输入电压。优选的，本实施例中的三极管Q1和三极管Q2的面积比例设置为1：1。
其中，如图2所示，第一电流源电路2包括MOS管M3和单刀双掷开关S1，MOS管M3的源极与电源电压输入端VDD电连接，MOS管M3的漏极与单刀双掷开关S1的静触点电连接，单刀双掷开关S1的第一动触点与三极管Q1的发射极电连接，单刀双掷开关S1的第二动触点与三极管Q2的发射极电连接。
第二电流源电路4包括MOS管M4、MOS管M5、MOS管M6、MOS管M7、MOS管M8、单刀双掷开关S2、单刀双掷开关S3、单刀双掷开关S4、单刀双掷开关S5、单刀双掷开关S6，电源电压输入端VDD分别与MOS管M4的源极、MOS管M5的源极、MOS管M6的源极、MOS管M7的源极、MOS管M8的源极电连接，MOS管M4的漏极与单刀双掷开关S2的静触点电连接，单刀双掷开关S2的第一动触点与三极管Q1的发射极电连接，单刀双掷开关S2的第二动触点与三极管Q2的发射极电连接；MOS管M5的漏极与单刀双掷开关S3的静触点电连接，单刀双掷开关S3的第一动触点与三极管Q1的发射极电连接，单刀双掷开关S3的第二动触点与三极管Q2的发射极电连接；MOS管M6的漏极与单刀双掷开关S4的静触点电连接，单刀双掷开关S4的第一动触点与三极管Q1的发射极电连接，单刀双掷开关S4的第二动触点与三极管Q2的发射极电连接；MOS管M7的漏极与单刀双掷开关S5的静触点电连接，单刀双掷开关S5的第一动触点与三极管Q1的发射极电连接，单刀双掷开关S5的第二动触点与三极管Q2的发射极电连接；MOS管M8的漏极与单刀双掷开关S6的静触点电连接，单刀双掷开关S6的第一动触点与三极管Q1的发射极电连接，单刀双掷开关S6的第二动触点与三极管Q2的发射极电连接。
优选的，MOS管M3的栅极与MOS管M4栅极电连接，MOS管M4栅极与MOS管M5栅极电连接，MOS管M5栅极与MOS管M6栅极电连接，MOS管M6栅极与MOS管M7栅极电连接，MOS管M7栅极与MOS管M8栅极电连接。
传感器前端电路10设有动态电流镜匹配模块6，动态电流镜匹配模块6分别与单刀双掷开关S1、单刀双掷开关S2、单刀双掷开关S3、单刀双掷开关S4、单刀双掷开关S5、单刀双掷开关S6电连接。MOS管M1、MOS管M2、MOS管M3、MOS管M4、MOS管M5、MOS管M6、MOS管M7、MOS管M8组成一个电流镜电路开始工作后，由于本实施例中动态电流镜匹配模块6为数字电路，能够通过6位数字信号分别控制单刀双掷开关S1、单刀双掷开关S2、单刀双掷开关S3、单刀双掷开关S4、单刀双掷开关S5、单刀双掷开关S6的导通，动态电流镜匹配模块6中有1位数字信号与其他5位数字信号反相，即单刀双掷开关S1的静触点与第一动触点导通时，单刀双掷开关S2、单刀双掷开关S3、单刀双掷开关S4、单刀双掷开关S5、单刀双掷开关S6的静触点与第二动触点导通。这样，动态电流镜匹配模块6通过分别控制单刀双掷开关S1、单刀双掷开关S2、单刀双掷开关S3、单刀双掷开关S4、单刀双掷开关S5、单刀双掷开关S6降低了电流镜电路中六个MOS管之间电流的不匹配，使得从三极管Q1的发射极能够输出精确的电压，从三极管Q2的发射极也能够输出精确的电压。
参见图2，传感器前端电路10设有偏置电路5，偏置电路5分别与第一电流源电路2以及第二电流源电路4电连接。偏置电路5包括MOS管M1、MOS管M2、运算放大器U1、三极管Q3、电阻R1、电阻R2、三极管Q4，其中，电源电压输入端VDD分别与MOS管M1的源极以及MOS管M2的源极电连接，MOS管M1的栅极与MOS管M2的栅极电连接，MOS管M2的栅极与MOS管M3的栅极电连接，MOS管M1的漏极与三极管Q3的发射极电连接，MOS管M2的漏极与电阻R1的第一端电连接，运算放大器U1的输出端分别与MOS管M1的栅极以及MOS管M2的栅极电连接，运算放大器U1的异相输入端与三极管Q3的发射极电连接，运算放大器U1的同相输入端与电阻R1的第一端电连接，电阻R1的第二端与三极管Q4的发射极电连接，三极管Q3的基极与电阻R2的第一端电连接，电阻R2的第二端与三极管Q4的基极接地，三极管Q3的集电极与三极管Q4的集电极接地。
优选的，偏置电路5中的三极管Q3和三极管Q4的面积比例设置为1:1，且三极管Q1和三极管Q2的面积为三极管Q3和三极管Q4的面积的2倍，起到产生稳定的偏置电流的目的。且电阻R1和电阻R2的电阻值比例设置为5:1，MOS管M1和MOS管M2的面积比例设置为5:1，起到了补偿三极管Q3和三极管Q4的正向电流增益的影响。本实施例中的偏置电流5还设有斩波器U2和斩波器U3，斩波器U2和斩波器U3分别与运算放大器U1电连接，斩波器U2和斩波器U3起到减少运放放大器U1的偏移电压(offset)的作用。
传感器前端电路10还可以设有选择器8、电压输出端A以及电压输出端B，三极管Q1的发射极与选择器8的第一输入端电连接，三极管Q2的发射极与选择器8的第二输入端电连接，选择器8的第一输出端与电压输出端A电连接，选择器8的第二输出端与电压输出端B电连接，电压输出端A和电压输出端B分别与模数转换器20电连接，选择器8通过电压输出端A向模数转换器20输出电压VBE1、选择器8通过电压输出端B向模数转换器20输出电压VBE2。本实施例中的选择器8是数据选择器，起到了保持电压输出端A一直输出电压VBE1、保持电压输出端B一直输出电压VBE2的作用。
传感器前端电路10工作时，电源电压通过电源电压输入端VDD输入电压至传感器前端电路10，偏置电路5开始工作，为传感器前端电路10提供稳定的偏置电压和偏置电流，从电源电压输入端VDD分别输出电压给电流源电路2和电流源电路4，电流I1从电流源电路2流入三极管Q1的发射极，电流I2从电流源电路4流入三极管Q2的发射极，其中，电流I1的值与电流I2的值之比为1：5，从三极管Q1输出电压VBE1至模数转换器20，从三极管Q2输出电压VBE2至模数转换器20。其中，电压VBE1和电压VBE2与温度成反比例线性关系。
由上述可知，传感器前端电路10能够通过三极管Q1将温度转换为与温度成反比例线性关系的电压VBE1，传感器前端电路10能够通过三极管Q2将温度转换为与温度成反比例线性关系的电压VBE2，实际情况下，由于存在非线性因素，电压VBE1和电压VBE2与温度成近似线性关系。
下面对模数转换器20的具体结构进行介绍，参见图1，模数转换器20包括虚拟模块21、Σ-Δ调制器30、数字滤波器40、动态电容匹配模块50，三极管Q1向虚拟模块21输入电压VBE1，三极管Q2向 虚拟模块21输入电压VBE2，虚拟模块21分别对电压VBE1和电压VBE2进行采样、放大后输出给模块转换电路30，Σ-Δ调制器30对输入的两个电压进行采样、相减、积分以及比较处理后，分别向数字滤波器40、动态电容匹配模块50输出BS值，动态匹配电容模块50根据接收到的BS值向虚拟模块21输出控制信号，数字滤波器40对Σ-Δ调制器30输出的BS值进行计数后输出系数值μ′。
本实施例中的虚拟模块21包括采样放大模块22、开关S11、开关S12、开关S13、开关S14、第一放大模块24、第二放大模块25、第三放大模块26、第四放大模块27。其中，采样放大模块22用于将接收到的电压VBE1和电压VBE2进行相减计算后得到电压ΔVBE并对电压ΔVBE进行放大α倍，第一放大模块24用于将输入的电压进行放大K1倍；第二放大模块25用于将输入的电压进行放大K3倍，第三放大模块26用于将输入的电压进行放大K2倍，第四放大模块27用于将输入的电压进行放大K4倍，开关S11用于控制采样放大模块22和第一放大模块24是否工作，开关S12用于控制采样放大模块22和第二放大模块25是否工作，开关S13用于控制第三放大模块26是否工作，开关S14用于控制第四放大模块27是否工作。
优选的，本实施例中的动态电容匹配模块50是数字电路，能够通过判断输入的BS的值，分别向开关S11、开关S12、开关S13、以及开关S14输出控制信号。例如，当BS＝0时，动态电容匹配模块50分别向开关S11、开关S12、开关S13、开关S14输出控制信号，开关S11和开关S13闭合，采样放大模块22、第一放大模块24和第三放大模块26工作；当BS＝1时，动态电容匹配模块50分别向开关S11、开关S12、开关S13、开关S14输出控制信号，开关S12和开关S14闭合，采样放大模块22、第二放大模块25和第四放大模块27工作。这样，通过动态电容匹配模块50根据BS的值对开关S11、开关S12、开关S13以及开关S14输出控制信号，达到对下一时钟周期时传感器前端电路10输出的电压进行放大的倍数进行控制的目的。
本实施例中虚拟模块21的各个模块的采样、放大功能实际上由采样放大电路60实现，如图3所示，采样放大电路60包括第一开关电容阵列电路61、第二开关电容阵列电路62、电压输入端A1、电压输入端A2、电压输入端B1、电压输入端B2、电压输出端A3以及电压输出端B3。电压输入端A1、电压输入端A2和电压输入端B1、电压输入端B2通过开关分别与三极管Q1的发射极、三极管Q2的发射极 以及地电连接，开关由时钟信号Φ1、时钟信号Φ2控制，不同开关闭合时电压输入端A1、电压输入端A2、电压输入端B1、电压输入端B2分别连接到电压VBE1或者电压VBE2或者地。
具体的，当时钟信号Φ1为高电平时，电压输入端A1接地，电压输入端A2连接至三极管Q2的发射极，即连接到电压VBE2；当时钟信号Φ2为高电平时，电压输入端A1连接至三极管Q2的发射极，即连接到电压VBE2，电压输入端A2连接至三极管Q1的发射极，即连接到电压VBE1。相应的，当时钟信号Φ1为高电平时，电压输入端B1连接至三极管Q2的发射极，即连接到电压VBE2，电压输入端B2连接至三极管Q1的发射极，即连接到电压VBE1；当时钟信号Φ2为高电平时，电压输入端B1接地，电压输入端B2连接至三极管Q2的发射极，即连接到电压VBE2。
第一开关电容阵列电路61包括多个开关S21、多个采样电容C1，每一开关S21的第一动触点分别与电压输入端A1电连接，每一开关S21的第二动触点分别与电压输入端A2电连接，每一开关S21的静触点分别与一个采样电容C1的第一端电连接，每一采样电容C1的第二端分别与电压输出端A3电连接，每一开关S21分别接收动态电容匹配模块50输出的控制信号。实际上，本实施例中第一开关电容阵列电路61包括的多个开关S21为图3中的开关{S21，1}至开关{S21，x}，其中，x为根据不同的放大系数而确定的开关S21的数量。第一开关电容阵列电路61包括的多个采样电容C1为图3中采样电容{C1，1}至采样电容{C1，x}，其中，x为根据不同的放大系数而确定的采样电容C1的数量。例如，放大系数为K2，则开关S21和采样电容C1的数量为K2，K2个开关S21为图3中的开关{S21，1}至开关{S21，K2}，K2个采样电容C1为图3中的采样电容{C1，1}至采样电容{C1，K2}。
第二开关电容阵列电路62包括多个开关S22、多个采样电容C2，每一开关S22的第一动触点分别与电压输入端B1电连接，每一开关S22的第二动触点分别与电压输入端B2电连接，每一开关S22的静触点分别与一个采样电容C2的第一端电连接，每一采样电容C2的第二端分别与电压输出端B3电连接，每一开关S22分别接收动态电容匹配模块50输出的控制信号。其中，每一电容C1的电容值为单位电容值，每一采样电容C2的电容值为单位电容值。实际上，本实施例中第二开关电容阵列电路62包括的多个开关S22为图3中的开关{S22，1}至{S22，x}，其中，x为根据不同的放大系数而确定的开关S22的数量。 第二开关电容阵列电路62包括的多个采样电容C2为图3中采样电容{C2，1}至采样电容{C2，x}，其中，x为根据不同的放大系数而确定的采样电容C2的数量。以本实施例为例，本实施例需要同时产生的放大倍数为αK1和K2、αK3和K4，x取(αK1+K2)和(αK3+K4)两者中大的那者，即，如果(αK1+K2)>(αK3+K4),x取(αK1+K2)的值。
优选的，本实施例中第一开关电容阵列61和第二开关电容阵列62组成了一个差分电路，抗干扰能力更强。
采样放大电路60工作时以第一开关电容阵列电路61来进行说明，具体地，动态电容匹配模块50判断输入的BS值后向多个开关S21输出控制信号。当BS＝0，时钟信号Φ1为高电平时，开关{S21，1}至开关{S21，x}由动态电容匹配模块50输出的控制信号控制，开关{S21，1}至开关{S21，K2}的静触点与第一动触点闭合，连接到电压输入端A1，电压输入端A1此时连接到地；紧接着，时钟信号Φ2为高电平时，开关{S21，1}至开关{S21，x}由动态电容匹配模块50输出的控制信号控制，开关{S21，1}至开关{S21，K2}的静触点与第一动触点闭合，连接到电压输入端A1，电压输入端A1此时连接到电压VBE2(未使用到的电容由动态电容匹配模块50输出的控制信号控制，通过对应的开关连接到共模电平，不产生电荷量的变化)；使得电容{C1,1}至电容{C1,K2}上积累的电荷量为Q＝-K2×Cunit×VBE2；
当BS＝0，时钟信号Φ1为高电平时，开关{S21，1}至开关{S21，x}由动态电容匹配模块50输出的控制信号控制，开关{S21，(K2+1)}至开关{S21，(αK1-K2-1)}的静触点与第一动触点闭合，连接到电压输入端A2,电压输入端A2连接到电压VBE2；紧接着，时钟信号Φ2为高电平时，开关{S21，1}至开关{S21，x}由动态电容匹配模块50输出的控制信号控制，开关{S21，(K2+1)}至开关{S21，(αK1-K2-1)}的静触点与第一动触点闭合，连接到电压输入端A2，电压输入端A2此时连接到电压VBE1(未使用到的电容由动态电容匹配模块50输出的控制信号控制，通过对应的开关连接到共模电平，不产生电荷量的变化)；使得采样电容{C1，(K2+1)}至采样电容{C1，(αK1-K2-1)}上的电荷量为Q＝αK1×Cunit×(VBE2-VBE1)＝αK1×Cunit×ΔVBE；
以上积累的电荷在时钟信号Φ2为高电平时，全部转移到积分电容C3上；积分电容C3上的电荷量变为Q＝αK1×Cunit×ΔVBE-K2×Cunit×VBE。这样，通过将采样电容C1或采 样电容C2上的电荷搬移到积分电容C3上，即在积分电路33的电压输出端A5和电压输出端B5产生了输出电压。
可见，采样放大模块22和放大模块24工作时，在第一开关电容阵列电路61中通过多个开关S21接入数量为α×K1的电容C1对电压VBE1和电压VBE2同时进行采样后，对采样后输出的电压ΔVBE进行放大α×K1倍，通过将采样电容C1上的电荷搬移到积分电容C3上，即在积分电路33的电压输出端A5和电压输出端B5产生输出电压。
采样放大模块22和放大模块25工作时，在第一开关电容阵列电路61中通过多个开关S21接入数量为α×K3的电容C1对电压VBE1和电压VBE2同时进行采样后，对采样后输出的电压ΔVBE进行放大α×K3倍，通过将采样电容C1上的电荷搬移到积分电容C3上，即在积分电路33的电压输出端A5和电压输出端B5产生了输出电压。
第三放大模块26工作时，在第一开关电容阵列电路61中通过多个开关接入数量为K2的电容对电压VBE2进行采样后，对采样后输出的电压VBE2进行放大K2倍，通过将采样电容C1上的电荷搬移到积分电容C3上，即在积分电路33的电压输出端A5和B5产生了输出电压。
放大模块27工作时，在第一开关电容阵列电路61中可通过多个开关接入数量为K4的电容对电压VBE2进行采样后，对采样后输出的电压VBE2进行放大K4倍，通过将采样电容C1上的电荷搬移到积分电容C3上，即在积分电路33的电压输出端A5和电压输出端B5产生了输出电压。
本实施例中，α是一个固定的增益系数(由使用工艺的三极管特性决定)，根据实际情况选择合适数量的采样电容C1来实现。K1、K2、K3以及K4分别是一个可调整的放大系数，可以根据不同的温度范围对接入电路的采样电容C1数量进行调整来实现的。
参见图4，Σ-Δ调制器30包括电压输入端A4、电压输入端B4、积分电路33、电压输出端A5、电压输出端B5、比较器U30、信号输出端E，积分电路33包括开关S31、开关S41、积分电容C3、开关S32、斩波器U21、运算放大器U20、斩波器U22、开关S33、开关S43、积分电容C4、开关S42，其中，电压输入端A4与图3中的电压输出端A3电连接，电压输入端B4与图3中的电压输出端B3电连接。电压输入端A4和电压输入端B4分别与斩波器U21电连接，斩波器U21与运算放大器U20电连接，运算放大器U20与斩波器U22电连接，斩 波器U22分别与电压输出端A5和电压输出端B5电连接，电压输出端A5和电压输出端B5分别与比较器U30电连接，比较器U30与信号输出端E电连接,开关S31的第一端和开关S41的第二端分别和电压输入端A4电连接，开关S33的第二端与积分电容C3的第一端电连接，积分电容C3的第二端和开关S31的第二端分别与比较器U30电连接，开关S32的第一端与积分电容C3的第一端电连接，开关S32的第二端与积分电容C3电连接,开关S41的第一端和开关S43的第二端分别和电压输入端B4电连接，开关S43的第二端与积分电容C4的第一端电连接，积分电容C4的第二端和开关S42的第二端分别与比较器U30电连接，开关S42的第一端与积分电容C4的第一端电连接，开关S42的第二端与积分电容C4电连接。其中，开关S32和开关S42分别在控制信号rst为高电平时闭合，开关S31和开关S41在时钟信号Φ1为高电平时闭合，开关S33和开关S43在时钟信号Φ2为高电平时闭合，斩波器U21和斩波器U22起到在运算放大器U20进行运放工作时减少运算放大器U20的偏移电压(offset)，从而减少该偏移电压对温度传感器测温精度的影响；运算放大器U20具有利用虚拟地，即图4中的电压输入端A4和电压输入端A5，不断的将输入端的电荷尽量无损的搬运到输出端的作用。
时钟信号Φ1为高电平时，电荷通过电压输入端A1、电压输入端A2、电压输入端B1、电压输入端B2以及被选中的开关S21和开关S22转移到选中的采样电容C1和采样电容C2上；再在时钟信号Φ2为高电平时，开关S33和S43闭合，被采样到采样电容C1和采样电容C2上的电荷通过电压输入端A4和电压输入端B4转移到积分电容C3和C4上。
这样，积分电路33在输出端A5和B5产生输出电压，并输出给比较器U30，比较器U30比较A5端和B5端的两个输入电压值的大小后通过信号输出端E输出BS值。
优选的，比较器U30分别与动态电容匹配模块50以及数字滤波器40电连接，这样，比较器U30能够分别将BS值输出给动态电容匹配模块50和数字滤波器40，数字滤波器40对输入的BS值中序号值为1的个数进行计数，然后数字滤波器40输出系数值μ′，其中，数字滤波器40进行计数的周期数由模数转换器30的分辨率大小决定。
下面介绍模数转换器20工作时，如何计算出温度传感器的系数值μ′的算法公式。模数转换器20开始工作时，当BS值为0时，开关S11 和开关S13闭合，采样放大模块22、第一放大模块24以及第三放大模块26开始工作，从三极管Q1的发射极输出电压VBE1至采样放大电路60，从三极管Q2输出电压VBE2至采样放大电路60，采样放大模块22和第一放大模块24开始工作，同时对电压VBE1和电压VBE2进行采样放大处理，在积分电路33的电压输出端A5和电压输出端B5输出αK1×ΔVBE；第三放大模块26开始工作，对电压-VBE2进行放大处理，输出K2倍的电压-VBE2，在积分电路33的电压输出端A5和电压输出端B5输出-K2×VBE2。然后比较器U30输出BS值至数字滤波器40，数字滤波器40根据接收到的BS值输出系数值μ’。此时，Σ-Δ调制器30中的积分电路33处于充电状态，积分电路33累计转移的电荷量的公式是Q0＝Cint×(αK1×ΔVBE-K2×VBE)，其中，Q0是BS为0时，积分电路33累计转移的电荷量，Cint为图4中积分电容C3、图3中采样电容{C1，1}、采样电容{C2，x}的单位电容值，α为采样放大模块22的放大系数，ΔVBE为电压ΔVBE的电压值，K1为第一放大模块24的放大系数，K2为第三放大模块26的放大系数，VBE为电压VBE2的电压值。
当BS值为1时，开关S12和开关S14闭合，采样放大模块22、第二放大模块25以及第四放大模块27开始工作，从三极管Q1的发射极输出电压VBE1至采样放大电路60，从三极管Q2的发射极输出电压VBE2至采样放大电路60，采样放大模块22和第二放大模块25开始工作，同时对电压VBE1和电压VBE2进行采样放大处理，在积分电路33的电压输出端A5和电压输出端B5输出α×K3倍的电压ΔVBE至Σ-Δ调制器30；第四放大模块27开始工作，对电压-VBE2进行放大处理，在积分电路33的电压输出端A5和电压输出端B5输出K4倍的电压-VBE2至Σ-Δ调制器30。然后从Σ-Δ调制器30输出BS值至数字滤波器40，数字滤波器40根据接收到的BS值输出系数值μ’。此时，Σ-Δ调制器30中的积分电路33处于放大状态，积分电路33累计转移的电荷量的公式是Q0＝Cint×(αK3×ΔVBE-K4×VBE)，其中，Q0是BS为1时，积分电路33累计转移的电荷量，Cint为图4中积分电容C3、图3中采样电容{C1,1}、采样电容{C2,1}的单位电容值，α为采样放大模块22的放大系数，ΔVBE为电压ΔVBE的电压值，K1为第一放大模块24的放大系数，K2为第三放大模块26的放大系数，VBE为电压VBE2的电压值。
这样，当积分电路33的积分周期足够大时，积分电路33的充电时累计转移的电荷量和放电时累计转移的电荷量相加的总和为零即Q0＝Q1，可以得到公式(Ntotoal-N1)×Cint×(αK1×ΔVBE-K2×VBE)+N1×Cint×(αK3×ΔVBE-K4×VBE)＝0，其中，Ntotoal为积分电路33总的时钟周期，N1为BS值为1时，积分电路33的时钟周期。
由于本实施例中的模数转换器20是Sigma-Delta模数转换器，且现有的Sigma-Delta模数转换器的分辨率为16位时，温度传感器在全温区的精度才能达到±0.1℃，根据Sigma-Delta ADC模数转换器可以得到已知公式有
Figure PCTCN2020075277-appb-000006
其中，μ’为本实施例中系数值，Ntotoal为积分电路33总的时钟周期，N1为BS值为1时，积分电路33的时钟周期。
这样，将公式(Ntotoal-N1)×Cint×(αK1×ΔVBE-K2×VBE)+N1×Cint×(αK3×ΔVBE-K4×VBE)＝0代入已知公式
Figure PCTCN2020075277-appb-000007
中，可以得到
Figure PCTCN2020075277-appb-000008
其中,由于本实施例中的系数值μ′的范围为0-1,需满足K1>K3,K4>K2,K1-K3＝K2-K4。
整理上述公式可以得到
Figure PCTCN2020075277-appb-000009
可以令公式中的
Figure PCTCN2020075277-appb-000010
由于K1、K2、K3以及K4都是常数，则G和C也是常数。可以看出，本实施例中得到的系数值μ’相对现有技术的系数值
Figure PCTCN2020075277-appb-000011
来说，放大了G倍，且在直角坐标系上来说，系数值μ’在y轴的坐标上纵向移动了C的距离值，使得系数值μ’的值控制在0-1的范围内。
优选的，当第二放大模块25的放大系数K3和第三放大模块26的放大系数K2都为0,第一放大模块24的放大系数K1和第四放大模块27的放大系数K4都为1时，即只存在采样放大模块22、第一放大模块24、第四放大模块工作的情况。可以得到如图4所示的结构框图，其中，图5所示的结构框图相对于图1所示的结构框图来说，虚拟模块21内不设有第二放大模块25、第三放大模块26、开关S12以及开关S13。这样，将K1＝K4＝1、K2＝K3＝0分别代入公式
Figure PCTCN2020075277-appb-000012
Figure PCTCN2020075277-appb-000013
中，得到的系数值μ’为
Figure PCTCN2020075277-appb-000014
可见，第二放大模块25的放大系数K1和第三放大模块26的放大系数K2都为0,第一放大模块24和第四放大模块27的系数都为1时，本实施例中得到的系数值μ’与现有技术的系数值μ相同。
图6是现有技术的温度传感器的系数值与温度之间的关系图，其中，系数值μ的范围为0-1，温度T的范围为-40℃至125℃即全温区的温度范围，系数值μ随着温度T的增加而变大。由于此时的现有技术的温度传感器的系数值为
Figure PCTCN2020075277-appb-000015
现有技术的温度传感器需要在温度范围-40℃至125℃下达到±0.1℃的测温精度，仍需模数转换器达到16位的分辨率。由于，在本实施例中的系数值
Figure PCTCN2020075277-appb-000016
Figure PCTCN2020075277-appb-000017
在K1＝K4＝1、K2＝K3＝0的情况下与现有技术的系数值相同，可以看出，本实施例的温度传感器可以通过改变K1、K2、K3、K4的值来重新设计电路即本实施例的温度传感器可以进行单点校准，使得温度传感器在不改变模数转换器20的分辨率的情况下也能够实现在不同的温度范围内实现不同的测温精度。
图7是本实施例的系数值与温度之间的关系图，其中，系数μ’的范围为0-1，温度T的范围为30℃至45℃，即体温区的温度范围，稳定系数μ’随着温度T的增加而变大，且本实施例中的系数值μ’随温度T变化的变化量是现有技术的系数值μ随温度T变化的变化量的G倍。
由上述可知，本实施例中的系数值μ’相对应现有的系数值μ在温度T的范围为30℃至45℃放大了G倍，使得在温度T的范围为30℃至45℃下时，排除温度传感器内各个电路模块的误差影响，模数转换器20的分辨率不用达到16位的分辨率也能使得温度传感器满足测温精度为±0.1℃的要求，例如，在温度T的范围为30℃至45℃的情况下时，模数转换器20的分辨率达到12位的分辨率也能使得温度传感器满足测温精度为±0.1℃的要求，达到提高温度传感器的测温精度的同时降低温度传感器的功耗的目的。
由于本实施例中的系数值μ’中，系数值μ’的大小与常数G有关，使得本可以通过调整K1、K2、K3以及K4的值即调整第一放大模块24、第二放大模块25、第三放大模块26以及第四放大模块27的放大系数可以达到在不同的温度范围内进行放大的效果，使得用户可以针对不同的温度范围，通过调整K1、K2、K3以及K4的值来对传感器前端电路10输出的电压进行采样放大，降低了对模数转换器20分辨率的需求，且能够使得用户根据对不同温度范围下的测温精度的需求对温度传感器的重新设计的成本进一步降低，还能够在不改变模数转换器20的分辨率的情况下也能够实现温度传感器在不同的温度范围内实现不同的测温精度。
需要说明的是，以上仅为本发明的优选实施例，但发明的设计构思并不局限于此，凡利用此构思对本发明做出的非实质性修改，也均入本发明的保护范围之内。
工业应用性
本发明的高精度温度传感器能够应用于人体温度检测，由于通过电容动态匹配模块根据BS输出的不同值进行判断后向采样放大电路输出不同的控制信号，分别对传感器前端电路产生的电压进行采样放大，实现了降低高精度传感器的能耗的目的。

Claims (12)

  1. 一种高精度温度传感器，包括传感器前端电路和模数转换器，所述传感器前端电路与所述模数转换器电连接，所述传感器前端电路包括电源电压输入端VDD、第一电流源电路、第二电流源电路、三极管Q1以及三极管Q2，所述电源电压输入端VDD分别与所述第一电流源电路以及所述第二电流源电路的输入端电连接，所述第一电流源电路的输出端与所述三极管Q1的发射极电连接，所述第二电流源电路的输出端与所述三极管Q2的发射极电连接，所述三极管Q1的基极和所述三极管Q2的基极接地，所述三极管Q1的集电极和三极管Q2的集电极接地，其特征在于：
    所述模数转换器包括采样放大电路和动态电容匹配模块，所述采样放大电路包括第一开关电容阵列电路、电压输入端A1、电压输入端A2、电压输出端A3，所述第一开关电容阵列电路包括多个开关S21、多个采样电容C1，每一所述开关S21的第一动触点分别与电压输入端A1电连接，每一所述开关S21的第二动触点分别与电压输入端A2电连接，每一所述开关S21的静触点分别与一个采样电容C1的第一端电连接，每一采样电容C1的第二端分别与电压输出端A3电连接，每一所述开关S21分别接收所述动态电容匹配模块输出的控制信号。
  2. 根据权利要求1所述的一种高精度温度传感器，其特征在于：
    所述模数转换器还包括Σ-Δ调制器以及数字滤波器，所述电压输出端A3和电压输出端B3分别与所述Σ-Δ调制器电连接，所述Σ-Δ调制器分别向所述数字滤波器和所述动态匹配模块输出BS值，所述动态匹配模块接收所述Σ-Δ调制器输出的BS值后，分别向每一所述开关S21输出控制信号，所述数字滤波器接收所述Σ-Δ调制器输出的BS值后输出系数值μ’。
  3. 根据权利要求2所述的一种高精度温度传感器，其特征在于：
    所述系数值μ’为
    Figure PCTCN2020075277-appb-100001
    其中，K1为所述第一开关电容阵列电路的第一放大系数，K2为所述第一开关电容阵列电路的第二放大系数，K3为所述第一开关电容阵列电路的第三放大系数，α为对ΔVBE进行放大的系数，ΔVBE为与温度成正比例线性关系的电压值，VBE为与温度成反比例线性关系的电压值。
  4. 根据权利要求2所述的一种高精度温度传感器，其特征在于：
    所述Σ-Δ调制器包括电压输入端A4、电压输入端B4、积分电路33、电压输出端A5、电压输出端B5、比较器U30、信号输出端E，所述积分电路33包括开关S31、开关S41、积分电容C3、开关S32、斩波器U21、运算放大器U20、斩波器U22、开关S33、开关S43、积分电容C4、开关S42，所述电压输入端A4和所述电压输入端B4分别与所述斩波器U21电连接，所述斩波器U21与所述运算放大器U20电连接，所述运算放大器U20与所述斩波器U22电连接，所述斩波器U22分别与所述电压输出端A5和电压输出端B5电连接，所述电压输出端A5和电压输出端B5分别与所述比较器U30电连接，所述比较器U30与所述信号输出端E电连接,所述开关S31的第一端和所述开关S41的第二端分别和所述电压输入端A4电连接，所述开关S33的第二端与所述积分电容C3的第一端电连接，积分电容C3的第二端和开关S31的第二端分别与比较器U30电连接，开关S32的第一端与积分电容C3的第一端电连接，开关S32的第二端与积分电容C3电连接,开关S41的第一端和开关S43的第一端分别和电压输入端B4电连接，开关S43的第二端与积分电容C4的第一端电连接，积分电容C4的第二端和开关S42的第二端分别与比较器U30电连接，开关S42的第一端与积分电容C4的第一端电连接，开关S42的第二端与积分电容C4电连接。
  5. 根据权利要求1至4任一项所述的一种高精度温度传感器，其特征在于：
    所述第一电流源电路包括MOS管M3和单刀双掷开关S1，所述MOS管M3的源极与所述电源电压输入端VDD电连接，所述MOS管M3的漏极与所述单刀双掷开关S1的静触点电连接，所述单刀双掷开关S1的第一动触点与所述三极管Q1的发射极电连接，所述单刀双掷开关S1的第二动触点与所述三极管Q2的发射极电连接。
  6. 根据权利要求5所述的一种高精度温度传感器，其特征在于：
    所述第二电流源电路包括MOS管M4、MOS管M5、MOS管M6、MOS管M7、MOS管M8、单刀双掷开关S2、单刀双掷开关S3、单刀双掷开关S4、单刀双掷开关S5、单刀双掷开关S6，所述电源电压输入端VDD分别与MOS管M4的源极、MOS管M5的源极、MOS管M6的源极、MOS管M7的源极、MOS管M8的源极电连接，所述MOS管M4的漏极与所述单刀双掷开关S2的静触点电连接，所述单刀双掷开关S2的第一动触点与所述三极管Q1的发射极电连接，所述单刀双掷开关S2的第二动触点与所述三极管Q2的发射极电连接，所 述MOS管M5的漏极与所述单刀双掷开关S3的静触点电连接，所述单刀双掷开关S3的第一动触点与所述三极管Q1的发射极电连接，所述单刀双掷开关S3的第二动触点与所述三极管Q2的发射极电连接，所述MOS管M6的漏极与所述单刀双掷开关S4的静触点电连接，所述单刀双掷开关S4的第一动触点与所述三极管Q1的发射极电连接，所述单刀双掷开关S4的第二动触点与所述三极管Q2的发射极电连接，所述MOS管M7的漏极与所述单刀双掷开关S5的静触点电连接，所述单刀双掷开关S5的第一动触点与所述三极管Q1的发射极电连接，所述单刀双掷开关S5的第二动触点与所述三极管Q2的发射极电连接，所述MOS管M8的漏极与所述单刀双掷开关S6的静触点电连接，所述单刀双掷开关S6的第一动触点与所述三极管Q1的发射极电连接，所述单刀双掷开关S6的第二动触点与所述三极管Q2的发射极电连接，所述MOS管M3的栅极与所述MOS管M4栅极电连接，所述MOS管M4栅极与所述MOS管M5栅极电连接，所述MOS管M5栅极与所述MOS管M6栅极电连接，所述MOS管M6栅极与所述MOS管M7栅极电连接，所述MOS管M7栅极与所述MOS管M8栅极电连接。
  7. 根据权利要求6所述的一种高精度温度传感器，其特征在于：
    所述传感器前端电路设有动态电流镜匹配模块，所述动态电流镜匹配模块分别与所述单刀双掷开关S1、所述单刀双掷开关S2、所述单刀双掷开关S3、所述单刀双掷开关S4、所述单刀双掷开关S5、所述单刀双掷开关S6电连接。
  8. 根据权利要求6所述的一种高精度温度传感器，其特征在于：
    所述传感器前端电路设有偏置电路，所述偏置电路包括MOS管M1、MOS管M2、运算放大器U1、三极管Q3、电阻R1、电阻R2、三极管Q4，所述电源电压输入端VDD分别与所述MOS管M1的源极以及所述MOS管M2的源极电连接，所述MOS管M1的栅极与所述MOS管M2的栅极电连接，所述MOS管M2的栅极与所述MOS管M3的栅极电连接，所述MOS管M1的漏极与所述三极管Q3的发射极电连接，所述MOS管M2的漏极与所述电阻R1的第一端电连接，所述运算放大器U1的输出端分别与所述MOS管M1的栅极以及所述MOS管M2的栅极电连接，所述运算放大器U1的异相输入端与所述三极管Q3的发射极电连接，所述运算放大器U1的同相输入端与电阻R1的第一端电连接，电阻R1的第二端与三极管Q4的发射极电连接， 三极管Q3的基极与电阻R2的第一端电连接，电阻R2的第二端与三极管Q4的基极接地，三极管Q3的集电极与三极管Q4的集电极接地。
  9. 根据权利要求8所述的一种高精度温度传感器，其特征在于：
    所述三极管Q3和所述三极管Q4的面积比例为1：1。
  10. 根据权利要求8所述的一种高精度温度传感器，其特征在于：
    所述三极管Q1的面积为所述三极管Q3的面积的2倍。
  11. 根据权利要求8所述的一种高精度温度传感器，其特征在于：
    所述电阻R1与所述电阻R2的电阻值比例为5：1。
  12. 根据权利要求1至11任一项所述的一种高精度温度传感器，其特征在于：
    所述传感器前端电路还可以设有选择器、电压输出端A以及电压输出端B，所述三极管Q2的发射极与所述选择器的第一输入端电连接，所述三极管Q2的发射极与所述选择器的第一输入端电连接，所述三极管Q1的发射极与所述选择器的第二输入端电连接，所述选择器的输出端与所述电压输出端A电连接，所述选择器的第二输出端与所述电压输出端B电连接。
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