WO2020211145A1 - 一种发光元件及其制作方法、阵列基板 - Google Patents

一种发光元件及其制作方法、阵列基板 Download PDF

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WO2020211145A1
WO2020211145A1 PCT/CN2019/087753 CN2019087753W WO2020211145A1 WO 2020211145 A1 WO2020211145 A1 WO 2020211145A1 CN 2019087753 W CN2019087753 W CN 2019087753W WO 2020211145 A1 WO2020211145 A1 WO 2020211145A1
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Prior art keywords
light
emitting unit
gallium nitride
type gallium
nitride layer
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PCT/CN2019/087753
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English (en)
French (fr)
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柳铭岗
樊勇
陈书志
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020211145A1 publication Critical patent/WO2020211145A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating

Definitions

  • This application relates to the field of display technology, in particular to a light-emitting element, a manufacturing method thereof, and an array substrate.
  • Micro LED Display is a new generation of display technology.
  • the structure is a miniaturized LED array, that is, the LED structure is designed to be thin, miniaturized and arrayed to make the volume approximately the size of the current mainstream LED
  • Each pixel can be addressed and individually driven to emit light, reducing the distance of the pixel point from the original millimeter to micron level.
  • Micro-light-emitting diode displays inherit the characteristics of LEDs, and have the advantages of low power consumption, high brightness, ultra-high resolution and color saturation, fast response speed, ultra-power saving, longer life and higher efficiency.
  • the edge leakage and edge non-radiation recombination phenomenon of the small-size micro-light-emitting diode chip is more significant, which will cause the light-emitting of the micro-light-emitting diode chip.
  • the efficiency has dropped significantly.
  • the present application provides a light-emitting element, a manufacturing method thereof, and an array substrate, so as to improve the edge leakage and edge non-radiation recombination phenomenon of a small-size micro-light-emitting diode chip, thereby improving luminous efficiency.
  • inventions of the present application provide a method for manufacturing a light-emitting element.
  • the method for manufacturing a light-emitting element includes: providing a base substrate; fabricating a light-emitting unit smaller than a predetermined size on the base substrate; The side is deactivated.
  • the step of deactivating the side surface of the light-emitting unit specifically includes: performing wet etching on the side surface of the light-emitting unit for a preset time.
  • the step of wet etching the side of the light-emitting unit for a preset time includes: providing an etching solution, the etching solution being hydrofluoric acid solution, nitric acid solution, potassium hydroxide solution or sodium hydroxide solution; Put the side into the corrosive liquid for a preset length of corrosion.
  • the step of deactivating the side surface of the light-emitting unit specifically includes: annealing the side surface of the light-emitting unit, and the annealing temperature is not lower than a preset temperature.
  • the step of annealing the side surface of the light-emitting unit specifically includes: heating the side surface of the light-emitting unit to not less than 500° C. and keeping it for 3 to 5 minutes; and cooling the side surface of the light-emitting unit.
  • the step of deactivating the side surface of the light-emitting unit specifically includes: covering the side surface of the light-emitting unit with a passivation film.
  • the material of the passivation film is silicon nitride, silicon dioxide or aluminum oxide.
  • the method further includes: performing wet etching on the side surface of the light-emitting unit for a preset time; annealing the side surface of the light-emitting unit, and the annealing temperature is not lower than Preset temperature.
  • the step of fabricating a light-emitting unit smaller than a predetermined size on a base substrate specifically includes: sequentially forming an n-type gallium nitride layer, a quantum well layer, and a p-type gallium nitride layer on the base substrate; The gallium nitride layer, the quantum well layer and the n-type gallium nitride layer are etched to form at least one light-emitting unit smaller than a predetermined size.
  • the step of etching the p-type gallium nitride layer, the quantum well layer and the n-type gallium nitride layer to form at least one light-emitting unit smaller than a predetermined size specifically includes: removing the predetermined size by dry etching The p-type gallium nitride layer, the quantum well layer and the n-type gallium nitride layer in the region to form a plurality of mesa structures smaller than a predetermined size and a cutting channel located between two adjacent mesa structures, wherein the mesa structure
  • the width of the n-type gallium nitride layer is greater than the width of the p-type gallium nitride layer in the mesa structure and the width of the quantum well layer in the mesa structure; after the step of deactivating the side surface of the light-emitting unit, it further includes: A first electrode is fabricated on the p-type gallium nitride layer of the structure, and a second electrode
  • the step of fabricating a light emitting unit smaller than a predetermined size on the base substrate specifically includes: fabricating a light emitting unit smaller than 100 microns in size on the base substrate.
  • the embodiments of the present application also provide a light-emitting element, the light-emitting element comprising: a base substrate; a light-emitting unit smaller than a predetermined size, the light-emitting unit is arranged on the base substrate, and the side of the light-emitting unit passes through Deactivation treatment.
  • the light-emitting element further includes a passivation film, and the passivation film covers the side surface.
  • the material of the passivation film is silicon nitride, silicon dioxide or aluminum oxide.
  • the light-emitting unit has a mesa structure, and the mesa structure includes an n-type gallium nitride layer, a quantum well layer, and a p-type gallium nitride layer that are sequentially away from the base substrate, and the width of the n-type gallium nitride layer is greater than the width of the quantum well layer And the width of the p-type gallium nitride layer; the light-emitting element further includes: a first electrode, the first electrode is located on the p-type gallium nitride layer; a second electrode, the second electrode is located on the n-type gallium nitride layer.
  • the light-emitting unit smaller than the predetermined size is a light-emitting unit smaller than 50 microns in size.
  • the embodiments of the present application also provide an array substrate, which includes a light-emitting element and a control circuit electrically connected to the light-emitting element, wherein the light-emitting unit includes: a base substrate; The light-emitting unit is arranged on the base substrate, and the side surface of the light-emitting unit is deactivated.
  • the light-emitting element further includes a passivation film, and the passivation film covers the side surface.
  • the material of the passivation film is silicon nitride, silicon dioxide or aluminum oxide.
  • the light-emitting unit has a mesa structure, and the mesa structure includes an n-type gallium nitride layer, a quantum well layer, and a p-type gallium nitride layer that are sequentially away from the base substrate, and the width of the n-type gallium nitride layer is greater than the width of the quantum well layer And the width of the p-type gallium nitride layer; the light-emitting element further includes: a first electrode, the first electrode is located on the p-type gallium nitride layer; a second electrode, the second electrode is located on the n-type gallium nitride layer.
  • the method for manufacturing the light-emitting element provided by the present application is capable of manufacturing a light-emitting unit smaller than a preset size on a base substrate and deactivating the side surface of the light-emitting unit. Reduce side defects and dangling bonds, and then improve the edge leakage and edge non-radiation recombination phenomenon of small-size micro-light-emitting diode chips to improve luminous efficiency.
  • FIG. 1 is a schematic flowchart of a method for manufacturing a light-emitting element according to an embodiment of the present application
  • FIG. 2 is a schematic diagram of the flow of S12 in Figure 1;
  • FIG. 3 is a schematic diagram of another process of a method for manufacturing a light-emitting element according to an embodiment of the present application
  • FIG. 4 is a schematic diagram of another process of a method for manufacturing a light-emitting element according to an embodiment of the present application
  • FIG. 5 is another schematic flow chart of the manufacturing method of the light-emitting element provided by the embodiment of the present application.
  • FIG. 6 is a schematic diagram of another process of a method for manufacturing a light-emitting element according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a light-emitting element provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of another structure of a light-emitting element provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of another structure of a light-emitting element provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • the technical solution adopted in this application is to provide a method for manufacturing a light-emitting element to improve the edge leakage and edge non-radiation recombination phenomenon of the small-sized micro-light-emitting diode chip, and improve the luminous efficiency.
  • FIG. 1 is a schematic flow chart of a method for manufacturing a light-emitting element according to an embodiment of the present application.
  • the specific flow of the method for manufacturing the light-emitting element may be as follows:
  • the material of the base substrate can be sapphire, silicon carbide, silicon, gallium arsenide, zinc oxide, etc.
  • a light-emitting unit with a size of 100 microns or less is fabricated on a base substrate.
  • S12 may specifically include:
  • the metal organic chemical vapor deposition (MOCVD) method is used to first epitaxially grow a gallium nitride transition layer on a sapphire substrate, and then sequentially epitaxially grow an n-type gallium nitride layer and a quantum well on the gallium nitride transition layer Layer and p-type gallium nitride layer.
  • MOCVD metal organic chemical vapor deposition
  • the quantum well layer may include alternately grown InGaN well layers and GaN barrier layers, and the alternate period may be controlled within 7-15.
  • S122 etching the p-type gallium nitride layer, the quantum well layer and the n-type gallium nitride layer to form at least one light-emitting unit smaller than a predetermined size.
  • the p-type gallium nitride layer, the quantum well layer, and the n-type gallium nitride layer are photolithographic, dry-etched, and cleaned and removed.
  • the width of the n-type gallium nitride layer in the light-emitting unit is equal to or greater than the width of the p-type gallium nitride layer in the light-emitting unit.
  • S122 may specifically include:
  • the p-type gallium nitride layer, quantum well layer and n-type gallium nitride layer in the preset area are removed to form a plurality of mesa structures smaller than the preset size and two adjacent mesa structures
  • the width of the n-type gallium nitride layer in the mesa structure is greater than the width of the p-type gallium nitride layer in the mesa structure and the width of the quantum well layer in the mesa structure, so that it is located in the p-type gallium nitride layer
  • a partial area of the lower n-type gallium nitride layer is exposed to facilitate subsequent manufacturing processes of the light-emitting element, such as making electrodes.
  • dangling bonds and defects may be generated on the side of the light-emitting unit.
  • the light-emitting element may be a Micro LED chip, and the size of the corresponding light-emitting unit is generally less than 50 ⁇ m.
  • the size of Micro LED chips becomes smaller, and the edge effect of the chips is prominent. Therefore, the edge leakage and non-radiative recombination phenomenon caused by defects and dangling bonds on the side of the light-emitting unit will be more significant, which will seriously affect the Micro The electrical characteristics and luminous efficiency of LED chips.
  • the side surface of the light-emitting unit is deactivated to reduce the side defects and dangling bonds, thereby improving the Micro LED chip.
  • the luminous efficiency of the LED chip is improved.
  • S13 may specifically include:
  • S131 Perform wet etching on the side of the light-emitting unit for a preset time.
  • the etching liquid can be acidic etching liquids such as hydrofluoric acid (HF) and nitric acid (HNO3), and alkaline etching liquids such as potassium hydroxide (KOH) and sodium hydroxide (NaOH).
  • acidic etching liquids such as hydrofluoric acid (HF) and nitric acid (HNO3)
  • alkaline etching liquids such as potassium hydroxide (KOH) and sodium hydroxide (NaOH).
  • Type gallium nitride layer, quantum well layer and n-type gallium nitride layer it is required to select a corrosive solution with a certain corrosion strength and control the corrosion time. For example, use a 30% potassium hydroxide aqueous solution with a corrosion time of 1 second.
  • S13 may specifically include:
  • S132 Perform annealing treatment on the side surface of the light-emitting unit, and the annealing temperature is not lower than a preset temperature.
  • the annealing temperature can be 500°C and the time is 3 to 5 minutes.
  • the material on the side of the light-emitting unit is heated to a temperature higher than the critical point, so that the material on the side of the light-emitting unit is recrystallized.
  • the crystal grains on the side of the light-emitting unit can be coarsened, and then Can reduce defects and dangling bonds on the side.
  • S13 may specifically include:
  • S133 Cover the side surface of the light-emitting unit with a passivation film.
  • the material of the passivation film can be inorganic materials such as silicon nitride, silicon dioxide, and aluminum oxide.
  • silicon nitride silicon dioxide
  • aluminum oxide silicon oxide
  • a layer of silicon nitride film is deposited on the side of the light-emitting unit.
  • covering the side surface of the light-emitting unit with a passivation film can repair defects on the side surface of the light-emitting unit, and the chemical bonds in the passivation film can be combined with the dangling bonds on the side surface of the light-emitting unit. Defects and dangling bonds.
  • S131, S132 and S133 can be implemented not only individually, but also in combination to reduce defects and dangling bonds on the side of the light-emitting unit, thereby improving Micro
  • the edge leakage and edge non-radiation compound phenomena of the LED chip improve the luminous efficiency.
  • the edge effect of Micro LED chip is improved compared to the edge effect of Micro LED chip when any one of S131, S132 and S133 is implemented separately. The improvement effect is better.
  • S13 may specifically include S131 and S132 executed in sequence, or S131 and S133 executed in sequence, or S132 and S133 executed in sequence, or S131, S132 and S133 executed in sequence.
  • S12 includes the foregoing S121 and S122, and S122 is specifically: removing the p-type gallium nitride layer, quantum well layer, and n Type gallium nitride layer to form a plurality of mesa structures smaller than a preset size and a cutting channel located between two adjacent mesa structures, wherein the width of the n-type gallium nitride layer in the mesa structure is greater than the p
  • the width of the type gallium nitride layer and the width of the quantum well layer in the mesa structure, S13 includes the above S131, S132 and S133, and after S13, it may also include:
  • S14 fabricating a first electrode on the p-type gallium nitride layer of the mesa structure, and fabricating a second electrode on the n-type gallium nitride layer of the mesa structure.
  • a metal layer of chromium or aluminum is deposited on the p-type gallium nitride layer of the mesa structure to form the first electrode, and a metal layer of nickel or silver is deposited on the n-type gallium nitride layer of the mesa structure To form a second electrode.
  • the base substrate before cutting the base substrate, the base substrate can be thinned first, and then the thinned base substrate can be laser cut based on the cutting channel located between two adjacent mesa structures.
  • the light-emitting element shown in Fig. 9 was obtained.
  • the method for fabricating a light-emitting element can reduce side defects and dangling by fabricating a light-emitting unit smaller than a predetermined size on a base substrate and deactivating the side surface of the light-emitting unit. Key to improve the edge leakage and edge non-radiation recombination phenomenon of the small-size micro light emitting diode chip to improve the luminous efficiency.
  • FIG. 7 is a schematic structural diagram of a light-emitting element provided by an embodiment of the present application.
  • the light-emitting element 70 includes a base substrate 71 and a light-emitting unit 72 smaller than a predetermined size.
  • the light-emitting unit 72 is disposed on the base substrate 71, and the side surface 72A of the light-emitting unit 72 is deactivated. .
  • the light-emitting element 70 may be a Micro LED chip, and the size of the corresponding light-emitting unit 72 is generally less than 50 ⁇ m. Compared with LED chips of conventional size (1 ⁇ 10mm), the size of Micro LED chips becomes smaller, and the edge effect of the chips is prominent. Therefore, the edge leakage and non-radiative recombination phenomenon caused by defects and dangling bonds of the light-emitting unit 72 on its side surface 72A will be more significant, which will seriously affect the luminous efficiency of the Micro LED chip.
  • the side surface 72A of the light-emitting unit 72 is deactivated to reduce defects and dangling bonds on the side surface 72A, thereby improving the luminous efficiency of the Micro LED chip.
  • the method for deactivating the side surface 72A of the light-emitting unit 72 includes: performing wet etching on the side surface 72A of the light-emitting unit 72 for a preset time; performing high-temperature annealing treatment on the side surface 72A of the light-emitting unit 72;
  • the side surface 72A of the unit 72 is covered with a passivation film or the like.
  • the specific implementation of the above-mentioned various deactivation treatment methods can refer to the previous embodiments, which will not be repeated here.
  • the light-emitting unit 72 has a mesa structure, and the mesa structure 72 includes an n-type gallium nitride layer 721, a quantum well layer 722, and a p-type gallium nitride layer 723 that are sequentially away from the base substrate 71.
  • the width of the n-type gallium nitride layer 721 is greater than the width of the quantum well layer 722 and the width of the p-type gallium nitride layer 723, so that a part of the n-type gallium nitride layer 721 under the p-type gallium nitride layer 723
  • the regions are exposed to facilitate subsequent manufacturing processes of the light-emitting element 70, such as making electrodes.
  • the material of the base substrate 71 can be sapphire, silicon carbide, silicon, gallium arsenide, zinc oxide, and the like.
  • the quantum well layer 722 may include alternately grown InGaN well layers and GaN barrier layers, and the alternate period may be controlled at 7-15.
  • the light emitting element 70 may further include a first electrode 73 and a second electrode 74, wherein the first electrode 73 is located on the p-type gallium nitride layer 723, and the second electrode 74 is located on the n-type gallium nitride layer.
  • the first electrode 73 may be a chromium or aluminum metal layer
  • the second electrode 74 may be a nickel or silver metal layer.
  • the light-emitting element 70 further includes a passivation film 75, and the passivation film 75 covers the side surface 72A.
  • the material of the passivation film 75 may be inorganic materials such as silicon nitride, silicon dioxide, and aluminum oxide.
  • the side surface 72A of the light emitting unit 72 may be subjected to wet etching or high temperature annealing treatment, or the side surface 72A of the light emitting unit 72 may be subjected to wet etching first.
  • the side surface 72A of the light-emitting unit 72 is then subjected to high-temperature annealing treatment, so as to more effectively reduce the defects and dangling bonds on the side surface 72A of the light-emitting unit, thereby improving the edge leakage and edge non-radiation recombination phenomenon of the Micro LED chip and improving the luminous efficiency.
  • the light-emitting element provided in this embodiment can reduce side defects and dangling bonds by fabricating a light-emitting unit smaller than a predetermined size on a base substrate and deactivating the side surface of the light-emitting unit. Improve the edge leakage and edge non-radiation recombination phenomenon of the small-size micro-light-emitting diode chip to improve the luminous efficiency.
  • FIG. 10 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • the array substrate 90 includes a light-emitting element 91 and a control circuit electrically connected to the light-emitting element 91.
  • the light-emitting element 91 includes a base substrate and a light-emitting unit smaller than a predetermined size, wherein the light-emitting unit is disposed on the base substrate, and the side surface of the light-emitting unit is deactivated.
  • the array substrate provided in this embodiment can reduce side defects and dangling bonds by fabricating a light-emitting unit smaller than a predetermined size on a base substrate and deactivating the side surface of the light-emitting unit. Improve the edge leakage and edge non-radiation recombination phenomenon of the small-size micro-light-emitting diode chip to improve the luminous efficiency.

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Abstract

一种发光元件（70）及其制作方法、阵列基板，该发光元件（70）的制作方法包括：提供衬底基板（71）；在衬底基板（71）上制作小于预设尺寸的发光单元（72）；对发光单元（72）的侧面（72A）进行去活化处理。

Description

一种发光元件及其制作方法、阵列基板 技术领域
本申请涉及显示技术领域，具体涉及一种发光元件及其制作方法、阵列基板。
 背景技术
微发光二极体显示器(Micro LED Display)为新一代的显示技术，结构是微型化LED阵列，也就是将LED结构设计进行薄膜化、微小化与阵列化，使其体积约为目前主流LED大小的1％，每一个像素都能定址、单独驱动发光，将像素点的距离由原本的毫米级降到微米级。微发光二极体显示器承继了LED的特性，具有低功耗、高亮度、超高分辨率与色彩饱和度、反应速度快、超省电、寿命较长、效率较高等优点。
但是，在微发光二极体显示器技术中，由于芯片尺寸变小，而小尺寸微发光二极体芯片的边缘漏电和边缘非辐射复合现象比较显著，故会导致微发光二极体芯片的发光效率明显下降。
 技术问题
本申请提供了一种发光元件及其制作方法、阵列基板，以改善小尺寸微发光二极体芯片的边缘漏电和边缘非辐射复合现象，进而提高发光效率。
 技术解决方案
为了解决上述问题，本申请实施例提供了一种发光元件的制作方法，该发光元件的制作方法包括：提供衬底基板；在衬底基板上制作小于预设尺寸的发光单元；对发光单元的侧面进行去活化处理。
其中，对发光单元的侧面进行去活化处理的步骤，具体包括：对发光单元的侧面进行预设时长的湿法腐蚀。
其中，对发光单元的侧面进行预设时长的湿法腐蚀的步骤，具体包括：提供腐蚀液，腐蚀液为氢氟酸溶液、硝酸溶液、氢氧化钾溶液或氢氧化钠溶液；将发光单元的侧面放入腐蚀液中进行预设时长的腐蚀。
其中，对发光单元的侧面进行去活化处理的步骤，具体包括：对发光单元的侧面进行退火处理，且退火温度不低于预设温度。
其中，对发光单元的侧面进行退火处理的步骤，具体包括：加热发光单元的侧面至不低于500℃，并保持3~5分钟；对发光单元的侧面进行冷却。
其中，对发光单元的侧面进行去活化处理的步骤，具体包括：在发光单元的侧面上覆盖一层钝化膜。
其中，钝化膜的材质为氮化硅、二氧化硅或三氧化二铝。
其中，在发光单元的侧面上覆盖一层钝化膜的步骤之前，还包括：对发光单元的侧面进行预设时长的湿法腐蚀；对发光单元的侧面进行退火处理，且退火温度不低于预设温度。
其中，在衬底基板上制作小于预设尺寸的发光单元的步骤，具体包括：在衬底基板上，依次形成n型氮化镓层、量子阱层和p型氮化镓层；对p型氮化镓层、量子阱层和n型氮化镓层进行刻蚀，以形成至少一个小于预设尺寸的发光单元。
其中，对p型氮化镓层、量子阱层和n型氮化镓层进行刻蚀，以形成至少一个小于预设尺寸的发光单元的步骤，具体包括：通过干法刻蚀，去掉预设区域的p型氮化镓层、量子阱层和n型氮化镓层，以形成多个小于预设尺寸的台面结构和位于相邻两个台面结构之间的切割沟道，其中，台面结构中n型氮化镓层的宽度大于台面结构中p型氮化镓层的宽度和台面结构中量子阱层的宽度；在对发光单元的侧面进行去活化处理的步骤之后，还包括：在台面结构的p型氮化镓层上制作第一电极，并在台面结构的n型氮化镓层上制作第二电极；基于切割沟道对衬底基板进行切割，形成多个发光元件。
其中，在衬底基板上制作小于预设尺寸的发光单元的步骤，具体包括：在衬底基板上制作尺寸小于100微米的发光单元。
为了解决上述问题，本申请实施例还提供了一种发光元件，该发光元件，包括：衬底基板；小于预设尺寸的发光单元，发光单元设置于衬底基板上，且发光单元的侧面经过去活化处理。
其中，发光元件还包括钝化膜，钝化膜覆盖侧面。
其中，钝化膜的材质为氮化硅、二氧化硅或三氧化二铝。
其中，发光单元为台面结构，台面结构包括依次远离衬底基板的n型氮化镓层、量子阱层和p型氮化镓层，且n型氮化镓层的宽度大于量子阱层的宽度和p型氮化镓层的宽度；发光元件还包括：第一电极，第一电极位于p型氮化镓层上；第二电极，第二电极位于n型氮化镓层上。
其中，小于预设尺寸的发光单元为尺寸小于50微米的发光单元。
为了解决上述问题，本申请实施例还提供了一种阵列基板，该阵列基板包括发光元件、以及与发光元件电连接的控制电路，其中，发光单元包括：衬底基板；小于预设尺寸的发光单元，发光单元设置于衬底基板上，且发光单元的侧面经过去活化处理。
其中，发光元件还包括钝化膜，钝化膜覆盖侧面。
其中，钝化膜的材质为氮化硅、二氧化硅或三氧化二铝。
其中，发光单元为台面结构，台面结构包括依次远离衬底基板的n型氮化镓层、量子阱层和p型氮化镓层，且n型氮化镓层的宽度大于量子阱层的宽度和p型氮化镓层的宽度；发光元件还包括：第一电极，第一电极位于p型氮化镓层上；第二电极，第二电极位于n型氮化镓层上。
 有益效果
本申请的有益效果是：区别于现有技术，本申请提供的发光元件的制作方法，通过在衬底基板上制作小于预设尺寸的发光单元，并对发光单元的侧面进行去活化处理，能够减少侧面的缺陷和悬空键，进而改善小尺寸微发光二极体芯片的边缘漏电和边缘非辐射复合现象，以提高发光效率。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的发光元件的制作方法的流程示意图；
图2是图1中S12的流程示意图；
图3是本申请实施例提供的发光元件的制作方法的另一流程示意图；
图4是本申请实施例提供的发光元件的制作方法的另一流程示意图；
图5是本申请实施例提供的发光元件的制作方法的另一流程示意图；
图6是本申请实施例提供的发光元件的制作方法的另一流程示意图；
图7是本申请实施例提供的发光元件的结构示意图；
图8是本申请实施例提供的发光元件的另一结构示意图；
图9是本申请实施例提供的发光元件的另一结构示意图；
图10是本申请实施例提供的阵列基板的结构示意图。
 本发明的实施方式
下面结合附图和实施例，对本申请作进一步地详细描述。特别指出的是，以下实施例仅用于说明本申请，但不对本申请的范围进行限定。同样的，以下实施例仅为本申请的部分实施例而非全部实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本申请保护的范围。
目前，在微发光二极体显示器技术中，由于芯片尺寸变小，而小尺寸微发光二极体芯片的边缘漏电和边缘非辐射复合现象比较显著，故会导致微发光二极体芯片的发光效率明显下降。为了解决上述技术问题，本申请采用的技术方案是提供一种发光元件的制作方法，以改善小尺寸微发光二极体芯片的边缘漏电和边缘非辐射复合现象，提高发光效率。
请参阅图1，图1是本申请实施例提供的发光元件的制作方法的流程示意图，该发光元件的制作方法具体流程可以如下：
S11：提供衬底基板。
其中，衬底基板的材质可以为蓝宝石、碳化硅、硅、砷化镓、氧化锌等。
S12：在衬底基板上制作小于预设尺寸的发光单元。
例如，在衬底基板上制作尺寸在100微米以下的发光单元。
在一个实施例中，如图2所示，S12可以具体包括：
S121：在衬底基板上，依次形成n型氮化镓层、量子阱层和p型氮化镓层。
例如，采用金属有机物化学气相沉积（MOCVD）的方法，先在蓝宝石衬底上外延生长得到氮化镓过渡层，然后在氮化镓过渡层上依次外延生长得到n型氮化镓层、量子阱层和p型氮化镓层。
其中，量子阱层可以包括交替生长的InGaN阱层和GaN垒层，交替周期可以控制在7~15个。
S122：对p型氮化镓层、量子阱层和n型氮化镓层进行刻蚀，以形成至少一个小于预设尺寸的发光单元。
例如，沿p型氮化镓层至n型氮化镓层的方向，对p型氮化镓层、量子阱层和n型氮化镓层进行光刻、干法刻蚀以及清洗去胶，以得到至少一个尺寸小于100μm的发光单元，其中，发光单元中n型氮化镓层的宽度等于或大于发光单元中p型氮化镓层的宽度。
在一个具体实施例中，S122可以具体包括：
通过干法刻蚀的方法，去掉预设区域的p型氮化镓层、量子阱层和n型氮化镓层，以形成多个小于预设尺寸的台面结构和位于相邻两个台面结构之间的切割沟道，其中，台面结构中n型氮化镓层的宽度大于台面结构中p型氮化镓层的宽度和台面结构中量子阱层的宽度，使得位于p型氮化镓层下方的n型氮化镓层的局部区域暴露出来，以便于发光元件的后续制程，例如制作电极等。
S13：对发光单元的侧面进行去活化处理。
具体地，在将上述p型氮化镓层、量子阱层和n型氮化镓层分隔成至少一个小于预设尺寸的发光单元的过程中，发光单元的侧面会产生悬空键和缺陷。
在本实施例中，发光元件可以为Micro LED芯片，对应的发光单元的尺寸通常小于50μm。与常规尺寸（1~10mm）的LED芯片相比，Micro LED芯片的尺寸变小，芯片的边缘效应凸显。因此，发光单元由于其侧面存在缺陷和悬空键而导致的边缘漏电和非辐射复合现象会比较显著，进而严重影响的Micro LED芯片的电学特性和发光效率。
在本实施例中，为了改善Micro LED芯片的边缘效应，通过对发光单元的侧面进行去活化处理，以减少侧面的缺陷和悬空键，进而提高Micro LED芯片的发光效率。
在一个实施例中，如图3所示，S13可以具体包括：
S131：对发光单元的侧面进行预设时长的湿法腐蚀。
其中，腐蚀液可以使用氢氟酸（HF）、硝酸（HNO3）等酸性腐蚀液，以及氢氧化钾（KOH）、氢氧化钠（NaOH）等碱性腐蚀液。
具体地，在将发光单元放入腐蚀液中进行预设时长的湿法腐蚀时，既要保证能够减少发光单元侧面上的缺陷和悬空键，又要保证不会过度地腐蚀发光单元中的p型氮化镓层、量子阱层和n型氮化镓层。因此，要求选择具有一定的腐蚀强度的腐蚀液，以及控制腐蚀时长，例如，使用质量分数为30%的氢氧化钾水溶液，腐蚀时间1秒。
在另一个实施例中，如图4所示，S13可以具体包括：
S132：对发光单元的侧面进行退火处理，且退火温度不低于预设温度。
例如，退火温度可以为500℃，时间为3~5分钟。
具体地，将位于发光单元侧面上的材料加热至高于临界点的温度，以使发光单元侧面上的材料发生重结晶，如此，高温退火时，能够实现发光单元侧面上晶粒的粗化，进而能够减少侧面上的缺陷和悬空键。
在又一个实施例中，如图5所示，S13可以具体包括：
S133：在发光单元的侧面上覆盖一层钝化膜。
其中，钝化膜的材质可以为氮化硅、二氧化硅，三氧化二铝等无机材料。例如，在发光单元的侧面上沉积一层氮化硅薄膜。
具体地，在发光单元的侧面上覆盖一层钝化膜，能够修复发光单元侧面上的缺陷，并且钝化膜中的化学键可以与发光单元侧面上的悬空键结合，如此，以减少侧面上的缺陷和悬空键。
值得注意的是，上述S131、S132和S133不仅可以单独实施，也可以组合实施，以减少发光单元侧面上的缺陷和悬空键，进而改善Micro LED芯片的边缘漏电和边缘非辐射复合现象，提高发光效率。并且，将S131、S132和S133中两种或三种方案作为组合实施时对Micro LED芯片边缘效应的改善效果，比S131、S132和S133中任一一种方案单独实施时对Micro LED芯片边缘效应的改善效果更佳。
进一步地，当将S131、S132和S133中两种或三种方案作为组合实施时，S131、S132和S133的执行顺序为先S131再S132后S133，以更加有效地减少发光单元侧面上的缺陷和悬空键，进而改善Micro LED芯片的边缘漏电和边缘非辐射复合现象，提高发光效率。例如，S13可以具体包括依次执行的S131和S132，或者依次执行的S131和S133，或者依次执行的S132和S133，或者依次执行的S131、S132和S133。
在一个具体实施例中，如图6所示，S12包括上述S121和S122，且S122具体为：通过干法刻蚀的方法，去掉预设区域的p型氮化镓层、量子阱层和n型氮化镓层，以形成多个小于预设尺寸的台面结构和位于相邻两个台面结构之间的切割沟道，其中，台面结构中n型氮化镓层的宽度大于台面结构中p型氮化镓层的宽度和台面结构中量子阱层的宽度，S13包括上述S131、S132和S133，并且在S13之后，还可以包括：
S14：在台面结构的p型氮化镓层上制作第一电极，并在台面结构的n型氮化镓层上制作第二电极。
例如，利用电子束蒸发的方法，在台面结构的p型氮化镓层上沉积铬或铝金属层以形成第一电极，并在台面结构的n型氮化镓层上沉积镍或银金属层以形成第二电极。
S15：基于切割沟道对衬底基板进行切割，形成多个发光元件。
例如，可以在对衬底基板进行切割前，先对衬底基板进行减薄处理，然后基于位于相邻两个台面结构之间的切割沟道对减薄后的衬底基板进行激光切割，以得到如图9所示的发光元件。
区别于现有技术，本实施例提供的发光元件的制作方法，通过在衬底基板上制作小于预设尺寸的发光单元，并对发光单元的侧面进行去活化处理，能够减少侧面的缺陷和悬空键，进而改善小尺寸微发光二极体芯片的边缘漏电和边缘非辐射复合现象，以提高发光效率。
请参阅图7，图7是本申请实施例提供的发光元件的结构示意图。如图7所示，该发光元件70包括衬底基板71、以及小于预设尺寸的发光单元72，其中，发光单元72设置于衬底基板71上，且发光单元72的侧面72A经过去活化处理。
在本实施例中，发光元件70可以为Micro LED芯片，对应的发光单元72的尺寸通常小于50μm。与常规尺寸（1~10mm）的LED芯片相比，Micro LED芯片的尺寸变小，芯片的边缘效应凸显。因此，发光单元72由于其侧面72A存在缺陷和悬空键而导致的边缘漏电和非辐射复合现象会比较显著，严重影响的Micro LED芯片的发光效率。
在本实施例中，为了改善Micro LED芯片的边缘效应，通过对发光单元72的侧面72A进行去活化处理，以减少侧面72A的缺陷和悬空键，进而提高Micro LED芯片的发光效率。
具体地，对发光单元72的侧面72A进行去活化处理的方法，包括：对发光单元72的侧面72A进行预设时长的湿法腐蚀；对发光单元72的侧面72A进行高温退火处理；以及在发光单元72的侧面72A上覆盖一层钝化膜等。其中，上述各种去活化处理的方法的具体实施可以参见前面的实施例，在此不再赘述。
在一个实施例中，继续参阅图7，发光单元72为台面结构，台面结构72包括依次远离衬底基板71的n型氮化镓层721、量子阱层722和p型氮化镓层723，且n型氮化镓层721的宽度大于量子阱层722的宽度和p型氮化镓层723的宽度，如此，使得位于p型氮化镓层723下方的n型氮化镓层721的局部区域暴露出来，以便于发光元件70的后续制程，例如制作电极等。其中，衬底基板71的材质可以为蓝宝石、碳化硅、硅、砷化镓、氧化锌等。量子阱层722可以包括交替生长的InGaN阱层和GaN垒层，交替周期可以控制在7~15个。
进一步地，请参阅图8，发光元件70还可以包括第一电极73和第二电极74，其中，第一电极73位于p型氮化镓层723上，第二电极74位于n型氮化镓层721上。其中，第一电极73可以为铬或铝金属层，第二电极74可以为镍或银金属层。
在一个具体实施例中，请参阅图9，发光元件70还包括钝化膜75，钝化膜75覆盖侧面72A。其中，钝化膜75的材质可以为氮化硅、二氧化硅，三氧化二铝等无机材料。
具体地，在发光单元72的侧面72A上形成钝化膜75之前，可以对发光单元72的侧面72A进行湿法腐蚀或者高温退火处理，或者，先对发光单元72的侧面72A进行湿法腐蚀，再对发光单元72的侧面72A进行高温退火处理，如此，以更加有效地减少发光单元侧面72A上的缺陷和悬空键，进而改善Micro LED芯片的边缘漏电和边缘非辐射复合现象，提高发光效率。
区别于现有技术，本实施例提供的发光元件，通过在衬底基板上制作小于预设尺寸的发光单元，并对发光单元的侧面进行去活化处理，能够减少侧面的缺陷和悬空键，进而改善小尺寸微发光二极体芯片的边缘漏电和边缘非辐射复合现象，以提高发光效率。
请参阅图10，图10是本申请实施例提供的阵列基板的结构示意图。如图10所示，该阵列基板90包括发光元件91、以及与发光元件91电连接的控制电路。
具体地，发光元件91包括衬底基板、以及小于预设尺寸的发光单元，其中，发光单元设置于衬底基板上，且发光单元的侧面经过去活化处理。
区别于现有技术，本实施例提供的阵列基板，通过在衬底基板上制作小于预设尺寸的发光单元，并对发光单元的侧面进行去活化处理，能够减少侧面的缺陷和悬空键，进而改善小尺寸微发光二极体芯片的边缘漏电和边缘非辐射复合现象，以提高发光效率。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种发光元件的制作方法，其包括：
    提供衬底基板；
    在所述衬底基板上制作小于预设尺寸的发光单元；
    对所述发光单元的侧面进行去活化处理。
  2. 根据权利要求1 所述的制作方法，其中，对所述发光单元的侧面进行去活化处理的步骤，具体包括：
    对所述发光单元的侧面进行预设时长的湿法腐蚀。
  3. 根据权利要求2 所述的制作方法，其中，对所述发光单元的侧面进行预设时长的湿法腐蚀的步骤，具体包括：
    提供腐蚀液，所述腐蚀液为氢氟酸溶液、硝酸溶液、氢氧化钾溶液或氢氧化钠溶液；
    将所述发光单元的侧面放入所述腐蚀液中进行预设时长的腐蚀。
  4. 根据权利要求1 所述的制作方法，其中，对所述发光单元的侧面进行去活化处理的步骤，具体包括：
    对所述发光单元的侧面进行退火处理，且退火温度不低于预设温度。
  5. 根据权利要求4 所述的制作方法，其中，对所述发光单元的侧面进行退火处理的步骤，具体包括：
    加热所述发光单元的侧面至不低于500℃，并保持3~5分钟；
    对所述发光单元的侧面进行冷却。
  6. 根据权利要求1 所述的制作方法，其中，对所述发光单元的侧面进行去活化处理的步骤，具体包括：
    在所述发光单元的侧面上覆盖一层钝化膜。
  7. 根据权利要求6 所述的制作方法，其中，所述钝化膜的材质为氮化硅、二氧化硅或三氧化二铝。
  8. 根据权利要求6 所述的制作方法，其中，在所述发光单元的侧面上覆盖一层钝化膜的步骤之前，还包括：
    对所述发光单元的侧面进行预设时长的湿法腐蚀；
    对所述发光单元的侧面进行退火处理，且退火温度不低于预设温度。
  9. 根据权利要求1 所述的制作方法，其中，在所述衬底基板上制作小于预设尺寸的发光单元的步骤，具体包括：
    在所述衬底基板上，依次形成n型氮化镓层、量子阱层和p型氮化镓层；
    对所述p型氮化镓层、所述量子阱层和所述n型氮化镓层进行刻蚀，以形成至少一个小于预设尺寸的发光单元。
  10. 根据权利要求9 所述的制作方法，其中，对所述p型氮化镓层、所述量子阱层和所述n型氮化镓层进行刻蚀，以形成至少一个小于预设尺寸的发光单元的步骤，具体包括：
    通过干法刻蚀，去掉预设区域的所述p型氮化镓层、所述量子阱层和所述n型氮化镓层，以形成多个小于预设尺寸的台面结构和位于相邻两个所述台面结构之间的切割沟道，其中，所述台面结构中所述n型氮化镓层的宽度大于所述台面结构中所述p型氮化镓层的宽度和所述台面结构中所述量子阱层的宽度；
    在对所述发光单元的侧面进行去活化处理的步骤之后，还包括：
    在所述台面结构的所述p型氮化镓层上制作第一电极，并在所述台面结构的所述n型氮化镓层上制作第二电极；
    基于所述切割沟道对所述衬底基板进行切割，形成多个发光元件。
  11. 根据权利要求1 所述的制作方法，其中，在所述衬底基板上制作小于预设尺寸的发光单元的步骤，具体包括：
    在所述衬底基板上制作尺寸小于100微米的发光单元。
  12. 一种发光元件，其包括：
    衬底基板；
    小于预设尺寸的发光单元，所述发光单元设置于所述衬底基板上，且所述发光单元的侧面经过去活化处理。
  13. 根据权利要求12所述的发光元件，其中，所述发光元件还包括钝化膜，所述钝化膜覆盖所述侧面。
  14. 根据权利要求13所述的发光元件，其中，所述钝化膜的材质为氮化硅、二氧化硅或三氧化二铝。
  15. 根据权利要求12所述的发光元件，其中，所述发光单元为台面结构，所述台面结构包括依次远离所述衬底基板的n型氮化镓层、量子阱层和p型氮化镓层，且所述n型氮化镓层的宽度大于所述量子阱层的宽度和所述p型氮化镓层的宽度；
    所述发光元件还包括：
    第一电极，所述第一电极位于所述p型氮化镓层上；
    第二电极，所述第二电极位于所述n型氮化镓层上。
  16. 根据权利要求12所述的发光元件，其中，所述小于预设尺寸的发光单元为尺寸小于50微米的发光单元。
  17. 一种阵列基板，其包括发光元件、以及与所述发光元件电连接的控制电路，其中，所述发光元件包括：
    衬底基板；
    小于预设尺寸的发光单元，所述发光单元设置于所述衬底基板上，且所述发光单元的侧面经过去活化处理。
  18. 根据权利要求15所述的阵列基板，其中，所述发光元件还包括：
    钝化膜，所述钝化膜覆盖所述侧面。
  19. 根据权利要求18所述的阵列基板，其中，所述钝化膜的材质为氮化硅、二氧化硅或三氧化二铝。
  20. 根据权利要求15所述的阵列基板，其中，所述发光单元为台面结构，所述台面结构包括依次远离所述衬底基板的n型氮化镓层、量子阱层和p型氮化镓层，且所述n型氮化镓层的宽度大于所述量子阱层的宽度和所述p型氮化镓层的宽度；
    所述发光元件还包括：
    第一电极，所述第一电极位于所述p型氮化镓层上；
    第二电极，所述第二电极位于所述n型氮化镓层上。
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