WO2020211059A1 - 一种多相信号控制电路及方法 - Google Patents

一种多相信号控制电路及方法 Download PDF

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Publication number
WO2020211059A1
WO2020211059A1 PCT/CN2019/083307 CN2019083307W WO2020211059A1 WO 2020211059 A1 WO2020211059 A1 WO 2020211059A1 CN 2019083307 W CN2019083307 W CN 2019083307W WO 2020211059 A1 WO2020211059 A1 WO 2020211059A1
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Prior art keywords
signal
phase
circuit
pulse width
output
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PCT/CN2019/083307
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English (en)
French (fr)
Inventor
陈悦
汪家轲
陈亮
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201980088926.1A priority Critical patent/CN113302827B/zh
Priority to CN202310123631.1A priority patent/CN115996045A/zh
Priority to EP19924931.9A priority patent/EP3958453A4/en
Priority to PCT/CN2019/083307 priority patent/WO2020211059A1/zh
Publication of WO2020211059A1 publication Critical patent/WO2020211059A1/zh
Priority to US17/504,368 priority patent/US11558042B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • H03K5/1515—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs non-overlapping
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/084—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters using a control circuit common to several phases of a multi-phase system
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H02M3/077—Charge pumps of the Schenkel-type with parallel connected charge pump stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • This application relates to the field of electronic technology, and in particular to a multi-phase signal control circuit and method.
  • a voltage converter is a circuit topology that converts an input voltage to an output voltage according to voltage requirements, and usually includes an inductor-based voltage converter and a switched capacitor (SC) type voltage converter.
  • Voltage converters based on switched capacitor types because their main power devices are capacitors, have the advantages of high power density, fast response speed and high efficiency, so they are widely used in more and more scenarios.
  • the voltage converter based on the switched capacitor type is realized through the charge-discharge duty cycle of the capacitor.
  • the triangular wave signal and the feedback control signal determined by the error between the actual output voltage and the ideal output voltage are usually used as the input of the comparator to generate the control output power.
  • Pulse width modulation (PWM) signal and down-convert the PWM signal through a frequency divider; then, the down-frequency signal and the PWM signal are processed by an AND gate to obtain a multi-phase signal, and The frequency-reduced signal passes through a NOT gate, and then passes through another AND gate together with the PWM signal to obtain another phase signal.
  • Figure 2 is a signal timing diagram corresponding to Figure 1, taking the multi-phase signal including P1 signal and P2 signal as an example for description.
  • P1 allowable working signal represents the signal after the PWM signal is down-converted
  • P2 allowable working signal represents P1 allowing the working signal to proceed.
  • P1 allows the working signal and the PWM signal to perform the logical AND operation to generate the P1 signal
  • P2 allows the working signal and the PWM signal to perform the logical AND operation to generate the P2 signal.
  • the P1 signal and P2 signal ensure the stability of the voltage converter output by alternately charging and discharging.
  • the above method of directly reducing the frequency of the PWM signal to generate the allowable working signal of each phase is only applicable when the switching period of the PWM signal is stable.
  • the switching period of the PWM signal is unstable, the switching period of the signal after being divided by the frequency divider is also unstable. Therefore, the P1 signal and P2 signal generated by the above PWM signal and the frequency-divided PWM signal may not meet the normal working conditions of the subsequent power stage circuit, resulting in abnormal operation of the power stage circuit, such as lockup or other reliability problems.
  • the present application provides a multi-phase signal control circuit and method, which are used to solve the problem of abnormal operation of the power stage circuit when the switching period of the PWM signal is unstable in the prior art.
  • a multi-phase signal control circuit which is characterized by comprising: a signal generation circuit for generating a triangular wave signal and a phase switching signal; a comparator for comparing the triangular wave signal with a feedback control signal to output the first A pulse width modulated PWM signal, the feedback control signal is the signal fed back by the power stage circuit; a phase cut circuit, used to receive the phase switching signal and the first pulse width modulation signal to generate the first phase signal and the second phase signal, The first phase signal and the second phase signal are used to control the power stage circuit to generate an output voltage signal.
  • the phase switching signal generated by the signal generating circuit in the multiphase signal control circuit does not depend on the first PWM signal, that is, the phase switching signal is not affected by the change of the switching period of the first PWM signal. Therefore, when the switching period of the first PWM signal is unstable, the phase switching signal can still stably control the phase cut circuit to generate the first phase signal and the second phase signal, and the first phase signal and the second phase signal can satisfy The normal working conditions of the subsequent power stage circuit enable the power stage circuit to work normally and also improve the performance of the multi-phase signal control circuit.
  • the signal generating circuit includes: a signal generator for generating the triangle wave signal and a trigger signal with the same frequency as the triangle wave signal; a frequency divider for triggering the signal
  • the signal undergoes frequency division processing to obtain the phase switching signal.
  • the position of the transition edge of the trigger signal corresponds to the position of the crest or trough of the triangular wave signal.
  • the signal generating circuit can perform corresponding frequency division processing on the trigger signal generated by the signal generator through a frequency divider according to different frequency requirements, thereby obtaining a phase switching signal that meets the frequency requirements, thereby improving The accuracy of generating the phase switching signal.
  • the multi-phase signal control circuit further includes a latch, which is used to latch the first pulse width modulation signal to generate a second pulse width modulation signal, and to combine the second pulse width modulation signal The wide modulation signal is output to the phase cut circuit.
  • the foregoing possible implementation manners generate the second pulse width modulation signal by latching the first pulse width modulation signal, thereby further ensuring that the charging and discharging time of the multiphase signal generated by the phase cut circuit can meet the normal operating conditions of the power stage circuit , Thereby ensuring the load capacity of the voltage converter and the stability of the output ripple.
  • the phase cut circuit includes: a first AND gate, configured to perform a logical AND operation on the phase switching signal and the second pulse width modulation signal to output the first phase signal;
  • the first NOT gate is used to perform logical negation on the phase switching signal;
  • the second AND gate is used to perform logical AND operation on the signal after the logical negation and the second pulse width modulation signal to output the second phase signal .
  • the signal generator includes: a ring oscillator, a buffer, a first delay circuit, and an integrating circuit; wherein the ring oscillator is used to generate an oscillating signal; the buffer, Used to buffer the oscillating signal to output the clock signal; the first delay circuit is used to delay the clock signal by the first phase to output the trigger signal; the integration circuit is used to integrate the trigger signal, To output the triangular wave signal.
  • the signal generator includes: a relaxation oscillator and a first delay circuit; a relaxation oscillator for generating a clock signal and generating the triangular wave signal according to the clock signal; and a first delay circuit for receiving the clock signal , And delay the clock signal by the first phase to output the trigger signal.
  • the signal generator is further used to generate a pulse hold signal, and output the pulse hold signal to the enable terminal of the latch, and the pulse hold signal is high voltage
  • the position of the flat pulse width corresponds to the position of the high-level pulse width of the trigger signal.
  • the signal generator further includes: a second delay circuit and a D flip-flop; wherein, the second delay circuit is used to delay the clock signal by the second phase to output Clock delay signal, the second phase is equal to twice the first phase; D flip-flop, used to receive the clock signal through the clock input terminal, and the clock delay signal through the setting terminal, and according to the clock signal and the clock delay signal The pulse hold signal is generated.
  • the signal generator further includes: a second delay circuit and a logic operation circuit; wherein the second delay circuit is used to delay the clock signal by a second phase to output a clock delay signal, and the second phase is equal to the first phase Logic operation circuit, used to perform logic NOT operation on the clock delay signal, and perform logical AND operation on the signal after the operation and the clock signal to generate the pulse hold signal.
  • a second delay circuit and a logic operation circuit used to delay the clock signal by a second phase to output a clock delay signal, and the second phase is equal to the first phase Logic operation circuit, used to perform logic NOT operation on the clock delay signal, and perform logical AND operation on the signal after the operation and the clock signal to generate the pulse hold signal.
  • the high-level pulse width of the pulse hold signal is equal to any one of the following situations: twice the minimum off time, twice the minimum on time, or minimum Double the maximum value of the off time and the minimum on time.
  • the signal generator can flexibly set the high-level pulse width of the pulse hold signal according to actual requirements, thereby improving the accuracy of the pulse hold signal generated.
  • the frequency of the phase switching signal is N times that of the triangular wave signal, and N is an integer greater than or equal to 1; the result of the logical OR of the first phase signal and the second phase signal It is the first pulse width modulation signal.
  • a multi-phase signal control circuit including: a signal generating circuit for generating a triangular wave signal and a phase switching signal, the frequency of the phase switching signal is N times the triangular wave signal, and N is greater than or equal to 1. Integer; a comparator for comparing the triangle wave signal and the feedback control signal to output the first pulse width modulation PWM signal, the feedback control signal is the signal fed back by the power stage circuit; the phase cut circuit is used to use the phase switching signal to pair The first pulse width modulation performs phase-cutting processing to obtain the first phase signal and the second phase signal.
  • the result of the logical OR of the first phase signal and the second phase signal is the first pulse width modulation signal, the first phase signal and the first phase signal
  • the two-phase signal is used to control the power stage circuit to generate an output voltage signal.
  • the phase switching signal generated by the signal generating circuit in the multi-phase signal control circuit does not depend on the first PWM signal, that is, the phase switching signal is not affected by the change of the switching period of the first PWM signal.
  • the phase switching signal can still stably control the phase cut circuit to generate the first phase signal and the second phase signal that are alternately charged and discharged, the first phase signal and the second phase signal
  • the two-phase signal can meet the normal working conditions of the subsequent power stage circuit, so that the power stage circuit can normally generate a stable output voltage signal, and at the same time can ensure the load capacity of the voltage converter and the stability of the output ripple.
  • a signal generator is used to generate the triangle wave signal and a trigger signal with the same frequency as the triangle wave signal; a frequency divider is used to divide the frequency of the trigger signal , To obtain the phase switching signal, and the position of the transition edge of the trigger signal corresponds to the position of the crest or trough of the triangular wave signal.
  • the signal generating circuit can perform corresponding frequency division processing on the trigger signal generated by the signal generator through a frequency divider according to different frequency requirements, thereby obtaining a phase switching signal that meets the frequency requirements, thereby improving The accuracy of generating the phase switching signal.
  • the multi-phase signal control circuit further includes: a latch for latching the first pulse width modulation signal to output the second pulse width modulation signal, and The pulse width modulation signal is output to the phase cut circuit; optionally, the signal generator is also used to: generate a pulse hold signal, the position of the high level pulse width of the pulse hold signal can be the same as the high level pulse width of the trigger signal Position correspondence, the high-level pulse width of the pulse hold signal can be greater than or equal to the high-level pulse width of the trigger signal at the corresponding position; the latch is specifically used to latch the first pulse width modulation according to the pulse hold signal Signal to output the second pulse width modulation signal.
  • the first pulse width modulation signal is latched by the pulse hold signal to output the second pulse width modulation signal, so as to ensure that the charge and discharge time of the multiphase signal generated by the second pulse width modulation signal can meet the power requirements.
  • the minimum turn-off time and the minimum turn-on time requirements in the stage circuit ensure the load capacity of the voltage converter and the stability of the output ripple.
  • the high-level pulse width of the pulse hold signal is equal to any one of the following situations: twice the minimum off time, twice the minimum on time, or minimum Double the maximum value of the off time and the minimum on time.
  • the phase cut circuit includes: a first AND gate, configured to perform a logical AND operation on the phase switching signal and the second pulse width modulation signal to output the first phase signal; A NOT gate is used to perform a logical negation operation on the phase switching signal; a second AND gate is used to perform a logical AND operation on the signal after the logical negation operation and the second pulse width modulation signal to output a second phase signal.
  • the phase switching signal is used to phase-cut the second pulse width modulation signal, and the charge and discharge time of the generated multi-phase signal can meet the requirements for the minimum off time and minimum on time in the power stage circuit , Thereby ensuring the load capacity of the voltage converter and the stability of the output ripple.
  • the signal generator includes: a ring oscillator, a buffer, a first delay circuit, and an integrating circuit; wherein the ring oscillator is used to generate an oscillating signal; the buffer is used The oscillating signal is buffered to output the clock signal; the first delay circuit is used to delay the clock signal by the first phase to output the trigger signal; the integration circuit is used to integrate the trigger signal to The triangular wave signal is output.
  • the signal generator includes: a relaxation oscillator and a first delay circuit; a relaxation oscillator for generating a clock signal and generating the triangular wave signal according to the clock signal; a first delay circuit for receiving the clock signal, The clock signal is delayed by the first phase to output the trigger signal.
  • the signal generator further includes: a second delay circuit and a D flip-flop; wherein, the second delay circuit is configured to delay the clock signal by a second phase to output Clock delay signal, the second phase is equal to twice the first phase; D flip-flop, used to receive the clock signal through the clock input terminal, and the clock delay signal through the setting terminal, and according to the clock signal and the clock delay signal The pulse hold signal is generated.
  • the signal generator further includes: a second delay circuit and a logic operation circuit; wherein, the second delay circuit is used to delay the clock signal by a second phase to output a clock delay signal, and the second phase is equal to the first phase.
  • the logic operation circuit is used to perform a logic negation operation on the clock delay signal, and perform a logical AND operation between the calculated signal and the clock signal to generate the pulse hold signal.
  • a multi-phase signal control method comprising: generating a triangular wave signal and a phase switching signal, the frequency of the phase switching square wave signal is N times that of the triangular wave signal, and N is an integer greater than or equal to 1;
  • the triangular wave signal and the feedback control signal are compared to output a first pulse width modulation signal, the feedback control signal is related to the error between the output voltage signal and the preset voltage signal;
  • the phase switching signal is used to perform the first pulse width modulation signal Phase cut processing to obtain the first phase signal and the second phase signal, the logical OR result of the first phase signal and the second phase signal is the first pulse width modulation signal, the first phase signal and the second phase signal are used to generate the output Voltage signal.
  • generating a triangle wave signal and a phase switching signal includes: generating the triangle wave signal and a trigger signal with the same frequency as the triangle wave signal; performing frequency division processing on the trigger signal to obtain The position of the transition edge of the phase switching signal and the trigger signal corresponds to the position of the crest or trough of the triangular wave signal.
  • the method further includes: latching the first pulse width modulation signal to output a second pulse width modulation signal; correspondingly, using the phase switching signal to modulate the first pulse width modulation signal
  • the signal is subjected to phase cutting processing to obtain the first phase signal and the second phase signal, specifically: using the phase switching signal to perform phase cutting processing on the second pulse width modulation signal to obtain the first phase signal and the second phase signal.
  • the method further includes: generating a pulse hold signal, the position of the high level pulse width of the pulse hold signal corresponding to the position of the high level pulse width of the trigger signal; correspondingly, latching the first pulse width modulation Signal to output the second pulse width modulation signal, including: latching the first pulse width modulation signal according to the pulse holding signal to output the second pulse width modulation signal.
  • the high-level pulse width of the pulse hold signal is equal to any of the following situations: twice the minimum off time, twice the minimum on time, or the minimum Double the maximum value of the off time and the minimum on time.
  • phase-cutting the pulse width modulation signal by using the phase switching signal to obtain the first phase signal and the second phase signal includes: the phase switching signal and the second phase signal Perform logical AND operation on the pulse width modulation signal to output the first phase signal; perform logical NOT operation on the phase switching signal, and perform the logical AND operation on the calculated signal and the second pulse width modulation signal to output the second phase signal .
  • generating a triangle wave signal and generating a trigger signal with the same frequency as the triangle wave signal includes: generating an oscillation signal; buffering the oscillation signal to output a clock signal; The signal is delayed by the first phase to output the trigger signal; the trigger signal is integrated to output the triangle wave signal.
  • generating a triangular wave signal and generating a trigger signal with the same frequency as the triangular wave signal includes: generating a clock signal, and generating the triangular wave signal according to the clock signal; delaying the clock signal by a first phase to output the trigger signal.
  • generating the pulse hold signal includes: delaying the clock signal by a second phase to output a clock delay signal, the second phase is equal to twice the first phase; according to the clock signal and The clock delay signal generates the pulse hold signal.
  • a voltage converter in a fourth aspect, includes: and a power stage circuit, and a multiphase signal control circuit as provided in the first aspect or any possible implementation of the first aspect; wherein, The multi-phase signal control circuit is used to generate a first phase signal and a second phase signal according to the feedback control signal, and the power stage circuit is used to generate an output voltage signal according to the first phase signal and the second phase signal.
  • a voltage conversion chip in a fifth aspect, includes: a multi-phase signal control circuit as provided in the first aspect or any possible implementation of the first aspect.
  • a voltage conversion chip in a sixth aspect, includes: a power stage circuit and a multi-phase signal control circuit as provided in the first aspect or any possible implementation of the first aspect; wherein, the The multiphase signal control circuit is used to generate the first phase signal and the second phase signal according to the feedback control signal, and the power stage circuit is used to generate the output voltage signal according to the first phase signal and the second phase signal.
  • a communication device in a seventh aspect, is provided.
  • the device may be a terminal or a base station.
  • the communication device includes a processing chip and the voltage conversion chip provided in the sixth aspect, the voltage conversion chip being used to supply power to the processing chip.
  • any of the multi-phase signal control methods, voltage converters, voltage conversion chips, and communication devices provided above can all be implemented by the corresponding multi-phase signal control circuits provided above.
  • beneficial effects that can be achieved refer to the beneficial effects in the multi-phase signal control circuit provided above, which will not be repeated here.
  • Fig. 1 is a schematic structural diagram of a multi-phase signal control circuit provided by the prior art
  • Figure 2 is a signal timing diagram for generating a multiphase signal provided by the prior art
  • FIG. 3 is a schematic structural diagram of a voltage converter according to an embodiment of the application.
  • FIG. 4 is a signal sequence diagram 1 for generating a multiphase signal according to an embodiment of the application
  • FIG. 5 is a signal timing diagram 2 for generating a multiphase signal according to an embodiment of the application
  • FIG. 6 is a first structural diagram of a multi-phase signal control circuit provided by an embodiment of the application.
  • FIG. 7 is a timing diagram of a phase switching signal provided by an embodiment of the application.
  • FIG. 8 is a second structural diagram of a multi-phase signal control circuit provided by an embodiment of the application.
  • FIG. 9 is a signal sequence diagram 3 for generating a multiphase signal according to an embodiment of the application.
  • FIG. 10 is a fourth signal timing diagram for generating a multiphase signal according to an embodiment of the application.
  • FIG. 11 is a third structural diagram of a multi-phase signal control circuit provided by an embodiment of the application.
  • 12 is a signal timing diagram 5 for generating a multiphase signal according to an embodiment of the application.
  • FIG. 13 is a structural schematic diagram 1 of a signal generator provided by an embodiment of the present application.
  • FIG. 13A is a second structural diagram of a signal generator provided by an embodiment of this application.
  • FIG. 13B is a third structural schematic diagram of a signal generator provided by an embodiment of the present application.
  • FIG. 14 is a fourth structural diagram of a signal generator provided by an embodiment of the present application.
  • FIG. 14A is a fifth structural schematic diagram of a signal generator provided by an embodiment of this application.
  • FIG. 14B is a sixth structural diagram of a signal generator provided by an embodiment of the present application.
  • 15 is a schematic structural diagram of a power stage circuit provided by an embodiment of this application.
  • FIG. 16 is a schematic flowchart of a multi-phase signal control method provided by an embodiment of the application.
  • At least one refers to one or more, and “multiple” refers to two or more.
  • And/or describes the association relationship of the associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A alone exists, both A and B exist, and B exists alone, where A, B can be singular or plural.
  • the following at least one item (a) or similar expressions refers to any combination of these items, including any combination of a single item (a) or plural items (a).
  • At least one of a, b, or c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.
  • the character "/" generally indicates that the associated objects are in an "or” relationship.
  • words such as "first” and “second” do not limit the number and execution order.
  • FIG. 3 is a schematic structural diagram of a voltage converter provided by an embodiment of the application.
  • the voltage converter includes a multi-phase signal control circuit 110 and a power stage circuit 120.
  • the multi-phase signal control circuit 110 is used to generate a pulse width modulation (PWM) signal according to the feedback control signal fed back by the power stage circuit 120, and generate a multi-phase signal for alternating charging and discharging based on the PWM signal, for example,
  • the multi-phase signal may be a two-phase signal or a three-phase signal with different phases; the power stage circuit 120 is used to generate a stable output voltage signal according to the multi-phase signal.
  • PWM pulse width modulation
  • the pulse width modulation (PWM) signal is usually reduced in frequency to generate the allowable working signal of each phase; after that, Perform logic operations on the allowable working signal of each phase and the PWM signal to generate a multiphase signal that works alternately.
  • the PWM signal is logically ANDed with the P1 allowable working signal and the P2 allowable working signal to generate the P1 signal and the P2 signal.
  • the P1 signal and the P2 signal are charged and charged alternately. Discharge to ensure the stability of the voltage converter output.
  • this method is only applicable when the switching period of the PWM signal is stable and the frequency is not extreme. When the switching period of the PWM signal is unstable and the frequency is too low or too high, the allowable working signal of each phase cannot be normally generated.
  • the shortest pulse width corresponding to the high level of the PWM signal (denoted as T1 in Figure 5) and the shortest pulse width corresponding to the low level (denoted as T2) is used to ensure the reliability of the voltage converter.
  • the shortest pulse width corresponding to high level is set to be equal to the minimum on-time minTon
  • the shortest pulse width corresponding to low level is set to be equal to the minimum off-time minToff.
  • the minimum on time and minimum off time are determined by the response time of the power stage circuit to control charging and discharging. The minimum on time and minimum off time are used to avoid the output voltage signal generated by the power stage circuit between the power terminal and the ground terminal There is a short circuit.
  • the embodiment of the present application provides a multi-phase signal control circuit, which can normally generate the allowable working signals of each phase when the switching period of the PWM signal is unstable, and then work according to the PWM signal and the allowable operation of each phase
  • the signal generates a multi-phase signal of alternating charging and discharging, so that the power stage circuit can generate a stable output voltage signal according to the multi-phase signal, and at the same time can ensure the load capacity of the voltage converter and the stability of the output ripple.
  • the multi-phase signal control circuit includes a signal generation circuit 201, a comparator 202, and a phase cut circuit 203.
  • the signal generating circuit 201 is used to generate a triangular wave signal and a phase switching signal.
  • the frequency of the phase switching signal may be N times that of the triangular wave signal, and N is an integer greater than or equal to 1.
  • the signal generating circuit 201 may be used to generate a clock signal, and generate the triangular wave signal and the phase switching signal according to the clock signal.
  • the phase switching signal may be a signal generated close to the peak or valley of the triangular wave signal.
  • the phase switching The signal can be a pulse signal, a square wave signal, a sawtooth wave signal, or any specific signal.
  • the phase switching signal shown in Figure 7 (a) is a signal generated close to the peak of the triangular wave signal
  • the phase switching signal shown in Figure 7 (b) The signal is the signal generated near the trough of the triangular wave signal.
  • the signal generating circuit 201 includes a signal generator 2011 and a frequency divider 2012; the signal generator 2011 is specifically used to generate a triangle wave signal and trigger the same frequency (that is, the same frequency) as the triangle wave signal Signal (the trigger signal can be a pulse signal, a square wave signal, a sawtooth signal, or any specific signal, etc.), the position of the transition edge of the trigger signal can be the same as the position of the peak or valley of the triangle wave signal, frequency divider 2012 is specifically used to perform frequency division processing on the trigger signal to obtain the phase switching signal. It should be noted that the signal generating circuit 201 may only include the signal generator 2011.
  • the phase switching signal is the trigger signal, and the frequency of the phase switching signal is the same as the frequency of the triangular wave signal; when the signal generating circuit 201
  • the frequency of the phase switching signal is an integer multiple of the frequency of the triangular wave signal.
  • the frequency of the triangular wave signal generated by the signal generator 2011 may be stable.
  • the comparator 202 is used to compare the triangle wave signal and the feedback control signal to output a first pulse width modulation PWM signal, and the feedback control signal is a signal fed back from the power stage circuit.
  • the feedback control signal may be a signal of arbitrary waveform
  • the feedback control signal may be a signal generated by the power stage circuit according to the error between the actual output voltage and the preset output voltage, that is, the sum of the feedback control signal and the output voltage signal The error between the preset voltage signals is related.
  • the comparator 202 may be specifically used to receive the triangular wave signal generated by the signal generating circuit 201 and the feedback control signal output by the power stage circuit, and compare the triangular wave signal with the feedback control signal to output the first PWM signal. Exemplarily, the comparator 202 may output a high level when the feedback control signal is greater than the triangular wave signal, and output a low level when the feedback control signal is less than the triangular wave signal, thereby obtaining the first PWM signal.
  • the phase cut circuit 203 is used to perform phase cut processing on the first PWM signal by using the phase switching signal to obtain a first phase signal and a second phase signal.
  • the first phase signal and the second phase signal are used to control the power stage circuit to generate output Voltage signal.
  • the phase cut circuit 203 may use the phase switching signal to divide the high-level pulse width of the first PWM signal into at least one of the first phase signal or the second phase signal (for example, the first PWM signal One high-level pulse width is divided into the first phase signal, the second high-level pulse width is divided into the second phase signal, and a part of the third high-level pulse width is divided into the first phase signal , The other part is divided into the second phase signal); or, the phase cut circuit 203 can use the phase switching signal to divide the low-level pulse width of the first PWM signal, and process the two signals obtained by the division through an inverter respectively, Obtain the first phase signal and the second phase signal.
  • the result of the logical OR of the first phase signal and the second phase signal may
  • the phase cut circuit 203 may include a first AND gate 2031, a NOT gate 2032, and a second AND gate 2033; wherein, the first AND gate 2031 is used to switch the signal and the first AND gate to the phase.
  • a PWM signal is logically AND (that is, processed by an AND gate) to obtain the first phase signal P1.
  • the NOT gate 2032 is used to perform a logical NOT (that is, processed by a NOT gate) on the phase switching signal.
  • the second AND gate 2033 It is used to perform a logical AND operation between the signal obtained by the logical negation operation and the first PWM signal (that is, through the AND gate processing) to obtain the second phase signal P2.
  • the timing of each signal generated in the multi-phase signal control circuit may be as shown in FIG. 9.
  • S TR represents the triangular wave signal
  • S PH represents the phase switching signal
  • the PWM1 signal represents the first PWM signal output by the comparator 202
  • P1 represents the first phase signal output by the phase cut circuit 203
  • P2 represents the first phase signal output by the phase cut circuit 203.
  • the shortest pulse width corresponding to the high level or the shortest pulse width corresponding to the low level in the first PWM signal does not overlap with the rising and falling edges of the phase switching signal S PH , that is, the phase switching is used
  • the charge and discharge time of the P1 signal and P2 signal generated by the phase-cutting processing of the first PWM signal by the signal S PH will not be less than the minimum pulse width corresponding to the high level or the minimum pulse width corresponding to the low level in the first PWM signal.
  • minTon in Figure 9 represents the shortest pulse width corresponding to the high level in the first PWM signal
  • minToff represents the shortest pulse width corresponding to the low level in the first PWM signal
  • the discharge time in the P1 signal and the P2 signal is greater than or equal to
  • the charging time in minTon, P1 signal and P2 signal is greater than or equal to minToff, so that the power stage circuit can generate an output voltage signal according to the P1 signal and P2 signal, while ensuring the load capacity and output ripple of the voltage converter stability.
  • the phase switching signal when the rising and falling edges overlap, that is, the charge and discharge time of the P1 signal and the P2 signal generated by the phase-cutting processing of the first PWM signal by the phase switching signal S PH , there will be less than the minimum pulse width corresponding to the high level of the first PWM signal Or the minimum pulse width corresponding to the low level, at this time, the multiphase signal control circuit can specifically generate the multiphase signal in the following manner.
  • the multi-phase signal control circuit may further include: a latch 204, which is used to latch the first PWM signal to output the second PWM signal.
  • the signal generator 2011 is also used to: generate a pulse hold signal, the position of the high-level pulse width of the pulse hold signal corresponds to the position of the high-level pulse width of the trigger signal (that is, in the same time period, the pulse The high-level duration of the hold signal is greater than or equal to the high-level duration of the trigger signal), and the clock for generating the pulse hold signal can be the same as the clock for generating the triangular wave signal and the phase switching signal.
  • the aforementioned first PWM signal output by the comparator 202 may also be referred to as a PWM_CMP signal), and the latch 204 is specifically configured to latch the first PWM signal according to the pulse holding signal to output the second PWM signal, for example, a latch
  • the register 204 can be used to maintain the current state of the first PWM signal for a period of time when the first PWM signal overlaps the rising edge of the pulse hold signal, and the duration is equal to the high level pulse width of the pulse hold signal. time.
  • the phase cut circuit 203 can be specifically used to perform phase cut processing on the second PWM signal by using the phase switching signal to output the first phase signal and the second phase signal. At this time, the logic of the first phase signal and the second phase signal
  • the result of OR can be the second PWM signal.
  • the high-level pulse width of the pulse hold signal can be equal to 2 times the minimum on time (ie 2*minTon), 2 times the minimum off time (ie 2*minToff), or the minimum on time and 2 times the maximum value in the minimum off time (ie 2*max(minTon, minToff)).
  • the high-level pulse width of the pulse hold signal when the phase switching signal is a signal generated close to the valley of the triangular wave signal, can be equal to twice the minimum off time, when the phase When the switching signal is a signal generated close to the peak of the triangular wave signal, the high-level pulse width of the pulse hold signal can be equal to twice the minimum on-time.
  • the timing of each signal generated in the multi-phase signal control circuit may be as shown in FIG. 12.
  • S TR represents the triangular wave signal generated by the signal generating circuit 201
  • S PH represents the phase switching signal generated by the signal generating circuit 201
  • S HOLD represents the pulse hold signal generated by the signal generating circuit 201
  • the high-level pulse width of S HOLD is represented as 2*max(minTon, minToff)
  • PWM_CMP represents the first PWM signal output by the comparator 202
  • the PWM2 signal represents the second PWM signal output by the latch 204
  • P1 represents the first phase signal output by the phase cut circuit 203
  • P2 represents The second phase signal output by the phase cut circuit 203.
  • the PWM1 signal (ie PWM_CMP signal) is latched by the pulse hold signal S HOLD , which can make the minimum pulse width corresponding to the high level or the minimum pulse width corresponding to the low level in the output PWM2 signal larger than Or equal to the high-level pulse width of the pulse hold signal S HOLD , so that the phase switching signal S PH is used to phase-cut the PWM2 signal.
  • the charge and discharge time of the generated P1 signal and P2 signal can meet the minimum conduction of the power stage circuit Time and minimum off time requirements, so that the power stage circuit can generate a stable output voltage signal according to the P1 signal and the P2 signal, while ensuring the load capacity of the voltage converter and the stability of the output ripple.
  • the signal generator 2011 in the multi-phase signal control circuit may specifically include the following two different structures, which are specifically described below.
  • the signal generator 2011 may include: a ring oscillator 11, a buffer 12, a first delay circuit 13, and an integration circuit 14.
  • the ring oscillator 11 is used to output an oscillating signal.
  • the ring oscillator 11 may be an N-stage ring oscillator including N NOT gates. The output and input terminals of the N NOT gates are connected end to end, and N is greater than Or an integer equal to 3.
  • the buffer 12 is used to receive the oscillation signal generated by the ring oscillator and buffer the oscillation signal to output a clock signal.
  • buffering the oscillation signal may specifically refer to shaping the waveform of the oscillation signal.
  • the first delay circuit 13 is configured to receive the clock signal and delay the clock signal by a first phase to output a trigger signal.
  • the integrating circuit 14 is used for integrating the trigger signal to generate a triangular wave signal.
  • the signal generator 2011 may further include: a second delay circuit 15 and a D flip-flop 16.
  • the second delay circuit 15 is used to delay the clock signal output by the buffer 12 by a second phase to output a clock delay signal, and the second phase is equal to twice the first phase.
  • the D flip-flop 16 is used to receive the clock signal output by the buffer 12 through the clock input terminal (CLK), receive the clock delay signal output by the second delay circuit 15 through the setting terminal (RESET), and according to the clock signal and the clock delay signal A pulse hold signal is generated, and the pulse hold signal is output from the Q output terminal of the D flip-flop 16, and the D input terminal of the D flip-flop 16 is set to a high level "1".
  • the signal generator 2011 may further include: a second delay circuit 15 and a logic operation circuit 17, and the logic operation circuit 17 includes a NOT gate 171 and an AND gate 172.
  • the second delay circuit 15 is used to delay the clock signal output by the buffer 12 by a second phase to output a clock delay signal, and the second phase is equal to twice the first phase.
  • the logic operation circuit 17 is used to perform a logical NOT operation on the clock delay signal output by the second delay circuit 15 through the NOT gate 171, and perform a logical AND operation on the calculated signal and the clock signal output by the buffer 12 through the AND gate 172, To generate a pulse hold signal.
  • a in FIGS. 13, 13A and 13B can represent the clock signal output by the buffer 12
  • B can represent the trigger signal output by the first delay circuit 13
  • C can represent the clock output by the second delay circuit 15. Delay the signal.
  • the signal generator 2011 may include: a relaxation oscillator 21 and a first delay circuit 22.
  • the relaxation oscillator 21 is used to generate a clock signal, and a triangular wave signal is generated according to the clock signal;
  • the first delay circuit 22 is used to receive the clock signal output by the relaxation oscillator 21 and delay the clock signal by a first phase to Output trigger signal.
  • the relaxation oscillator 21 may include a charging and discharging circuit 211, a first comparator 212, a second comparator 213 and an RS flip-flop 214; wherein the Q output terminal of the RS flip-flop 214 is used to control the power supply of the charging and discharging circuit 211 (When the Q output terminal is high, the power terminal switch is closed, and the power terminal charges the capacitor through the charging current), the QB output terminal of the RS flip-flop 214 is used to control the switch of the ground terminal of the charging and discharging circuit (when the QB output When the terminal is low, the switch at the ground terminal is closed, and the ground terminal discharges the capacitor through the discharge current); the output terminal of the charging and discharging circuit 211 is connected to an input terminal of the first comparator 212 and an input terminal of the second comparator 213 respectively Connected, the other input terminal of the first comparator 212 is used to receive a high reference voltage, the other input terminal of the second comparator 213 is used to receive a low reference
  • the signal generator 2011 may further include: a second delay circuit 23 and a D flip-flop 24.
  • the second delay circuit 23 is used to delay the clock signal output by the relaxation oscillator 21 by a second phase to output a clock delay signal, and the second phase is equal to twice the first phase.
  • the D flip-flop 24 is used to receive the clock signal output by the relaxation oscillator 21 through the clock input terminal (CLK), receive the clock delay signal output by the second delay circuit 23 through the setting terminal (RESET), and delay according to the clock signal and the clock
  • CLK clock input terminal
  • REET setting terminal
  • the signal generates a pulse hold signal, which is output from the Q output terminal of the D flip-flop 24, and the D input terminal of the D flip-flop 24 is set to a high level "1".
  • the signal generator 2011 may further include: a second delay circuit 23 and a logic operation circuit 25, and the logic operation circuit 25 includes a NOT gate 251 and an AND gate 252.
  • the second delay circuit 23 is used to delay the clock signal output by the relaxation oscillator 21 by a second phase to output a clock delay signal, and the second phase is equal to twice the first phase.
  • the logic operation circuit 25 is used to perform a logical NOT operation on the clock delay signal output by the second delay circuit 23 through the NOT gate 251, and perform a logical AND operation on the signal after the operation and the clock signal output by the relaxation oscillator 21 through the AND gate 252 , To generate pulse hold signal.
  • A can represent the clock signal output by the relaxation oscillator 21
  • B can represent the trigger signal output by the first delay circuit 22
  • C can represent the output of the second delay circuit 23 The clock delay signal.
  • the power stage circuit includes: a first signal control circuit, a second signal control circuit, and A voltage output circuit between the first signal control signal and the second signal control circuit.
  • the first signal control circuit may include: a first capacitor C1, two switches (represented as SW11 and SW12 in FIG. 15) controlled by the first phase signal P1, and the inverse signal of the first phase signal. Control the two switches (shown as SW13 and SW14 in Figure 15).
  • the first signal control circuit can be used to receive the first phase signal P1, and according to the first phase signal P1 and the inverse signal of the first phase signal Control multiple switches (ie SW11 to SW14) in the first signal control circuit.
  • the second signal control circuit can include: a second capacitor C2, two switches (represented as SW21 and SW22 in FIG. 15) controlled by the second phase signal P2, and the inverse signal of the second phase signal. Control the two switches (shown as SW23 and SW24 in Figure 15).
  • the second signal control circuit is capable of receiving the second phase signal P2, and according to the second phase signal P2 and the inverse signal of the second phase signal Control multiple switches (ie SW21 to SW24) in the second signal control circuit.
  • the voltage output circuit may include: an inductor L, a third capacitor C3, and a switch controlled by an N signal (represented as SW0 in FIG. 15), and the N signal is the inverse signal of the PWM signal.
  • One end of the inductor L and one end of the switch SW0 are connected to the coupling end LX of the first control circuit and the second control circuit, the other end of the switch SW0 is coupled to the ground end, and the other end of the inductor L is connected to one end of the third capacitor C3.
  • the coupling is used as a voltage output terminal, and the other terminal of the third capacitor C3 is coupled to the ground terminal.
  • the inverse signal of the first phase signal when it is high level, SW11 and SW12 are both open, SW13 and SW14 are both closed, the two ends of the first capacitor C1 are power and ground (GND) respectively, so the power supply charges the first capacitor C1; in the first phase signal P1 is High level, inverse signal of first phase signal At low level, both SW11 and SW12 are closed, SW13 and SW14 are both open, and the two ends of the first capacitor C1 are the LX ends of the power supply and the inductor L respectively.
  • the lower board of the first capacitor C1 After the power is connected, the voltage of the LX terminal connected to the upper plate is twice the power supply voltage.
  • the working principle of the second signal control circuit is similar to the working principle of the first signal control circuit, and will not be repeated in the embodiment of the present application.
  • the first phase signal P1 and the second phase signal P2 are obtained by phase-cutting the PWM signal, when the PWM signal is high, one of the first phase signal P1 and the second phase signal P2 is always high. Therefore, the first phase signal P1 and the second phase signal P2 work alternately through logic to ensure that the voltage at the LX terminal is always twice the power terminal voltage.
  • the inverse signal N of the PWM signal is at a high level. At this time, at the LX terminal node, the inductor L is in a discharge state.
  • the embodiments of the present application also provide a voltage converter.
  • the structure of the voltage converter can be referred to as shown in FIG. 3 above.
  • the voltage converter may include: as shown in FIG. 6, FIG. 8 or FIG.
  • the power stage circuit can be used to generate an output voltage signal according to the first phase signal and the second phase signal.
  • the present application also provides a voltage conversion chip.
  • the structure of the voltage conversion chip can be seen in FIG. 3 above.
  • the voltage conversion chip may include: FIG. 6, FIG. 8 or FIG. 11
  • the voltage conversion chip may further include a power stage circuit, and the structure of the power stage circuit may be as shown in FIG. 15.
  • the present application also provides a communication device.
  • the device may be a terminal or a base station.
  • the device may include: a processing chip and the voltage conversion chip provided above.
  • the voltage conversion chip uses To power the processing chip.
  • Fig. 16 is a multiphase signal control method provided by an embodiment of the application. The method includes the following steps: S301-S303.
  • S301 Generate a triangle wave signal and a phase switching signal.
  • generating a triangular wave signal and a phase switching signal may specifically include: generating a triangular wave signal and generating a trigger signal according to the triangular wave signal; performing frequency division processing on the trigger signal to obtain the phase switching signal and the transition edge of the trigger signal
  • the position of is corresponding to the position of the peak or valley of the triangular wave signal, the frequency of the phase-switched square wave signal is N times of the triangular wave signal, and N is an integer greater than or equal to 1.
  • S302 Compare the triangle wave signal and the feedback control signal to output a first pulse width modulation signal, where the feedback control signal is related to the error between the output voltage signal and the preset voltage signal.
  • S303 Generate a first phase signal and a second phase signal according to the phase switching signal and the first pulse width modulation signal.
  • the result of the logical OR of the first phase signal and the second phase signal is the first pulse width modulation signal, and the first phase signal and the second phase signal are used to generate the output voltage signal.
  • the method further includes: latching the first pulse width modulation signal to generate a second pulse width modulation signal; correspondingly, generating the first phase signal and the second phase signal according to the phase switching signal and the first pulse width modulation signal
  • the signal is specifically: generating a first phase signal and a second phase signal according to the phase switching signal and the second pulse width modulation signal.
  • the method further includes: generating a pulse hold signal, the position of the high-level pulse width of the pulse hold signal may correspond to the position of the high-level pulse width of the trigger signal; correspondingly, the lock
  • the storing of the first pulse width modulation signal to generate the second pulse width modulation signal may specifically include: latching the first pulse width modulation signal according to the pulse holding signal to output the second pulse width modulation signal.
  • the high-level pulse width of the pulse hold signal is equal to any one of the following situations: two times the minimum off time, two times the minimum on time, or one of the minimum off time and the minimum on time Twice the maximum value.
  • the first phase signal and the second phase signal are generated according to the phase switching signal and the first pulse width modulation signal, specifically: performing a logical AND operation on the phase switching signal and the second pulse width modulation signal to Output a first phase signal; perform a logical NOT operation on the phase switching signal, and perform a logical AND operation on the calculated signal and the second pulse width modulation signal to output a second phase signal.
  • generating a triangle wave signal and generating a trigger signal with the same frequency as the triangle wave signal may specifically be: generating an oscillation signal; buffering the oscillation signal to output a clock signal; delaying the clock signal The first phase is to output the trigger signal; the trigger signal is integrated to output the triangle wave signal.
  • generating a triangular wave signal and generating a trigger signal with the same frequency as the triangular wave signal may specifically be: generating a clock signal, and generating the triangular wave signal according to the clock signal; delaying the clock signal by the first One phase to output the trigger signal.
  • generating the pulse hold signal may specifically include: delaying the clock signal by a second phase to output a clock delay signal, the second phase is equal to twice the first phase; the clock signal and the clock delay signal are respectively Input the clock input terminal and setting terminal of the D flip-flop to generate the pulse hold signal.
  • generating a pulse hold signal may specifically include: delaying the clock signal by a second phase to output a clock delay signal, the second phase being equal to twice the first phase; performing a logical NOT operation on the clock delay signal, and Perform a logical AND operation between the calculated signal and the clock signal to generate the pulse hold signal.
  • the generated phase switching signal does not depend on the first PWM signal, that is, the phase switching signal is not affected by the change of the switching period of the first PWM signal. Therefore, when the switching period of the first PWM signal is unstable, the phase switching of the first PWM signal by the phase switching signal can still stably generate the first phase signal and the second phase signal that are alternately charged and discharged.
  • the phase signal and the second phase signal can meet the normal operating conditions of the subsequent power stage circuit, so that the power stage circuit can generate a stable output voltage signal according to the first phase signal and the second phase signal, while also ensuring voltage conversion The load capacity of the device and the stability of the output ripple.
  • circuit and method can be implemented in other ways.
  • the circuit embodiments described above are merely illustrative.
  • the division of the described modules or units is only a logical function division, and there may be other divisions in actual implementation, such as multiple units or components. It can be combined or integrated into another device, or some features can be omitted or not implemented.
  • the units described as separate parts may or may not be physically separate.
  • the parts displayed as units may be one physical unit or multiple physical units, that is, they may be located in one place, or they may be distributed to multiple different places. . Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

Abstract

本申请提供一种多相信号控制电路及方法，涉及电子技术领域，用于解决现有技术中在PWM信号的开关周期不稳定时，造成后级功率级电路工作异常的问题。该多相信号控制电路，包括：比较器，用于比较所述三角波信号和反馈控制信号，以输出第一脉宽调制信号，所述反馈控制信号为功率级电路反馈的信号；切相电路，用于接收所述相位切换信号和所述第一脉宽调制信号，以产生第一相位信号和第二相位信号，所述第一相位信号和所述第二相位信号用于控制所述功率级电路生成输出电压信号。

Description

一种多相信号控制电路及方法 技术领域
本申请涉及电子技术领域，尤其涉及一种多相信号控制电路及方法。
背景技术
电压转换器是一种根据电压需求将输入电压转换为输出电压的电路拓扑，通常包括基于电感类型的电压转换器和基于开关电容(switched capacitor，SC)类型的电压转换器。基于开关电容类型的电压转换器，因为其主功率器件为电容，具有功率密度高、响应速度快和高效率等优点，因此在越来越多的场景中被广泛使用。其中，基于开关电容类型的电压转换器是通过电容的充电-放电工作循环来实现的，但由于充电时间的存在会限制电压转换器连续输出的能力和输出纹波，因此，通常采用两相或者多相交替工作来保证输出的稳定性。
如图1所示，现有的基于开关电容类型的电压转换器中，通常是将三角波信号和由实际输出电压与理想输出电压误差决定的反馈控制信号作为比较器的输入来产生控制输出功率的脉宽调制(pulse width modulation，PWM)信号，并通过分频器对该PWM信号进行降频处理；之后，将降频后的信号与该PWM信号经过一个与门处理得到一个多相信号，以及将降频后的信号先经过一个非门，再与该PWM信号一起经过另一个与门处理，得到另一个相位信号。图2为图1对应的信号时序图，以多相信号包括P1信号和P2信号为例进行说明，P1允许工作信号表示PWM信号降频处理后的信号，P2允许工作信号表示P1允许工作信号进行逻辑非运算之后的信号，P1允许工作信号与PWM信号进行逻辑与运算产生P1信号，P2允许工作信号与PWM信号进行逻辑与运算产生P2信号。P1信号和P2信号通过交替充电和放电来保证电压转换器输出的稳定性。
但是，上述利用PWM信号直接降频产生各个相位的允许工作信号的方法，仅适用于PWM信号的开关周期稳定的情况下。当PWM信号的开关周期不稳定时，其经过分频器进行分频后的信号的开关周期也不稳定。因此，通过上述PWM信号和分频后的PWM信号产生的P1信号和P2信号，可能无法满足后级功率级电路正常工作条件，造成功率级电路工作异常，例如锁死或者其他可靠性问题。
发明内容
本申请提供一种多相信号控制电路及方法，用于解决现有技术中在PWM信号的开关周期不稳定时，造成功率级电路工作异常的问题。
第一方面，提供一种多相信号控制电路，其特征在于，包括：信号发生电路，用于产生三角波信号和相位切换信号；比较器，用于比较该三角波信号和反馈控制信号，以输出第一脉宽调制PWM信号，该反馈控制信号为功率级电路反馈的信号；切相电路，用于接收该相位切换信号和第一脉宽调制信号，以产生第一相位信号和第二相位信号，第一相位信号和所述第二相位信号用于控制该功率级电路生成输出电压信号。
上述技术方案中，该多相信号控制电路中的信号发生电路产生的相位切换信号不 依赖于第一PWM信号，即该相位切换信号不受第一PWM信号的开关周期变化的影响。因此，当第一PWM信号开关周期不稳定的时候，该相位切换信号依然可以稳定地控制切相电路产生第一相位信号和第二相位信号，该第一相位信号和该第二相位信号能够满足后级功率级电路正常工作条件，从而使得功率级电路能够正常工作，同时也提高了该多相信号控制电路的性能。
在第一方面的一种可能的实现方式中，该信号发生电路包括：信号发生器，用于产生该三角波信号、和与该三角波信号同频的触发信号；分频器，用于对该触发信号进行分频处理，以得到该相位切换信号。可选的，该触发信号的跳变沿的位置与该三角波信号的波峰或波谷的位置对应。上述可能的实现方式，该信号发生电路可以根据不同的频率需求，通过分频器对信号发生器产生的触发信号进行相应的分频处理，从而得到满足该频率需求的相位切换信号，从而提高了产生该相位切换信号的准确性。
在第一方面的一种可能的实现方式中，该多相信号控制电路还包括：锁存器，用于锁存第一脉宽调制信号以产生第二脉宽调制信号，并将第二脉宽调制信号输出至该切相电路。上述可能的实现方式，通过锁存第一脉宽调制信号以产生第二脉宽调制信号，从而能够进一步保证该切相电路产生的多相信号的充放电时间能够满足功率级电路的正常工作条件，进而保证电压转换器的带载能力和输出纹波的稳定性。
在第一方面的一种可能的实现方式中，该切相电路包括：第一与门，用于对该相位切换信号和第二脉宽调制信号进行逻辑与运算，以输出第一相位信号；第一非门，用于对该相位切换信号进行逻辑非运算；第二与门，用于将该逻辑非运算后的信号和第二脉宽调制信号进行逻辑与运算，以输出第二相位信号。上述可能的实现方式提供的切相电路的结构简单有效，从而在一定程度上能够简化该多相信号控制电路的结构。
在第一方面的一种可能的实现方式中，该信号发生器包括：环形振荡器、缓冲器、第一延时电路和积分电路；其中，环形振荡器，用于产生振荡信号；缓冲器，用于对该振荡信号进行缓冲，以输出时钟信号；第一延时电路，用于将该时钟信号延迟第一相位，以输出该触发信号；积分电路，用于对该触发信号进行积分处理，以输出该三角波信号。或者，该信号发生器包括：张弛振荡器和第一延时电路；张弛振荡器，用于产生时钟信号，并根据该时钟信号产生该三角波信号；第一延时电路，用于接收该时钟信号，并将该时钟信号延迟第一相位，以输出该触发信号。上述可能的实现方式，能够提高信号发生器设计的多样性和灵活性，从而进一步提高该多相信号控制电路设计的多样性和灵活性。
在第一方面的一种可能的实现方式中，该信号发生器还用于：产生脉冲保持信号，并将该脉冲保持信号输出至该锁存器的使能端，该脉冲保持信号的高电平脉宽的位置与该触发信号的高电平脉宽的位置对应。上述可能的实现方式，能够在该相位切换信号的升降沿与第一脉宽调制信号的高电平脉宽发生重叠时，保证该切相电路产生的第一相位信号和第二相位信号能够满足功率级电路正常工作的要求。
在第一方面的一种可能的实现方式中，该信号发生器还包括：第二延时电路和D触发器；其中，第二延时电路，用于将时钟信号延迟第二相位，以输出时钟延迟信号，第二相位等于第一相位的两倍；D触发器，用于通过时钟输入端接收该时钟信号，及通过设置端接收该时钟延迟信号，并根据该时钟信号和该时钟延迟信号产生该脉冲保 持信号。或者，该信号发生器还包括：第二延时电路和逻辑运算电路；其中，第二延时电路，用于将时钟信号延迟第二相位，以输出时钟延迟信号，第二相位等于第一相位的两倍；逻辑运算电路，用于对该时钟延迟信号进行逻辑非运算，并将运算后的信号和该时钟信号进行逻辑与运算，以产生该脉冲保持信号。上述可能的实现方式，能够进一步提高信号发生器设计的多样性和灵活性，从而进一步提高该多相信号控制电路设计的多样性和灵活性。
在第一方面的一种可能的实现方式中，该脉冲保持信号的高电平脉宽等于以下情况中的任一项：最小关断时间的两倍、最小导通时间的两倍、或者最小关断时间和最小导通时间中最大值的两倍。上述可能的实现方式中，能够使得该信号发生器根据实际需求灵活地设置该脉冲保持信号的高电平脉宽，从而提高了产生的脉冲保持信号的准确性。
在第一方面的一种可能的实现方式中，该相位切换信号的频率是该三角波信号的N倍，N为大于或等于1的整数；第一相位信号和第二相位信号的逻辑或的结果为第一脉宽调制信号。上述可能的实现方式，能够使得该切换电路产生的第一相位信号和第二相位信号满足功率级电路正常工作的要求，同时提高该多相信号控制电路的性能。
第二方面，提供一种多相信号控制电路，包括：信号发生电路，用于产生三角波信号和相位切换信号，该相位切换信号的频率是该三角波信号的N倍，N为大于或等于1的整数；比较器，用于比较该三角波信号和反馈控制信号，以输出第一脉宽调制PWM信号，该反馈控制信号为功率级电路反馈的信号；切相电路，用于利用该相位切换信号对第一脉宽调制进行切相处理，以得到第一相位信号和第二相位信号，第一相位信号和第二相位信号的逻辑或的结果为第一脉宽调制信号，第一相位信号和第二相位信号用于控制该功率级电路生成输出电压信号。上述技术方案中，该多相信号控制电路中的信号发生电路产生的相位切换信号不依赖于第一PWM信号，即该相位切换信号不受第一PWM信号的开关周期变化的影响。因此，当第一PWM信号开关周期不稳定的时候，该相位切换信号依然可以稳定地控制切相电路产生交替充电和放电的第一相位信号和第二相位信号，该第一相位信号和该第二相位信号能够满足后级功率级电路正常工作条件，从而使得功率级电路能够正常产生稳定的输出电压信号，同时也能够保证电压转换器的带载能力和输出纹波的稳定性。
在第二方面的一种可能的实现方式中，信号发生器，用于产生该三角波信号、和与该三角波信号同频的触发信号；分频器，用于并对该触发信号进行分频处理，以得到该相位切换信号，该触发信号的跳变沿的位置与该三角波信号的波峰或波谷的位置对应。上述可能的实现方式，该信号发生电路可以根据不同的频率需求，通过分频器对信号发生器产生的触发信号进行相应的分频处理，从而得到满足该频率需求的相位切换信号，从而提高了产生该相位切换信号的准确性。
在第二方面的一种可能的实现方式中，该多相信号控制电路还包括：锁存器，用于锁存第一脉宽调制信号，以输出第二脉宽调制信号，并将第二脉宽调制信号输出至切相电路；可选的，信号发生器还用于：产生脉冲保持信号，该脉冲保持信号的高电平脉宽的位置可以与该触发信号的高电平脉宽的位置对应，该脉冲保持信号的高电平脉宽可以大于或等于对应位置上的该触发信号的高电平脉宽；锁存器，具体用于根据 该脉冲保持信号锁存第一脉宽调制信号，以输出第二脉宽调制信号。上述可能的实现方式，通过脉冲保持信号锁存第一脉宽调制信号，以输出第二脉宽调制信号，从而能够保证利用第二脉宽调制信号产生的多相信号的充放电时间能够满足功率级电路中对于最小关断时间和最小导通时间的要求，进而保证电压转换器的带载能力和输出纹波的稳定性。
在第二方面的一种可能的实现方式中，该脉冲保持信号的高电平脉宽等于以下情况中的任一项：最小关断时间的两倍、最小导通时间的两倍、或者最小关断时间和最小导通时间中最大值的两倍。上述可能的实现方式，能够使得该信号发生器根据实际需求灵活地设置该脉冲保持信号的高电平脉宽，从而提高了产生的脉冲保持信号的准确性。
在第二方面的一种可能的实现方式中，切相电路包括：第一与门，用于对该相位切换信号和第二脉宽调制信号进行逻辑与运算，以输出第一相位信号；第一非门，用于对该相位切换信号进行逻辑非运算；第二与门，用于将逻辑非运算后的信号和第二脉宽调制信号进行逻辑与运算，以输出第二相位信号。上述可能的实现方式中，利用该相位切换信号对第二脉宽调制信号进行切相，产生的多相信号的充放电时间能够满足功率级电路中对于最小关断时间和最小导通时间的要求，进而保证电压转换器的带载能力和输出纹波的稳定性。
在第二方面的一种可能的实现方式中，信号发生器包括：环形振荡器、缓冲器、第一延时电路和积分电路；其中，环形振荡器，用于产生振荡信号；缓冲器，用于对该振荡信号进行缓冲，以输出时钟信号；第一延时电路，用于将该时钟信号延迟第一相位，以输出该触发信号；积分电路，用于对该触发信号进行积分处理，以输出该三角波信号。或者，信号发生器包括：张弛振荡器和第一延时电路；张弛振荡器，用于产生时钟信号，并根据该时钟信号产生该三角波信号；第一延时电路，用于接收该时钟信号，并将该时钟信号延迟第一相位，以输出该触发信号。上述可能的实现方式，能够提高信号发生器设计的多样性和灵活性，从而进一步提高该多相信号控制电路设计的多样性和灵活性。
在第二方面的一种可能的实现方式中，信号发生器还包括：第二延时电路和D触发器；其中，第二延时电路，用于将该时钟信号延迟第二相位，以输出时钟延迟信号，第二相位等于第一相位的两倍；D触发器，用于通过时钟输入端接收该时钟信号，及通过设置端接收该时钟延迟信号，并根据该时钟信号和该时钟延迟信号产生该脉冲保持信号。或者，该信号发生器还包括：第二延时电路和逻辑运算电路；其中，第二延时电路，用于将该时钟信号延迟第二相位，以输出时钟延迟信号，第二相位等于第一相位的两倍；该逻辑运算电路，用于对该时钟延迟信号进行逻辑非运算，并将运算后的信号和该时钟信号进行逻辑与运算，以产生该脉冲保持信号。上述可能的实现方式，能够进一步提高信号发生器设计的多样性和灵活性，从而进一步提高该多相信号控制电路设计的多样性和灵活性。
第三方面，提供一种多相信号控制方法，该方法包括：产生三角波信号和相位切换信号，该相位切换方波信号的频率是该三角波信号的N倍，N为大于或等于1的整数；比较该三角波信号和反馈控制信号，以输出第一脉宽调制信号，该反馈控制信号 与输出电压信号和预设电压信号之间的误差有关；利用该相位切换信号对第一脉宽调制信号进行切相处理，得到第一相位信号和第二相位信号，第一相位信号和第二相位信号的逻辑或结果为第一脉宽调制信号，第一相位信号和第二相位信号用于生成该输出电压信号。
在第三方面的一种可能的实现方式中，产生三角波信号和相位切换信号，包括：产生该三角波信号、和与该三角波信号同频的触发信号；对该触发信号进行分频处理，以得到该相位切换信号，该触发信号的跳变沿的位置与该三角波信号的波峰或波谷的位置对应。
在第三方面的一种可能的实现方式中，该方法还包括：锁存第一脉宽调制信号，以输出第二脉宽调制信号；相应的，利用该相位切换信号对第一脉宽调制信号进行切相处理，得到第一相位信号和第二相位信号，具体为：利用该相位切换信号对第二脉宽调制信号进行切相处理，得到第一相位信号和第二相位信号。可选的，该方法还包括：产生脉冲保持信号，该脉冲保持信号的高电平脉宽的位置与该触发信号的高电平脉宽的位置对应；相应的，锁存第一脉宽调制信号，以输出第二脉宽调制信号，包括：根据该脉冲保持信号锁存第一脉宽调制信号，以输出第二脉宽调制信号。
在第三方面的一种可能的实现方式中，该脉冲保持信号的高电平脉宽等于以下情况中的任一项：最小关断时间的两倍、最小导通时间的两倍、或者最小关断时间和最小导通时间中最大值的两倍。
在第三方面的一种可能的实现方式中，利用该相位切换信号对该脉宽调制信号进行切相处理，得到第一相位信号和第二相位信号，包括：对该相位切换信号和第二脉宽调制信号进行逻辑与运算，以输出第一相位信号；对该相位切换信号进行逻辑非运算，并将运算后的信号和第二脉宽调制信号进行逻辑与运算，以输出第二相位信号。
在第三方面的一种可能的实现方式中，产生三角波信号、以及产生与该三角波信号同频的触发信号，包括：产生振荡信号；对该振荡信号进行缓冲，以输出时钟信号；将该时钟信号延迟第一相位，以输出该触发信号；对该触发信号进行积分处理，以输出该三角波信号。
或者，产生三角波信号、以及产生与该三角波信号同频的触发信号，包括：产生时钟信号，并根据该时钟信号产生该三角波信号；将该时钟信号延迟第一相位，以输出该触发信号。
在第三方面的一种可能的实现方式中，产生脉冲保持信号，包括：将时钟信号延迟第二相位，以输出时钟延迟信号，第二相位等于第一相位的两倍；根据该时钟信号和该时钟延迟信号产生该脉冲保持信号。
第四方面，提供一种电压转换器，该电压转换器包括：和功率级电路，以及如第一方面或者第一方面的任一种可能的实现方式所提供的多相信号控制电路；其中，该多相信号控制电路用于根据反馈控制信号产生第一相位信号和第二相位信号，该功率级电路用于根据第一相位信号和第二相位信号生成输出电压信号。
第五方面，提供一种电压转换芯片，该电压转换芯片包括：如第一方面或者第一方面的任一种可能的实现方式所提供的多相信号控制电路。
第六方面，提供一种电压转换芯片，该电压转换芯片包括：功率级电路、以及如 第一方面或者第一方面的任一种可能的实现方式所提供的多相信号控制电路；其中，该多相信号控制电路用于根据反馈控制信号产生第一相位信号和第二相位信号，该功率级电路用于根据第一相位信号和第二相位信号生成输出电压信号。
第七方面，提供一种通信设备，该设备可以为终端或者基站，该通信设备包括：处理芯片、以及如第六方面所提供的电压转换芯片，该电压转换芯片用于为该处理芯片供电。
可以理解地，上述提供的任一种多相信号控制方法、电压转换器、电压转换芯片和通信设备等，均可以由上文所提供的对应的多相信号控制电路来实现，因此，其所能达到的有益效果可参考上文所提供的多相信号控制电路中的有益效果，此处不再赘述。
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图1为现有技术提供的一种多相信号控制电路的结构示意图；
图2为现有技术提供的一种产生多相信号的信号时序图；
图3为本申请实施例提供的一种电压转换器的结构示意图；
图4为本申请实施例提供的一种产生多相信号的信号时序图一；
图5为本申请实施例提供的一种产生多相信号的信号时序图二；
图6为本申请实施例提供的一种多相信号控制电路的结构示意图一；
图7为本申请实施例提供的一种相位切换信号的时序图；
图8为本申请实施例提供的一种多相信号控制电路的结构示意图二；
图9为本申请实施例提供的一种产生多相信号的信号时序图三；
图10为本申请实施例提供的一种产生多相信号的信号时序图四；
图11为本申请实施例提供的一种多相信号控制电路的结构示意图三；
图12为本申请实施例提供的一种产生多相信号的信号时序图五；
图13本申请实施例提供的一种信号发生器的结构示意图一；
图13A为本申请实施例提供的一种信号发生器的结构示意图二；
图13B本申请实施例提供的一种信号发生器的结构示意图三；
图14本申请实施例提供的一种信号发生器的结构示意图四；
图14A为本申请实施例提供的一种信号发生器的结构示意图五；
图14B本申请实施例提供的一种信号发生器的结构示意图六；
图15为本申请实施例提供的一种功率级电路的结构示意图；
图16为本申请实施例提供的一种多相信号控制方法的流程示意图。
具体实施方式
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a-b，a-c，b-c或a-b-c，其中a、b和c可以是单个，也可以是多个。字符“/”一般表示前后关联对象是一种“或”的关系。另外，在本申请的实施例中，“第一”、“第二”等字样并不对数量和执行次序进行限定。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
图3为本申请实施例提供的一种电压转换器的结构示意图，参见图3，该电压转换器包括多相信号控制电路110和功率级电路120。其中，多相信号控制电路110用于根据功率级电路120反馈的反馈控制信号产生脉宽调制(pulse width modulation，PWM)信号，并基于该PWM信号产生交替充电和放电的多相信号，比如，该多相信号可以是相位不同的两相信号或者三相信号等；功率级电路120用于根据该多相信号来生成稳定的输出电压信号。需要说明的是，功率级电路120根据该多相信号来生成稳定的输出电压信号的具体过程可以参见下文中图13中的相关描述，本申请实施例在此不再赘述。
目前，在基于开关电容(switched capacitor，SC)类型的电压转换器中，通常是通过对脉宽调制(pulse width modulation，PWM)信号进行降频处理，来产生各个相位的允许工作信号；之后，将各个相位的允许工作信号与PWM信号进行逻辑运算来产生交替工作的多相信号。比如，在图2所示的信号时序图中，通过将PWM信号分别与P1允许工作信号和P2允许工作信号进行逻辑与运算，来产生P1信号和P2信号，P1信号和P2信号通过交替充电和放电来保证电压转换器输出的稳定性。但是，该方法仅适用于PWM信号的开关周期稳定，且处于非极端频率的情况。当PWM信号的开关周期不稳定，出现频率过低或者过高的情况时，都无法正常产生各个相位的允许工作信号。
示例性的，如图4所示，当PWM信号的频率过低时，电压转换器因为输出能力不足需要全周期放电，从而会导致PWM信号在图4所示的t01时间段内处于直通锁死状态(即PWM信号一直处于高电平状态，无法实现相位切换)，此时则无法通过降频产生用于相位切换的P1允许工作信号和P2允许工作信号，进而会导致电压转换器工作状态异常。在此情况下，可以利用图4中虚线框所示的时钟重置CLK_RESETN信号与直通锁死的PWM信号(虚线框中表示为PWM_COMP信号)进行逻辑运算，来产生新PWM信号，进而通过新PWM信号来实现相位切换。
示例性的，如图5所示，当PWM信号的频率过高时，会导致长放电周期后出现短充电后放电的情况，比如，在图5所示的t11时间段长放电后、出现在t12时间段短充电后在t3时间段内放电的情况(P1允许工作信号和P2允许工作信号中的高电平为放电、低电平为充电)，此时功率级电路中开关管的寄生电感会在大电流充电状态下突然转换为放电，电流方向突变后会造成功率级电路中开关管上极高的毛刺电压，从而影响电压转换器的可靠性，进而导致电压转换器工作状态异常。在此情况下，可以利用图5中虚线框所示的增加PWM信号中高电平对应的最短脉宽(图5中表示为T1)、以及低电平对应的最短脉宽(图5中表示为T2)的方式来保证电压转换器的可靠性，比如，设置高电平对应的最短脉宽等于最小导通时间minTon、设置低电平对应的最短脉宽等于最小关断时间minToff。最小导通时间和最小关断时间由功率级电路控制充电和放电的响应时间决定，最小导通时间和最小关断时间用于避免功率级电路产生的输出电压信号在电源端与接地端之间出现短路的情况。
但是，在图4所示的方式中，如果CLK_RESETN的频率过高，则容易误触发PWM信号发生翻转，进而影响电压转换器的正常工作，如果CLK_RESETN的频率过低又会降低充电放电的切换频率，从而降低电压转换器的带载能力。在图5所示的方式中，增加PWM信号中高电平对应的最短脉宽会使得最大输出占空比下降，增加PWM信号中低电平对应的最短脉宽会使得最小输出占空比下降，这样会使得输出电压信号更早的开始跳周期，从而会导致电压转换器的带载能力下降，输出纹波增加。
基于此，本申请实施例提供一种多相信号控制电路，能够在PWM信号的开关周期不稳定的情况下，仍能够正常产生各个相位的允许工作信号，进而根据PWM信号和各个相位的允许工作信号产生交替充电和放电的多相信号，从而使得功率级电路能够根据该多相信号产生稳定的输出电压信号，同时也能够保证电压转换器的带载能力和输出纹波的稳定性。
图6为本申请实施例提供的一种多相信号控制电路的结构示意图，该多相信号控制电路包括：信号发生电路201、比较器202和切相电路203。
在本申请实施例中，信号发生电路201，用于产生三角波信号和相位切换信号，该相位切换信号的频率可以是三角波信号的N倍，N为大于或等于1的整数。其中，信号发生电路201可以用于产生一时钟信号，并根据该时钟信号产生该三角波信号和该相位切换信号，该相位切换信号可以是靠近该三角波信号的波峰或者波谷产生的信号，该相位切换信号可以是脉冲信号、方波信号、锯齿波信号、或者是任意特定信号等。比如，以该相位切换信号为方波信号为例，图7中的(a)所示的相位切换信号是靠近该三角波信号的波峰产生的信号，图7中的(b)所示的相位切换信号是靠近该三角波信号的波谷产生的信号。可选的，如图8所示，信号发生电路201包括信号发生器2011和分频器2012；信号发生器2011具体用于产生三角波信号、和与该三角波信号同频(即频率相同)的触发信号(该触发信号可以是脉冲信号、方波信号、锯齿波信号、或者是任意特定信号等)，该触发信号的跳变沿的位置可以与该三角波信号的波峰或者波谷的位置，分频器2012具体用于对该触发信号进行分频处理，以得到该相位切换信号。需要说明的是，信号发生电路201可以仅包括信号发生器2011，此时，该相位切换信号即为该触发信号，且该相位切换信号的频率与该三角波信号的频率相同；当信号发生电路201同时包括信号发生器2011和分频器2012时，该相位切换信号的频率是该三角波信号的频率的整数倍。此外，该信号发生器2011产生的三角波信号的频率可以是稳定的。
比较器202，用于比较该三角波信号和反馈控制信号，以输出第一脉宽调制PWM信号，该反馈控制信号为功率级电路反馈的信号。其中，该反馈控制信号可以是任意波形的信号，且该反馈控制信号可以是功率级电路根据实际输出电压与预设输出电压之间的误差产生的信号，即该反馈控制信号与输出电压信号和预设电压信号之间的误差有关。另外，比较器202具体可以用于接收信号发生电路201产生的三角波信号和功率级电路输出的反馈控制信号，并比较该三角波信号和该反馈控制信号，以输出第一PWM信号。示例性的，比较器202可以在该反馈控制信号大于该三角波信号时输出高电平，在该反馈控制信号小于该三角波信号时输出低电平，从而得到第一PWM信号。
切相电路203，用于利用该相位切换信号对第一PWM信号进行切相处理，得到第 一相位信号和第二相位信号，第一相位信号和第二相位信号用于控制功率级电路生成输出电压信号。可选的，切相电路203可以利用该相位切换信号将第一PWM信号的高电平脉宽分割至第一相位信号或第二相位信号中的至少一个(比如，将第一PWM信号的第一个高电平脉宽分割至第一相位信号中，将第二个高电平脉宽分割至第二相位信号中，将第三个高电平脉宽中的一部分分割至第一相位信号、另一部分分割至第二相位信号)；或者，切相电路203可以利用该相位切换信号分割第一PWM信号的低电平脉宽，并将分割得到的两个信号分别通过反相器处理，得到第一相位信号和第二相位信号。其中，第一相位信号和第二相位信号的逻辑或的结果可以为第一PWM信号。
在一种可能的实现方式中，切相电路203可以包括第一个与门2031、非门2032和第二个与门2033；其中，第一个与门2031用于对该相位切换信号和第一PWM信号进行逻辑与运算(即经过与门处理)以得到第一相位信号P1，非门2032用于对该相位切换信号进行逻辑非(即经过非门处理)运算，第二个与门2033用于将逻辑非运算得到的信号与第一PWM信号进行逻辑与运算(即再经过与门处理)以得到第二相位信号P2。
示例性的，该多相信号控制电路中产生的各信号的时序可以如图9所示。其中，S TR表示三角波信号，S PH表示相位切换信号，PWM1信号表示比较器202输出的第一PWM信号，P1表示切相电路203输出的第一相位信号，P2表示切相电路203输出的第二相位信号。
在图9示出的时序图中，第一PWM信号中高电平对应的最短脉宽或低电平对应的最短脉宽，均未与相位切换信号S PH的升降沿发生重叠，即利用相位切换信号S PH对第一PWM信号进行切相处理产生的P1信号和P2信号的充放电时间，不会存在小于上述第一PWM信号中高电平对应的最小脉宽或低电平对应的最小脉宽的情况。比如，图9中的minTon表示第一PWM信号中高电平对应的最短脉宽，minToff表示第一PWM信号中低电平对应的最短脉宽，P1信号和P2信号中的放电时间均大于或等于minTon，P1信号和P2信号中的充电时间均大于或等于minToff，这样可以使得功率级电路能够根据P1信号和P2信号产生输出电压信号，同时能够保证电压转换器的带载能力和输出纹波的稳定性。
如图10所示，当第一PWM信号中高电平对应的最短脉宽(图10中表示为minTon)或低电平对应的最短脉宽(图10中表示为minToff)，与相位切换信号的升降沿发生重叠时，即利用相位切换信号S PH对第一PWM信号进行切相处理产生的P1信号和P2信号的充放电时间，会存在小于上述第一PWM信号中高电平对应的最小脉宽或低电平对应的最小脉宽的情况，此时，该多相信号控制电路具体可以通过以下方式产生多相信号。
如图11所示，该多相信号控制电路还可以包括：锁存器204，锁存器204用于锁存第一PWM信号，以输出第二PWM信号。其中，信号发生器2011还用于：产生脉冲保持信号，该脉冲保持信号的高电平脉宽的位置与所述触发信号的高电平脉宽的位置对应(即在同一时间段内，脉冲保持信号的高电平持续时间大于或等于该触发信号的高电平持续时间)，产生该脉冲保持信号的时钟可以与上述产生三角波信号和相位 切换信号的时钟同源。相应的，比较器202输出的上述第一PWM信号也可以称为PWM_CMP信号)，锁存器204具体用于根据该脉冲保持信号锁存第一PWM信号，以输出第二PWM信号，比如，锁存器204可用于在第一PWM信号与该脉冲保持信号的上升沿重叠时，保持第一PWM信号的当前状态持续一段时间，持续的这段时间等于该脉冲保持信号的高电平脉宽对应的时间。之后，切相电路203具体可用于利用该相位切换信号对第二PWM信号进行切相处理，以输出第一相位信号和第二相位信号，此时，第一相位信号和第二相位信号的逻辑或的结果可以为第二PWM信号。
可选的，该脉冲保持信号的高电平脉宽可以等于最小导通时间的2倍(即2*minTon)、最小关断时间的2倍(即2*minToff)、或者最小导通时间和最小关断时间中最大值的2倍(即2*max(minTon，minToff))。在一种可能的实现方式中，当该相位切换信号是靠近该三角波信号的谷值产生的信号时，该脉冲保持信号的高电平脉宽可以等于最小关断时间的2倍，当该相位切换信号是靠近该三角波信号的峰值产生的信号时，该脉冲保持信号的高电平脉宽可以等于最小导通时间的2倍。
示例性的，在此情况下，该多相信号控制电路中产生的各信号的时序可以如图12所示。其中，S TR表示信号发生电路201产生的三角波信号，S PH表示信号发生电路201产生的相位切换信号，S HOLD表示信号发生电路201产生的脉冲保持信号，S HOLD的高电平脉宽表示为2*max(minTon，minToff)，PWM_CMP表示比较器202输出的第一PWM信号，PWM2信号表示锁存器204输出的第二PWM信号，P1表示切相电路203输出的第一相位信号，P2表示切相电路203输出的第二相位信号。
由图12可以看出，通过脉冲保持信号S HOLD对PWM1信号(即PWM_CMP信号)进行锁存处理，能够使得输出的PWM2信号中高电平对应的最小脉宽或低电平对应的最小脉宽大于或等于脉冲保持信号S HOLD的高电平脉宽，从而在利用相位切换信号S PH对PWM2信号进行切相处理，产生的P1信号和P2信号的充放电时间能够满足功率级电路的最小导通时间和最小关断时间的要求，从而功率级电路能够根据P1信号和P2信号能够产生稳定的输出电压信号，同时能够保证电压转换器的带载能力和输出纹波的稳定性。
进一步的，该多相信号控制电路中的信号发生器2011具体可以包括以下两组不同的结构，具体如下所述。
第一组、如图13所示，信号发生器2011可以包括：环形振荡器11、缓冲器12、第一延迟电路13和积分电路14。其中，环形振荡器11，用于输出振荡信号，该环形振荡器11可以是包括N个非门的N级环形振荡器，该N个非门的输出端和输入端首尾相接，N为大于或等于3的整数。缓冲器12，用于接收该环形振荡器产生的振荡信号，并对该振荡信号进行缓冲，以输出时钟信号，这里对该振荡信号进行缓冲具体可以是指对该振荡信号的波形进行整形。第一延迟电路13，用于接收该时钟信号，并将该时钟信号延迟第一相位，以输出触发信号。积分电路14，用于对该触发信号进行积分处理，以产生三角波信号。
进一步的，参见图13A，信号发生器2011还可以包括：第二延迟电路15和D触发器16。其中，第二延迟电路15，用于将缓冲器12输出的时钟信号延迟第二相位，以输出时钟延迟信号，第二相位等于第一相位的两倍。D触发器16，用于通过时钟输 入端(CLK)接收缓冲器12输出的时钟信号，通过设置端(RESET)接收第二延迟电路15输出的时钟延迟信号，并根据该时钟信号和时钟延迟信号产生脉冲保持信号，该脉冲保持信号由D触发器16的Q输出端输出，D触发器16的D输入端置为高电平“1”。
或者，参见图13B，信号发生器2011还可以包括：第二延迟电路15和逻辑运算电路17，逻辑运算电路17包括非门171和与门172。其中，第二延迟电路15，用于将缓冲器12输出的时钟信号延迟第二相位，以输出时钟延迟信号，第二相位等于第一相位的两倍。逻辑运算电路17，用于将第二延迟电路15输出的时钟延迟信号通过非门171进行逻辑非运算，并将运算后的信号和缓冲器12输出的时钟信号通过与门172进行逻辑与运算，以产生脉冲保持信号。
需要说明的是，图13、图13A和图13B中的A可以表示缓冲器12输出的时钟信号，B可以表示第一延迟电路13输出的触发信号，C可以表示第二延迟电路15输出的时钟延迟信号。
第二组，如图14所示，信号发生器2011可以包括：张弛振荡器21和第一延迟电路22。其中，张弛振荡器21用于产生时钟信号，并根据该时钟信号产生三角波信号；第一延迟电路22，用于接收张弛振荡器21输出的时钟信号，并将该时钟信号延迟第一相位，以输出触发信号。具体的，张弛振荡器21可以包括充放电电路211、第一比较器212、第二比较器213和RS触发器214；其中，RS触发器214的Q输出端用于控制充放电电路211的电源端的开关(当Q输出端为高电平时，电源端的开关闭合，电源端通过充电电流对电容进行充电)，RS触发器214的QB输出端用于控制充放电电路的接地端的开关(当QB输出端为低电平时，接地端的开关闭合，接地端通过放电电流对电容进行放电)；充放电电路211的输出端分别与第一比较器212的一个输入端和第二比较器213的一个输入端连接，第一比较器212的另一输入端用于接收高参考电压，第二比较器213的另一输入端用于接收低参考电压，第一比较器212的输出端与RS触发器214的R输入端连接(第一比较器212通过比较高参考电路和充放电电路211的输出电压来控制R输入端为高电平或低电平)，第二比较器213的输出端与RS触发器214的S输入端连接(第二比较器213通过比较低参考电路和充放电电路211的输出电压来控制S输入端为高电平或低电平)。
进一步的，参见图14A，信号发生器2011还可以包括：第二延迟电路23和D触发器24。其中，第二延迟电路23，用于将张弛振荡器21输出的时钟信号延迟第二相位，以输出时钟延迟信号，第二相位等于第一相位的两倍。D触发器24，用于通过时钟输入端(CLK)接收张弛振荡器21输出的时钟信号，通过设置端(RESET)接收第二延迟电路23输出的时钟延迟信号，并根据该时钟信号和时钟延迟信号产生脉冲保持信号，该脉冲保持信号由D触发器24的Q输出端输出，D触发器24的D输入端置为高电平“1”。
或者，参见图14B，信号发生器2011还可以包括：第二延迟电路23和逻辑运算电路25，逻辑运算电路25包括非门251和与门252。其中，第二延迟电路23，用于将张弛振荡器21输出的时钟信号延迟第二相位，以输出时钟延迟信号，第二相位等于第一相位的两倍。逻辑运算电路25，用于对第二延迟电路23输出的时钟延迟信号通过非门251进行逻辑非运算，并将运算后的信号和张弛振荡器21输出的时钟信号通过 与门252进行逻辑与运算，以产生脉冲保持信号。
需要说明的是，在图14、图14A和图14B中，A可以表示张弛振荡器21输出的时钟信号，B可以表示第一延迟电路22输出的触发信号，C可以表示第二延迟电路23输出的时钟延迟信号。
进一步的，如图15所示，为本申请实施例提供的一种功率级电路的结构示意图，参见图15，该功率级电路包括：第一信号控制电路、第二信号控制电路、以及位于与第一信号控制信号与第二信号控制电路之间的电压输出电路。
其中，第一信号控制电路可以包括：第一电容C1、受第一相位信号P1控制的两个开关(图15中表示为SW11和SW12)，以及受第一相位信号的反信号
Figure PCTCN2019083307-appb-000001
控制的两个开关(图15中表示为SW13和SW14)。第一信号控制电路具有可用于接收第一相位信号P1，并根据第一相位信号P1和第一相位信号的反信号
Figure PCTCN2019083307-appb-000002
控制第一信号控制电路中的多个开关(即SW11至SW14)。
类似的，第二信号控制电路可以包括：第二电容C2、受第二相位信号P2控制的两个开关(图15中表示为SW21和SW22)，以及受第二相位信号的反信号
Figure PCTCN2019083307-appb-000003
控制的两个开关(图15中表示为SW23和SW24)。第二信号控制电路具有可用于接收第二相位信号P2，并根据第二相位信号P2和第二相位信号的反信号
Figure PCTCN2019083307-appb-000004
控制第二信号控制电路中的多个开关(即SW21至SW24)。
电压输出电路可以包括：电感L、第三电容C3、以及受N信号控制的开关(图15中表示为SW0)，N信号为PWM信号的反信号。其中，电感L的一端和开关SW0的一端与第一控制电路和第二控制电路的耦合端LX连接，开关SW0的另一端与接地端端耦合，电感L的另一端与第三电容C3的一端耦合作为电压输出端，第三电容C3的另一端与接地端耦合。
具体的，在第一信号控制电路中，当第一相位信号P1为低电平、第一相位信号的反信号
Figure PCTCN2019083307-appb-000005
为高电平时，SW11和SW12均打开，SW13和SW14均闭合，第一电容C1的两端分别为电源和地(GND)，从而电源对第一电容C1进行充电；在第一相位信号P1为高电平、第一相位信号的反信号
Figure PCTCN2019083307-appb-000006
为低电平时，SW11和SW12均闭合，SW13和SW14均打开，第一电容C1的两端分别为电源和电感L的LX端，此时，根据电容电荷不变原理，第一电容C1下级板接电源后上极板所连接的LX端的电压为2倍的电源电压。第二信号控制电路的工作原理与第一信号控制电路的工作原理类似，本申请实施例在此不再赘述。
由于第一相位信号P1和第二相位信号P2是PWM信号切相得到的，因此，在PWM信号为高电平时，第一相位信号P1和第二相位信号P2中总会有一个信号为高电平，从而第一相位信号P1和第二相位信号P2通过逻辑交替工作能够保证LX端的电压始终为2倍的电源端电压。当PWM信号为低电平时，PWM信号的反信号N为高电平，此时LX端节点，电感L处于放电状态。
基于上文所示，本申请实施例还提供一种电压转换器，该电压转换器的结构可以参见上述图3所示，该电压转换器可以包括：如图6、图8或图11所示的多相信号控制电路，以及如图15所示的功率级电路；其中，该多相信号控制电路，可用于根据该功率级电路反馈的反馈控制信号产生第一相位信号和第二相位信号；该功率级电路， 可用于根据第一相位信号和第二相位信号生成输出电压信号。其中，关于该多相信号控制电路和该功率级电路的具体描述可以参见上文所示，本申请实施例在此不再赘述。
在另一种可能的实施例中，本申请还提供一种电压转换芯片，该电压转换芯片的结构可以参见上述图3所示，该电压转换芯片可以包括：如图6、图8或图11所示的多相信号控制电路。进一步的，该电压转换芯片还可以包括：功率级电路，该功率级电路的结构可以如图15所示。
在另一种可能的实施例中，本申请还提供一种通信设备，该设备可以为终端或者基站，该设备可以包括：处理芯片、以及上文所提供的电压转换芯片，该电压转换芯片用于为该处理芯片供电。
图16为本申请实施例提供的一种多相信号控制方法，该方法包括以下步骤：S301-S303。
S301：产生三角波信号和相位切换信号。
其中，产生三角波信号和相位切换信号，具体可以为：产生三角波信号、以及根据该三角波信号产生触发信号；对该触发信号进行分频处理，以得到该相位切换信号，该触发信号的跳变沿的位置与该三角波信号的波峰或波谷的位置对应，该相位切换方波信号的频率是该三角波信号的N倍，N为大于或等于1的整数。
S302：比较该三角波信号和反馈控制信号，以输出第一脉宽调制信号，该反馈控制信号与输出电压信号和预设电压信号之间的误差有关。
S303：根据该相位切换信号和第一脉宽调制信号，产生第一相位信号和第二相位信号。其中，第一相位信号和第二相位信号的逻辑或的结果为该第一脉宽调制信号，第一相位信号和第二相位信号用于生成该输出电压信号。
进一步的，该方法还包括：锁存第一脉宽调制信号以产生第二脉宽调制信号；相应的，根据该相位切换信号和第一脉宽调制信号，产生第一相位信号和第二相位信号，具体为：根据该相位切换信号和第二脉宽调制信号，产生第一相位信号和第二相位信号。在一种可能的实现方式中，该方法还包括：产生脉冲保持信号，该脉冲保持信号的高电平脉宽的位置可以与该触发信号的高电平脉宽的位置对应；相应的，锁存第一脉宽调制信号以产生第二脉宽调制信号，具体可以为：根据该脉冲保持信号锁存第一脉宽调制信号，以输出第二脉宽调制信号。可选的，该脉冲保持信号的高电平脉宽等于以下情况中的任一项：最小关断时间的两倍、最小导通时间的两倍、或者最小关断时间和最小导通时间中最大值的两倍。
相应的，S303中根据该相位切换信号和第一脉宽调制信号，产生第一相位信号和第二相位信号，具体为：对该相位切换信号和第二脉宽调制信号进行逻辑与运算，以输出第一相位信号；对该相位切换信号进行逻辑非运算，并将运算后的信号和第二脉宽调制信号进行逻辑与运算，以输出第二相位信号。
在一种可能的实现方式中，产生三角波信号，以及产生与该三角波信号同频的触发信号，具体可以为：产生振荡信号；对该振荡信号进行缓冲，以输出时钟信号；将该时钟信号延迟第一相位，以输出该触发信号；对该触发信号进行积分处理，以输出该三角波信号。
在另一种可能的实现方式中，产生三角波信号，以及产生与该三角波信号同频的 触发信号，具体可以为：产生时钟信号，并根据该时钟信号产生该三角波信号；将该时钟信号延迟第一相位，以输出该触发信号。
进一步的，产生脉冲保持信号，具体可以为：将该时钟信号延迟第二相位，以输出时钟延迟信号，该第二相位等于该第一相位的两倍；将该时钟信号和该时钟延迟信号分别输入D触发器的时钟输入端和设置端，以产生该脉冲保持信号。或者，产生脉冲保持信号，具体可以为：将该时钟信号延迟第二相位，以输出时钟延迟信号，该第二相位等于该第一相位的两倍；对该时钟延迟信号进行逻辑非运算，并将运算后的信号和该时钟信号进行逻辑与运算，以产生该脉冲保持信号。
需要说明的是，本申请实施例提供的多相信号控制方法的详细描述，具体可以参见上文多相信号控制电路中的相应描述，本申请实施例在此不再赘述。
在本申请实施例中，产生的相位切换信号不依赖于第一PWM信号，即该相位切换信号不受第一PWM信号的开关周期变化的影响。因此，当第一PWM信号开关周期不稳定的时候，利用该相位切换信号对第一PWM信号进行切相依然可以稳定地产生交替充电和放电的第一相位信号和第二相位信号，该第一相位信号和该第二相位信号可以满足后级功率级电路正常工作条件，从而使得功率级电路能够根据该第一相位信号和该第二相位信号产生稳定的输出电压信号，同时也能够保证电压转换器的带载能力和输出纹波的稳定性。
在本申请所提供的几个实施例中，应该理解到，所揭露的电路和方法，可以通过其它的方式实现。例如，以上所描述的电路实施例仅仅是示意性的，例如，所描述的模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个装置，或一些特征可以忽略，或不执行。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是一个物理单元或多个物理单元，即可以位于一个地方，或者也可以分布到多个不同地方。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (25)

  1. 一种多相信号控制电路，其特征在于，包括：
    信号发生电路，用于产生三角波信号和相位切换信号；
    比较器，用于比较所述三角波信号和反馈控制信号，以输出第一脉宽调制信号，所述反馈控制信号为功率级电路反馈的信号；
    切相电路，用于接收所述相位切换信号和所述第一脉宽调制信号，以产生第一相位信号和第二相位信号，所述第一相位信号和所述第二相位信号用于控制所述功率级电路生成输出电压信号。
  2. 根据权利要求1所述的电路，其特征在于，所述信号发生电路，包括：
    信号发生器，用于产生所述三角波信号、和与所述三角波信号同频的触发信号；
    分频器，用于对所述触发信号进行分频处理，以得到所述相位切换信号。
  3. 根据权利要求1或2所述的电路，其特征在于，所述多相信号控制电路还包括：
    锁存器，用于锁存所述第一脉宽调制信号以产生第二脉宽调制信号，并将所述第二脉宽调制信号输出至所述切相电路。
  4. 根据权利要求3所述的电路，其特征在于，所述切相电路，包括：
    第一与门，用于对所述相位切换信号和所述第二脉宽调制信号进行逻辑与运算，以输出所述第一相位信号；
    第一非门，用于对所述相位切换信号进行逻辑非运算；
    第二与门，用于将所述逻辑非运算后的信号和所述第二脉宽调制信号进行逻辑与运算，以输出所述第二相位信号。
  5. 根据权利要求2至4任一项所述的电路，其特征在于，所述信号发生器包括：环形振荡器、缓冲器、第一延迟电路和积分电路；其中，
    所述环形振荡器，用于产生振荡信号；
    所述缓冲器，用于对所述振荡信号进行缓冲，以输出时钟信号；
    所述第一延迟电路，用于将所述时钟信号延迟第一相位，以输出所述触发信号；
    所述积分电路，用于对所述触发信号进行积分处理，以输出所述三角波信号。
  6. 根据权利要求2至4任一项所述的电路，其特征在于，所述信号发生器包括：张弛振荡器和第一延迟电路；
    所述张弛振荡器，用于产生时钟信号，并根据所述时钟信号产生所述三角波信号；
    所述第一延迟电路，用于接收所述时钟信号，并将所述时钟信号延迟第一相位，以输出所述触发信号。
  7. 根据权利要求3至6任一项所述的电路，其特征在于，所述信号发生器，还用于：
    产生脉冲保持信号，并将所述脉冲保持信号输出至所述锁存器的使能端，所述脉冲保持信号的高电平脉宽的位置与所述触发信号的高电平脉宽的位置对应。
  8. 根据权利要求7所述的电路，其特征在于，所述信号发生器还包括：第二延迟电路和D触发器；其中，
    所述第二延迟电路，用于将时钟信号延迟第二相位，以输出时钟延迟信号，所述 第二相位等于所述第一相位的两倍；
    所述D触发器，用于通过时钟输入端接收所述时钟信号，及通过设置端接收所述时钟延迟信号，并根据所述时钟信号和所述时钟延迟信号产生所述脉冲保持信号。
  9. 根据权利要求7所述的电路，其特征在于，所述信号发生器还包括：第二延迟电路和逻辑运算电路；其中，
    所述第二延迟电路，用于将时钟信号延迟第二相位，以输出时钟延迟信号，所述第二相位等于所述第一相位的两倍；
    所述逻辑运算电路，用于对所述时钟延迟信号进行逻辑非运算，并将运算后的信号和所述时钟信号进行逻辑与运算，以产生所述脉冲保持信号。
  10. 根据权利要求7至9任一项所述的电路，其特征在于，所述脉冲保持信号的高电平脉宽等于以下情况中的任一项：最小关断时间的两倍、最小导通时间的两倍、或者最小关断时间和最小导通时间中最大值的两倍。
  11. 根据权利要求1至10任一项所述的电路，其特征在于：
    所述相位切换信号的频率是所述三角波信号的N倍，N为大于或等于1的整数；
    所述第一相位信号和所述第二相位信号的逻辑或的结果为所述第一脉宽调制信号。
  12. 根据权利要求2至11任一项所述的电路，其特征在于，所述触发信号的跳变沿的位置与所述三角波信号的波峰或波谷的位置对应。
  13. 一种多相信号控制方法，其特征在于，包括：
    产生三角波信号和相位切换信号；
    比较所述三角波信号和反馈控制信号，以输出第一脉宽调制信号，所述反馈控制信号与输出电压信号和预设电压信号之间的误差有关；
    根据所述相位切换信号和所述第一脉宽调制信号，产生第一相位信号和第二相位信号，所述第一相位信号和所述第二相位信号用于生成所述输出电压信号。
  14. 根据权利要求13所述的方法，其特征在于，所述产生三角波信号和相位切换信号，包括：
    产生所述三角波信号、和与所述三角波信号同频的触发信号；
    对所述触发信号进行分频处理，以得到所述相位切换信号。
  15. 根据权利要求13或14所述的方法，其特征在于，所述方法还包括：锁存所述第一脉宽调制信号以产生第二脉宽调制信号；
    所述根据所述相位切换信号和所述第一脉宽调制信号，产生第一相位信号和第二相位信号，具体为：根据所述相位切换信号和所述第二脉宽调制信号，产生所述第一相位信号和所述第二相位信号。
  16. 根据权利要求15所述的方法，其特征在于，所述根据所述相位切换信号和所述第二脉宽调制信号，产生所述第一相位信号和所述第二相位信号，包括：
    对所述相位切换信号和所述第二脉宽调制信号进行逻辑与运算，以输出所述第一相位信号；
    对所述相位切换信号进行逻辑非运算，并将所述逻辑非运算后的信号和所述第二脉宽调制信号进行逻辑与运算，以输出所述第二相位信号。
  17. 根据权利要求14至16任一项所述的方法，其特征在于，所述产生所述三角波信号、和与所述三角波信号同频的触发信号，包括：
    产生振荡信号；
    对所述振荡信号进行缓冲，以输出时钟信号；
    将所述时钟信号延迟第一相位，以输出所述触发信号；
    对所述触发信号进行积分处理，以输出所述三角波信号。
  18. 根据权利要求14至16任一项所述的方法，其特征在于，所述产生所述三角波信号、和与所述三角波信号同频的触发信号，包括：
    产生时钟信号，并根据所述时钟信号产生所述三角波信号；
    将所述时钟信号延迟第一相位，以输出所述触发信号。
  19. 根据权利要求15至18任一项所述的方法，其特征在于，所述方法还包括：产生脉冲保持信号，所述脉冲保持信号的高电平脉宽的位置与所述触发信号的高电平脉宽的位置对应；
    所述锁存所述第一脉宽调制信号以产生第二脉宽调制信号，具体为：根据所述脉冲保持信号锁存所述第一脉宽调制信号，以产生第二脉宽调制信号。
  20. 根据权利要求19所述的方法，其特征在于，所述产生脉冲保持信号，包括：
    将时钟信号延迟第二相位，以输出时钟延迟信号，所述第二相位等于所述第一相位的两倍；
    根据所述时钟信号和所述时钟延迟信号，产生所述脉冲保持信号。
  21. 根据权利要求19或20所述的方法，其特征在于，所述脉冲保持信号的高电平脉宽等于以下情况中的任一项：最小关断时间的两倍、最小导通时间的两倍、或者最小关断时间和最小导通时间中最大值的两倍。
  22. 根据权利要求13至21任一项所述的方法，其特征在于：
    所述相位切换信号的频率是所述三角波信号的N倍，N为大于或等于1的整数；
    所述第一相位信号和所述第二相位信号的逻辑或的结果为所述第一脉宽调制信号。
  23. 根据权利要求14至22任一项所述的方法，其特征在于，所述触发信号的跳变沿的位置与所述三角波信号的波峰或波谷的位置对应。
  24. 一种电压转换芯片，其特征在于，所述电压转换芯片包括：功率级电路、以及如权利要求1-12任一项所述的多相信号控制电路；其中，
    所述多相信号控制电路，用于根据所述功率级电路反馈的反馈控制信号，产生第一相位信号和第二相位信号；
    所述功率级电路，用于根据所述第一相位信号和所述第二相位信号生成输出电压信号。
  25. 一种通信设备，其特征在于，所述设备包括：处理芯片、以及如权利要求24所述的电压转换芯片，所述电压转换芯片用于为所述处理芯片供电。
PCT/CN2019/083307 2019-04-18 2019-04-18 一种多相信号控制电路及方法 WO2020211059A1 (zh)

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