WO2020207443A1 - 一种基于低频参考信号的片上同步自修复系统 - Google Patents

一种基于低频参考信号的片上同步自修复系统 Download PDF

Info

Publication number
WO2020207443A1
WO2020207443A1 PCT/CN2020/084002 CN2020084002W WO2020207443A1 WO 2020207443 A1 WO2020207443 A1 WO 2020207443A1 CN 2020084002 W CN2020084002 W CN 2020084002W WO 2020207443 A1 WO2020207443 A1 WO 2020207443A1
Authority
WO
WIPO (PCT)
Prior art keywords
input
dual
chip
pll
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/084002
Other languages
English (en)
French (fr)
Inventor
徐志伟
王圣杰
刘嘉冰
邱良
弓悦
赵锴龙
宋春毅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhejiang University
Original Assignee
Zhejiang University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhejiang University filed Critical Zhejiang University
Priority to US17/043,667 priority Critical patent/US11705908B2/en
Priority to JP2020558604A priority patent/JP7240010B2/ja
Publication of WO2020207443A1 publication Critical patent/WO2020207443A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7825—Globally asynchronous, locally synchronous, e.g. network on chip
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0045—Correction by a latch cascade
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Definitions

  • the invention relates to the field of radar phased arrays, in particular to a synchronous self-repair system for the phases of local oscillator signals between digital transceiver chips on array element tiles in the phased array.
  • the synchronization system needs to compensate the delay to an integer multiple of the period. Because the wavelength of the low-frequency signal is too long (for example, the wavelength of the 10MHz reference signal in the air is 30 meters), and the size of the array element tile is usually much less than 1 meter. The use of a low-frequency synchronization system requires an equivalent delay line of up to 30 meters, which is unacceptable.
  • the present invention proposes a dual-input PLL-coupled on-chip synchronization self-repair system based on an adjustable left-handed material transmission line.
  • the system is based on a low-frequency reference signal, and the entire synchronization system is connected in a star or butterfly structure.
  • the IC chip synchronizes the transmitted reference signal with the received reference signal through the phase-locked loop. It is assumed that each array element tile can obtain a reference signal with the same phase, and on this basis, the local oscillator of each RF transceiver chip in the tile is guaranteed Signal synchronization.
  • An on-chip synchronous self-repair system based on a low-frequency reference signal characterized in that the system adopts a dual-input PLL star coupling structure or a dual-input PLL butterfly coupling structure, and single-line coupling between PLLs, dual-input type
  • the PLL star coupling structure connects n dual-input PLLs through chain closure, and transmits a quarter of the local oscillator signal to each other for interlocking to achieve on-chip local oscillator signal synchronization;
  • the dual-input PLL butterfly coupling structure is connected through a lumped connection m
  • Two dual-input PLLs are used to synchronize the local oscillator signals on each IC chip on the chip through a given reference signal; where n ⁇ 3, m ⁇ 3, the interconnection between the dual-input PLLs is based on left-handed materials Transmission line.
  • the dual-input PLL star coupling structure is characterized in that the dual-input PLL module is in the IC chip, and each IC chip is interconnected through a common IO port in turn, and the DLL module compensates for the interaction generated by the transmission line. Even phase shift, its structure is:
  • One common IO terminal of dual-input PLL1 is connected to a common IO terminal of dual-input PLL2, the other common IO terminal of dual-input PLL2 is connected to a common IO terminal of dual-input PLL3, and the other of dual-input PLL3
  • the common IO terminal is connected to a common IO terminal of the dual-input PLL4, and so on, a common IO terminal of the dual-input PLLn-1 is connected to a common IO terminal of the dual-input PLLn, and the other common IO terminal of the dual-input PLLn
  • the IO terminal is connected to the other common IO terminal of the dual-input PLL1 to form a closed loop.
  • the dual-input PLL butterfly coupling structure is characterized in that the LO and PLL modules are inside the IC chip, but the DLL module is outside the IC chip, all connected together, and the given reference is collectively transmitted Signal, each IC chip is connected to the lumped DLL module through a common IO port, and its structure is:
  • the dual-input PLL1, PLL2 and m DLLs of PLLm are connected to each other.
  • the DLL module compensates for the transmission phase shift, collectively transmits the given reference signal, and connects to PLL1, PLL2 and PLLm through the common IO port respectively, so that each IC on the chip The LO signal of the chip is synchronized.
  • the dual-input PLL star coupling structure and the dual-input PLL used in the butterfly coupling structure include an LC VCO oscillator, an injection-locked two-frequency divider, a four-frequency divider, and a single-wire connection block 1.
  • connection of the dual-input PLL is as follows: the transmission line connected to one end of the PLL is connected to an input end of the single-line connection block one; the output end of the single-line connection block one is connected to the input end of the buffer BUF3 and the input end of the buffer BUF4; single-line connection block The other input end of one is connected to the output end of the buffer BUF1; the output end of the buffer BUF3 is connected to an input end of the mixer Mixer1; the output end of the buffer BUF4 is connected to an input end of the mixer Mixer2; The output terminal of the mixer Mixer1 is connected to the input terminals of the drivers GM1 and GM7; the output terminal of the mixer Mixer2 is connected to the input terminals of the drivers GM2 and GM8; the output terminals of the drivers GM7 and GM8 are both connected to the control terminal and the single-wire connection block 1.
  • the input end of the low-pass filter LPF3 is connected; the other input end of the mixer Mixer1, the other input end of the Mixer2 and the output end of the four divider, the input end of the buffer BUF1, the input end of the buffer BUF2 and the mixer
  • One input of Mixer3 and one input of Mixer4 are connected; the input of the four-frequency divider is connected to the output of the injection-locked two-frequency divider; the input of the injection-locked two-frequency divider is connected to the output of the LC VCO oscillator
  • the input of the LC VCO oscillator is connected to the output of the drivers GM1, GM2, GM3, GM4 and the input of the low-pass filter LPF1;
  • the other input of the mixer Mixer3 is connected to the output of the buffer BUF5 ;
  • the other input of the mixer Mixer4 is connected to the output of the buffer BUF6; the output of the mixer Mixer3 is connected to the input of the drivers GM3 and GM5; the output of
  • the interconnection between the dual-input PLL adopts a transmission line based on a lumped cell ladder network of left-hand material, which is characterized in that the lumped cell ladder network is cascaded with LC cells of the same infinitesimal circuit model.
  • the transmission coefficient under lossless conditions is shown in the following formula
  • C is the capacitance value per unit length of the transmission line
  • L is the inductance value per unit length of the transmission line
  • ⁇ is the signal angular velocity of the transmission line.
  • the on-chip synchronization self-repair system of the present invention can realize strict synchronization of each radio frequency transceiver chip in the array element tile under the influence of any environment, and the system has a small area, low loss and strong self-adaptation.
  • the invention adopts a transmission line based on an adjustable left-handed material as the delay line. Since the left-hand transmission line can produce a leading phase, it can compensate for the positive time delay in single tone transmission. In addition, a ladder network of capacitive inductance lumped unit is used at low frequencies, and only a short transmission line is needed to complete synchronous compensation, with low loss and short physical distance.
  • Figure 1 is a schematic diagram of the structure of an on-chip synchronous self-repair system in an array element tile based on a low-frequency reference signal.
  • Figure 1a is a dual-input PLL star coupling structure
  • Figure 1b is a dual-input PLL butterfly coupling structure;
  • Figure 2 is a schematic diagram of a dual-input PLL structure
  • Figure 3 is a schematic diagram of an equivalent circuit of an artificial transmission line based on left-handed materials
  • Figure 4 is a schematic diagram of the simulation results of the left-hand transmission line phase.
  • the system adopts dual-input PLL star coupling structure or dual-input PLL butterfly coupling structure, and single-line coupling between PLLs and dual-input PLL star coupling
  • the structure connects n dual-input PLLs through chain closure, and transmits a quarter of the local oscillator signal to each other for interlocking to achieve synchronization of the on-chip local oscillator signal;
  • the dual-input PLL butterfly coupling structure connects m each dual input through lumped Type PLL, through a given reference signal to synchronize the local oscillator signals on each IC chip on the chip; where n ⁇ 3, m ⁇ 3, the interconnection between the PLLs uses a transmission line based on left-hand materials.
  • dual-input PLLs in the dual-input PLL star coupling structure or dual-input PLL butterfly coupling structure, as shown in Figure 1, where (a) is the dual-input PLL star-shaped
  • the coupling structure is composed of dual-input PLL1, PLL2, PLL3, and PLL4.
  • the dual-input PLL is in their own IC chip.
  • the A-end of the dual-input PLL1 is connected to the B-end of the dual-input PLL2.
  • the A terminal is connected to the B terminal of the dual input PLL3, the A terminal of the dual input PLL3 is connected to the B terminal of the dual input PLL4, and the A terminal of the dual input PLL4 is connected to the B terminal of the dual input PLL1 to form a closed loop
  • the lines connected between the PLLs can realize bidirectional transmission.
  • Each chip transmits a quarter of the local oscillator signal to each other for interlocking, and the local oscillator signal is synchronized with the reference signal through a phase-locked loop to ensure the phase synchronization of each IC chip on the chip.
  • Figure 1 (b) is a dual-input PLL butterfly coupling structure, composed of dual-input PLL1, PLL2, PLL3, and PLL4.
  • the PLL and LO modules are in their respective IC chips, and the DLL modules are all outside the IC chip.
  • the dual-input PLL1 is connected with the DLL modules of the dual-input PLL2, the dual-input PLL3, and the dual-input PLL4. Given a reference signal, it is connected to the corresponding PLL module through the DLL, and the transmission line can realize bidirectional transmission.
  • Dual-input PLL consists of LC VCO oscillator; Injection-Locked 2-Divider; Four-divider Div4; Single-wire coupling block1, Single-wire coupling block2; Phase detector PD1, PD2 ; Drivers GM1, GM2, GM3, GM4, GM5, GM6, GM7, GM8; buffers BUF1, BUF2, BUF3, BUF4, BUF5, BUF6 and low-pass filters LPF1, LPF2, LPF3.
  • the phase detector PD1 is composed of mixers Mixer1 and Mixer2, and the phase detector PD2 is composed of mixers Mixer3 and Mixer4.
  • the connection mode of the dual-input PLL is shown in Figure 2:
  • the transmission line of the A end is connected to the single-wire coupling block 1 end a; the single-wire coupling block 1 c end and the buffer BUF3 end a, buffer
  • the terminal a of the single-wire coupling block 1 is connected to the terminal a of the buffer BUF1;
  • the terminal d of the single-wire coupling block 1 is connected to the terminal b of the driver GM7 and the terminal b of the driver GM8 ,
  • the low-pass filter LPF3 is connected to end a;
  • the b end of the buffer BUF3 is connected to the a end of the mixer Mixer1;
  • the b end of the buffer BUF4 is connected to the a end of the mixer Mixer2;
  • the c end of the mixer Mixer1 Connect with terminal a of driver GM1 and terminal a of driver GM7;
  • terminal c of mixer Mixer2 is connected with terminal a of driver GM
  • the LO chain is composed of LC-VCO, which can drive a low-power frequency adjustable injection-locked two-frequency divider, and then generate a signal through the four-frequency divider Div4 and drive the phase detector And the output buffers BUF1 and BUF2 matched to 50 ⁇ . Two-way coupling is realized through the output buffer in the dual-input PLL, and the VCO signal and reference signal at each common IO port are distinguished. And by introducing an adjustable phase shift greater than 2 ⁇ between the output driver (BUF1 K or BUF2 K ) in PLP K and the input of the phase detector (PD2 K-1 or PD1 K+1 ) in the adjacent PLL.
  • the phase shift generated on the transmission line connected between the PLLs can be fine-tuned to ensure the quadrature phase difference between the input signals of the phase detectors PD1 and PD2.
  • Figure 3 shows the equivalent circuit diagram of a transmission line based on adjustable left-handed materials used for connection between PLLs.
  • the interconnection between dual-input PLLs uses a transmission line of a lumped unit ladder network based on left-handed materials.
  • the ladder network passes through stages.
  • LC unit shown in Figure 3 its unit length immittance value is very small, and its transmission coefficient is shown in the following formula under lossless conditions
  • C is the capacitance value per unit length of the transmission line
  • L is the inductance value per unit length of the transmission line
  • ⁇ is the signal angular velocity of the transmission line.
  • Figure 4 shows a schematic diagram of the simulation results of the left-hand material transmission line. Since the left-hand transmission line can produce a leading phase, it can compensate for the positive delay in single-tone transmission. At low frequencies, a ladder network of capacitive inductance lumped cells is used. Only a short transmission line is needed to complete synchronous compensation, so that the transmission line loss is low and the physical distance is short. Then the delay phase lock loop ensures that the reference signal is in the same phase in each RF transceiver chip to automatically Repair the asynchronous phenomenon caused by environmental changes.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Software Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

一种基于低频参考信号的片上同步自修复系统，该系统采用双输入型PLL星状耦合结构或双输入型PLL蝶形耦合结构，通过发射出去的参考信号和接收到的参考信号同步使整个回路的延时是参考信号的整数倍，以此保证各IC芯片的本振信号同步，并应用基于可调左手材料的传输线作为延迟线连接双输入型PLL，实现低损耗，同时减小了延迟线的物理距离。该系统具有面积小、损耗低，自适应强，在各种环境下严格同步的优点。

Description

一种基于低频参考信号的片上同步自修复系统 技术领域
本发明涉及雷达相控阵领域，具体涉及相控阵列中阵元瓦片上数字收发芯片间本振信号相位的同步自修复系统。
背景技术
在大型阵列中，如何同步各个阵元是相控阵的关键技术。阵列使用要求严格同步，对于模拟阵各阵元之间相位差固定，对于数字阵各阵元之间相位相同；大型数字相控阵通常由多个阵元瓦片构成，各阵元瓦片包含几个到几十个数字收发芯片。系统中有两类同步要求：阵元瓦片内同步和阵元瓦片间同步。环境的变化会导致安装时的同步失效，阵元瓦片内多个IC芯片的LO信号之间存在相位偏移，这种静态偏移对于相控阵来说是不希望出现的，需要最小化实现阵元瓦片内的同步。
另外，同步系统需要将时延补到整数倍周期，由于低频信号的波长太长(如10MHz的参考信号在空气中的波长为30米)，而阵元瓦片的尺寸通常远小于1米，采用低频同步系统需要产生长达30米的等效延迟线，这是不可以接受的。
发明内容
针对现有技术的不足，本发明提出一种基于可调左手材料传输线的双输入型PLL耦合的片上同步自修复系统，该系统基于低频参考信号，整个同步系统连接成星状或蝶形结构，IC芯片通过锁相环将发射出去的参考信号和接收到的参考信号同步，假设各阵元瓦片可以得到一个相位相同的参考信号，在此基础上保证瓦片内各射频收发芯片的本振信号同步。
本发明实现上述目的所采用的技术方案如下：
一种基于低频参考信号的片上同步自修复系统，其特征在于，所述的系统采用双输入型PLL星状耦合结构或双输入型PLL蝶形耦合结构，且PLL之间单线耦合，双输入型PLL星状耦合结构通过链式闭合连接n个双输入型PLL，互传四分之一的本振信号进行互锁实现片上本振信号同步；双输入型PLL蝶形耦合结构通过集总连接m个双输入型PLL，通过给定的参考信号使得片内各IC芯片上的本振信号同步；其中，n≥3，m≥3，所述的双输入型PLL间的互连采用基于左手材料的传输线。
进一步地，所述的双输入型PLL星状耦合结构，其特征在于，其双输入型PLL模块在IC芯片内，各个IC芯片依次通过一个公共IO端口互连，通过DLL模块补偿传输线产生的互连 相移，其结构为：
双输入型PLL1的一公共IO端与双输入型PLL2的一公共IO端相连，双输入型PLL2的另一公共IO端与双输入型PLL3的一公共IO端相连，双输入型PLL3的另一公共IO端与双输入型PLL4的一公共IO端相连，以此类推，双输入型PLLn-1的一公共IO端与双输入型PLLn的一公共IO端相连，双输入型PLLn的另一公共IO端与双输入型PLL1的另一公共IO端相连，形成一个闭合环路。
进一步地，所述的双输入型PLL蝶形耦合结构，其特征在于，其LO以及PLL模块在IC芯片内，但其DLL模块处于IC芯片外，全部连接在一起，集总传输给定的参考信号，每个IC芯片与集总DLL模块通过一个公共IO端口相连，其结构为：
双输入型PLL1、PLL2直到PLLm的m个DLL彼此相连，经过DLL模块补偿传输相移，集总传输给定的参考信号，并通过公共IO端口分别与PLL1、PLL2直到PLLm相连，使片上各个IC芯片的LO信号同步。
进一步地，所述的双输入型PLL星状耦合结构和蝶形耦合结构中用到的双输入型PLL，其包括LC VCO振荡器、注入锁定二分频器、四分频器、单线连接块一、单线连接块二；鉴相器PD1、PD2；驱动器GM1、GM2、GM3、GM4、GM5、GM6、GM7、GM8；缓冲器BUF1、BUF2、BUF3、BUF4、BUF5、BUF6和低通滤波器LPF1、LPF2、LPF3，其中鉴相器PD1包括混频器Mixer1和Mixer2，鉴相器PD2包括混频器Mixer3和Mixer4，
双输入型PLL的连接如下：PLL一端连接的传输线与单线连接块一的一输入端相连；单线连接块一的输出端与缓冲器BUF3的输入端、缓冲器BUF4的输入端相连；单线连接块一的另一输入端与缓冲器BUF1的输出端相连；缓冲器BUF3的输出端与混频器Mixer1的一输入端相连；缓冲器BUF4的输出端与混频器Mixer2的一输入端相连；混频器Mixer1的输出端与驱动器GM1、GM7的输入端相连；混频器Mixer2的输出端与驱动器GM2、GM8的输入端相连；驱动器GM7、GM8的输出端均与单线连接块一的控制端和低通滤波器LPF3的输入端相连；混频器Mixer1的另一输入端、Mixer2的另一输入端与四分频器的输出端、缓冲器BUF1的输入端、缓冲器BUF2的输入端以及混频器Mixer3的一输入端、Mixer4的一输入端相连；四分频器的输入端与注入锁定二分频器的输出端相连；注入锁定二分频器的输入端与LC VCO振荡器的输出端相连；LC VCO振荡器的输入端与驱动器GM1、GM2、GM3、GM4的输出端以及低通滤波器LPF1的输入端相连；混频器Mixer3的另一输入端与缓冲器BUF5的输出端相连；混频器Mixer4的另一输入端与缓冲器BUF6的输出端相连；混频器Mixer3 的输出端与驱动器GM3、GM5的输入端相连；混频器Mixer4的输出端与驱动器GM4、GM6的输入端相连；缓冲器BUF5、BUF6的输入端均与单线连接块二的输出端相连；驱动器GM5、GM6的输出端均与低通滤波器LPF2的输入端、单线连接块二的控制端相连；单线连接块二的一输入端与缓冲器BUF2的输出端相连；单线连接块二的另一输入端与PLL另一端的传输线相连。
进一步地，所述的双输入型PLL间的互连采用基于左手材料的集总单元梯形网络的传输线，其特征在于，该集总单元梯形网络通过级联与无穷小电路模型相同的LC单元，在无损情况下其传输系数如下式所示
Figure PCTCN2020084002-appb-000001
其中，C为传输线单位长度的电容值，L为传输线单位长度的电感值，ω为传输线的信号角速度。
本发明的有益效果：
本发明的片上同步自修复系统，能够在任意环境的影响下，实现阵元瓦片内的各个射频收发芯片严格同步，并且该系统面积小、损耗低、自适应强。
本发明采用基于可调左手材料的传输线作为延迟线，由于左手传输线可以产生超前的相位，在单音传输中能够补偿正的时延。并且在低频采用电容电感集总单元梯形网络，只需要较短的传输线就可以完成同步补偿，损耗低并且物理距离短。
附图说明
图1是基于低频参考信号的阵元瓦片内的片上同步自修复系统结构示意图，图1a为双输入型PLL星状耦合结构，图1b为双输入型PLL蝶形耦合结构；
图2是双输入型PLL结构示意图；
图3是基于左手材料的人造传输线的等效电路示意图；
图4是左手传输线相位的仿真结果示意图。
具体实施方式
下面根据附图和优选实施例详细描述本发明，本发明的目的和效果将变得更加明白，以下结合附图和实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
一种基于低频参考信号的片上同步自修复系统，所述的系统采用双输入型PLL星状耦合结构或双输入型PLL蝶形耦合结构，且PLL之间单线耦合，双输入型PLL星状耦合结构通 过链式闭合连接n个双输入PLL，互传四分之一的本振信号进行互锁实现片内本振信号同步；双输入型PLL蝶形耦合结构通过集总连接m个各双输入型PLL，通过给定的参考信号使得片内各IC芯片上的本振信号同步；其中，n≥3，m≥3，所述的PLL间的互连采用基于左手材料的传输线。
本实施例中双输入型PLL星状耦合结构或双输入型PLL蝶形耦合结构中双输入型PLL均为4个，如图1所示，图1中(a)为双输入型PLL星状耦合结构，由双输入型PLL1、PLL2、PLL3、PLL4组成，双输入型PLL都在各自的IC芯片内，双输入型PLL1的A端与双输入型PLL2的B端相连，双输入型PLL2的A端与双输入型PLL3的B端相连，双输入型PLL3的A端与双输入型PLL4的B端相连，双输入型PLL4的A端与双输入型PLL1的B端相连，形成一个闭合环路，PLL间相连的线可以实现双向传输。各芯片互传四分之一的本振信号进行互锁，通过锁相环将本振信号和参考信号同步来保证片上各IC芯片相位同步。
图1中(b)为双输入型PLL蝶形耦合结构，由双输入型PLL1、PLL2、PLL3、PLL4组成，其中PLL和LO模块都在各自的IC芯片内，DLL模块都在IC芯片外，双输入型PLL1与双输入型PLL2、双输入型PLL3、双输入型PLL4的DLL模块连接在一起，给定一个参考信号，通过DLL与对应的PLL模块相连，传输线可以实现双向传输。
图2所示为耦合结构中用到的双输入型PLL结构示意图。双输入型PLL由LC VCO振荡器；注入锁定二分频器Injection-Locked 2-Divider；四分频器Div4；单线连接块Single-wire coupling block1、Single-wire coupling block2；鉴相器PD1、PD2；驱动器GM1、GM2、GM3、GM4、GM5、GM6、GM7、GM8；缓冲器BUF1、BUF2、BUF3、BUF4、BUF5、BUF6和低通滤波器LPF1、LPF2、LPF3组成。其中鉴相器PD1由混频器Mixer1和Mixer2组成，鉴相器PD2由混频器Mixer3和Mixer4组成。
双输入型PLL的连接方式如图2所示：A端的传输线与单线连接块single-wire coupling block1的a端相连；单线连接块single-wire coupling block1的c端与缓冲器BUF3的a端、缓冲器BUF4的a端相连；单线连接块single-wire coupling block1的b端与缓冲器BUF1的a端相连；单线连接块single-wire coupling block1的d端与驱动器GM7的b端、驱动器GM8的b端、低通滤波器LPF3的a端相连；缓冲器BUF3的b端与混频器Mixer1的a端相连；缓冲器BUF4的b端与混频器Mixer2的a端相连；混频器Mixer1的c端与驱动器GM1的a端、驱动器GM7的a端相连；混频器Mixer2的c端与驱动器GM2的a端、驱动器GM8的a端相连；混频器Mixer1的b端、混频器Mixer2的b端与四分频器Div4的a端、缓冲器BUF1 的b端、缓冲器BUF2的b端以及混频器Mixer3的b端、混频器Mixer4的b端相连；四分频器Div4的b端与注入锁定二分频器Injection-Locked 2-Divider的a端相连；注入锁定二分频器Injection-Locked 2-Divider的b端与LC VCO振荡器的a端相连；LC VCO振荡器的b端与驱动器GM1的b端、驱动器GM2的b端、驱动器GM3的b端、驱动器GM4的b端以及低通滤波器LPF1的a端相连；混频器Mixer3的c端与驱动器GM3的a端、驱动器GM5的a端相连；混频器Mixer4的c端与驱动器GM4的a端、驱动器GM6的a端相连；混频器Mixer3的a端与缓冲器BUF5的b端相连；混频器Mixer4的a端与缓冲器BUF6的b端相连；缓冲器BUF5的a端、缓冲器BUF6的a端与单线连接块single-wire coupling block2的c端相连；单线连接块single-wire coupling block2的b端与缓冲器BUF2的a端相连；单线连接块single-wire coupling block2的a端与B端的传输线相连；单线连接块single-wire coupling block2的d端与驱动器GM5的b端、驱动器GM6的b端以及低通滤波器LPF2的a端相连。
如上所述的双输入型PLL，其工作原理为：LO链由LC-VCO组成，可驱动低功率频率可调的注入锁定二分频器，然后通过四分频器Div4产生信号并驱动鉴相器PD1、PD2以及匹配到50Ω的输出缓冲器BUF1、BUF2。通过双输入型PLL中的输出缓冲器实现双向耦合，同时区分每个公共IO端口处的VCO信号和参考信号。并通过在PLP K中的输出驱动器(BUF1 K或BUF2 K)与相邻的PLL中的鉴相器(PD2 K-1或PD1 K+1)输入端之间引入大于2π的可调相移来调节互连相移以实现鉴相器输入间的低静态相位偏移。通过输出缓冲器BUF1和BUF2从CML分频器中选择任意一个正交相位来实现约90度相移的粗调，并通过DLL模块控制IO耦合模块中的可变电容，实现可变相移来补偿PLL间连接的传输线上产生的相移，实现细调，以确保鉴相器PD1、PD2输入信号间的正交相位差。
图3所示为用于PLL间连接的基于可调左手材料的传输线的等效电路示意图，双输入型PLL间的互连采用基于左手材料的集总单元梯形网络的传输线，该梯形网络通过级联如图3所示的LC单元，其单位长度导抗值非常小，在无损情况下其传输系数如下式所示
Figure PCTCN2020084002-appb-000002
其中，C为传输线单位长度的电容值，L为传输线单位长度的电感值，ω为传输线的信号角速度。
图4所示为左手材料传输线的仿真结果示意图。由于左手传输线可以产生超前的相位，在单音传输中能够补偿正的时延。在低频采用电容电感集总单元梯形网络，只需要较短的传输线就可以完成同步补偿，使得传输线损耗低并且物理距离短，然后通过延迟锁相环保证参 考信号在各个射频收发芯片相位相同从而自动修复环境变化引起的不同步现象。
本领域普通技术人员可以理解，以上所述仅为发明的优选实例而已，并不用于限制发明，尽管参照前述实例对发明进行了详细的说明，对于本领域的技术人员来说，其依然可以对前述各实例记载的技术方案进行修改，或者对其中部分技术特征进行等同替换。凡在发明的精神和原则之内，所做的修改、等同替换等均应包含在发明的保护范围之内。

Claims (5)

  1. 一种基于低频参考信号的片上同步自修复系统，其特征在于，所述的系统采用双输入型PLL星状耦合结构或双输入型PLL蝶形耦合结构，且PLL之间单线耦合，双输入型PLL星状耦合结构通过链式闭合连接n个双输入型PLL，互传四分之一的本振信号进行互锁实现片上本振信号同步；双输入型PLL蝶形耦合结构通过集总连接m个双输入型PLL，通过给定的参考信号使得片内各IC芯片上的本振信号同步；其中，n≥3，m≥3，所述的双输入型PLL间的互连采用基于左手材料的传输线。
  2. 根据权利要求1所述的基于低频参考信号的片上同步自修复系统，其特征在于，所述的双输入型PLL星状耦合结构，其双输入型PLL模块在IC芯片内，各个IC芯片依次通过一个公共IO端口互连，通过DLL模块补偿传输线产生的互连相移，所述的双输入型PLL星状耦合结构为：
    双输入型PLL1的一公共IO端与双输入型PLL2的一公共IO端相连，双输入型PLL2的另一公共IO端与双输入型PLL3的一公共IO端相连，双输入型PLL3的另一公共IO端与双输入型PLL4的一公共IO端相连，以此类推，双输入型PLLn-1的一公共IO端与双输入型PLLn的一公共IO端相连，双输入型PLLn的另一公共IO端与双输入型PLL1的另一公共IO端相连，形成一个闭合环路。
  3. 根据权利要求1所述的基于低频参考信号的片上同步自修复系统，其特征在于，所述的双输入型PLL蝶形耦合结构，其LO以及PLL模块在IC芯片内，但其DLL模块处于IC芯片外，全部连接在一起，集总传输给定的参考信号，每个IC芯片与集总DLL模块通过一个公共IO端口相连，所述的双输入型PLL蝶形耦合结构为：
    双输入型PLL1、PLL2直到PLLm的m个DLL彼此相连，经过DLL模块补偿传输相移，集总传输给定的参考信号，并通过公共IO端口分别与PLL1、PLL2直到PLLm相连，使片上各个IC芯片的LO信号同步。
  4. 根据权利要求2或3所述的基于低频参考信号的片上同步自修复系统，其特征在于，所述的双输入型PLL包括LC VCO振荡器、注入锁定二分频器、四分频器、单线连接块一、单线连接块二；鉴相器PD1、PD2；驱动器GM1、GM2、GM3、GM4、GM5、GM6、GM7、GM8；缓冲器BUF1、BUF2、BUF3、BUF4、BUF5、BUF6和低通滤波器LPF1、LPF2、LPF3，其中鉴相器PD1包括混频器Mixer1和Mixer2，鉴相器PD2包括混频器Mixer3和Mixer4。
    双输入型PLL的连接如下：PLL一端连接的传输线与单线连接块一的一输入端相连；单 线连接块一的输出端与缓冲器BUF3的输入端、缓冲器BUF4的输入端相连；单线连接块一的另一输入端与缓冲器BUF1的输出端相连；缓冲器BUF3的输出端与混频器Mixer1的一输入端相连；缓冲器BUF4的输出端与混频器Mixer2的一输入端相连；混频器Mixer1的输出端与驱动器GM1、GM7的输入端相连；混频器Mixer2的输出端与驱动器GM2、GM8的输入端相连；驱动器GM7、GM8的输出端均与单线连接块一的控制端和低通滤波器LPF3的输入端相连；混频器Mixer1的另一输入端、Mixer2的另一输入端与四分频器的输出端、缓冲器BUF1的输入端、缓冲器BUF2的输入端以及混频器Mixer3的一输入端、Mixer4的一输入端相连；四分频器的输入端与注入锁定二分频器的输出端相连；注入锁定二分频器的输入端与LC VCO振荡器的输出端相连；LC VCO振荡器的输入端与驱动器GM1、GM2、GM3、GM4的输出端以及低通滤波器LPF1的输入端相连；混频器Mixer3的另一输入端与缓冲器BUF5的输出端相连；混频器Mixer4的另一输入端与缓冲器BUF6的输出端相连；混频器Mixer3的输出端与驱动器GM3、GM5的输入端相连；混频器Mixer4的输出端与驱动器GM4、GM6的输入端相连；缓冲器BUF5、BUF6的输入端均与单线连接块二的输出端相连；驱动器GM5、GM6的输出端均与低通滤波器LPF2的输入端、单线连接块二的控制端相连；单线连接块二的一输入端与缓冲器BUF2的输出端相连；单线连接块二的另一输入端与PLL另一端的传输线相连。
  5. 根据权利要求2或3所述的基于低频参考信号的片上同步自修复系统，其特征在于，所述的双输入型PLL间的互连采用基于左手材料的集总单元梯形网络的传输线，该网络通过级联与无穷小电路模型相同的LC单元，在无损情况下其传输系数如下式所示
    Figure PCTCN2020084002-appb-100001
    其中，C为传输线单位长度的电容值，L为传输线单位长度的电感值，ω为传输线的信号角速度。
PCT/CN2020/084002 2019-04-11 2020-04-09 一种基于低频参考信号的片上同步自修复系统 Ceased WO2020207443A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US17/043,667 US11705908B2 (en) 2019-04-11 2020-04-09 On-chip synchronous self-repairing system based on low-frequency reference signal
JP2020558604A JP7240010B2 (ja) 2019-04-11 2020-04-09 低周波基準信号に基づくオンチップの同期自己修復システム

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910289884.XA CN110209625B (zh) 2019-04-11 2019-04-11 一种基于低频参考信号的片上同步自修复系统
CN201910289884.X 2019-04-11

Publications (1)

Publication Number Publication Date
WO2020207443A1 true WO2020207443A1 (zh) 2020-10-15

Family

ID=67785287

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/084002 Ceased WO2020207443A1 (zh) 2019-04-11 2020-04-09 一种基于低频参考信号的片上同步自修复系统

Country Status (4)

Country Link
US (1) US11705908B2 (zh)
JP (1) JP7240010B2 (zh)
CN (1) CN110209625B (zh)
WO (1) WO2020207443A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110209625B (zh) * 2019-04-11 2020-08-11 浙江大学 一种基于低频参考信号的片上同步自修复系统
WO2023159649A1 (zh) * 2022-02-28 2023-08-31 华为技术有限公司 一种相控阵装置、通信设备及控制方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103608694A (zh) * 2011-04-12 2014-02-26 德克萨斯仪器股份有限公司 太赫兹相控阵列系统的模拟基带电路
CN104020453A (zh) * 2013-03-01 2014-09-03 富士通株式会社 电子电路、雷达设备和对雷达设备执行自诊断的方法
CN105790760A (zh) * 2015-01-14 2016-07-20 英飞凌科技股份有限公司 通过使用减小的频率信号传输使多个振荡器同步的系统和方法
CN107251319A (zh) * 2015-02-26 2017-10-13 特拉维夫大学拉莫特有限公司 用于改进片上天线的效率的技术
CN109375182A (zh) * 2018-10-30 2019-02-22 浙江大学 雷达接收机幅相一致性校正系统
CN109379102A (zh) * 2018-12-06 2019-02-22 西南电子技术研究所（中国电子科技集团公司第十研究所） 多通道捷变频收发装置
US10243573B1 (en) * 2018-03-27 2019-03-26 Texas Instruments Incorporated Phase syncronizing PLL output across reference and VCO clock domains
CN110209625A (zh) * 2019-04-11 2019-09-06 浙江大学 一种基于低频参考信号的片上同步自修复系统

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5634343B2 (ja) 2011-07-05 2014-12-03 三菱電機株式会社 注入同期発振装置
JP5811863B2 (ja) 2012-01-26 2015-11-11 富士通株式会社 クロック分配器、及び、電子装置
US9225507B1 (en) * 2013-06-04 2015-12-29 Pmc-Sierra Us, Inc. System and method for synchronizing local oscillators
JP6263906B2 (ja) 2013-08-28 2018-01-24 富士通株式会社 電子回路および制御方法
US9270289B2 (en) 2014-02-13 2016-02-23 Fujitsu Limited Monolithic signal generation for injection locking
US9602587B2 (en) * 2014-06-26 2017-03-21 Altera Corporation Multiple plane network-on-chip with master/slave inter-relationships
US9825694B2 (en) * 2015-08-18 2017-11-21 Maxlinear, Inc. Transceiver array with adjustment of local oscillator signals based on phase difference
US9735793B2 (en) 2015-12-08 2017-08-15 Nxp Usa, Inc. Low-power clock repeaters and injection locking protection for high-frequency clock distributions
US10439623B2 (en) 2017-05-30 2019-10-08 Globalfoundries Inc. Injection locked oscillator system and processes
US10680623B2 (en) * 2018-04-17 2020-06-09 Huawei Technologies Co., Ltd. System for coherent distribution of oscillator signal
US10374558B1 (en) * 2018-04-30 2019-08-06 Speedlink Technology Inc. Wideband distributed power amplifier utilizing metamaterial transmission line conception with impedance transformation

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103608694A (zh) * 2011-04-12 2014-02-26 德克萨斯仪器股份有限公司 太赫兹相控阵列系统的模拟基带电路
CN104020453A (zh) * 2013-03-01 2014-09-03 富士通株式会社 电子电路、雷达设备和对雷达设备执行自诊断的方法
CN105790760A (zh) * 2015-01-14 2016-07-20 英飞凌科技股份有限公司 通过使用减小的频率信号传输使多个振荡器同步的系统和方法
CN107251319A (zh) * 2015-02-26 2017-10-13 特拉维夫大学拉莫特有限公司 用于改进片上天线的效率的技术
US10243573B1 (en) * 2018-03-27 2019-03-26 Texas Instruments Incorporated Phase syncronizing PLL output across reference and VCO clock domains
CN109375182A (zh) * 2018-10-30 2019-02-22 浙江大学 雷达接收机幅相一致性校正系统
CN109379102A (zh) * 2018-12-06 2019-02-22 西南电子技术研究所（中国电子科技集团公司第十研究所） 多通道捷变频收发装置
CN110209625A (zh) * 2019-04-11 2019-09-06 浙江大学 一种基于低频参考信号的片上同步自修复系统

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
YANG, LIJIE ET AL.: "Key technologies of wideband digital phased array for ocean surveillance", SCIENCE & TECHNOLOGY REVIEW, vol. 35, no. 20, 28 October 2017 (2017-10-28), DOI: 20200628205321A *

Also Published As

Publication number Publication date
US11705908B2 (en) 2023-07-18
JP2021520744A (ja) 2021-08-19
CN110209625B (zh) 2020-08-11
JP7240010B2 (ja) 2023-03-15
US20220052695A1 (en) 2022-02-17
CN110209625A (zh) 2019-09-06

Similar Documents

Publication Publication Date Title
US7368961B2 (en) Clock distribution network supporting low-power mode
JP5022575B2 (ja) クロック信号復元のための回路及び方法
CN102342024B (zh) 用于在同步系统中使用的基于晶体的振荡器
KR100811766B1 (ko) 주파수-체배 지연 동기 루프 및 그를 이용하여 출력 클록 신호를 생성하는 방법
CN104753524B (zh) 一种延时锁定环路
US6897699B1 (en) Clock distribution network with process, supply-voltage, and temperature compensation
CN110581709B (zh) 一种基于多级同步的零延时锁相环频率综合器
CN104836573B (zh) 一种超大面阵cmos相机多路高速信号的同步时钟系统
CN106716831B (zh) 多相位时钟生成
US11777475B2 (en) Multiple adjacent slicewise layout of voltage-controlled oscillator
US20160191062A1 (en) Semiconductor Device and Method for Accurate Clock Domain Synchronization Over a Wide Frequency Range
CN110209625B (zh) 一种基于低频参考信号的片上同步自修复系统
CN115987275B (zh) 校准方法、校准装置及多相时钟电路
KR20010034111A (ko) 자기 보상 위상 검출기
US20060020836A1 (en) Semiconductor integrated circuit
CN104615192B (zh) 一种强化异步时钟管理的复杂可编程逻辑器件
US8269533B2 (en) Digital phase-locked loop
US11916558B1 (en) DDR phy parallel clock paths architecture
US10659059B2 (en) Multi-phase clock generation circuit
Liu et al. A Low-Jitter 10GHz PLL Based on Adaptive Bandwidth Technique for Muti-Rate Serial Link Data Transmitter
CN116455362A (zh) 一种fpga内部实现环形振荡器的方法
CN121614000A (zh) 基于低频校准时钟的多系统时钟同步方法
Lin et al. Research on Self-biased PLL Technique for High Speed SERDES Chips
JPH05191392A (ja) クロック出力回路

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2020558604

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20787719

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20787719

Country of ref document: EP

Kind code of ref document: A1