WO2020206973A1 - 阵列基板驱动电路及阵列基板驱动方法 - Google Patents

阵列基板驱动电路及阵列基板驱动方法 Download PDF

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Publication number
WO2020206973A1
WO2020206973A1 PCT/CN2019/111904 CN2019111904W WO2020206973A1 WO 2020206973 A1 WO2020206973 A1 WO 2020206973A1 CN 2019111904 W CN2019111904 W CN 2019111904W WO 2020206973 A1 WO2020206973 A1 WO 2020206973A1
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array substrate
level
clock signal
unit
signal
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French (fr)
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周学兵
温亦谦
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present invention relates to the field of display technology, in particular to a display panel of a GOA driving circuit and a driving method.
  • the bezel of the display is gradually narrowed, and it is developing towards a borderless display panel.
  • the array substrate row drive (Gate On Array, GOA) display technology is to integrate GOA units on the array substrate in the existing array substrate with thin film transistors arranged in an array, instead of the old gate drive
  • the unit and the source drive unit are respectively located on the longitudinal and lateral sides of the display panel.
  • the display panel 12 in the display 10 is connected to the driving circuit board 14.
  • the driving circuit board 14 is used to generate data signals and transmit the data signals to the display panel 12 through the data line 140 ⁇ pixel unit.
  • the display 10 also has a GOA circuit 16 on the side of the display panel 12.
  • the GOA circuit 16 receives the start signal 102 and the clock signal 104 from the driving circuit board 14.
  • the GOA circuit 16 has several GOA units, and the GOA circuit 16
  • the gate driving unit is arranged on one side of the array substrate, and the gate driving unit sends scan signals to the display panel 12 row by row through several parallel gate lines 160 to turn on the thin film transistors on the array substrate row by row, In this way, the pixel unit of the display is driven to display the gray scale.
  • the frame area occupied by the conventional gate driving unit is saved, thereby realizing the design of the narrow frame panel.
  • the process of progressive scanning needs to sequentially output high levels to the gate lines.
  • the number of data lines 140 and gate lines 160 includes the equivalent of equivalent capacitance, equivalent inductance, and equivalent resistance.
  • the impedance value will increase as the panel size becomes larger.
  • the CK signal of GOA is transmitted from the near end to the far end, the CK signal received by the far end will be transmitted to the gate line 160 due to propagation delay.
  • the clock signal 104 at the end is delayed (Delay).
  • the GOA circuit 16 shown in FIG. 1 includes multiple GOA units 20.
  • the clock signal 104 has four clock signals CK1-CK4 as an example.
  • the GOA unit of the first stage The scan signal G(1) of the first stage will be generated according to the start signal 102 and the clock signal CK1, and the GOA unit of the second stage will generate the second stage according to the scan signal G(1) and the clock signal CK2 of the previous stage.
  • the GOA unit of the (4n+1)th level will generate the first scan signal G(4n) and the clock signal CK1 of the previous level. (4n+1)-level scanning signal G(4n+1).
  • the clock signal received by the GOA unit of the (4n+1)th stage is the clock signal CK1-n of the nth stage, which is the same as that received by the GOA unit of the first stage.
  • CK1-n has a delay of CK_D.
  • the high level of the clock signal will drive the gate line 160 to output the scan signal. Therefore, the delay of the clock signal will cause the delay G_D of the scan signal, which will reduce the charging time of the pixel at the remote location or cause the wrong charging to cause the panel The screen is abnormal.
  • the present invention provides an array substrate driving circuit, which is arranged in a display panel.
  • the display panel has a plurality of crisscrossed data lines and a plurality of gate lines, including a control unit, a controllable power management chip, Level switching unit and several array substrate row driving units.
  • the control unit is used to generate a start signal, a clock signal and a control signal.
  • the adjustable power management chip is used to generate a reference high level and a reference low level according to the control signal.
  • the level switching unit is used to provide a sub-clock signal according to the control signal, the reference high level, the reference low level, and the clock signal, and according to the control generated by the adjustable power management chip
  • the reference high level and the control reference low level provide a higher level sub-clock signal of the row driving unit of the array substrate at the end.
  • the plurality of array substrate row driving units are arranged on the side of the display panel, each of the array substrate row driving units is connected to one of the gate lines, and the array substrate row driving unit is based on the received sub-clock signal
  • a scan signal is generated to the gate line, wherein the sub-clock signal level received by the row driving unit of the array substrate at the end is higher.
  • the control unit controls the level generated by the power management unit according to the driven pixel position, and the scanning signal level generated by the row driving unit of the array substrate at the end is higher.
  • the present invention also provides an array substrate driving circuit, which is arranged in a display panel.
  • the display panel has a plurality of crisscrossed data lines and a plurality of gate lines, which includes a control unit, a power management unit and a level switching unit.
  • the control unit is used to generate a start signal, a clock signal and a control signal.
  • the power management unit is used to generate a reference high level and a reference low level according to the control signal.
  • the level switching unit is used to provide a sub-clock signal according to the control signal, the reference high level, the reference low level, and the clock signal. Wherein, the control unit controls the level generated by the power management unit according to the driven pixel position.
  • the array substrate driving circuit has a plurality of array substrate row driving units arranged on the side of the display panel, each of the array substrate row driving units is connected to one of the gate lines, and the array The substrate row driving unit generates a scan signal to the gate line according to the received sub-clock signal, wherein the sub-clock signal level received by the array substrate row driving unit at the end is higher.
  • the power management unit is a controllable power management chip, which generates a controllable reference high level and a reference low level according to the control signal, and the level switching unit is based on the control generated by the power management chip
  • the reference high level and the control reference low level provide a higher level sub-clock signal of the row driving unit of the array substrate at the end.
  • the scanning signal level generated by the row driving unit of the array substrate at the end is higher.
  • control unit and the power management unit are connected through an inter-chip bus, a serial peripheral interface or a local bus.
  • the present invention also provides a method for driving an array substrate for a display panel.
  • the display panel has a plurality of data lines and a plurality of gate lines interlaced in a crisscross pattern.
  • the method for driving the array substrate includes: a control unit outputs data signals to all The data line, and generate a start signal, a clock signal, and a control signal; the power management unit generates a reference high level and a reference low level according to the control signal; and the level switch unit generates a reference high level and a reference low level according to the control signal and the reference high The level, the reference low level and the clock signal provide a sub-clock signal.
  • the control unit controls the level generated by the power management unit according to the driven pixel position.
  • an array substrate drive circuit having a plurality of array substrate row drive units is arranged on the side of the display panel, each of the array substrate row drive units is connected to one of the gate lines, and the array substrate
  • the row driving unit generates a scan signal to the gate line according to the received sub-clock signal, wherein the level of the sub-clock signal received by the row driving unit of the array substrate at the end is higher.
  • the power management unit is a controllable power management chip, which generates a controllable reference high level and a reference low level according to the control signal, and the level switching unit is based on the control generated by the power management chip
  • the reference high level and the control reference low level provide a higher level sub-clock signal of the row driving unit of the array substrate at the end.
  • the scanning signal level generated by the row driving unit of the array substrate at the end is higher.
  • control unit and the power management unit are connected through an inter-chip bus, a serial peripheral interface or a local bus.
  • the advantage of the present invention is that the array substrate driving circuit provided by the present invention can reduce the delay of the end clock signal and the scanning signal caused by the line parasitic impedance of the large-size display panel, and improve the display quality.
  • Figure 1 shows a schematic diagram of the structure of an existing GOA display
  • FIG. 2 shows a schematic diagram of the timing delay of the clock signal and the scanning signal in the existing GOA display
  • FIG. 3 is a schematic diagram of the structure of the display panel of the present invention.
  • Figure 5 shows a timing diagram of the clock signal of the present invention
  • FIG. 6 is a schematic diagram showing the delay of the clock signal and the scanning signal in the display panel of the present invention.
  • FIG. 3 is a schematic diagram of the structure of the display panel of the present invention.
  • the display panel 30 of the present invention includes a display panel 32, a GOA circuit 36, a control unit 302, a level switching unit 304, and a power management unit 306.
  • the control unit 302 may be a time controller chip, and the level switching unit 304 It may be a level shifter chip, and the power management unit 306 may be a power management integrated chip. circuit, PMIC).
  • One or any combination of the control unit 302, the level switching unit 304, and the power management unit 306 may be located in the driving circuit board of the display panel, or may be independently disposed outside the driving circuit board.
  • control unit 302 and the power management unit 306 are connected through an Inter-Integrated Circuit Bus (Inter-Integrated Circuit Bus, I2C Bus), Serial Peripheral Interface (Serial Peripheral Interface, SPI), local bus, etc.
  • the control unit 302 generates a clock signal and transmits it to the level switch unit 304.
  • the power management unit 306 provides a high level signal VGH and a low level signal VGL to the level switch unit 304 as a reference level.
  • the level switch unit 304 uses the clock signal ,
  • the high-level signal VGH and the low-level signal VGL generate sub-clock signals CK1-CK4 to the GOA circuit 36.
  • the display panel 30 of the present invention is characterized in that the control unit 302 enables the power management unit 306 to adjust the level of the reference high-level signal VGH according to the pixel position to be driven, and the power management unit 306 outputs the corresponding output according to the pixel position to be driven.
  • the reference high-level signal VGH to the level switching unit 304.
  • the control unit 30 of the present invention controls the power management unit 306 to provide a higher gate line level according to the pixel position to be driven. Refer to the high level signal VGH to shorten the delay time of the end clock signal.
  • the reference low-level signal VGL with the lower the level of the gate line at the end can also be given to achieve the shortened end clock signal. The effect of delay time.
  • FIG. 4 is a schematic diagram of the GOA driving method of the present invention.
  • the GOA unit of the first stage generates the scan signal G(1) of the first stage according to the subclock signal CK1 and the start signal STA
  • the GOA unit of the second stage generates the first scan signal G(1) according to the subclock signal CK2-1 and the scan signal of the upper stage.
  • the second level scan signal G(2), and so on, the GOA unit of the 4n+1 level generates the (4n+1) level scan according to the sub-clock signal CK1-n and the scan signal G(4n) of the previous level Signal G(4n+1).
  • the control unit 302 controls the power management unit 306 to provide the GOA unit at the end, the higher the reference high level VGH, so that the level switch unit 304 outputs a higher clock signal to the GOA unit at the end
  • the level of the sub-clock signal CK1-n received by the GOA unit of the (4n+1)th stage is higher than the level of the sub-clock signal CK1-1 received by the GOA unit of the first stage.
  • the level of the sub-clock signal CK1-m before the first level and the (4n+1)th is between the levels of CK1-1 and CK1-n.
  • the control unit 306 can also control the power management unit 306 to provide the lower reference low level VGL to the GOA unit at the end.
  • FIG. 5 shows a timing diagram of the clock signal CK output by the power management unit 306, where the interval A is the time of one frame, and the interval B is the time of the next frame.
  • the power management unit 306 is a power management chip with a controllable and adjustable output function.
  • the control unit 302 can further control the power management unit to achieve controllable output, so that the power management unit 306 can be driven according to the
  • the pixel bit value generates a regulated clock signal.
  • the high level and low level of the clock signal are VGH and VGL respectively.
  • the reference high level VGH has the maximum value VGHmax and the minimum value VGHmin
  • the reference low level has the maximum value VGLmax and the minimum value.
  • the level switching unit 304 then generates regulated sub-clock signals CK1-CK4 to the GOA unit 360 in the GOA circuit 36 according to the received clock signal CK.
  • FIG. 6 is a schematic diagram of the delay of the clock signal and the scan signal of the present invention.
  • the several GOA unit 360 units of the present invention generate scan signals according to the received clock signal.
  • the first-stage GOA unit receives the clock signal CK1-1 and generates the first-stage scan signal G(1), the (4n+1)th stage
  • the GOA unit receives the clock signal CK1-n and generates the (4n+1)th stage scanning signal G(4n+1).
  • the delay CK_Delay generated by the clock signal CK1-n received by the (4n+1)-th GOA unit at the end is greatly shortened, while the (4n+1)-th scan signal G(4n+1) generates
  • the delay G_Delay is also greatly shortened, so it can effectively solve the signal delay caused by the parasitic impedance of the transmission line in a large-size display panel, and it can effectively improve the problem of insufficient charging time or incorrect charging due to signal delay. Improve the display quality of the panel.
  • the technical solutions provided by the embodiments of the present invention avoid the problem of clock signal and gate drive signal delay caused by the equivalent impedance of the data lines and scan lines in the GOA driving circuit of the large-size display panel, thereby improving the pixel unit at the end
  • the problem of insufficient charging time or wrong charging improves the display quality.

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  • Physics & Mathematics (AREA)
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Abstract

一种阵列基板驱动电路，设置于显示面板中，所述显示面板具有纵横交错的数条数据线及数条栅极线，其包括控制单元、电源管理单元以及电平切换单元。所述控制单元用来产生起始信号、时钟信号及控制信号。所述电源管理单元用来根据所述控制信号产生参考高电平与参考低电平。所述电平切换单元用来根据所述控制信号、所述参考高电平、所述参考低电平及所述时钟信号，提供子时钟信号。其中，所述控制单元根据所驱动的像素位置控制所述电源管理单元所产生的电平大小。

Description

阵列基板驱动电路及阵列基板驱动方法 技术领域
本发明涉及显示技术领域，尤其是涉及一种GOA驱动电路及驱动方法的显示面板。
 背景技术
随著显示技术的进步，现今显示器除了显示质量进步外，为了让使用者的视觉有更好的视觉体验，显示器的边框也渐渐地窄化，朝向无边框显示面板的方向发展。
其中，阵列基板行驱动(Gate On Array, GOA)显示技术，即是在现有具有以阵列排列的薄膜晶体管的阵列基板中，将GOA单元整合制作于阵列基板上，取代旧有的栅级驱动单元与源级驱动单元分别位于显示面板的纵向与横向侧边的设置。如图１所示现有GOA显示器中，显示器10中的显示面板12与驱动电路板14相接，驱动电路板14用来产生数据信号，并将数据信号通过数据线140传送至显示面板12中的像素单元。此外，显示器10还具有位于显示面板12侧边的GOA电路16，GOA电路16接收来自驱动电路板14的起始信号102与时钟信号104，GOA电路16中具有数个GOA单元，GOA电路16中的栅极驱动单元排列于阵列基板的一侧，栅级驱动单元通过数条平行排列的栅极线160逐行送出扫描信号至显示面板12，以逐行地开启位于阵列基板上的薄膜晶体管，藉此来驱动显示器的像素单元显示灰阶。通过GOA单元整合于阵列基板上的设置，节省旧有的栅极驱动单元所占用的边框面积，以此来实现窄边框面板的设计。
 技术问题
在GOA显示技术中，逐行扫描的过程需要依序对栅极线输出高电平，然而，数据线140与栅极线160数上包含等效电容、等效电感与等效电阻的等效阻抗值会随着面板尺寸变大而增加，对于大尺寸面板，GOA的CK信号从近端传输到远端时，远端接收的CK信号因将产生传播延迟导致传输到栅极线160上远端的时钟信号104出现延迟（Delay）。如图2所示，图1所示的GOA电路16中包含有多个GOA单元20，本发明的实施例是以时钟信号104具有4个时钟信号CK1-CK4为例，第一级的GOA单元会根据起始信号102以及时钟信号CK1来产生第一级的扫描信号G(1)，第二级的GOA单元会根据上一级的扫描信号G(1)以及时钟信号CK2来产生第二级的扫描信号G(2)，以此类推，每四个GOA单元为一组，第（4n+1）级的GOA单元会根据上一级的扫描信号G(4n)以及时钟信号CK1来产生第(4n+1)级的扫描信号G(4n+1)。此时由于传输时钟信号的传输线具有等效阻抗22，因此第(4n+1)级的GOA单元所接收的时钟信号为第n级时钟信号CK1-n，与第一级的GOA单元所接收的时钟信号CK1-1相比，CK1-n具有延迟CK_D。而GOA电路中，时钟信号的高电平会驱动栅极线160输出扫描信号，因此时钟信号的延迟将引起扫描信号的延迟G_D，导致远端位置的像素充电时间减少或出现错充，引起面板画面的异常。
因此，需要提供一种GOA驱动电路及GOA驱动方法，来改善大尺寸的面板因等效阻抗较大而造成的信号延迟问题。
 技术解决方案
为解决上述问题，本发明提供一种阵列基板驱动电路，设置于显示面板中，所述显示面板具有纵横交错的数条数据线及数条栅极线，包括控制单元、可调控电源管理芯片、电平切换单元以及数个阵列基板行驱动单元。所述控制单元用来产生起始信号、时钟信号及控制信号。所述可调控电源管理芯片用来根据所述控制信号产生参考高电平与参考低电平。所述电平切换单元用来根据所述控制信号、所述参考高电平、所述参考低电平及所述时钟信号，提供子时钟信号，并根据所述可调控电源管理芯片产生的调控参考高电平与调控参考低电平，提供较末端的所述阵列基板行驱动单元电平较高的子时钟信号。所述数个阵列基板行驱动单元设置于所显示面板的侧边，每一个所述阵列基板行驱动单元连接至一条所述栅极线，所述阵列基板行驱动单元根据所接收的子时钟信号产生扫描信号至所述栅极线，其中较末端的所述阵列基板行驱动单元所接收的子时钟信号电平较高。其中，所述控制单元根据所驱动的像素位置控制所述电源管理单元所产生的电平大小，末端的阵列基板行驱动单元所产生的扫描信号电平较高。
本发明另提供一种阵列基板驱动电路，设置于显示面板中，所述显示面板具有纵横交错的数条数据线及数条栅极线，其包括控制单元、电源管理单元以及电平切换单元。所述控制单元用来产生起始信号、时钟信号及控制信号。所述电源管理单元用来根据所述控制信号产生参考高电平与参考低电平。所述电平切换单元用来根据所述控制信号、所述参考高电平、所述参考低电平及所述时钟信号，提供子时钟信号。其中，所述控制单元根据所驱动的像素位置控制所述电源管理单元所产生的电平大小。
较佳地，所述阵列基板驱动电路具有数个阵列基板行驱动单元，设置于所述显示面板的侧边，每一个所述阵列基板行驱动单元连接至一条所述栅极线，所述阵列基板行驱动单元根据所接收的子时钟信号产生扫描信号至所述栅极线，其中较末端的所述阵列基板行驱动单元所接收的子时钟信号电平较高。
较佳地，所述电源管理单元为可调控电源管理芯片，根据所述控制信号产生可调控的参考高电平与参考低电平，所述电平切换单元根据所述电源管理芯片产生的调控参考高电平与调控参考低电平，提供较末端的所述阵列基板行驱动单元电平较高的子时钟信号。
较佳地，较末端的阵列基板行驱动单元所产生的扫描信号电平较高。
较佳地，所述控制单元与所述电源管理单元之间通过芯片间总线、串行外设接口或局部总线连接。
本发明另提供一种阵列基板驱动方法，用于显示面板，所述显示面板具有纵横交错的数条数据线及数条栅极线，所述阵列基板驱动方法包括：控制单元输出数据信号至所述数据线，并产生起始信号、时钟信号及控制信号；电源管理单元根据所述控制信号产生参考高电平与参考低电平；以及电平切换单元根据所述控制信号、所述参考高电平、所述参考低电平及所述时钟信号，提供子时钟信号。其中，所述控制单元根据所驱动的像素位置控制所述电源管理单元所产生的电平大小。
较佳地，具有数个阵列基板行驱动单元的阵列基板驱动电路，设置于所述显示面板的侧边，每一个所述阵列基板行驱动单元连接至一条所述栅极线，所述阵列基板行驱动单元根据所接收的子时钟信号产生扫描信号至所述栅极线，其中较末端的所述阵列基板行驱动单元所接收的子时钟信号电平较高。
较佳地，所述电源管理单元为可调控电源管理芯片，根据所述控制信号产生可调控的参考高电平与参考低电平，所述电平切换单元根据所述电源管理芯片产生的调控参考高电平与调控参考低电平，提供较末端的所述阵列基板行驱动单元电平较高的子时钟信号。
较佳地，较末端的阵列基板行驱动单元所产生的扫描信号电平较高。
较佳地，所述控制单元与所述电源管理单元之间通过芯片间总线、串行外设接口或局部总线连接。
 有益效果
本发明的优点在于通过本发明所提供的阵列基板驱动电路可以减少大尺寸显示面板因线路寄生阻抗造成末端时钟信号及扫描信号的延迟，改善显示品质。
 附图说明
图1绘示现有GOA显示器的结构示意图；
图2绘示现有GOA显示器中时钟信号与扫描信号时序延迟示意图；
图3绘示本发明显示面板的结构示意图；
图4绘示本发明阵列基板驱动方法示意图；
图5绘示本发明时钟信号时序图；
图6绘示本发明显示面板中时钟信号与扫描信号延迟示意图。
 本发明的最佳实施方式
下面结合附图对本发明提供的显示面板及显示装置做详细说明。显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图3为本发明显示面板的结构示意图。本发明的显示面板30包含显示面板32、GOA电路36、控制单元302、电平切换单元304以及电源管理单元306，其中控制单元302可以是一个时序控制(time controller)芯片，电平切换单元304可以是一个电平转换(level shifter)芯片，电源管理单元306可以是一个电源管理芯片(power manage integrated circuit, PMIC)。控制单元302、电平切换单元304及电源管理单元306其中之一或其任意组合可以位于显示面板的驱动电路板中，也可以是独立设置于驱动电路板外。较佳地，控制单元302与电源管理单元306之间通过芯片间总线(Inter–Integrated Circuit Bus, I2C Bus)、串行外设接口(Serial Peripheral Interface, SPI)、局部总线等方式连接。控制单元302产生时钟信号并传送到电平切换单元304，电源管理单元306提供高电平信号VGH与低电平信号VGL给电平切换单元304作为参考电平，电平切换单元304根据时钟信号、高电平信号VGH与低电平信号VGL产生子时钟信号CK1-CK4至GOA电路36。本发明的显示面板30特征在于，控制单元302会根据所要驱动的像素位置，使电源管理单元306可调控参考高电平信号VGH的电平高低，电源管理单元306依据所要驱动的像素位置输出对应的参考高电平信号VGH至电平切换单元304。具体而言，由于末端的时钟信号具有较长的延迟时间，因此本发明的控制单元30根据所要驱动的像素位置，控制单元302控制电源管理单元306提供越末端的栅极线电平越高的参考高电平信号VGH，以缩短末端时钟信号的延迟时间。此外，除了给予越末端的栅极线电平越高的参考高电平信号VGH，也可以给予末端的栅极线电平越低的参考低电平信号VGL，以达到所述缩短末端时钟信号延迟时间的效果。
请参考图4，图4所示为本发明的GOA驱动方法示意图。 GOA电路36中具有数个GOA单元360。第一级的GOA单元根据子时钟信号CK1以及起始信号STA产生第一级的扫描信号G(1)，第二级的GOA单元根据子时钟信号CK2-1以及上一级的扫描信号产生第二级的扫描信号G(2)，以此类推，第4n+1级的GOA单元根据子时钟信号CK1-n以及上一级的扫描信号G(4n)产生第(4n+1)级的扫描信号G(4n+1)。本发明所提供的显示面板中，控制单元302会控制电源管理单元306提供给越末端的GOA单元越高参考高电平VGH，使得电平切换单元304输出较高的时钟信号给末端的GOA单元，如图4所示，第(4n+1)级的GOA单元所接收的子时钟信号CK1-n的电平高于第一级的GOA单元所接收的子时钟信号CK1-1，而在第一级与第(4n+1)之前的子时钟信号CK1-m的电平则介于CK1-1与CK1-n的电平之间。相对地，控制单元306也可以控制电源管理单元306提供给越末端的GOA单元越低的参考低电平VGL。
请参考图5，图5所示为电源管理单元306所输出的时钟信号CK的时序图，其中区间A为一帧的时间，区间B则为下一帧的时间。在同一帧内，时钟信号的CK的高电平随着时间增加而变大，时钟信号CK的低电平随着时间的增加而变低。在本发明较佳的实施例中，电源管理单元306是具有可控调整输出功能的电源管理芯片，控制单元302可进一步地控制电源管理单元实现可控输出，使电源管理单元306根据所要驱动的像素位值产生调控的时钟信号，时钟信号的高电平与低电平分别为VGH与VGL，其中参考高电平VGH具有最大值VGHmax与最小值VGHmin，参考低电平具有最大值VGLmax与最小值VGLmin。电平切换单元304再根据所接收的时钟信号CK产生调控过的子时钟信号CK1-CK4至GOA电路36中的GOA单元360。
请参考图6，图6所示为本发明的时钟信号及扫描信号延迟示意图。本发明的数个GOA单元360单元根据所接收的时钟信号来产生扫描信号，第一级GOA单元接收时钟信号CK1-1并产生第一级扫描信号G(1)，第(4n+1)级GOA单元接收时钟信号CK1-n并产生第(4n+1)级的扫描信号G(4n+1)。如图6所示，在末端第(4n+1)级GOA单元所接收时钟信号CK1-n产生的延迟CK_Delay大幅缩短，同时第(4n+1)级的扫描信号G(4n+1)产生的延迟G_Delay也大幅缩短，因此可以有效解决在大尺寸的显示面板中，由于传输的线路寄生阻抗过高而造成的信号延迟，同时可以有效改善因信号延迟而造成充电时间不足或错充的问题，改善面板的显示品质。
通过本发明实施例所提供的技术方案避免大尺寸显示面板的GOA驱动电路中，由于数据线及扫描线的等效阻抗造成的时钟信号及栅极驱信号延迟的问题，从而改善末端的像素单元充电时间不足或错充的问题，提升显示品质。
以上所述仅是本发明的优选实施方式，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种阵列基板驱动电路，设置于显示面板中，所述显示面板具有纵横交错的数条数据线及数条栅极线，其包括：
    控制单元，用来产生起始信号、时钟信号及控制信号；
    可调控电源管理芯片，用来根据所述控制信号产生参考高电平与参考低电平；
    电平切换单元，用来根据所述控制信号、所述参考高电平、所述参考低电平及所述时钟信号，提供子时钟信号，并根据所述可调控电源管理芯片产生的调控参考高电平与调控参考低电平，提供较末端的所述阵列基板行驱动单元电平较高的子时钟信号；以及
    数个阵列基板行驱动单元，设置于所述显示面板的侧边，每一个所述阵列基板行驱动单元连接至一条所述栅极线，所述阵列基板行驱动单元根据所接收的子时钟信号产生扫描信号至所述栅极线，其中较末端的所述阵列基板行驱动单元所接收的子时钟信号电平较高；
    其中，所述控制单元根据所驱动的像素位置控制所述电源管理单元所产生的电平大小，末端的阵列基板行驱动单元所产生的扫描信号电平较高。
  2. 一种阵列基板驱动电路，设置于显示面板中，所述显示面板具有纵横交错的数条数据线及数条栅极线，其包括：
    控制单元，用来产生起始信号、时钟信号及控制信号；
    电源管理单元，用来根据所述控制信号产生参考高电平与参考低电平；以及
    电平切换单元，用来根据所述控制信号、所述参考高电平、所述参考低电平及所述时钟信号，提供子时钟信号；
    其中，所述控制单元根据所驱动的像素位置控制所述电源管理单元所产生的电平大小。
  3. 如权利要求2所述的阵列基板驱动电路，其中所述阵列基板驱动电路具有数个阵列基板行驱动单元，设置于所显示面板的侧边，每一个所述阵列基板行驱动单元连接至一条所述栅极线，所述阵列基板行驱动单元根据所接收的子时钟信号产生扫描信号至所述栅极线，其中较末端的所述阵列基板行驱动单元所接收的子时钟信号电平较高。
  4. 如权利要求3所述的阵列基板驱动电路，其中所述电源管理单元为可调控电源管理芯片，根据所述控制信号产生可调控的参考高电平与参考低电平，所述电平切换单元根据所述可调控电源管理芯片产生的调控参考高电平与调控参考低电平，提供较末端的所述阵列基板行驱动单元电平较高的子时钟信号。
  5. 如权利要求3所述的阵列基板驱动电路，其中末端的阵列基板行驱动单元所产生的扫描信号电平较高。
    6如权利要求5所述的阵列基板驱动电路，其中所述控制单元与所述电源管理单元之间通过芯片间总线、串行外设接口或局部总线连接。
  6. 一种阵列基板驱动方法，用于显示面板，所述显示面板具有纵横交错的数条数据线及数条栅极线，其包括：
    控制单元产生起始信号、时钟信号及控制信号；
    电源管理单元根据所述控制信号产生参考高电平与参考低电平；以及
    电平切换单元根据所述控制信号、所述参考高电平、所述参考低电平及所述时钟信号，提供子时钟信号；
    其中，所述控制单元根据所驱动的像素位置控制所述电源管理单元所产生的电平大小。
  7. 如权利要求7所述的阵列基板驱动方法，其中所述阵列基板驱动方法包含具有数个阵列基板行驱动单元的阵列基板驱动电路，设置于所述显示面板的侧边，每一个所述阵列基板行驱动单元连接至一条所述栅极线，所述阵列基板行驱动单元根据所接收的子时钟信号产生扫描信号至所述栅极线，其中较末端的所述阵列基板行驱动单元所接收的子时钟信号电平较高。
  8. 如权利要求8所述的阵列基板驱动方法，其中所述电源管理单元为可调控电源管理芯片，根据所述控制信号产生可调控的参考高电平与参考低电平，所述电平切换单元根据所述电源管理芯片产生的调控参考高电平与调控参考低电平，提供较末端的所述阵列基板行驱动单元电平较高的子时钟信号。
  9. 如权利要求8所述的阵列基板驱动方法，其中较末端的阵列基板行驱动单元所产生的扫描信号电平较高。
  10. 如权利要求7所述的阵列基板驱动方法，其中所述控制单元与所述电源管理单元之间通过芯片间总线、串行外设接口或局部总线连接。
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