WO2020206898A1 - Goa驱动单元、goa电路及显示装置 - Google Patents

Goa驱动单元、goa电路及显示装置 Download PDF

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Publication number
WO2020206898A1
WO2020206898A1 PCT/CN2019/101739 CN2019101739W WO2020206898A1 WO 2020206898 A1 WO2020206898 A1 WO 2020206898A1 CN 2019101739 W CN2019101739 W CN 2019101739W WO 2020206898 A1 WO2020206898 A1 WO 2020206898A1
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Prior art keywords
transistor
resistor
signal
output
goa
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PCT/CN2019/101739
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English (en)
French (fr)
Inventor
程江坤
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/494,423 priority Critical patent/US11289007B2/en
Publication of WO2020206898A1 publication Critical patent/WO2020206898A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0204—Compensation of DC component across the pixels in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

Definitions

  • This application relates to the field of display technology, in particular to a GOA driving unit, a GOA circuit and a display device.
  • the output signal of the upper-level GOA unit is not only transmitted to the display area as the gate drive signal of the corresponding pixel unit, but also used as the input signal of the next-level GOA unit to participate in the work of the next-level GOA unit.
  • granulation causes the GOA output scan signal to be short-circuited with other signals, such as ELVDD, ELVSS, Vi, etc.
  • the input signal of the first level is pulled down or pulled up, and at this time, the GOA units of the next level and below will not work normally, and the poor performance is the panel split screen display, which seriously affects the panel function.
  • the present application provides a GOA driving unit, a GOA circuit, and a display device, which can avoid the occurrence of undesirable phenomena due to the short circuit between the output terminal of the GOA and other signals.
  • This application provides a GOA drive unit, including:
  • the GOA module is used to output a low level signal at its first output terminal under the control of a first clock signal, and used to output a high level signal at its first output terminal under the control of a second clock signal, the first The output terminal is used to output a high-level signal or a low-level signal to the next-stage GOA driving unit;
  • a protection module whose control terminal is connected to a constant DC signal, its input terminal is connected to the first output terminal, and its second output terminal is used to output a high-level signal or a low-level signal under the control of the constant DC signal Give the pixel unit.
  • the GOA module includes a high-level output sub-module and a low-level output sub-module;
  • the high-level output sub-module is configured to output a high-level signal at the first output terminal under the control of the second clock signal;
  • the low-level output sub-module is configured to output a high-level signal at the first output terminal under the control of the first clock signal.
  • the high-level output sub-module includes: a first transistor, a second transistor, a third transistor, and a first storage capacitor;
  • the drain of the first transistor is connected to a first low-level signal VGL, the gate of the first transistor is connected to the second clock signal, and the source of the first transistor is connected to the first storage capacitor
  • One end of the third transistor, the gate of the third transistor, and the source of the second transistor are connected, and the other end of the first storage capacitor is connected to the drain of the third transistor and connected to a first high-level signal
  • the drain of the second transistor is connected to the second clock signal, the gate of the second transistor is connected to the low-level output sub-module, and the source of the third transistor is connected to the first The output terminal is connected.
  • the low-level output submodule includes: a fourth transistor, a fifth transistor, a sixth transistor, and a second storage capacitor;
  • the drain of the fourth transistor is used to connect to the first output terminal of the GOA driving unit of the previous stage to access the turn-on signal, the source of the fourth transistor, the gate of the second transistor, the The gate of the fifth transistor is connected to one end of the second storage capacitor, the gate of the fourth transistor is connected to the second clock signal, and the drain of the fifth transistor is connected to the first low voltage.
  • the source of the fifth transistor is connected to the drain of the sixth transistor, the gate of the sixth transistor is connected to the first clock signal, and the source of the sixth transistor is connected to the The other end of the second storage capacitor is connected to the first output end.
  • the protection module includes: a seventh transistor, a first resistor, and a second resistor; the drain of the seventh transistor is connected to the first output terminal, and the seventh transistor The source of the transistor is connected to the second output terminal, the gate of the seventh transistor is connected to one end of the second resistor, and the other end of the second resistor is connected to the constant DC signal; One end of a resistor is connected to the common node of the seventh transistor and the second resistor, and the other end of the first resistor is connected to the source of the seventh transistor.
  • the protection module includes: a seventh transistor, a first resistor, and a second resistor; the drain of the seventh transistor is connected to the first output terminal, and the seventh transistor The source of the transistor is connected to the second output terminal, the gate of the seventh transistor is connected to one end of the second resistor, and the other end of the second resistor is connected to the constant DC signal; One end of a resistor is connected to the common node of the seventh transistor and the second resistor, and the other end of the first resistor is connected to the drain of the seventh transistor.
  • the protection module includes: a seventh transistor, a first resistor, a second resistor, and a third resistor; the drain of the seventh transistor is connected to the first output terminal, The source of the seventh transistor is connected to the second output terminal, the gate of the seventh transistor is connected to one end of the second resistor, and the other end of the second resistor is connected to the constant DC signal One end of the first resistor is connected to the common node of the seventh transistor and the second resistor, the other end of the first resistor is connected to the drain of the seventh transistor, and the third resistor is One end is connected to the common node of the seventh transistor and the second resistor, and the other end of the third resistor is connected to the source of the seventh transistor.
  • the seventh transistor is an N-type field effect thin film transistor.
  • the GOA circuit includes at least two cascaded GOA drive units, each of the GOA units is any one of the above-mentioned GOA drive units, wherein the input signal of the first-stage GOA drive unit is frame-based The start signal, the input signal of the n-th GOA driving unit is the voltage signal output by the first output terminal of the n-1th GOA driving unit.
  • a display device includes the GOA circuit described above.
  • this application provides a protection module, the control terminal of the protection module is connected to a constant DC signal, the input terminal of the protection module is connected to the first output terminal, and the second output terminal is used for Under the control of a constant DC signal, a high-level signal or a low-level signal is output to the pixel unit as the gate drive signal of the corresponding pixel unit, so as to avoid the short-circuit of the output terminal of the GOA and other signals.
  • FIG. 1 is a first structure diagram of GOA driving units in some embodiments provided by this application;
  • FIG. 2 is a second structure diagram of GOA driving units in some embodiments provided by this application.
  • FIG. 3 is a third structural diagram of the GOA driving unit in some embodiments provided by this application.
  • FIG. 4 is a structural diagram of the GOA circuit provided by this application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present invention, “plurality” means two or more than two, unless specifically defined otherwise.
  • the "above” or “below” of the first feature of the second feature may include the first and second features in direct contact, or may include the first and second features Not in direct contact but through other features between them.
  • “above”, “above” and “above” the second feature of the first feature include the first feature being directly above and obliquely above the second feature, or merely indicating that the first feature is higher in level than the second feature.
  • the “below”, “below” and “below” the first feature of the second feature include the first feature directly below and obliquely below the second feature, or it simply means that the level of the first feature is smaller than the second feature.
  • FIG. 1 is a structural diagram of a GOA driving unit in some embodiments of the present application.
  • the GOA driving unit includes: a GOA module 101 and a protection module 102.
  • the GOA module 101 is used to output a low level signal at its first output terminal OUTPUTa under the control of a first clock signal CK, and used to output a high level signal at its first output terminal OUTPUTa under the control of a second clock signal XCK
  • the first output terminal OUTPUTa is used to output a high-level signal or a low-level signal to the next-stage GOA driving unit.
  • the control terminal of the protection module 102 is connected to a constant DC signal VRE, the input terminal of the protection module 102 is connected to the first output terminal OUTPUTa, and the second output terminal OUTPUT is used to output under the control of the constant DC signal VRE
  • the high-level signal or the low-level signal is given to the pixel unit as the gate drive signal of the corresponding pixel unit.
  • the GOA module 101 includes a high-level output sub-module 1012 and a low-level output sub-module 1011; the high-level output sub-module is used to control the first output under the control of the second clock signal XCK
  • the terminal OUTPUTa outputs a high-level signal; the low-level output sub-module is used to output a high-level signal at the first output terminal OUTPUTa under the control of the first clock signal CK.
  • the high-level output submodule 1012 includes: a first transistor T1, a second transistor T2, a third transistor T3, and a first storage capacitor C1; wherein, the drain of the first transistor T1 is connected to the first transistor T1.
  • a low-level signal VGL, the gate of the first transistor T1 is connected to the second clock signal XCK, the source of the first transistor T1 and one end of the first storage capacitor C1, the third The gate of the transistor T3 is connected to the source of the second transistor T2, and the other end of the first storage capacitor C1 is connected to the drain of the third transistor T3 and connected to the first high level signal VGH;
  • the drain of the second transistor T2 is connected to the second clock signal XCK, the gate of the second transistor T2 is connected to the low-level output sub-module, and the source of the third transistor T3 is connected to the The first output terminal OUTPUTa is connected.
  • the low-level output submodule 1011 includes: a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a second storage capacitor C2; wherein, the drain of the fourth transistor T4 is used for The first output terminal OUTPUTa of the first-stage GOA driving unit is connected to connect to the turn-on signal STV, the source of the fourth transistor T4, the gate of the second transistor T2, the gate of the fifth transistor T5, and One end of the second storage capacitor C2 is connected, the gate of the fourth transistor T4 is connected to the second clock signal XCK, and the drain of the fifth transistor T5 is connected to the first low level signal VGL , The source of the fifth transistor T5 is connected to the drain of the sixth transistor T6, the gate of the sixth transistor T6 is connected to the first clock signal CK, and the source of the sixth transistor T6 It is connected to the other end of the second storage capacitor C2 and the first output terminal OUTPUTa.
  • the protection module 102 includes: a seventh transistor T7, a first resistor R1, and a second resistor R2; the drain of the seventh transistor T7 is connected to the first output terminal OUTPUTa, and the seventh transistor
  • the source of T7 is connected to the second output terminal OUTPUT, the gate of the seventh transistor T7 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the constant DC signal VRE; one end of the first resistor R1 is connected to the common node of the seventh transistor T7 and the second resistor R2, and the other end of the first resistor R1 is connected to the source of the seventh transistor T7.
  • the first resistor R1 and the second resistor R2 are voltage divider resistors.
  • the first resistor R1 and the second resistor R2 can be made of metal, a-Si, Poly-Si and other materials;
  • the Vout circuit is fed back to the gate of the seventh transistor T7 to adjust the on and off state of the seventh transistor T7;
  • the VGS voltage of the seventh transistor T7 is (VOUTPUTa-Vre)*R1/(R1+R2), Vre, After the values of R1 and R2 are set, when OUTPUTa changes, the VGS voltage changes accordingly and controls the working state of the seventh transistor T7.
  • the protection module 102 may also include: a seventh transistor T7, a first resistor R1, and a Two resistors R2; the drain of the seventh transistor T7 is connected to the first output terminal OUTPUTa, the source of the seventh transistor T7 is connected to the second output terminal OUTPUT, and the gate of the seventh transistor T7
  • the electrode is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the constant DC signal VRE; one end of the first resistor R1 is connected to the seventh transistor T7 and the second The common node of the resistor R2 is connected, and the other end of the first resistor R1 is connected to the drain of the seventh transistor T7.
  • the protection module can be adjusted as follows. As shown in FIG. 3, the protection module 102 may also include: a seventh transistor T7, a first resistor R1, and a first resistor R1.
  • the drain of the seventh transistor T7 is connected to the first output terminal OUTPUTa, the source of the seventh transistor T7 is connected to the second output terminal OUTPUT, and the The gate of the seventh transistor T7 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the constant DC signal VRE; one end of the first resistor R1 is connected to the seventh transistor T7 Is connected to the common node of the second resistor R2, the other end of the first resistor R1 is connected to the drain of the seventh transistor T7, and one end of the third resistor R3 is connected to the seventh transistor T7 and the The common node of the second resistor R2 is connected, and the other end of the third resistor R3 is connected to the source of the seventh transistor T7.
  • the seventh transistor T7 is an N-type field effect thin film transistor.
  • the present application also provides a GOA circuit.
  • the GOA circuit includes at least two cascaded GOA driving units 100, and each of the GOA units 100 is any one of the aforementioned GOA driving units 100.
  • the input signal of the first-stage GOA driving unit 100 is a frame start signal
  • the input signal of the nth-stage GOA driving unit 100 is a voltage signal output by the first output terminal OUTPUTa of the n-1th-stage GOA driving unit 100.
  • the present invention also provides a display device including the GOA circuit described above.
  • a protection module is provided, the control terminal of the protection module is connected to a constant DC signal, the input terminal of the protection module is connected to the first output terminal, and the second output terminal is used for under the control of the constant DC signal Outputting a high-level signal or a low-level signal to the pixel unit is used as the gate drive signal of the corresponding pixel unit, thereby avoiding the occurrence of undesirable phenomena due to the short circuit between the output terminal of the GOA and other signals.
  • the subject of this application can be manufactured and used in industry and has industrial applicability.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

本申请提供了一种GOA驱动单元(100)、GOA电路及显示装置。该GOA驱动单元(100)，包括：GOA模块（101），用于在第一时钟信号（CK）控制下在其第一输出端（OUTPUTa）输出低电平信号(VGL)，以及用于在第二时钟信号(XCK)控制下在其第一输出端（OUTPUTa）输出高电平信号(VGH)，第一输出端（OUTPUTa）用于输出高电平信号(VGH)或低电平信号(VGL)给下一级GOA驱动单元；保护模块(102)，其控制端接入恒定直流信号(VRE)，其输入端与第一输出端（OUTPUTa）连接，其第二输出端（OUTPUT）用于在恒定直流信号(VRE)的控制下输出高电平信号(VGH)或低电平信号(VGL)给像素单元作为对应像素单元的栅极驱动信号。

Description

GOA驱动单元、GOA电路及显示装置 技术领域
本申请涉及显示技术领域，特别涉及一种GOA驱动单元、GOA电路及显示装置。
 背景技术
随着平面显示技术的提升，各种搭载平面显示模组的产品应用于生活中，如智能手机、智能网络电视等大量普及；消费者对显示轻薄化、窄边框等提出了更高的要求；GOA（栅极驱动）技术可以很好的满足窄边框需求。
 技术问题
在GOA电路里，上一级GOA单元的输出信号除了会传输至显示区作为对应像素单元的栅极驱动信号以外，还会作为下一级GOA单元的输入信号，参与下一级GOA单元工作。
通常情况下，由于面板制程过程中存在颗粒化等问题，容易导致显示区d有瑕疵，典型的比如颗粒化导致GOA输出扫描信号与其他信号短路，如ELVDD、ELVSS、Vi等信号，会导致下一级的输入信号被拉低或者拉高，此时会造成下一级及以下所有级GOA单元无法正常工作，表现出现的不良现象为面板分屏显示，严重影响面板功能。
因此，现有技术存在缺陷，急需改进。
 技术解决方案
本申请提供一种GOA驱动单元、GOA电路及显示装置，可以避免因为GOA的输出端与其他信号短路而出现不良现象。
本申请提供了一种GOA驱动单元，包括：
GOA模块，用于在第一时钟信号控制下在其第一输出端输出低电平信号，以及用于在第二时钟信号控制下在其第一输出端输出高电平信号，所述第一输出端用于输出高电平信号或低电平信号给下一级GOA驱动单元；
保护模块，其控制端接入恒定直流信号，其输入端与所述第一输出端连接，其第二输出端用于在所述恒定直流信号的控制下输出高电平信号或低电平信号给像素单元。
在本申请所述的GOA驱动单元中，所述GOA模块包括高电平输出子模块以及低电平输出子模块；
所述高电平输出子模块用于在所述第二时钟信号控制下在所述第一输出端输出高电平信号；
所述低电平输出子模块用于在所述第一时钟信号控制下在所述第一输出端输出高电平信号。
在本申请所述的GOA驱动单元中，所述高电平输出子模块包括：第一晶体管、第二晶体管、第三晶体管以及第一存储电容；
所述第一晶体管的漏极接入第一低电平信号VGL，所述第一晶体管的栅极接入所述第二时钟信号，所述第一晶体管的源极与所述第一存储电容的一端、所述第三晶体管的栅极以及所述第二晶体管的源极连接，所述第一存储电容的另一端与所述第三晶体管的漏极连接并接入第一高电平信号；所述第二晶体管的漏极接入所述第二时钟信号，所述第二晶体管的栅极与所述低电平输出子模块连接，所述第三晶体管的源极与所述第一输出端连接。
在本申请所述的GOA驱动单元中，所述低电平输出子模块包括：第四晶体管、第五晶体管、第六晶体管以及第二存储电容；
所述第四晶体管的漏极用于与上一级的GOA驱动单元的第一输出端连接以接入开启信号，所述第四晶体管的源极、所述第二晶体管的栅极、所述第五晶体管的栅极以及所述第二存储电容的一端连接，所述第四晶体管的栅极接入所述第二时钟信号，所述第五晶体管的漏极接入所述第一低电平信号，所述第五晶体管的源极与所述第六晶体管的漏极连接，所述第六晶体管的栅极接入所述第一时钟信号，所述第六晶体管的源极与所述第二存储电容的另一端以及所述第一输出端连接。
在本申请所述的GOA驱动单元中，所述保护模块包括：第七晶体管、第一电阻以及第二电阻；所述第七晶体管的漏极与所述第一输出端连接，所述第七晶体管的源极与所述第二输出端连接，所述第七晶体管的栅极与所述第二电阻的一端连接，所述第二电阻的另一端接入所述恒定直流信号；所述第一电阻的一端与所述第七晶体管和所述第二电阻的公共节点连接，所述第一电阻的另一端与所述第七晶体管的源极连接。
在本申请所述的GOA驱动单元中，所述保护模块包括：第七晶体管、第一电阻以及第二电阻；所述第七晶体管的漏极与所述第一输出端连接，所述第七晶体管的源极与所述第二输出端连接，所述第七晶体管的栅极与所述第二电阻的一端连接，所述第二电阻的另一端接入所述恒定直流信号；所述第一电阻的一端与所述第七晶体管和所述第二电阻的公共节点连接，所述第一电阻的另一端与所述第七晶体管的漏极连接。
在本申请所述的GOA驱动单元中，所述保护模块包括：第七晶体管、第一电阻、第二电阻以及第三电阻；所述第七晶体管的漏极与所述第一输出端连接，所述第七晶体管的源极与所述第二输出端连接，所述第七晶体管的栅极与所述第二电阻的一端连接，所述第二电阻的另一端接入所述恒定直流信号；所述第一电阻的一端与所述第七晶体管和所述第二电阻的公共节点连接，所述第一电阻的另一端与所述第七晶体管的漏极连接，所述第三电阻的一端与所述第七晶体管和所述第二电阻的公共节点连接，所述第三电阻的另一端与所述第七晶体管的源极连接。
在本申请所述的GOA驱动单元中，所述第七晶体管为N型场效应薄膜晶体管。
一种GOA电路，所述GOA电路包括至少两个级联的GOA驱动单元，各所述GOA 单元均为上述任一所述的GOA驱动单元，其中第一级GOA驱动单元的输入信号为帧起始信号，第n级GOA驱动单元的输入信号为第n-1级GOA驱动单元的第一输出端输出的电压信号。
一种显示装置，包括上述的GOA电路。
 有益效果
本申请的优点在于，本申请通过设置保护模块，该保护模块的控制端接入恒定直流信号，该保护模块的输入端与所述第一输出端连接，其第二输出端用于在所述恒定直流信号的控制下输出高电平信号或低电平信号给像素单元作为对应像素单元的栅极驱动信号，从而可以避免因为GOA的输出端与其他信号短路而出现不良现象。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请提供一些实施例中的GOA驱动单元的第一种结构图；
图2为本申请提供一些实施例中的GOA驱动单元的第二种结构图；
图3为本申请提供一些实施例中的GOA驱动单元的第三种结构图；
图4为本申请提供的GOA电路的结构图。
 本发明的实施方式
下面详细描述本发明的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
参阅图1，图1是本申请一些实施例中的一种GOA驱动单元的结构图。
在一些实施例中，该GOA驱动单元，包括：GOA模块101以及保护模块102。
该GOA模块101用于在第一时钟信号CK控制下在其第一输出端OUTPUTa输出低电平信号，以及用于在第二时钟信号XCK控制下在其第一输出端OUTPUTa输出高电平信号，所述第一输出端OUTPUTa用于输出高电平信号或低电平信号给下一级GOA驱动单元。
该保护模块102的控制端接入恒定直流信号VRE，该保护模块102的输入端与所述第一输出端OUTPUTa连接，其第二输出端OUTPUT用于在所述恒定直流信号VRE的控制下输出高电平信号或低电平信号给像素单元作为对应像素单元的栅极驱动信号。
具体地，该GOA模块101包括高电平输出子模块1012以及低电平输出子模块1011；所述高电平输出子模块用于在所述第二时钟信号XCK控制下在所述第一输出端OUTPUTa输出高电平信号；所述低电平输出子模块用于在所述第一时钟信号CK控制下在所述第一输出端OUTPUTa输出高电平信号。
在一些实施例中，该高电平输出子模块1012包括：第一晶体管T1、第二晶体管T2、第三晶体管T3以及第一存储电容C1；其中，该第一晶体管T1的漏极接入第一低电平信号VGL，所述第一晶体管T1的栅极接入所述第二时钟信号XCK，所述第一晶体管T1的源极与所述第一存储电容C1的一端、所述第三晶体管T3的栅极以及所述第二晶体管T2的源极连接，所述第一存储电容C1的另一端与所述第三晶体管T3的漏极连接并接入第一高电平信号VGH；所述第二晶体管T2的漏极接入所述第二时钟信号XCK，所述第二晶体管T2的栅极与所述低电平输出子模块连接，所述第三晶体管T3的源极与所述第一输出端OUTPUTa连接。
在一些实施例中，低电平输出子模块1011包括：第四晶体管T4、第五晶体管T5、第六晶体管T6以及第二存储电容C2；其中，该第四晶体管T4的漏极用于与上一级的GOA驱动单元的第一输出端OUTPUTa连接以接入开启信号STV，所述第四晶体管T4的源极、所述第二晶体管T2的栅极、所述第五晶体管T5的栅极以及所述第二存储电容C2的一端连接，所述第四晶体管T4的栅极接入所述第二时钟信号XCK，所述第五晶体管T5的漏极接入所述第一低电平信号VGL，所述第五晶体管T5的源极与所述第六晶体管T6的漏极连接，所述第六晶体管T6的栅极接入所述第一时钟信号CK，所述第六晶体管T6的源极与所述第二存储电容C2的另一端以及所述第一输出端OUTPUTa连接。
在一些实施例中，保护模块102包括：第七晶体管T7、第一电阻R1以及第二电阻R2；所述第七晶体管T7的漏极与所述第一输出端OUTPUTa连接，所述第七晶体管T7的源极与所述第二输出端OUTPUT连接，所述第七晶体管T7的栅极与所述第二电阻R2的一端连接，所述第二电阻R2的另一端接入所述恒定直流信号VRE；所述第一电阻R1的一端与所述第七晶体管T7和所述第二电阻R2的公共节点连接，所述第一电阻R1的另一端与所述第七晶体管T7的源极连接。其中，第一电阻R1、第二电阻R2为分压电阻，在实际制作过程中，第一电阻R1、第二电阻R2均可用金属、a-Si、Poly-Si等材质制作；电路通过侦测Vout电路并反馈至第七晶体管T7栅极处，来调节第七晶体管T7的导通与截止状态；第七晶体管T7的VGS电压为（VOUTPUTa-Vre）*R1/(R1+R2)，Vre、R1、R2值设定后，当OUTPUTa发生变化时，VGS电压随之变化，并控制第七晶体管T7的工作状态。
可以理解地，另外针对GOA电路输出波形差异性，如EM GOA等，保护模块可做如下调整，如图2所示，该保护模块102还可以包括：第七晶体管T7、第一电阻R1以及第二电阻R2；所述第七晶体管T7的漏极与所述第一输出端OUTPUTa连接，所述第七晶体管T7的源极与所述第二输出端OUTPUT连接，所述第七晶体管T7的栅极与所述第二电阻R2的一端连接，所述第二电阻R2的另一端接入所述恒定直流信号VRE；所述第一电阻R1的一端与所述第七晶体管T7和所述第二电阻R2的公共节点连接，所述第一电阻R1的另一端与所述第七晶体管T7的漏极连接。
可以理解地，另外针对GOA电路输出波形差异性，如EM GOA等，保护模块可做如下调整，如图3所示，该保护模块102还可以包括：第七晶体管T7、第一电阻R1、第二电阻R2以及第三电阻R3；所述第七晶体管T7的漏极与所述第一输出端OUTPUTa连接，所述第七晶体管T7的源极与所述第二输出端OUTPUT连接，所述第七晶体管T7的栅极与所述第二电阻R2的一端连接，所述第二电阻R2的另一端接入所述恒定直流信号VRE；所述第一电阻R1的一端与所述第七晶体管T7和所述第二电阻R2的公共节点连接，所述第一电阻R1的另一端与所述第七晶体管T7的漏极连接，所述第三电阻R3的一端与所述第七晶体管T7和所述第二电阻R2的公共节点连接，所述第三电阻R3的另一端与所述第七晶体管T7的源极连接。
其中，该第七晶体管T7为N型场效应薄膜晶体管。
请参照图4，本申请还提供了一种GOA电路，所述GOA电路包括至少两个级联的GOA驱动单元100，各所述GOA 单元100均为上述任一所述的GOA驱动单元100，其中第一级GOA驱动单元100的输入信号为帧起始信号，第n级GOA驱动单元100的输入信号为第n-1级GOA驱动单元100的第一输出端OUTPUTa输出的电压信号。
本发明还提供了一种显示装置，包括上述的GOA电路。
本申请通过设置保护模块，该保护模块的控制端接入恒定直流信号，该保护模块的输入端与所述第一输出端连接，其第二输出端用于在所述恒定直流信号的控制下输出高电平信号或低电平信号给像素单元作为对应像素单元的栅极驱动信号，从而可以避免因为GOA的输出端与其他信号短路而出现不良现象。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。
 工业实用性
本申请的主题可以在工业中制造和使用，具备工业实用性。

Claims (10)

  1. 一种GOA驱动单元，其特征在于，包括：
    GOA模块，用于在第一时钟信号控制下在其第一输出端输出低电平信号，以及用于在第二时钟信号控制下在其第一输出端输出高电平信号，所述第一输出端用于输出高电平信号或低电平信号给下一级GOA驱动单元；所述GOA模块包括高电平输出子模块以及低电平输出子模块；所述高电平输出子模块用于在所述第二时钟信号控制下在所述第一输出端输出高电平信号；所述低电平输出子模块用于在所述第一时钟信号控制下在所述第一输出端输出高电平信号;
    保护模块，其控制端接入恒定直流信号，其输入端与所述第一输出端连接，其第二输出端用于在所述恒定直流信号的控制下输出高电平信号或低电平信号给像素单元作为对应像素单元的栅极驱动信号；所述保护模块包括：第七晶体管、第一电阻以及第二电阻；所述第七晶体管的漏极与所述第一输出端连接，所述第七晶体管的源极与所述第二输出端连接，所述第七晶体管的栅极与所述第二电阻的一端连接，所述第二电阻的另一端接入所述恒定直流信号；所述第一电阻的一端与所述第七晶体管和所述第二电阻的公共节点连接，所述第一电阻的另一端与所述第七晶体管的源极连接。
  2. 一种GOA驱动单元，其特征在于，包括：
    GOA模块，用于在第一时钟信号控制下在其第一输出端输出低电平信号，以及用于在第二时钟信号控制下在其第一输出端输出高电平信号，所述第一输出端用于输出高电平信号或低电平信号给下一级GOA驱动单元；
    保护模块，其控制端接入恒定直流信号，其输入端与所述第一输出端连接，其第二输出端用于在所述恒定直流信号的控制下输出高电平信号或低电平信号给像素单元作为对应像素单元的栅极驱动信号。
  3. 根据权利要求2所述的GOA驱动单元，其特征在于，所述GOA模块包括高电平输出子模块以及低电平输出子模块；
    所述高电平输出子模块用于在所述第二时钟信号控制下在所述第一输出端输出高电平信号；
    所述低电平输出子模块用于在所述第一时钟信号控制下在所述第一输出端输出高电平信号。
  4. 根据权利要求3所述的GOA驱动单元，其特征在于，所述高电平输出子模块包括：第一晶体管、第二晶体管、第三晶体管以及第一存储电容；
    所述第一晶体管的漏极接入第一低电平信号VGL，所述第一晶体管的栅极接入所述第二时钟信号，所述第一晶体管的源极与所述第一存储电容的一端、所述第三晶体管的栅极以及所述第二晶体管的源极连接，所述第一存储电容的另一端与所述第三晶体管的漏极连接并接入第一高电平信号；所述第二晶体管的漏极接入所述第二时钟信号，所述第二晶体管的栅极与所述低电平输出子模块连接，所述第三晶体管的源极与所述第一输出端连接。
  5. 根据权利要求4所述的GOA驱动单元，其特征在于，所述低电平输出子模块包括：第四晶体管、第五晶体管、第六晶体管以及第二存储电容；
    所述第四晶体管的漏极用于与上一级的GOA驱动单元的第一输出端连接以接入开启信号，所述第四晶体管的源极、所述第二晶体管的栅极、所述第五晶体管的栅极以及所述第二存储电容的一端连接，所述第四晶体管的栅极接入所述第二时钟信号，所述第五晶体管的漏极接入所述第一低电平信号，所述第五晶体管的源极与所述第六晶体管的漏极连接，所述第六晶体管的栅极接入所述第一时钟信号，所述第六晶体管的源极与所述第二存储电容的另一端以及所述第一输出端连接。
  6. 根据权利要求2所述的GOA驱动单元，其特征在于，所述保护模块包括：第七晶体管、第一电阻以及第二电阻；所述第七晶体管的漏极与所述第一输出端连接，所述第七晶体管的源极与所述第二输出端连接，所述第七晶体管的栅极与所述第二电阻的一端连接，所述第二电阻的另一端接入所述恒定直流信号；所述第一电阻的一端与所述第七晶体管和所述第二电阻的公共节点连接，所述第一电阻的另一端与所述第七晶体管的源极连接。
  7. 根据权利要求2所述的GOA驱动单元，其特征在于，所述保护模块包括：第七晶体管、第一电阻以及第二电阻；所述第七晶体管的漏极与所述第一输出端连接，所述第七晶体管的源极与所述第二输出端连接，所述第七晶体管的栅极与所述第二电阻的一端连接，所述第二电阻的另一端接入所述恒定直流信号；所述第一电阻的一端与所述第七晶体管和所述第二电阻的公共节点连接，所述第一电阻的另一端与所述第七晶体管的漏极连接。
  8. 根据权利要求2所述的GOA驱动单元，其特征在于，所述保护模块包括：第七晶体管、第一电阻、第二电阻以及第三电阻；所述第七晶体管的漏极与所述第一输出端连接，所述第七晶体管的源极与所述第二输出端连接，所述第七晶体管的栅极与所述第二电阻的一端连接，所述第二电阻的另一端接入所述恒定直流信号；所述第一电阻的一端与所述第七晶体管和所述第二电阻的公共节点连接，所述第一电阻的另一端与所述第七晶体管的漏极连接，所述第三电阻的一端与所述第七晶体管和所述第二电阻的公共节点连接，所述第三电阻的另一端与所述第七晶体管的源极连接。
  9. 根据权利要求8所述的GOA驱动单元，其特征在于，所述第七晶体管为N型场效应薄膜晶体管。
  10. 一种GOA电路，其特征在于，所述GOA电路包括至少两个级联的GOA驱动单元，各所述GOA 单元均为权利要求1-8任一所述的GOA驱动单元，其中第一级GOA驱动单元的输入信号为帧起始信号，第n级GOA驱动单元的输入信号为第n-1级GOA驱动单元的第一输出端输出的电压信号。
PCT/CN2019/101739 2019-04-08 2019-08-21 Goa驱动单元、goa电路及显示装置 Ceased WO2020206898A1 (zh)

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