WO2020206858A1 - 一种选通管器件的预处理方法 - Google Patents

一种选通管器件的预处理方法 Download PDF

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Publication number
WO2020206858A1
WO2020206858A1 PCT/CN2019/095696 CN2019095696W WO2020206858A1 WO 2020206858 A1 WO2020206858 A1 WO 2020206858A1 CN 2019095696 W CN2019095696 W CN 2019095696W WO 2020206858 A1 WO2020206858 A1 WO 2020206858A1
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voltage
tube
strobe
gate tube
gate
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PCT/CN2019/095696
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English (en)
French (fr)
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童浩
何达
缪向水
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华中科技大学
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Priority to US17/042,954 priority Critical patent/US11641748B2/en
Publication of WO2020206858A1 publication Critical patent/WO2020206858A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H10B63/24—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the Ovonic threshold switching type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/041—Modification of switching materials after formation, e.g. doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe

Definitions

  • the invention belongs to the field of micro-nano, and more specifically, relates to a pretreatment method of a gate tube device.
  • next generation of new non-volatile memory devices such as phase change memory, resistive random access memory and other devices have become the most popular next-generation memory devices due to their extremely fast erasing and writing speed, excellent miniaturization performance, and three-dimensional stackability.
  • a huge leakage current will inevitably be generated during the operation process, leading to misoperation of unselected cells.
  • a two-terminal strobe device is used to vertically integrate the memory cell, and the high resistance state of the strobe tube can effectively suppress the leakage current while reducing the operating power consumption.
  • the strobe tube In order to increase the scale of the integrated array, the strobe tube must be able to withstand the huge current when the memory cell is erased and written, and at the same time effectively suppress the leakage current of the non-strobe cell. In other words, the strobe tube needs to have a large switching ratio.
  • the switching ratio of the strobe tube directly determines the number of memory cells that can be integrated, and can also affect the power consumption and crosstalk resistance of the memory.
  • the bidirectional threshold switch (Ovonic Threshold Switch, OTS), which is usually composed of a chalcogen compound, can effectively meet the above requirements for the gate layer.
  • OTS Organic Threshold Switch
  • the currently reported OTS strobe tubes have disadvantages such as small switching ratio, poor stability, and insufficient drive current.
  • the most direct way is to reduce the leakage current by reducing the number of defects in the chalcogenide material.
  • the purpose of the present invention is to provide a pretreatment method for a strobe tube device, which aims to solve the problem that the high switching ratio and high on-state current in the prior strobe tube technology cannot be achieved simultaneously, which limits The technical problem of the application of the strobe tube in the storage device.
  • the present invention provides a pretreatment method for a strobe tube device, including:
  • I cc(n-1) ⁇ I cc(n) , and the initial value of n is 2;
  • the read voltage is 0.5 times the on voltage of the strobe device after the first voltage scan
  • the first limited current I cc1 is: 500 nA ⁇ I cc1 ⁇ 1000 uA; the nth limited current I cc(n) is: I cc(n-1) ⁇ I cc(n) ⁇ 1100 uA.
  • the voltage scan range is 0-4V th ; the voltage scan mode is: the voltage starts from 0 and increases to the maximum voltage, and then sweeps back from the maximum voltage to 0; where V th is the on-voltage of the strobe tube.
  • the gate tube includes a first electrode layer, a sulfur-based gate material layer, and a second electrode layer; the sulfur-based gate material layer is interposed between the first electrode layer and the second electrode layer.
  • the material of the sulfur-based gate material layer is at least SiTe x , CTe x , BTe x , GeTe x , AlTe x , GeSb x Te y , GeSb x , BiTe x , AsTe x , SnTe x , and BiTe x
  • the first electrode layer and the second electrode layer are both inert electrode materials, and the inert electrode materials are W, TiW, Pt, Au, Ru, Al, TiN, Ta, TaN, IrO 2 , ITO and At least one of IZO.
  • the present invention performs voltage scanning pretreatment on the gate tube, which can effectively reduce the number of defects in the gate tube material, thereby effectively reducing the leakage current of the gate tube and improving ⁇ Switch ratio.
  • the present invention adopts at least two The continuous increase of the secondary limiting current ensures the realization of a high switching ratio while avoiding the phenomenon of device damage caused by excessively high primary limiting current.
  • the pretreatment method adopted by the present invention can increase the on-state of the gate tube Current.
  • the pretreatment method for the gating tube provided by the present invention is an electrical treatment method, which is very simple and stable. It is different from techniques such as doping, which will increase the process requirements, and can not only effectively reduce the gating tube The number of defects in the material, and the changes in device performance can be observed in real time and accurately.
  • FIG. 1 is a schematic flowchart of a pretreatment method for a gating tube provided in Embodiment 1;
  • Figure 2 is a voltage-current curve diagram of the gate tube after S1 in embodiment 1;
  • FIG. 3 is a comparison diagram of voltage-current curves of the gate tube after passing through S1 and passing through S1 and S2 in embodiment 1;
  • Figure 4 is a comparison diagram of the voltage-current curves of the gate tube after S1, S1, S2 and the verification test in Example 1;
  • FIG. 5 is a voltage-current curve diagram of the gate tube obtained during the pretreatment process in Embodiment 2;
  • Fig. 6 is a voltage-current curve diagram of the gate tube without pretreatment in embodiment 2;
  • FIG. 7 is a voltage-current curve diagram of the gate tube obtained during the pretreatment process in Embodiment 3.
  • the present invention provides a pretreatment method of a gate tube device, including:
  • I cc(n-1) ⁇ I cc(n) , and the initial value of n is 2;
  • the read voltage is 0.5 times the on voltage of the strobe device after the first voltage scan
  • the first limited current I cc1 is: 500 nA ⁇ I cc1 ⁇ 1000 uA; the nth limited current I cc(n) is: I cc(n-1) ⁇ I cc(n) ⁇ 1100 uA.
  • the voltage scan range is 0-4V th ; the voltage scan mode is: the voltage starts from 0 and increases to the maximum voltage, and then sweeps back from the maximum voltage to 0; where V th is the on-voltage of the strobe tube.
  • the gate tube includes a first electrode layer, a sulfur-based gate material layer, and a second electrode layer; the sulfur-based gate material layer is interposed between the first electrode layer and the second electrode layer.
  • the material of the sulfur-based gate material layer is at least SiTe x , CTe x , BTe x , GeTe x , AlTe x , GeSb x Te y , GeSb x , BiTe x , AsTe x , SnTe x , and BiTe x
  • the first electrode layer and the second electrode layer are both inert electrode materials, and the inert electrode materials are W, TiW, Pt, Au, Ru, Al, TiN, Ta, TaN, IrO 2 , ITO and At least one of IZO.
  • the pretreatment method for the gating tube device provided by the present invention is applicable to all types of gating tubes whose switch layer is a layer of sulfur-based gating material, and is not limited to the above-mentioned gating tubes.
  • the sulfur-based gate material layer of the gate device is GeTe x
  • the first electrode layer and the second electrode layer are both TiW.
  • the voltage scan range is set to 0V ⁇ 1.5V, and the voltage scan range remains unchanged during the pretreatment process.
  • the preprocessing process is shown in Figure 1, and the details are as follows:
  • the dotted line in Figure 3 represents the curve obtained by S1
  • the solid line represents the curve obtained by step S2. It can be seen from Figure 3 that during the voltage flyback of S2, the leakage current after the gate tube is turned off is significantly reduced, and S2 is limited by increasing The current further reduces the number of defects in the gate tube material; at the same time, because the pretreatment of S1 eliminates some of the defects that are too concentrated, S2 can still avoid device damage while increasing the limited current.
  • This step satisfies the reading voltage Under the condition of, it shows that the voltage sweep makes the resistance state of the sub-threshold region of the strobe tube improved.
  • the solid line in Figure 4 is the IV curve obtained after S1 and S2 preprocessing, and the dotted and dashed line is the IV curve obtained after this verification test. It can be seen from Figure 4 that after steps S1 and S2, the switch ratio is relatively first. After this voltage sweep, it increased by 1000 times, reaching 10 4 .
  • the sulfur-based gate material layer of the gate tube is GeSb x Te y
  • the first electrode layer and the second electrode layer are both TiW.
  • the voltage scan range is set to 0V ⁇ 1.5V, and the voltage scan range remains unchanged during the pretreatment process.
  • the specific pretreatment process is as follows:
  • the third voltage scan was performed to obtain the IV characteristic curve as shown in Fig. 5. It can be seen from Fig. 5 that the strobe tube’s performance after preprocessing The switching ratio is increased from less than 10 to 10 4 orders of magnitude.
  • the dashed line in Fig. 6 is the IV curve corresponding to the first unit of the strobe device. Comparing the IV curve represented by the solid line and the dashed line in Fig. 6 shows that the second unit undergoes a phase change under an on-state current of 500uA. It can return to the high-impedance state, when the switching ratio of the device is close to 0; and the first unit maintains stable and good switching characteristics at an on-state current of 500uA.
  • the sulfur-based gate material layer of the gate device is GeTe x
  • the first electrode layer and the second electrode layer are both TiW.
  • Set the limit current to I cc1 100uA, repeat the voltage sweep of the gate tube 7 times to obtain the IV curve as shown in Figure 7. From Figure 7, it can be seen that if the limit current remains unchanged in the pretreatment, the switching ratio remains as Around 10, repeated voltage scanning did not improve the performance of the strobe device. Comparing Embodiment 1 with Embodiment 3, it can be seen that the pretreatment method of the strobe tube provided by the present invention can increase the on-state current by continuously increasing the limit current and realize the high switching ratio of the strobe tube.

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Abstract

一种选通管器件的预处理方法，包括：（1）通过选取电压扫描范围且设置第一限制电流Icc1，对选通管进行第一次电压扫描，获取选通管亚阈值区域的阻态R1；（2）根据第n-1次电压扫描后的选通管亚阈值区域的阻态Rn-1，设置第n限制电流Icc(n)，并对选通管进行第n次电压扫描，获取其亚阈值区域的阻态Rn；其中，Icc(n-1)＜Icc(n)，n的初始值为2；（3）在读电压下，若第n次电压扫描后的选通管器件的高阻态阻值大于第一次电压扫描后的选通管器件的高阻态阻值，则停止对选通管器件的电压扫描；否则，n＝n+1，转至步骤（2）。该预处理方法同时提高了选通管的开态电流和开关比，进而提高了选通管的性能使其在存储器件中的应用更广泛。

Description

一种选通管器件的预处理方法 【技术领域】
本发明属于微纳领域，更具体地，涉及一种选通管器件的预处理方法。
【背景技术】
下一代的新型非易失存储器如相变存储器、阻变存储器等器件由于其极快的擦写速度、极佳的微缩性能、可三维堆叠等特性成为当前最热门的下一代存储器。摩尔定律日渐失效的当今，三维堆叠存储单元能够降低有效单元面积，从而大幅度提高存储密度。然而，存储单元三维堆叠后，其操作过程会不可避免产生巨大的漏电流，导致误操作非选中单元。为了解决上述问题，使用一种二端的选通管器件与存储单元垂直集成，通过选通管的高阻态来有效抑制漏电流，同时还降低了操作功耗。
为了提高集成阵列的规模，选通管要能够承受存储单元擦写时的巨大电流，同时有效抑制未选通单元的漏电流。换而言之，选通管需要有很大的开关比。选通管的开关比直接决定了能够集成的存储单元数量，也能够影响存储器的功耗大小和抗串扰水平。
选通层通常由硫系化合物构成的双向阈值开关器件(Ovonic Threshold Switch，OTS)能够有效契合上述要求。但是，当前已经报道的OTS选通管有着诸如开关比小、稳定性差、可驱动开电流不足等缺点。一方面，为了提高开关比，最直接的方式是通过减少硫系材料中的缺陷数量来减少漏电流，当前技术中往往通过掺杂其他元素来减少缺陷数量，但是引入的新的元素时需要精确调控其组分比，增加了工艺的复杂程度，提高了对成膜技术均匀性、一致性等的要求，降低成品率；另一方面，由于硫系材料在电流过大时往往会由于电压和热量的作用发生相变，导致关态电阻降低，这也就限制了可驱动的最大电流。
因此，如何通过更加简单的操作方法提高选通管器件的开关比、稳定性和可驱动电流是当务之急。
发明内容
针对现有技术的缺陷，本发明的目的在于提供一种选通管器件的预处理方法，旨在解决现有选通管技术中存在的高开关比、高开态电流无法同时实现，限制了选通管在存储器件中的应用的技术问题。
为实现上述目的，本发明提供了一种选通管器件的预处理方法，包括：
(1)通过选取电压扫描范围且设置第一限制电流I cc1，对选通管进行第一次电压扫描，获取其亚阈值区域的阻态R 1；
(2)根据第n-1次电压扫描后的选通管亚阈值区域的阻态，设置第n限制电流I cc(n)，并对选通管进行第n次电压扫描，获取其亚阈值区域的阻态R n，
其中，I cc(n-1)＜I cc(n)，n的初始值为2；
(3)在读电压下，若第n次电压扫描后的选通管器件的高阻态阻值大于第一次电压扫描后的选通管器件的高阻态阻值，则停止对选通管器件的电压扫描；否则，n＝n+1，转至步骤(2)。
优选地，所述读电压为第一次电压扫描后的选通管器件的0.5倍开电压；
优选地，所述第一限制电流I cc1为：500nA＜I cc1＜1000uA；所述第n限制电流I cc(n)为：I cc(n-1)＜I cc(n)＜1100uA。
优选地，所述电压扫描范围为0～4V th；电压扫描方式为：电压从0开始递增到最大电压，再从最大电压回扫到0；其中，V th为选通管的开电压。
优选地，所述选通管包括第一电极层、硫系选通材料层和第二电极层；所述硫系选通材料层介于第一电极层和第二电极层之间。
优选地，所述硫系选通材料层的材料为SiTe x、CTe x、BTe x、GeTe x、AlTe x、GeSb xTe y、GeSb x、BiTe x、AsTe x、SnTe x、BiTe x中至少一种，或者 SiTe x、CTe x、BTe x、GeTe x、AlTe x、GeSb xTe y、GeSb x、BiTe x、AsTe x、SnTe x、BiTe x中至少一种化合物掺杂N、Sb、Bi、C中的至少一种元素形成的混合物，或者SiTe x、CTe x、BTe x、GeTe x、AlTe x、GeSb xTe y、GeSb x、BiTe x、AsTe x、SnTe x、BiTe x中至少一种化合物掺杂Si元素形成的混合物。
优选地，所述第一电极层和第二电极层均为惰性电极材料，且所述惰性电极材料为W、TiW、Pt、Au、Ru、Al、TiN、Ta、TaN、IrO 2、ITO和IZO的至少一种。
通过本发明所构思的以上技术方案，与现有技术相比，能够取得以下
有益效果：
(1)本发明至少通过两次限制电流的增加，对选通管进行电压扫描的预处理，可有效地减少选通管材料中的缺陷数量，从而有效减少了选通管的漏电流，提高了开关比。
(2)由于沉积态材料中的缺陷分布及元素分布非常不均匀，当通过较大的高开态电流极易导致材料部分区域产生过多热量，导致器件容易损坏，因此，本发明采用至少两次限制电流的不断增加，在保证实现高开关比的同时避免了经一次限制电流过高导致器件损坏的现象发生，简而言之，本发明采用的预处理方法可以增加选通管的开态电流。
(3)本发明提供的对选通管预处理方法为电学处理方法，该预处理方法非常简单且稳定，不同于诸如掺杂等技术会提高对工艺的要求，不但可以有效地减少选通管材料的缺陷数量，而且可以实时、准确地观察器件性能的变化。
【附图说明】
图1是实施例1提供的一种选通管预处理方法的流程示意图；
图2是实施例1中经S1后选通管的电压-电流曲线图；
图3是实施例1中经S1和经S1、S2后选通管的电压-电流曲线对比图；
图4是实施例1中经S1、经S1、S2和经验证试验后选通管的电压-电 流曲线对比图；
图5是实施例2中预处理过程中获取的选通管的电压-电流曲线图；
图6是实施例2中未预处理的选通管的电压-电流曲线图；
图7是实施例3中预处理过程中获取的选通管的电压-电流曲线图。
【具体实施方式】
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
本发明提供了一种选通管器件的预处理方法，包括：
(1)通过选取电压扫描范围且设置第一限制电流I cc1，对选通管进行第一次电压扫描，获取其亚阈值区域的阻态R 1；
(2)根据第n-1次电压扫描后选通管亚阈值区域的阻态R n-1，设置第n限制电流I cc(n)，并对选通管进行第n次电压扫描，获取其亚阈值区域的阻态R n，
其中，I cc(n-1)＜I cc(n)，n的初始值为2；
(3)在读电压下，对比第n次电压扫描后的选通管器件与第一次电压扫描后的选通管器件的高阻态阻值，若满足阈值条件，停止对选通管器件的电压扫描；否则，n＝n+1，转至步骤(2)。
优选地，所述读电压为第一次电压扫描后选通管器件的0.5倍开电压；
优选地，所述第一限制电流I cc1为：500nA＜I cc1＜1000uA；所述第n限制电流I cc(n)为：I cc(n-1)＜I cc(n)＜1100uA。
优选地，所述电压扫描范围为0～4V th；电压扫描方式为：电压从0开始递增到最大电压，再从最大电压回扫到0；其中，V th为选通管的开电压。
优选地，所述选通管包括第一电极层、硫系选通材料层和第二电极层；所述硫系选通材料层介于第一电极层和第二电极层之间。
优选地，所述硫系选通材料层的材料为SiTe x、CTe x、BTe x、GeTe x、AlTe x、GeSb xTe y、GeSb x、BiTe x、AsTe x、SnTe x、BiTe x中至少一种，或者SiTe x、CTe x、BTe x、GeTe x、AlTe x、GeSb xTe y、GeSb x、BiTe x、AsTe x、SnTe x、BiTe x中至少一种化合物掺杂N、Sb、Bi、C中的至少一种元素形成的混合物，或者SiTe x、CTe x、BTe x、GeTe x、AlTe x、GeSb xTe y、GeSb x、BiTe x、AsTe x、SnTe x、BiTe x中至少一种化合物掺杂Si元素形成的混合物。
优选地，所述第一电极层和第二电极层均为惰性电极材料，且所述惰性电极材料为W、TiW、Pt、Au、Ru、Al、TiN、Ta、TaN、IrO 2、ITO和IZO的至少一种。
本发明提供的选通管器件的预处理方法适用于开关层为硫系选通材料层的所有类型的选通管，并不局限于上述涉及到的选通管。
实施例1
本实施例中选通管器件的硫系选通材料层是GeTe x，第一电极层和第二电极层均为TiW。选通管器件的预处理方法中，电压扫描范围设置为0V～1.5V，在预处理过程中电压扫描范围保持不变。预处理过程如图1所示，具体如下：
S1:设置第一限制电流I cc1＝100uA，进行第一次电压扫描，获取如图2所示的I-V特性曲线及其亚阈值区域阻态R 1，从图2可知，选通管的开关比为10；
通过S1的操作，一方面获取了选通管的初始状态数据，另一方面在场致效应和电流热效应作用下，选通管材料内部部分过于集中的缺陷被消除，同时由于此时限制电流较小，不会造成材料晶化等问题。
S2:设置第一限制电流I cc2＝1.5I cc1＝150uA，进行第二次电压扫描，获取如图3所示的I-V特性曲线及其亚阈值区域阻态R 2；
图3中虚线表示S1得到的曲线，实线表示S2步骤获取的曲线，从图3 可以看出，在S2的电压回扫过程中，选通管关闭后的漏电流显著减少，S2通过提高限制电流进一步减少了选通管材料内的缺陷数量；同时由于S1的预处理消除了部分过于集中的缺陷，S2在增加限制电流的情况下仍能避免器件的损坏。
S3:设置读电压V read＝0.25V，得知在该读电压下存在：
Figure PCTCN2019095696-appb-000001
停止对选通管器件的电压扫描。
该步在读电压下满足
Figure PCTCN2019095696-appb-000002
的条件时，说明电压扫描使得选通管的亚阈值区域阻态得到了提高。
为了更加直观的说明经过预处理后选通管器件的性能有所提升，进行了第三次电压扫描进行验证试验，具体如下：
设置第三限制电流I cc3＝2I cc1＝200uA，进行第三次电压扫描，获取如图4所示的I-V特性曲线以及选通管的开关比。
图4中实线为经过S1、S2预处理后获取的I-V曲线，点虚线为再经过该次验证试验后获取的I-V曲线，从图4可知，经过步骤S1、S2后，开关比相对第一次电压扫描后提高了1000倍，达到了10 4。
实施例2
本实施例中选通管的硫系选通材料层是GeSb xTe y，所述第一电极层、第二电极层均为TiW。
选通管器件的第一单元的预处理方法中，电压扫描范围设置为0V～1.5V，在预处理过程中电压扫描范围保持不变。具体预处理过程如下：
S1：设置第一限制电流I cc1＝400uA，进行第一次电压扫描，获取选通管的I-V特性曲线和其亚阈值区域阻态R 1；
S2：设置第二限制电流I cc2＝500uA，进行第二次电压扫描，获取选通管的亚阈值区域阻态R 2；
S3：设置读电压V read＝0.3V，得知在该读电压下存在：
Figure PCTCN2019095696-appb-000003
停止对选通管器件的电压扫描。
为了更加直观的说明经过预处理后选通管器件的性能有所提升，进行了第三次电压扫描，获取了如图5的I-V特性曲线，从图5可知，通过预处理后选通管的开关比从小于10提高到了10 4量级。
选通管器件的第二单元与选通管器件的第一单元完全相同，直接设置限制电流为I cc＝I cc2＝500uA，获取如图6中实线所示的I-V曲线；
图6中的虚线为选通管器件的第一单元对应的I-V曲线，对比图6中的实线与虚线表示的I-V曲线可知，第二单元在500uA的开态电流下发生了相变，未能回到高阻态，此时器件开关比接近0；而第一单元在500uA的开态电流下保持稳定且较好的开关特性。
实施例3
本实施例中选通管器件的硫系选通材料层是GeTe x，第一电极层和第二电极层均为TiW。设置限制电流为I cc1＝100uA，对选通管重复电压扫描7次，获取如图7所示的I-V曲线，从图7可知，若限制电流在预处理中保持不变，则开关比保持为10左右，重复电压扫描并没有对选通管器件性能的提升。实施例1与实施例3对比可知，本发明提供的选通管的预处理方法通过不断提高限制电流，可提升开态电流的同时实现了选通管的高开关比。
本领域的技术人员容易理解，以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (7)

  1. 一种选通管器件的预处理方法，其特征在于，包括：
    (1)通过选取电压扫描范围且设置第一限制电流I cc1，对选通管进行第一次电压扫描，获取其亚阈值区域的阻态R 1；
    (2)根据第n-1次电压扫描后的选通管亚阈值区域的阻态R n-1，设置第n限制电流I cc(n)，并对选通管进行第n次电压扫描，获取其亚阈值区域的阻态R n，
    其中，I cc(n-1)＜I cc(n)，n的初始值为2；
    (3)在读电压下，若第n次电压扫描后选通管器件的高阻态阻值大于第一次电压扫描后的选通管器件的高阻态阻值，则停止对选通管器件的电压扫描；否则，n＝n+1，转至步骤(2)。
  2. 如权利要求1所述的预处理方法，其特征在于，所述读电压为第一次电压扫描后的选通管器件的0.5倍开电压。
  3. 如权利要求1或2所述的预处理方法，其特征在于，
    所述第一限制电流I cc1为：500nA＜I cc1＜1000uA；
    所述第n限制电流I cc(n)为：I cc(n-1)＜I cc(n)＜1100uA。
  4. 如权利要求3所述的预处理方法，其特征在于，
    所述电压扫描范围为0～4V th；
    所述电压扫描的方式为：电压从0开始递增到最大电压，再从最大电压回扫到0；
    其中，V th为选通管的开电压。
  5. 如权利要求4所述的预处理方法，其特征在于，所述选通管包括第一电极层、硫系选通材料层和第二电极层；所述硫系选通材料层介于第一电极层和第二电极层之间。
  6. 如权利要求5所述的预处理方法，其特征在于，所述硫系选通材料层的材料为SiTe x、CTe x、BTe x、GeTe x、AlTe x、GeSb xTe y、GeSb x、BiTe x、AsTe x、SnTe x、BiTe x中至少一种，或者SiTe x、CTe x、BTe x、GeTe x、AlTe x、GeSb xTe y、GeSb x、BiTe x、AsTe x、SnTe x、BiTe x中至少一种化合物掺杂N、Sb、Bi、C中的至少一种元素形成的混合物，或者SiTe x、CTe x、BTe x、GeTe x、AlTe x、GeSb xTe y、GeSb x、BiTe x、AsTe x、SnTe x、BiTe x中至少一种化合物掺杂Si元素形成的混合物。
  7. 如权利要求4或5所述的预处理方法，其特征在于，所述第一电极层和第二电极层均为惰性电极材料，且所述惰性电极材料为W、TiW、Pt、Au、Ru、Al、TiN、Ta、TaN、IrO 2、ITO和IZO的至少一种。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102129886A (zh) * 2010-01-12 2011-07-20 中芯国际集成电路制造(上海)有限公司 电阻随机存储器的初始化以及设置、复位方法
WO2017124873A1 (zh) * 2016-01-22 2017-07-27 清华大学 阻变存储器的操作方法及阻变存储器装置
CN106992251A (zh) * 2017-05-12 2017-07-28 华中科技大学 一种基于VOx选通管的相变存储单元
WO2019009296A1 (ja) * 2017-07-06 2019-01-10 日本電気株式会社 スイッチ素子、スイッチ方法および半導体装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102122636B (zh) * 2010-12-08 2013-06-19 中国科学院上海微系统与信息技术研究所 三维电阻转换存储芯片制备方法
US9425237B2 (en) * 2014-03-11 2016-08-23 Crossbar, Inc. Selector device for two-terminal memory
CN104347800B (zh) * 2014-09-17 2018-03-30 曲阜师范大学 一种相变存储器选通管及其存储单元
US11348973B2 (en) * 2016-09-23 2022-05-31 Intel Corporation Threshold switching selector based memory
CN106601907B (zh) * 2016-12-14 2019-02-22 中国科学院上海微系统与信息技术研究所 一种选通管材料、选通管单元及其制作方法
CN107732010B (zh) * 2017-09-29 2020-07-10 华中科技大学 一种选通管器件及其制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102129886A (zh) * 2010-01-12 2011-07-20 中芯国际集成电路制造(上海)有限公司 电阻随机存储器的初始化以及设置、复位方法
WO2017124873A1 (zh) * 2016-01-22 2017-07-27 清华大学 阻变存储器的操作方法及阻变存储器装置
CN106992251A (zh) * 2017-05-12 2017-07-28 华中科技大学 一种基于VOx选通管的相变存储单元
WO2019009296A1 (ja) * 2017-07-06 2019-01-10 日本電気株式会社 スイッチ素子、スイッチ方法および半導体装置

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